FreeBSD/Linux Kernel Cross Reference
sys/pci/if_wb.c
1 /*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD$
33 */
34
35 /*
36 * Winbond fast ethernet PCI NIC driver
37 *
38 * Supports various cheap network adapters based on the Winbond W89C840F
39 * fast ethernet controller chip. This includes adapters manufactured by
40 * Winbond itself and some made by Linksys.
41 *
42 * Written by Bill Paul <wpaul@ctr.columbia.edu>
43 * Electrical Engineering Department
44 * Columbia University, New York City
45 */
46
47 /*
48 * The Winbond W89C840F chip is a bus master; in some ways it resembles
49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
50 * one major difference which is that while the registers do many of
51 * the same things as a tulip adapter, the offsets are different: where
52 * tulip registers are typically spaced 8 bytes apart, the Winbond
53 * registers are spaced 4 bytes apart. The receiver filter is also
54 * programmed differently.
55 *
56 * Like the tulip, the Winbond chip uses small descriptors containing
57 * a status word, a control word and 32-bit areas that can either be used
58 * to point to two external data blocks, or to point to a single block
59 * and another descriptor in a linked list. Descriptors can be grouped
60 * together in blocks to form fixed length rings or can be chained
61 * together in linked lists. A single packet may be spread out over
62 * several descriptors if necessary.
63 *
64 * For the receive ring, this driver uses a linked list of descriptors,
65 * each pointing to a single mbuf cluster buffer, which us large enough
66 * to hold an entire packet. The link list is looped back to created a
67 * closed ring.
68 *
69 * For transmission, the driver creates a linked list of 'super descriptors'
70 * which each contain several individual descriptors linked toghether.
71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
72 * abuse as fragment pointers. This allows us to use a buffer managment
73 * scheme very similar to that used in the ThunderLAN and Etherlink XL
74 * drivers.
75 *
76 * Autonegotiation is performed using the external PHY via the MII bus.
77 * The sample boards I have all use a Davicom PHY.
78 *
79 * Note: the author of the Linux driver for the Winbond chip alludes
80 * to some sort of flaw in the chip's design that seems to mandate some
81 * drastic workaround which signigicantly impairs transmit performance.
82 * I have no idea what he's on about: transmit performance with all
83 * three of my test boards seems fine.
84 */
85
86 #include "bpfilter.h"
87 #include "opt_bdg.h"
88
89 #include <sys/param.h>
90 #include <sys/systm.h>
91 #include <sys/sockio.h>
92 #include <sys/mbuf.h>
93 #include <sys/malloc.h>
94 #include <sys/kernel.h>
95 #include <sys/socket.h>
96
97 #include <net/if.h>
98 #include <net/if_arp.h>
99 #include <net/ethernet.h>
100 #include <net/if_dl.h>
101 #include <net/if_media.h>
102
103 #if NBPFILTER > 0
104 #include <net/bpf.h>
105 #endif
106
107 #ifdef BRIDGE
108 #include <net/bridge.h>
109 #endif
110
111 #include <vm/vm.h> /* for vtophys */
112 #include <vm/pmap.h> /* for vtophys */
113 #include <machine/clock.h> /* for DELAY */
114 #include <machine/bus_memio.h>
115 #include <machine/bus_pio.h>
116 #include <machine/bus.h>
117
118 #include <pci/pcireg.h>
119 #include <pci/pcivar.h>
120
121 #define WB_USEIOSPACE
122
123 /* #define WB_BACKGROUND_AUTONEG */
124
125 #include <pci/if_wbreg.h>
126
127 #ifndef lint
128 static const char rcsid[] =
129 "$FreeBSD$";
130 #endif
131
132 /*
133 * Various supported device vendors/types and their names.
134 */
135 static struct wb_type wb_devs[] = {
136 { WB_VENDORID, WB_DEVICEID_840F,
137 "Winbond W89C840F 10/100BaseTX" },
138 { CP_VENDORID, CP_DEVICEID_RL100,
139 "Compex RL100-ATX 10/100baseTX" },
140 { 0, 0, NULL }
141 };
142
143 /*
144 * Various supported PHY vendors/types and their names. Note that
145 * this driver will work with pretty much any MII-compliant PHY,
146 * so failure to positively identify the chip is not a fatal error.
147 */
148
149 static struct wb_type wb_phys[] = {
150 { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" },
151 { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" },
152 { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"},
153 { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" },
154 { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" },
155 { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" },
156 { 0, 0, "<MII-compliant physical interface>" }
157 };
158
159 static unsigned long wb_count = 0;
160 static const char *wb_probe __P((pcici_t, pcidi_t));
161 static void wb_attach __P((pcici_t, int));
162
163 static int wb_newbuf __P((struct wb_softc *,
164 struct wb_chain_onefrag *,
165 struct mbuf *));
166 static int wb_encap __P((struct wb_softc *, struct wb_chain *,
167 struct mbuf *));
168
169 static void wb_rxeof __P((struct wb_softc *));
170 static void wb_rxeoc __P((struct wb_softc *));
171 static void wb_txeof __P((struct wb_softc *));
172 static void wb_txeoc __P((struct wb_softc *));
173 static void wb_intr __P((void *));
174 static void wb_start __P((struct ifnet *));
175 static int wb_ioctl __P((struct ifnet *, u_long, caddr_t));
176 static void wb_init __P((void *));
177 static void wb_stop __P((struct wb_softc *));
178 static void wb_watchdog __P((struct ifnet *));
179 static void wb_shutdown __P((int, void *));
180 static int wb_ifmedia_upd __P((struct ifnet *));
181 static void wb_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
182
183 static void wb_eeprom_putbyte __P((struct wb_softc *, int));
184 static void wb_eeprom_getword __P((struct wb_softc *, int, u_int16_t *));
185 static void wb_read_eeprom __P((struct wb_softc *, caddr_t, int,
186 int, int));
187 static void wb_mii_sync __P((struct wb_softc *));
188 static void wb_mii_send __P((struct wb_softc *, u_int32_t, int));
189 static int wb_mii_readreg __P((struct wb_softc *, struct wb_mii_frame *));
190 static int wb_mii_writereg __P((struct wb_softc *, struct wb_mii_frame *));
191 static u_int16_t wb_phy_readreg __P((struct wb_softc *, int));
192 static void wb_phy_writereg __P((struct wb_softc *, int, int));
193
194 static void wb_autoneg_xmit __P((struct wb_softc *));
195 static void wb_autoneg_mii __P((struct wb_softc *, int, int));
196 static void wb_setmode_mii __P((struct wb_softc *, int));
197 static void wb_getmode_mii __P((struct wb_softc *));
198 static void wb_setcfg __P((struct wb_softc *, int));
199 static u_int8_t wb_calchash __P((caddr_t));
200 static void wb_setmulti __P((struct wb_softc *));
201 static void wb_reset __P((struct wb_softc *));
202 static int wb_list_rx_init __P((struct wb_softc *));
203 static int wb_list_tx_init __P((struct wb_softc *));
204
205 #define WB_SETBIT(sc, reg, x) \
206 CSR_WRITE_4(sc, reg, \
207 CSR_READ_4(sc, reg) | x)
208
209 #define WB_CLRBIT(sc, reg, x) \
210 CSR_WRITE_4(sc, reg, \
211 CSR_READ_4(sc, reg) & ~x)
212
213 #define SIO_SET(x) \
214 CSR_WRITE_4(sc, WB_SIO, \
215 CSR_READ_4(sc, WB_SIO) | x)
216
217 #define SIO_CLR(x) \
218 CSR_WRITE_4(sc, WB_SIO, \
219 CSR_READ_4(sc, WB_SIO) & ~x)
220
221 /*
222 * Send a read command and address to the EEPROM, check for ACK.
223 */
224 static void wb_eeprom_putbyte(sc, addr)
225 struct wb_softc *sc;
226 int addr;
227 {
228 register int d, i;
229
230 d = addr | WB_EECMD_READ;
231
232 /*
233 * Feed in each bit and stobe the clock.
234 */
235 for (i = 0x400; i; i >>= 1) {
236 if (d & i) {
237 SIO_SET(WB_SIO_EE_DATAIN);
238 } else {
239 SIO_CLR(WB_SIO_EE_DATAIN);
240 }
241 DELAY(100);
242 SIO_SET(WB_SIO_EE_CLK);
243 DELAY(150);
244 SIO_CLR(WB_SIO_EE_CLK);
245 DELAY(100);
246 }
247
248 return;
249 }
250
251 /*
252 * Read a word of data stored in the EEPROM at address 'addr.'
253 */
254 static void wb_eeprom_getword(sc, addr, dest)
255 struct wb_softc *sc;
256 int addr;
257 u_int16_t *dest;
258 {
259 register int i;
260 u_int16_t word = 0;
261
262 /* Enter EEPROM access mode. */
263 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
264
265 /*
266 * Send address of word we want to read.
267 */
268 wb_eeprom_putbyte(sc, addr);
269
270 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
271
272 /*
273 * Start reading bits from EEPROM.
274 */
275 for (i = 0x8000; i; i >>= 1) {
276 SIO_SET(WB_SIO_EE_CLK);
277 DELAY(100);
278 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
279 word |= i;
280 SIO_CLR(WB_SIO_EE_CLK);
281 DELAY(100);
282 }
283
284 /* Turn off EEPROM access mode. */
285 CSR_WRITE_4(sc, WB_SIO, 0);
286
287 *dest = word;
288
289 return;
290 }
291
292 /*
293 * Read a sequence of words from the EEPROM.
294 */
295 static void wb_read_eeprom(sc, dest, off, cnt, swap)
296 struct wb_softc *sc;
297 caddr_t dest;
298 int off;
299 int cnt;
300 int swap;
301 {
302 int i;
303 u_int16_t word = 0, *ptr;
304
305 for (i = 0; i < cnt; i++) {
306 wb_eeprom_getword(sc, off + i, &word);
307 ptr = (u_int16_t *)(dest + (i * 2));
308 if (swap)
309 *ptr = ntohs(word);
310 else
311 *ptr = word;
312 }
313
314 return;
315 }
316
317 /*
318 * Sync the PHYs by setting data bit and strobing the clock 32 times.
319 */
320 static void wb_mii_sync(sc)
321 struct wb_softc *sc;
322 {
323 register int i;
324
325 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN);
326
327 for (i = 0; i < 32; i++) {
328 SIO_SET(WB_SIO_MII_CLK);
329 DELAY(1);
330 SIO_CLR(WB_SIO_MII_CLK);
331 DELAY(1);
332 }
333
334 return;
335 }
336
337 /*
338 * Clock a series of bits through the MII.
339 */
340 static void wb_mii_send(sc, bits, cnt)
341 struct wb_softc *sc;
342 u_int32_t bits;
343 int cnt;
344 {
345 int i;
346
347 SIO_CLR(WB_SIO_MII_CLK);
348
349 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
350 if (bits & i) {
351 SIO_SET(WB_SIO_MII_DATAIN);
352 } else {
353 SIO_CLR(WB_SIO_MII_DATAIN);
354 }
355 DELAY(1);
356 SIO_CLR(WB_SIO_MII_CLK);
357 DELAY(1);
358 SIO_SET(WB_SIO_MII_CLK);
359 }
360 }
361
362 /*
363 * Read an PHY register through the MII.
364 */
365 static int wb_mii_readreg(sc, frame)
366 struct wb_softc *sc;
367 struct wb_mii_frame *frame;
368
369 {
370 int i, ack, s;
371
372 s = splimp();
373
374 /*
375 * Set up frame for RX.
376 */
377 frame->mii_stdelim = WB_MII_STARTDELIM;
378 frame->mii_opcode = WB_MII_READOP;
379 frame->mii_turnaround = 0;
380 frame->mii_data = 0;
381
382 CSR_WRITE_4(sc, WB_SIO, 0);
383
384 /*
385 * Turn on data xmit.
386 */
387 SIO_SET(WB_SIO_MII_DIR);
388
389 wb_mii_sync(sc);
390
391 /*
392 * Send command/address info.
393 */
394 wb_mii_send(sc, frame->mii_stdelim, 2);
395 wb_mii_send(sc, frame->mii_opcode, 2);
396 wb_mii_send(sc, frame->mii_phyaddr, 5);
397 wb_mii_send(sc, frame->mii_regaddr, 5);
398
399 /* Idle bit */
400 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN));
401 DELAY(1);
402 SIO_SET(WB_SIO_MII_CLK);
403 DELAY(1);
404
405 /* Turn off xmit. */
406 SIO_CLR(WB_SIO_MII_DIR);
407 /* Check for ack */
408 SIO_CLR(WB_SIO_MII_CLK);
409 DELAY(1);
410 SIO_SET(WB_SIO_MII_CLK);
411 DELAY(1);
412 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
413 SIO_CLR(WB_SIO_MII_CLK);
414 DELAY(1);
415 SIO_SET(WB_SIO_MII_CLK);
416 DELAY(1);
417
418 /*
419 * Now try reading data bits. If the ack failed, we still
420 * need to clock through 16 cycles to keep the PHY(s) in sync.
421 */
422 if (ack) {
423 for(i = 0; i < 16; i++) {
424 SIO_CLR(WB_SIO_MII_CLK);
425 DELAY(1);
426 SIO_SET(WB_SIO_MII_CLK);
427 DELAY(1);
428 }
429 goto fail;
430 }
431
432 for (i = 0x8000; i; i >>= 1) {
433 SIO_CLR(WB_SIO_MII_CLK);
434 DELAY(1);
435 if (!ack) {
436 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
437 frame->mii_data |= i;
438 DELAY(1);
439 }
440 SIO_SET(WB_SIO_MII_CLK);
441 DELAY(1);
442 }
443
444 fail:
445
446 SIO_CLR(WB_SIO_MII_CLK);
447 DELAY(1);
448 SIO_SET(WB_SIO_MII_CLK);
449 DELAY(1);
450
451 splx(s);
452
453 if (ack)
454 return(1);
455 return(0);
456 }
457
458 /*
459 * Write to a PHY register through the MII.
460 */
461 static int wb_mii_writereg(sc, frame)
462 struct wb_softc *sc;
463 struct wb_mii_frame *frame;
464
465 {
466 int s;
467
468 s = splimp();
469 /*
470 * Set up frame for TX.
471 */
472
473 frame->mii_stdelim = WB_MII_STARTDELIM;
474 frame->mii_opcode = WB_MII_WRITEOP;
475 frame->mii_turnaround = WB_MII_TURNAROUND;
476
477 /*
478 * Turn on data output.
479 */
480 SIO_SET(WB_SIO_MII_DIR);
481
482 wb_mii_sync(sc);
483
484 wb_mii_send(sc, frame->mii_stdelim, 2);
485 wb_mii_send(sc, frame->mii_opcode, 2);
486 wb_mii_send(sc, frame->mii_phyaddr, 5);
487 wb_mii_send(sc, frame->mii_regaddr, 5);
488 wb_mii_send(sc, frame->mii_turnaround, 2);
489 wb_mii_send(sc, frame->mii_data, 16);
490
491 /* Idle bit. */
492 SIO_SET(WB_SIO_MII_CLK);
493 DELAY(1);
494 SIO_CLR(WB_SIO_MII_CLK);
495 DELAY(1);
496
497 /*
498 * Turn off xmit.
499 */
500 SIO_CLR(WB_SIO_MII_DIR);
501
502 splx(s);
503
504 return(0);
505 }
506
507 static u_int16_t wb_phy_readreg(sc, reg)
508 struct wb_softc *sc;
509 int reg;
510 {
511 struct wb_mii_frame frame;
512
513 bzero((char *)&frame, sizeof(frame));
514
515 frame.mii_phyaddr = sc->wb_phy_addr;
516 frame.mii_regaddr = reg;
517 wb_mii_readreg(sc, &frame);
518
519 return(frame.mii_data);
520 }
521
522 static void wb_phy_writereg(sc, reg, data)
523 struct wb_softc *sc;
524 int reg;
525 int data;
526 {
527 struct wb_mii_frame frame;
528
529 bzero((char *)&frame, sizeof(frame));
530
531 frame.mii_phyaddr = sc->wb_phy_addr;
532 frame.mii_regaddr = reg;
533 frame.mii_data = data;
534
535 wb_mii_writereg(sc, &frame);
536
537 return;
538 }
539
540 static u_int8_t wb_calchash(addr)
541 caddr_t addr;
542 {
543 u_int32_t crc, carry;
544 int i, j;
545 u_int8_t c;
546
547 /* Compute CRC for the address value. */
548 crc = 0xFFFFFFFF; /* initial value */
549
550 for (i = 0; i < 6; i++) {
551 c = *(addr + i);
552 for (j = 0; j < 8; j++) {
553 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
554 crc <<= 1;
555 c >>= 1;
556 if (carry)
557 crc = (crc ^ 0x04c11db6) | carry;
558 }
559 }
560
561 /*
562 * return the filter bit position
563 * Note: I arrived at the following nonsense
564 * through experimentation. It's not the usual way to
565 * generate the bit position but it's the only thing
566 * I could come up with that works.
567 */
568 return(~(crc >> 26) & 0x0000003F);
569 }
570
571 /*
572 * Program the 64-bit multicast hash filter.
573 */
574 static void wb_setmulti(sc)
575 struct wb_softc *sc;
576 {
577 struct ifnet *ifp;
578 int h = 0;
579 u_int32_t hashes[2] = { 0, 0 };
580 struct ifmultiaddr *ifma;
581 u_int32_t rxfilt;
582 int mcnt = 0;
583
584 ifp = &sc->arpcom.ac_if;
585
586 rxfilt = CSR_READ_4(sc, WB_NETCFG);
587
588 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
589 rxfilt |= WB_NETCFG_RX_MULTI;
590 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
591 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
592 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
593 return;
594 }
595
596 /* first, zot all the existing hash bits */
597 CSR_WRITE_4(sc, WB_MAR0, 0);
598 CSR_WRITE_4(sc, WB_MAR1, 0);
599
600 /* now program new ones */
601 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
602 ifma = ifma->ifma_link.le_next) {
603 if (ifma->ifma_addr->sa_family != AF_LINK)
604 continue;
605 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
606 if (h < 32)
607 hashes[0] |= (1 << h);
608 else
609 hashes[1] |= (1 << (h - 32));
610 mcnt++;
611 }
612
613 if (mcnt)
614 rxfilt |= WB_NETCFG_RX_MULTI;
615 else
616 rxfilt &= ~WB_NETCFG_RX_MULTI;
617
618 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
619 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
620 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
621
622 return;
623 }
624
625 /*
626 * Initiate an autonegotiation session.
627 */
628 static void wb_autoneg_xmit(sc)
629 struct wb_softc *sc;
630 {
631 u_int16_t phy_sts;
632
633 wb_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
634 DELAY(500);
635 while(wb_phy_readreg(sc, PHY_BMCR)
636 & PHY_BMCR_RESET);
637
638 phy_sts = wb_phy_readreg(sc, PHY_BMCR);
639 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR;
640 wb_phy_writereg(sc, PHY_BMCR, phy_sts);
641
642 return;
643 }
644
645 /*
646 * Invoke autonegotiation on a PHY.
647 */
648 static void wb_autoneg_mii(sc, flag, verbose)
649 struct wb_softc *sc;
650 int flag;
651 int verbose;
652 {
653 u_int16_t phy_sts = 0, media, advert, ability;
654 struct ifnet *ifp;
655 struct ifmedia *ifm;
656
657 ifm = &sc->ifmedia;
658 ifp = &sc->arpcom.ac_if;
659
660 ifm->ifm_media = IFM_ETHER | IFM_AUTO;
661
662 /*
663 * The 100baseT4 PHY on the 3c905-T4 has the 'autoneg supported'
664 * bit cleared in the status register, but has the 'autoneg enabled'
665 * bit set in the control register. This is a contradiction, and
666 * I'm not sure how to handle it. If you want to force an attempt
667 * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR
668 * and see what happens.
669 */
670 #ifndef FORCE_AUTONEG_TFOUR
671 /*
672 * First, see if autoneg is supported. If not, there's
673 * no point in continuing.
674 */
675 phy_sts = wb_phy_readreg(sc, PHY_BMSR);
676 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
677 if (verbose)
678 printf("wb%d: autonegotiation not supported\n",
679 sc->wb_unit);
680 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
681 return;
682 }
683 #endif
684
685 switch (flag) {
686 case WB_FLAG_FORCEDELAY:
687 /*
688 * XXX Never use this option anywhere but in the probe
689 * routine: making the kernel stop dead in its tracks
690 * for three whole seconds after we've gone multi-user
691 * is really bad manners.
692 */
693 wb_autoneg_xmit(sc);
694 DELAY(5000000);
695 break;
696 case WB_FLAG_SCHEDDELAY:
697 /*
698 * Wait for the transmitter to go idle before starting
699 * an autoneg session, otherwise wb_start() may clobber
700 * our timeout, and we don't want to allow transmission
701 * during an autoneg session since that can screw it up.
702 */
703 if (sc->wb_cdata.wb_tx_head != NULL) {
704 sc->wb_want_auto = 1;
705 return;
706 }
707 wb_autoneg_xmit(sc);
708 ifp->if_timer = 5;
709 sc->wb_autoneg = 1;
710 sc->wb_want_auto = 0;
711 return;
712 break;
713 case WB_FLAG_DELAYTIMEO:
714 ifp->if_timer = 0;
715 sc->wb_autoneg = 0;
716 break;
717 default:
718 printf("wb%d: invalid autoneg flag: %d\n", sc->wb_unit, flag);
719 return;
720 }
721
722 if (wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
723 if (verbose)
724 printf("wb%d: autoneg complete, ", sc->wb_unit);
725 phy_sts = wb_phy_readreg(sc, PHY_BMSR);
726 } else {
727 if (verbose)
728 printf("wb%d: autoneg not complete, ", sc->wb_unit);
729 }
730
731 media = wb_phy_readreg(sc, PHY_BMCR);
732
733 /* Link is good. Report modes and set duplex mode. */
734 if (wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
735 if (verbose)
736 printf("link status good ");
737 advert = wb_phy_readreg(sc, PHY_ANAR);
738 ability = wb_phy_readreg(sc, PHY_LPAR);
739
740 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
741 ifm->ifm_media = IFM_ETHER|IFM_100_T4;
742 media |= PHY_BMCR_SPEEDSEL;
743 media &= ~PHY_BMCR_DUPLEX;
744 printf("(100baseT4)\n");
745 } else if (advert & PHY_ANAR_100BTXFULL &&
746 ability & PHY_ANAR_100BTXFULL) {
747 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
748 media |= PHY_BMCR_SPEEDSEL;
749 media |= PHY_BMCR_DUPLEX;
750 printf("(full-duplex, 100Mbps)\n");
751 } else if (advert & PHY_ANAR_100BTXHALF &&
752 ability & PHY_ANAR_100BTXHALF) {
753 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
754 media |= PHY_BMCR_SPEEDSEL;
755 media &= ~PHY_BMCR_DUPLEX;
756 printf("(half-duplex, 100Mbps)\n");
757 } else if (advert & PHY_ANAR_10BTFULL &&
758 ability & PHY_ANAR_10BTFULL) {
759 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
760 media &= ~PHY_BMCR_SPEEDSEL;
761 media |= PHY_BMCR_DUPLEX;
762 printf("(full-duplex, 10Mbps)\n");
763 } else /* if (advert & PHY_ANAR_10BTHALF &&
764 ability & PHY_ANAR_10BTHALF) */ {
765 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
766 media &= ~PHY_BMCR_SPEEDSEL;
767 media &= ~PHY_BMCR_DUPLEX;
768 printf("(half-duplex, 10Mbps)\n");
769 }
770
771 media &= ~PHY_BMCR_AUTONEGENBL;
772
773 /* Set ASIC's duplex mode to match the PHY. */
774 wb_setcfg(sc, media);
775 wb_phy_writereg(sc, PHY_BMCR, media);
776 } else {
777 if (verbose)
778 printf("no carrier\n");
779 }
780
781 wb_init(sc);
782
783 if (sc->wb_tx_pend) {
784 sc->wb_autoneg = 0;
785 sc->wb_tx_pend = 0;
786 wb_start(ifp);
787 }
788
789 return;
790 }
791
792 static void wb_getmode_mii(sc)
793 struct wb_softc *sc;
794 {
795 u_int16_t bmsr;
796 struct ifnet *ifp;
797
798 ifp = &sc->arpcom.ac_if;
799
800 bmsr = wb_phy_readreg(sc, PHY_BMSR);
801 if (bootverbose)
802 printf("wb%d: PHY status word: %x\n", sc->wb_unit, bmsr);
803
804 /* fallback */
805 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
806
807 if (bmsr & PHY_BMSR_10BTHALF) {
808 if (bootverbose)
809 printf("wb%d: 10Mbps half-duplex mode supported\n",
810 sc->wb_unit);
811 ifmedia_add(&sc->ifmedia,
812 IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
813 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
814 }
815
816 if (bmsr & PHY_BMSR_10BTFULL) {
817 if (bootverbose)
818 printf("wb%d: 10Mbps full-duplex mode supported\n",
819 sc->wb_unit);
820 ifmedia_add(&sc->ifmedia,
821 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
822 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
823 }
824
825 if (bmsr & PHY_BMSR_100BTXHALF) {
826 if (bootverbose)
827 printf("wb%d: 100Mbps half-duplex mode supported\n",
828 sc->wb_unit);
829 ifp->if_baudrate = 100000000;
830 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
831 ifmedia_add(&sc->ifmedia,
832 IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
833 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
834 }
835
836 if (bmsr & PHY_BMSR_100BTXFULL) {
837 if (bootverbose)
838 printf("wb%d: 100Mbps full-duplex mode supported\n",
839 sc->wb_unit);
840 ifp->if_baudrate = 100000000;
841 ifmedia_add(&sc->ifmedia,
842 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
843 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
844 }
845
846 /* Some also support 100BaseT4. */
847 if (bmsr & PHY_BMSR_100BT4) {
848 if (bootverbose)
849 printf("wb%d: 100baseT4 mode supported\n", sc->wb_unit);
850 ifp->if_baudrate = 100000000;
851 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL);
852 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4;
853 #ifdef FORCE_AUTONEG_TFOUR
854 if (bootverbose)
855 printf("wb%d: forcing on autoneg support for BT4\n",
856 sc->wb_unit);
857 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL):
858 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
859 #endif
860 }
861
862 if (bmsr & PHY_BMSR_CANAUTONEG) {
863 if (bootverbose)
864 printf("wb%d: autoneg supported\n", sc->wb_unit);
865 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
866 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
867 }
868
869 return;
870 }
871
872 /*
873 * Set speed and duplex mode.
874 */
875 static void wb_setmode_mii(sc, media)
876 struct wb_softc *sc;
877 int media;
878 {
879 u_int16_t bmcr;
880 struct ifnet *ifp;
881
882 ifp = &sc->arpcom.ac_if;
883
884 /*
885 * If an autoneg session is in progress, stop it.
886 */
887 if (sc->wb_autoneg) {
888 printf("wb%d: canceling autoneg session\n", sc->wb_unit);
889 ifp->if_timer = sc->wb_autoneg = sc->wb_want_auto = 0;
890 bmcr = wb_phy_readreg(sc, PHY_BMCR);
891 bmcr &= ~PHY_BMCR_AUTONEGENBL;
892 wb_phy_writereg(sc, PHY_BMCR, bmcr);
893 }
894
895 printf("wb%d: selecting MII, ", sc->wb_unit);
896
897 bmcr = wb_phy_readreg(sc, PHY_BMCR);
898
899 bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL|
900 PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK);
901
902 if (IFM_SUBTYPE(media) == IFM_100_T4) {
903 printf("100Mbps/T4, half-duplex\n");
904 bmcr |= PHY_BMCR_SPEEDSEL;
905 bmcr &= ~PHY_BMCR_DUPLEX;
906 }
907
908 if (IFM_SUBTYPE(media) == IFM_100_TX) {
909 printf("100Mbps, ");
910 bmcr |= PHY_BMCR_SPEEDSEL;
911 }
912
913 if (IFM_SUBTYPE(media) == IFM_10_T) {
914 printf("10Mbps, ");
915 bmcr &= ~PHY_BMCR_SPEEDSEL;
916 }
917
918 if ((media & IFM_GMASK) == IFM_FDX) {
919 printf("full duplex\n");
920 bmcr |= PHY_BMCR_DUPLEX;
921 } else {
922 printf("half duplex\n");
923 bmcr &= ~PHY_BMCR_DUPLEX;
924 }
925
926 wb_setcfg(sc, bmcr);
927 wb_phy_writereg(sc, PHY_BMCR, bmcr);
928
929 return;
930 }
931
932 /*
933 * The Winbond manual states that in order to fiddle with the
934 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
935 * first have to put the transmit and/or receive logic in the idle state.
936 */
937 static void wb_setcfg(sc, bmcr)
938 struct wb_softc *sc;
939 int bmcr;
940 {
941 int i, restart = 0;
942
943 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
944 restart = 1;
945 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
946
947 for (i = 0; i < WB_TIMEOUT; i++) {
948 DELAY(10);
949 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
950 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
951 break;
952 }
953
954 if (i == WB_TIMEOUT)
955 printf("wb%d: failed to force tx and "
956 "rx to idle state\n", sc->wb_unit);
957 }
958
959 if (bmcr & PHY_BMCR_SPEEDSEL)
960 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
961 else
962 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
963
964 if (bmcr & PHY_BMCR_DUPLEX)
965 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
966 else
967 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
968
969 if (restart)
970 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
971
972 return;
973 }
974
975 static void wb_reset(sc)
976 struct wb_softc *sc;
977 {
978 register int i;
979
980 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
981
982 for (i = 0; i < WB_TIMEOUT; i++) {
983 DELAY(10);
984 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
985 break;
986 }
987 if (i == WB_TIMEOUT)
988 printf("wb%d: reset never completed!\n", sc->wb_unit);
989
990 /* Wait a little while for the chip to get its brains in order. */
991 DELAY(1000);
992
993 /* Reset the damn PHY too. */
994 if (sc->wb_pinfo != NULL)
995 wb_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
996
997 return;
998 }
999
1000 /*
1001 * Probe for a Winbond chip. Check the PCI vendor and device
1002 * IDs against our list and return a device name if we find a match.
1003 */
1004 static const char *
1005 wb_probe(config_id, device_id)
1006 pcici_t config_id;
1007 pcidi_t device_id;
1008 {
1009 struct wb_type *t;
1010
1011 t = wb_devs;
1012
1013 while(t->wb_name != NULL) {
1014 if ((device_id & 0xFFFF) == t->wb_vid &&
1015 ((device_id >> 16) & 0xFFFF) == t->wb_did) {
1016 return(t->wb_name);
1017 }
1018 t++;
1019 }
1020
1021 return(NULL);
1022 }
1023
1024 /*
1025 * Attach the interface. Allocate softc structures, do ifmedia
1026 * setup and ethernet/BPF attach.
1027 */
1028 static void
1029 wb_attach(config_id, unit)
1030 pcici_t config_id;
1031 int unit;
1032 {
1033 int s, i;
1034 #ifndef WB_USEIOSPACE
1035 vm_offset_t pbase, vbase;
1036 #endif
1037 u_char eaddr[ETHER_ADDR_LEN];
1038 u_int32_t command;
1039 struct wb_softc *sc;
1040 struct ifnet *ifp;
1041 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1042 unsigned int round;
1043 caddr_t roundptr;
1044 struct wb_type *p;
1045 u_int16_t phy_vid, phy_did, phy_sts;
1046
1047 s = splimp();
1048
1049 sc = malloc(sizeof(struct wb_softc), M_DEVBUF, M_NOWAIT);
1050 if (sc == NULL) {
1051 printf("wb%d: no memory for softc struct!\n", unit);
1052 return;
1053 }
1054 bzero(sc, sizeof(struct wb_softc));
1055
1056 /*
1057 * Handle power management nonsense.
1058 */
1059
1060 command = pci_conf_read(config_id, WB_PCI_CAPID) & 0x000000FF;
1061 if (command == 0x01) {
1062
1063 command = pci_conf_read(config_id, WB_PCI_PWRMGMTCTRL);
1064 if (command & WB_PSTATE_MASK) {
1065 u_int32_t iobase, membase, irq;
1066
1067 /* Save important PCI config data. */
1068 iobase = pci_conf_read(config_id, WB_PCI_LOIO);
1069 membase = pci_conf_read(config_id, WB_PCI_LOMEM);
1070 irq = pci_conf_read(config_id, WB_PCI_INTLINE);
1071
1072 /* Reset the power state. */
1073 printf("wb%d: chip is in D%d power mode "
1074 "-- setting to D0\n", unit, command & WB_PSTATE_MASK);
1075 command &= 0xFFFFFFFC;
1076 pci_conf_write(config_id, WB_PCI_PWRMGMTCTRL, command);
1077
1078 /* Restore PCI config data. */
1079 pci_conf_write(config_id, WB_PCI_LOIO, iobase);
1080 pci_conf_write(config_id, WB_PCI_LOMEM, membase);
1081 pci_conf_write(config_id, WB_PCI_INTLINE, irq);
1082 }
1083 }
1084
1085 /*
1086 * Map control/status registers.
1087 */
1088 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1089 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1090 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command);
1091 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1092
1093 #ifdef WB_USEIOSPACE
1094 if (!(command & PCIM_CMD_PORTEN)) {
1095 printf("wb%d: failed to enable I/O ports!\n", unit);
1096 free(sc, M_DEVBUF);
1097 goto fail;
1098 }
1099
1100 if (!pci_map_port(config_id, WB_PCI_LOIO,
1101 (pci_port_t *)&(sc->wb_bhandle))) {
1102 printf ("wb%d: couldn't map ports\n", unit);
1103 goto fail;
1104 }
1105 #ifdef __i386__
1106 sc->wb_btag = I386_BUS_SPACE_IO;
1107 #endif
1108 #ifdef __alpha__
1109 sc->wb_btag = ALPHA_BUS_SPACE_IO;
1110 #endif
1111 #else
1112 if (!(command & PCIM_CMD_MEMEN)) {
1113 printf("wb%d: failed to enable memory mapping!\n", unit);
1114 goto fail;
1115 }
1116
1117 if (!pci_map_mem(config_id, WB_PCI_LOMEM, &vbase, &pbase)) {
1118 printf ("wb%d: couldn't map memory\n", unit);
1119 goto fail;
1120 }
1121 #ifdef __i386__
1122 sc->wb_btag = I386_BUS_SPACE_MEM;
1123 #endif
1124 #ifdef __alpha__
1125 sc->wb_btag = I386_BUS_SPACE_MEM;
1126 #endif
1127 sc->wb_bhandle = vbase;
1128 #endif
1129
1130 /* Allocate interrupt */
1131 if (!pci_map_int(config_id, wb_intr, sc, &net_imask)) {
1132 printf("wb%d: couldn't map interrupt\n", unit);
1133 goto fail;
1134 }
1135
1136 /* Reset the adapter. */
1137 wb_reset(sc);
1138
1139 /*
1140 * Get station address from the EEPROM.
1141 */
1142 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0);
1143
1144 /*
1145 * A Winbond chip was detected. Inform the world.
1146 */
1147 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":");
1148
1149 sc->wb_unit = unit;
1150 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1151
1152 sc->wb_ldata_ptr = malloc(sizeof(struct wb_list_data) + 8,
1153 M_DEVBUF, M_NOWAIT);
1154 if (sc->wb_ldata_ptr == NULL) {
1155 free(sc, M_DEVBUF);
1156 printf("wb%d: no memory for list buffers!\n", unit);
1157 return;
1158 }
1159
1160 sc->wb_ldata = (struct wb_list_data *)sc->wb_ldata_ptr;
1161 round = (uintptr_t)sc->wb_ldata_ptr & 0xF;
1162 roundptr = sc->wb_ldata_ptr;
1163 for (i = 0; i < 8; i++) {
1164 if (round % 8) {
1165 round++;
1166 roundptr++;
1167 } else
1168 break;
1169 }
1170 sc->wb_ldata = (struct wb_list_data *)roundptr;
1171 bzero(sc->wb_ldata, sizeof(struct wb_list_data));
1172
1173 ifp = &sc->arpcom.ac_if;
1174 ifp->if_softc = sc;
1175 ifp->if_unit = unit;
1176 ifp->if_name = "wb";
1177 ifp->if_mtu = ETHERMTU;
1178 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1179 ifp->if_ioctl = wb_ioctl;
1180 ifp->if_output = ether_output;
1181 ifp->if_start = wb_start;
1182 ifp->if_watchdog = wb_watchdog;
1183 ifp->if_init = wb_init;
1184 ifp->if_baudrate = 10000000;
1185 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1;
1186
1187 if (bootverbose)
1188 printf("wb%d: probing for a PHY\n", sc->wb_unit);
1189 for (i = WB_PHYADDR_MIN; i < WB_PHYADDR_MAX + 1; i++) {
1190 if (bootverbose)
1191 printf("wb%d: checking address: %d\n",
1192 sc->wb_unit, i);
1193 sc->wb_phy_addr = i;
1194 wb_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
1195 DELAY(500);
1196 while(wb_phy_readreg(sc, PHY_BMCR)
1197 & PHY_BMCR_RESET);
1198 if ((phy_sts = wb_phy_readreg(sc, PHY_BMSR)))
1199 break;
1200 }
1201 if (phy_sts) {
1202 phy_vid = wb_phy_readreg(sc, PHY_VENID);
1203 phy_did = wb_phy_readreg(sc, PHY_DEVID);
1204 if (bootverbose)
1205 printf("wb%d: found PHY at address %d, ",
1206 sc->wb_unit, sc->wb_phy_addr);
1207 if (bootverbose)
1208 printf("vendor id: %x device id: %x\n",
1209 phy_vid, phy_did);
1210 p = wb_phys;
1211 while(p->wb_vid) {
1212 if (phy_vid == p->wb_vid &&
1213 (phy_did | 0x000F) == p->wb_did) {
1214 sc->wb_pinfo = p;
1215 break;
1216 }
1217 p++;
1218 }
1219 if (sc->wb_pinfo == NULL)
1220 sc->wb_pinfo = &wb_phys[PHY_UNKNOWN];
1221 if (bootverbose)
1222 printf("wb%d: PHY type: %s\n",
1223 sc->wb_unit, sc->wb_pinfo->wb_name);
1224 } else {
1225 printf("wb%d: MII without any phy!\n", sc->wb_unit);
1226 goto fail;
1227 }
1228
1229 /*
1230 * Do ifmedia setup.
1231 */
1232 ifmedia_init(&sc->ifmedia, 0, wb_ifmedia_upd, wb_ifmedia_sts);
1233
1234 wb_getmode_mii(sc);
1235 wb_autoneg_mii(sc, WB_FLAG_FORCEDELAY, 1);
1236 media = sc->ifmedia.ifm_media;
1237 wb_stop(sc);
1238
1239 ifmedia_set(&sc->ifmedia, media);
1240
1241 /*
1242 * Call MI attach routines.
1243 */
1244 if_attach(ifp);
1245 ether_ifattach(ifp);
1246
1247 #if NBPFILTER > 0
1248 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
1249 #endif
1250 at_shutdown(wb_shutdown, sc, SHUTDOWN_POST_SYNC);
1251
1252 fail:
1253 splx(s);
1254 return;
1255 }
1256
1257 /*
1258 * Initialize the transmit descriptors.
1259 */
1260 static int wb_list_tx_init(sc)
1261 struct wb_softc *sc;
1262 {
1263 struct wb_chain_data *cd;
1264 struct wb_list_data *ld;
1265 int i;
1266
1267 cd = &sc->wb_cdata;
1268 ld = sc->wb_ldata;
1269
1270 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1271 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
1272 if (i == (WB_TX_LIST_CNT - 1)) {
1273 cd->wb_tx_chain[i].wb_nextdesc =
1274 &cd->wb_tx_chain[0];
1275 } else {
1276 cd->wb_tx_chain[i].wb_nextdesc =
1277 &cd->wb_tx_chain[i + 1];
1278 }
1279 }
1280
1281 cd->wb_tx_free = &cd->wb_tx_chain[0];
1282 cd->wb_tx_tail = cd->wb_tx_head = NULL;
1283
1284 return(0);
1285 }
1286
1287
1288 /*
1289 * Initialize the RX descriptors and allocate mbufs for them. Note that
1290 * we arrange the descriptors in a closed ring, so that the last descriptor
1291 * points back to the first.
1292 */
1293 static int wb_list_rx_init(sc)
1294 struct wb_softc *sc;
1295 {
1296 struct wb_chain_data *cd;
1297 struct wb_list_data *ld;
1298 int i;
1299
1300 cd = &sc->wb_cdata;
1301 ld = sc->wb_ldata;
1302
1303 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1304 cd->wb_rx_chain[i].wb_ptr =
1305 (struct wb_desc *)&ld->wb_rx_list[i];
1306 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
1307 return(ENOBUFS);
1308 if (i == (WB_RX_LIST_CNT - 1)) {
1309 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
1310 ld->wb_rx_list[i].wb_next =
1311 vtophys(&ld->wb_rx_list[0]);
1312 } else {
1313 cd->wb_rx_chain[i].wb_nextdesc =
1314 &cd->wb_rx_chain[i + 1];
1315 ld->wb_rx_list[i].wb_next =
1316 vtophys(&ld->wb_rx_list[i + 1]);
1317 }
1318 }
1319
1320 cd->wb_rx_head = &cd->wb_rx_chain[0];
1321
1322 return(0);
1323 }
1324
1325 /*
1326 * Initialize an RX descriptor and attach an MBUF cluster.
1327 */
1328 static int wb_newbuf(sc, c, m)
1329 struct wb_softc *sc;
1330 struct wb_chain_onefrag *c;
1331 struct mbuf *m;
1332 {
1333 struct mbuf *m_new = NULL;
1334
1335 if (m == NULL) {
1336 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1337 if (m_new == NULL) {
1338 printf("wb%d: no memory for rx "
1339 "list -- packet dropped!\n", sc->wb_unit);
1340 return(ENOBUFS);
1341 }
1342
1343 MCLGET(m_new, M_DONTWAIT);
1344 if (!(m_new->m_flags & M_EXT)) {
1345 printf("wb%d: no memory for rx "
1346 "list -- packet dropped!\n", sc->wb_unit);
1347 m_freem(m_new);
1348 return(ENOBUFS);
1349 }
1350 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1351 } else {
1352 m_new = m;
1353 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1354 m_new->m_data = m_new->m_ext.ext_buf;
1355 }
1356
1357 m_adj(m_new, sizeof(u_int64_t));
1358
1359 c->wb_mbuf = m_new;
1360 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
1361 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | (MCLBYTES - 1);
1362 c->wb_ptr->wb_status = WB_RXSTAT;
1363
1364 return(0);
1365 }
1366
1367 /*
1368 * A frame has been uploaded: pass the resulting mbuf chain up to
1369 * the higher level protocols.
1370 */
1371 static void wb_rxeof(sc)
1372 struct wb_softc *sc;
1373 {
1374 struct ether_header *eh;
1375 struct mbuf *m;
1376 struct ifnet *ifp;
1377 struct wb_chain_onefrag *cur_rx;
1378 int total_len = 0;
1379 u_int32_t rxstat;
1380
1381 ifp = &sc->arpcom.ac_if;
1382
1383 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
1384 WB_RXSTAT_OWN)) {
1385 struct mbuf *m0 = NULL;
1386
1387 cur_rx = sc->wb_cdata.wb_rx_head;
1388 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
1389 m = cur_rx->wb_mbuf;
1390
1391 if ((rxstat & WB_RXSTAT_MIIERR)
1392 || WB_RXBYTES(cur_rx->wb_ptr->wb_status) == 0) {
1393 ifp->if_ierrors++;
1394 wb_reset(sc);
1395 printf("wb%x: receiver babbling: possible chip "
1396 "bug, forcing reset\n", sc->wb_unit);
1397 ifp->if_flags |= IFF_OACTIVE;
1398 ifp->if_timer = 2;
1399 return;
1400 }
1401
1402 if (rxstat & WB_RXSTAT_RXERR) {
1403 ifp->if_ierrors++;
1404 wb_newbuf(sc, cur_rx, m);
1405 continue;
1406 }
1407
1408 /* No errors; receive the packet. */
1409 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
1410
1411 /*
1412 * XXX The Winbond chip includes the CRC with every
1413 * received frame, and there's no way to turn this
1414 * behavior off (at least, I can't find anything in
1415 * the manual that explains how to do it) so we have
1416 * to trim off the CRC manually.
1417 */
1418 total_len -= ETHER_CRC_LEN;
1419
1420 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1421 total_len + ETHER_ALIGN, 0, ifp, NULL);
1422 wb_newbuf(sc, cur_rx, m);
1423 if (m0 == NULL) {
1424 ifp->if_ierrors++;
1425 continue;
1426 }
1427 m_adj(m0, ETHER_ALIGN);
1428 m = m0;
1429
1430 ifp->if_ipackets++;
1431 eh = mtod(m, struct ether_header *);
1432
1433 #ifdef BRIDGE
1434 if (do_bridge) {
1435 struct ifnet *bdg_ifp;
1436 bdg_ifp = bridge_in(m);
1437 if (bdg_ifp != BDG_LOCAL && bdg_ifp != BDG_DROP)
1438 bdg_forward(&m, bdg_ifp);
1439 if (((bdg_ifp != BDG_LOCAL) && (bdg_ifp != BDG_BCAST) &&
1440 (bdg_ifp != BDG_MCAST)) || bdg_ifp == BDG_DROP) {
1441 m_freem(m);
1442 continue;
1443 }
1444 }
1445 #endif
1446
1447 #if NBPFILTER > 0
1448 /*
1449 * Handle BPF listeners. Let the BPF user see the packet, but
1450 * don't pass it up to the ether_input() layer unless it's
1451 * a broadcast packet, multicast packet, matches our ethernet
1452 * address or the interface is in promiscuous mode.
1453 */
1454 if (ifp->if_bpf) {
1455 bpf_mtap(ifp, m);
1456 if (ifp->if_flags & IFF_PROMISC &&
1457 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
1458 ETHER_ADDR_LEN) &&
1459 (eh->ether_dhost[0] & 1) == 0)) {
1460 m_freem(m);
1461 continue;
1462 }
1463 }
1464 #endif
1465 /* Remove header from mbuf and pass it on. */
1466 m_adj(m, sizeof(struct ether_header));
1467 ether_input(ifp, eh, m);
1468 }
1469
1470 return;
1471 }
1472
1473 void wb_rxeoc(sc)
1474 struct wb_softc *sc;
1475 {
1476 wb_rxeof(sc);
1477
1478 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1479 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1480 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1481 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
1482 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1483
1484 return;
1485 }
1486
1487 /*
1488 * A frame was downloaded to the chip. It's safe for us to clean up
1489 * the list buffers.
1490 */
1491 static void wb_txeof(sc)
1492 struct wb_softc *sc;
1493 {
1494 struct wb_chain *cur_tx;
1495 struct ifnet *ifp;
1496
1497 ifp = &sc->arpcom.ac_if;
1498
1499 /* Clear the timeout timer. */
1500 ifp->if_timer = 0;
1501
1502 if (sc->wb_cdata.wb_tx_head == NULL)
1503 return;
1504
1505 /*
1506 * Go through our tx list and free mbufs for those
1507 * frames that have been transmitted.
1508 */
1509 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
1510 u_int32_t txstat;
1511
1512 cur_tx = sc->wb_cdata.wb_tx_head;
1513 txstat = WB_TXSTATUS(cur_tx);
1514
1515 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
1516 break;
1517
1518 if (txstat & WB_TXSTAT_TXERR) {
1519 ifp->if_oerrors++;
1520 if (txstat & WB_TXSTAT_ABORT)
1521 ifp->if_collisions++;
1522 if (txstat & WB_TXSTAT_LATECOLL)
1523 ifp->if_collisions++;
1524 }
1525
1526 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1527
1528 ifp->if_opackets++;
1529 m_freem(cur_tx->wb_mbuf);
1530 cur_tx->wb_mbuf = NULL;
1531
1532 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1533 sc->wb_cdata.wb_tx_head = NULL;
1534 sc->wb_cdata.wb_tx_tail = NULL;
1535 break;
1536 }
1537
1538 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1539 }
1540
1541 return;
1542 }
1543
1544 /*
1545 * TX 'end of channel' interrupt handler.
1546 */
1547 static void wb_txeoc(sc)
1548 struct wb_softc *sc;
1549 {
1550 struct ifnet *ifp;
1551
1552 ifp = &sc->arpcom.ac_if;
1553
1554 ifp->if_timer = 0;
1555
1556 if (sc->wb_cdata.wb_tx_head == NULL) {
1557 ifp->if_flags &= ~IFF_OACTIVE;
1558 sc->wb_cdata.wb_tx_tail = NULL;
1559 if (sc->wb_want_auto)
1560 wb_autoneg_mii(sc, WB_FLAG_SCHEDDELAY, 1);
1561 } else {
1562 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1563 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1564 ifp->if_timer = 5;
1565 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1566 }
1567 }
1568
1569 return;
1570 }
1571
1572 static void wb_intr(arg)
1573 void *arg;
1574 {
1575 struct wb_softc *sc;
1576 struct ifnet *ifp;
1577 u_int32_t status;
1578
1579 sc = arg;
1580 ifp = &sc->arpcom.ac_if;
1581
1582 if (!(ifp->if_flags & IFF_UP))
1583 return;
1584
1585 /* Disable interrupts. */
1586 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1587
1588 for (;;) {
1589
1590 status = CSR_READ_4(sc, WB_ISR);
1591 if (status)
1592 CSR_WRITE_4(sc, WB_ISR, status);
1593
1594 if ((status & WB_INTRS) == 0)
1595 break;
1596
1597 if (status & WB_ISR_RX_OK)
1598 wb_rxeof(sc);
1599
1600 if (status & WB_ISR_RX_IDLE)
1601 wb_rxeoc(sc);
1602
1603 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1604 ifp->if_ierrors++;
1605 #ifdef foo
1606 wb_stop(sc);
1607 wb_reset(sc);
1608 wb_init(sc);
1609 #endif
1610 }
1611
1612 if (status & WB_ISR_TX_OK)
1613 wb_txeof(sc);
1614
1615 if (status & WB_ISR_TX_NOBUF)
1616 wb_txeoc(sc);
1617
1618 if (status & WB_ISR_TX_IDLE) {
1619 wb_txeof(sc);
1620 if (sc->wb_cdata.wb_tx_head != NULL) {
1621 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1622 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1623 }
1624 }
1625
1626 if (status & WB_ISR_TX_UNDERRUN) {
1627 ifp->if_oerrors++;
1628 wb_txeof(sc);
1629 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1630 /* Jack up TX threshold */
1631 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1632 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1633 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1634 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1635 }
1636
1637 if (status & WB_ISR_BUS_ERR) {
1638 wb_reset(sc);
1639 wb_init(sc);
1640 }
1641
1642 }
1643
1644 /* Re-enable interrupts. */
1645 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1646
1647 if (ifp->if_snd.ifq_head != NULL) {
1648 wb_start(ifp);
1649 }
1650
1651 return;
1652 }
1653
1654 /*
1655 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1656 * pointers to the fragment pointers.
1657 */
1658 static int wb_encap(sc, c, m_head)
1659 struct wb_softc *sc;
1660 struct wb_chain *c;
1661 struct mbuf *m_head;
1662 {
1663 int frag = 0;
1664 struct wb_desc *f = NULL;
1665 int total_len;
1666 struct mbuf *m;
1667
1668 /*
1669 * Start packing the mbufs in this chain into
1670 * the fragment pointers. Stop when we run out
1671 * of fragments or hit the end of the mbuf chain.
1672 */
1673 m = m_head;
1674 total_len = 0;
1675
1676 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1677 if (m->m_len != 0) {
1678 if (frag == WB_MAXFRAGS)
1679 break;
1680 total_len += m->m_len;
1681 f = &c->wb_ptr->wb_frag[frag];
1682 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1683 if (frag == 0) {
1684 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1685 f->wb_status = 0;
1686 } else
1687 f->wb_status = WB_TXSTAT_OWN;
1688 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1689 f->wb_data = vtophys(mtod(m, vm_offset_t));
1690 frag++;
1691 }
1692 }
1693
1694 /*
1695 * Handle special case: we used up all 16 fragments,
1696 * but we have more mbufs left in the chain. Copy the
1697 * data into an mbuf cluster. Note that we don't
1698 * bother clearing the values in the other fragment
1699 * pointers/counters; it wouldn't gain us anything,
1700 * and would waste cycles.
1701 */
1702 if (m != NULL) {
1703 struct mbuf *m_new = NULL;
1704
1705 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1706 if (m_new == NULL) {
1707 printf("wb%d: no memory for tx list", sc->wb_unit);
1708 return(1);
1709 }
1710 if (m_head->m_pkthdr.len > MHLEN) {
1711 MCLGET(m_new, M_DONTWAIT);
1712 if (!(m_new->m_flags & M_EXT)) {
1713 m_freem(m_new);
1714 printf("wb%d: no memory for tx list",
1715 sc->wb_unit);
1716 return(1);
1717 }
1718 }
1719 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1720 mtod(m_new, caddr_t));
1721 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1722 m_freem(m_head);
1723 m_head = m_new;
1724 f = &c->wb_ptr->wb_frag[0];
1725 f->wb_status = 0;
1726 f->wb_data = vtophys(mtod(m_new, caddr_t));
1727 f->wb_ctl = total_len = m_new->m_len;
1728 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1729 frag = 1;
1730 }
1731
1732 if (total_len < WB_MIN_FRAMELEN) {
1733 f = &c->wb_ptr->wb_frag[frag];
1734 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1735 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1736 f->wb_ctl |= WB_TXCTL_TLINK;
1737 f->wb_status = WB_TXSTAT_OWN;
1738 frag++;
1739 }
1740
1741 c->wb_mbuf = m_head;
1742 c->wb_lastdesc = frag - 1;
1743 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1744 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1745
1746 return(0);
1747 }
1748
1749 /*
1750 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1751 * to the mbuf data regions directly in the transmit lists. We also save a
1752 * copy of the pointers since the transmit list fragment pointers are
1753 * physical addresses.
1754 */
1755
1756 static void wb_start(ifp)
1757 struct ifnet *ifp;
1758 {
1759 struct wb_softc *sc;
1760 struct mbuf *m_head = NULL;
1761 struct wb_chain *cur_tx = NULL, *start_tx;
1762
1763 sc = ifp->if_softc;
1764
1765 if (sc->wb_autoneg) {
1766 sc->wb_tx_pend = 1;
1767 return;
1768 }
1769
1770 /*
1771 * Check for an available queue slot. If there are none,
1772 * punt.
1773 */
1774 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1775 ifp->if_flags |= IFF_OACTIVE;
1776 return;
1777 }
1778
1779 start_tx = sc->wb_cdata.wb_tx_free;
1780
1781 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1782 IF_DEQUEUE(&ifp->if_snd, m_head);
1783 if (m_head == NULL)
1784 break;
1785
1786 /* Pick a descriptor off the free list. */
1787 cur_tx = sc->wb_cdata.wb_tx_free;
1788 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1789
1790 /* Pack the data into the descriptor. */
1791 wb_encap(sc, cur_tx, m_head);
1792
1793 if (cur_tx != start_tx)
1794 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1795
1796 #if NBPFILTER > 0
1797 /*
1798 * If there's a BPF listener, bounce a copy of this frame
1799 * to him.
1800 */
1801 if (ifp->if_bpf)
1802 bpf_mtap(ifp, cur_tx->wb_mbuf);
1803 #endif
1804 }
1805
1806 /*
1807 * If there are no packets queued, bail.
1808 */
1809 if (cur_tx == NULL)
1810 return;
1811
1812 /*
1813 * Place the request for the upload interrupt
1814 * in the last descriptor in the chain. This way, if
1815 * we're chaining several packets at once, we'll only
1816 * get an interupt once for the whole chain rather than
1817 * once for each packet.
1818 */
1819 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1820 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1821 sc->wb_cdata.wb_tx_tail = cur_tx;
1822
1823 if (sc->wb_cdata.wb_tx_head == NULL) {
1824 sc->wb_cdata.wb_tx_head = start_tx;
1825 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1826 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1827 } else {
1828 /*
1829 * We need to distinguish between the case where
1830 * the own bit is clear because the chip cleared it
1831 * and where the own bit is clear because we haven't
1832 * set it yet. The magic value WB_UNSET is just some
1833 * ramdomly chosen number which doesn't have the own
1834 * bit set. When we actually transmit the frame, the
1835 * status word will have _only_ the own bit set, so
1836 * the txeoc handler will be able to tell if it needs
1837 * to initiate another transmission to flush out pending
1838 * frames.
1839 */
1840 WB_TXOWN(start_tx) = WB_UNSENT;
1841 }
1842
1843 /*
1844 * Set a timeout in case the chip goes out to lunch.
1845 */
1846 ifp->if_timer = 5;
1847
1848 return;
1849 }
1850
1851 static void wb_init(xsc)
1852 void *xsc;
1853 {
1854 struct wb_softc *sc = xsc;
1855 struct ifnet *ifp = &sc->arpcom.ac_if;
1856 int s, i;
1857 u_int16_t phy_bmcr = 0;
1858
1859 if (sc->wb_autoneg)
1860 return;
1861
1862 s = splimp();
1863
1864 if (sc->wb_pinfo != NULL)
1865 phy_bmcr = wb_phy_readreg(sc, PHY_BMCR);
1866
1867 /*
1868 * Cancel pending I/O and free all RX/TX buffers.
1869 */
1870 wb_stop(sc);
1871 wb_reset(sc);
1872
1873 sc->wb_txthresh = WB_TXTHRESH_INIT;
1874
1875 /*
1876 * Set cache alignment and burst length.
1877 */
1878 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1879 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1880 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1881
1882 /* This doesn't tend to work too well at 100Mbps. */
1883 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1884
1885 wb_setcfg(sc, phy_bmcr);
1886
1887 /* Init our MAC address */
1888 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1889 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]);
1890 }
1891
1892 /* Init circular RX list. */
1893 if (wb_list_rx_init(sc) == ENOBUFS) {
1894 printf("wb%d: initialization failed: no "
1895 "memory for rx buffers\n", sc->wb_unit);
1896 wb_stop(sc);
1897 (void)splx(s);
1898 return;
1899 }
1900
1901 /* Init TX descriptors. */
1902 wb_list_tx_init(sc);
1903
1904 /* If we want promiscuous mode, set the allframes bit. */
1905 if (ifp->if_flags & IFF_PROMISC) {
1906 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1907 } else {
1908 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1909 }
1910
1911 /*
1912 * Set capture broadcast bit to capture broadcast frames.
1913 */
1914 if (ifp->if_flags & IFF_BROADCAST) {
1915 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1916 } else {
1917 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1918 }
1919
1920 /*
1921 * Program the multicast filter, if necessary.
1922 */
1923 wb_setmulti(sc);
1924
1925 /*
1926 * Load the address of the RX list.
1927 */
1928 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1929 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1930
1931 /*
1932 * Enable interrupts.
1933 */
1934 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1935 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1936
1937 /* Enable receiver and transmitter. */
1938 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1939 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1940
1941 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1942 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1943 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1944
1945 /* Restore state of BMCR */
1946 if (sc->wb_pinfo != NULL)
1947 wb_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1948
1949 ifp->if_flags |= IFF_RUNNING;
1950 ifp->if_flags &= ~IFF_OACTIVE;
1951
1952 (void)splx(s);
1953
1954 return;
1955 }
1956
1957 /*
1958 * Set media options.
1959 */
1960 static int wb_ifmedia_upd(ifp)
1961 struct ifnet *ifp;
1962 {
1963 struct wb_softc *sc;
1964 struct ifmedia *ifm;
1965
1966 sc = ifp->if_softc;
1967 ifm = &sc->ifmedia;
1968
1969 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1970 return(EINVAL);
1971
1972 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1973 wb_autoneg_mii(sc, WB_FLAG_SCHEDDELAY, 1);
1974 else
1975 wb_setmode_mii(sc, ifm->ifm_media);
1976
1977 return(0);
1978 }
1979
1980 /*
1981 * Report current media status.
1982 */
1983 static void wb_ifmedia_sts(ifp, ifmr)
1984 struct ifnet *ifp;
1985 struct ifmediareq *ifmr;
1986 {
1987 struct wb_softc *sc;
1988 u_int16_t advert = 0, ability = 0;
1989
1990 sc = ifp->if_softc;
1991
1992 ifmr->ifm_active = IFM_ETHER;
1993
1994 if (!(wb_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1995 if (wb_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1996 ifmr->ifm_active = IFM_ETHER|IFM_100_TX;
1997 else
1998 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
1999 if (wb_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
2000 ifmr->ifm_active |= IFM_FDX;
2001 else
2002 ifmr->ifm_active |= IFM_HDX;
2003 return;
2004 }
2005
2006 ability = wb_phy_readreg(sc, PHY_LPAR);
2007 advert = wb_phy_readreg(sc, PHY_ANAR);
2008 if (advert & PHY_ANAR_100BT4 &&
2009 ability & PHY_ANAR_100BT4) {
2010 ifmr->ifm_active = IFM_ETHER|IFM_100_T4;
2011 } else if (advert & PHY_ANAR_100BTXFULL &&
2012 ability & PHY_ANAR_100BTXFULL) {
2013 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX;
2014 } else if (advert & PHY_ANAR_100BTXHALF &&
2015 ability & PHY_ANAR_100BTXHALF) {
2016 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX;
2017 } else if (advert & PHY_ANAR_10BTFULL &&
2018 ability & PHY_ANAR_10BTFULL) {
2019 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX;
2020 } else if (advert & PHY_ANAR_10BTHALF &&
2021 ability & PHY_ANAR_10BTHALF) {
2022 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX;
2023 }
2024
2025 return;
2026 }
2027
2028 static int wb_ioctl(ifp, command, data)
2029 struct ifnet *ifp;
2030 u_long command;
2031 caddr_t data;
2032 {
2033 struct wb_softc *sc = ifp->if_softc;
2034 struct ifreq *ifr = (struct ifreq *) data;
2035 int s, error = 0;
2036
2037 s = splimp();
2038
2039 switch(command) {
2040 case SIOCSIFADDR:
2041 case SIOCGIFADDR:
2042 case SIOCSIFMTU:
2043 error = ether_ioctl(ifp, command, data);
2044 break;
2045 case SIOCSIFFLAGS:
2046 if (ifp->if_flags & IFF_UP) {
2047 wb_init(sc);
2048 } else {
2049 if (ifp->if_flags & IFF_RUNNING)
2050 wb_stop(sc);
2051 }
2052 error = 0;
2053 break;
2054 case SIOCADDMULTI:
2055 case SIOCDELMULTI:
2056 wb_setmulti(sc);
2057 error = 0;
2058 break;
2059 case SIOCGIFMEDIA:
2060 case SIOCSIFMEDIA:
2061 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2062 break;
2063 default:
2064 error = EINVAL;
2065 break;
2066 }
2067
2068 (void)splx(s);
2069
2070 return(error);
2071 }
2072
2073 static void wb_watchdog(ifp)
2074 struct ifnet *ifp;
2075 {
2076 struct wb_softc *sc;
2077
2078 sc = ifp->if_softc;
2079
2080 if (sc->wb_autoneg) {
2081 wb_autoneg_mii(sc, WB_FLAG_DELAYTIMEO, 1);
2082 return;
2083 }
2084
2085 ifp->if_oerrors++;
2086 printf("wb%d: watchdog timeout\n", sc->wb_unit);
2087
2088 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
2089 printf("wb%d: no carrier - transceiver cable problem?\n",
2090 sc->wb_unit);
2091
2092 wb_stop(sc);
2093 wb_reset(sc);
2094 wb_init(sc);
2095
2096 if (ifp->if_snd.ifq_head != NULL)
2097 wb_start(ifp);
2098
2099 return;
2100 }
2101
2102 /*
2103 * Stop the adapter and free any mbufs allocated to the
2104 * RX and TX lists.
2105 */
2106 static void wb_stop(sc)
2107 struct wb_softc *sc;
2108 {
2109 register int i;
2110 struct ifnet *ifp;
2111
2112 ifp = &sc->arpcom.ac_if;
2113 ifp->if_timer = 0;
2114
2115 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
2116 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
2117 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
2118 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
2119
2120 /*
2121 * Free data in the RX lists.
2122 */
2123 for (i = 0; i < WB_RX_LIST_CNT; i++) {
2124 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
2125 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
2126 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
2127 }
2128 }
2129 bzero((char *)&sc->wb_ldata->wb_rx_list,
2130 sizeof(sc->wb_ldata->wb_rx_list));
2131
2132 /*
2133 * Free the TX list buffers.
2134 */
2135 for (i = 0; i < WB_TX_LIST_CNT; i++) {
2136 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
2137 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
2138 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
2139 }
2140 }
2141
2142 bzero((char *)&sc->wb_ldata->wb_tx_list,
2143 sizeof(sc->wb_ldata->wb_tx_list));
2144
2145 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2146
2147 return;
2148 }
2149
2150 /*
2151 * Stop all chip I/O so that the kernel's probe routines don't
2152 * get confused by errant DMAs when rebooting.
2153 */
2154 static void wb_shutdown(howto, arg)
2155 int howto;
2156 void *arg;
2157 {
2158 struct wb_softc *sc = (struct wb_softc *)arg;
2159
2160 wb_stop(sc);
2161
2162 return;
2163 }
2164
2165 static struct pci_device wb_device = {
2166 "wb",
2167 wb_probe,
2168 wb_attach,
2169 &wb_count,
2170 NULL
2171 };
2172 DATA_SET(pcidevice_set, wb_device);
Cache object: 44b0aab3738708bfc18953090714d8fa
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