Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_wb.c
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1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * Winbond fast ethernet PCI NIC driver 37 * 38 * Supports various cheap network adapters based on the Winbond W89C840F 39 * fast ethernet controller chip. This includes adapters manufactured by 40 * Winbond itself and some made by Linksys. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86 #include "opt_bdg.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/queue.h> 96 97 #include <net/if.h> 98 #include <net/if_arp.h> 99 #include <net/ethernet.h> 100 #include <net/if_dl.h> 101 #include <net/if_media.h> 102 103 #include <net/bpf.h> 104 105 #include <vm/vm.h> /* for vtophys */ 106 #include <vm/pmap.h> /* for vtophys */ 107 #include <machine/clock.h> /* for DELAY */ 108 #include <machine/bus_memio.h> 109 #include <machine/bus_pio.h> 110 #include <machine/bus.h> 111 #include <machine/resource.h> 112 #include <sys/bus.h> 113 #include <sys/rman.h> 114 115 #include <pci/pcireg.h> 116 #include <pci/pcivar.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 121 /* "controller miibus0" required. See GENERIC if you get errors here. */ 122 #include "miibus_if.h" 123 124 #define WB_USEIOSPACE 125 126 #include <pci/if_wbreg.h> 127 128 #ifndef lint 129 static const char rcsid[] = 130 "$FreeBSD$"; 131 #endif 132 133 /* 134 * Various supported device vendors/types and their names. 135 */ 136 static struct wb_type wb_devs[] = { 137 { WB_VENDORID, WB_DEVICEID_840F, 138 "Winbond W89C840F 10/100BaseTX" }, 139 { CP_VENDORID, CP_DEVICEID_RL100, 140 "Compex RL100-ATX 10/100baseTX" }, 141 { 0, 0, NULL } 142 }; 143 144 static int wb_probe __P((device_t)); 145 static int wb_attach __P((device_t)); 146 static int wb_detach __P((device_t)); 147 148 static void wb_bfree __P((caddr_t, u_int)); 149 static int wb_newbuf __P((struct wb_softc *, 150 struct wb_chain_onefrag *, 151 struct mbuf *)); 152 static int wb_encap __P((struct wb_softc *, struct wb_chain *, 153 struct mbuf *)); 154 155 static void wb_rxeof __P((struct wb_softc *)); 156 static void wb_rxeoc __P((struct wb_softc *)); 157 static void wb_txeof __P((struct wb_softc *)); 158 static void wb_txeoc __P((struct wb_softc *)); 159 static void wb_intr __P((void *)); 160 static void wb_tick __P((void *)); 161 static void wb_start __P((struct ifnet *)); 162 static int wb_ioctl __P((struct ifnet *, u_long, caddr_t)); 163 static void wb_init __P((void *)); 164 static void wb_stop __P((struct wb_softc *)); 165 static void wb_watchdog __P((struct ifnet *)); 166 static void wb_shutdown __P((device_t)); 167 static int wb_ifmedia_upd __P((struct ifnet *)); 168 static void wb_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 169 170 static void wb_eeprom_putbyte __P((struct wb_softc *, int)); 171 static void wb_eeprom_getword __P((struct wb_softc *, int, u_int16_t *)); 172 static void wb_read_eeprom __P((struct wb_softc *, caddr_t, int, 173 int, int)); 174 static void wb_mii_sync __P((struct wb_softc *)); 175 static void wb_mii_send __P((struct wb_softc *, u_int32_t, int)); 176 static int wb_mii_readreg __P((struct wb_softc *, struct wb_mii_frame *)); 177 static int wb_mii_writereg __P((struct wb_softc *, struct wb_mii_frame *)); 178 179 static void wb_setcfg __P((struct wb_softc *, u_int32_t)); 180 static u_int8_t wb_calchash __P((caddr_t)); 181 static void wb_setmulti __P((struct wb_softc *)); 182 static void wb_reset __P((struct wb_softc *)); 183 static void wb_fixmedia __P((struct wb_softc *)); 184 static int wb_list_rx_init __P((struct wb_softc *)); 185 static int wb_list_tx_init __P((struct wb_softc *)); 186 187 static int wb_miibus_readreg __P((device_t, int, int)); 188 static int wb_miibus_writereg __P((device_t, int, int, int)); 189 static void wb_miibus_statchg __P((device_t)); 190 191 #ifdef WB_USEIOSPACE 192 #define WB_RES SYS_RES_IOPORT 193 #define WB_RID WB_PCI_LOIO 194 #else 195 #define WB_RES SYS_RES_MEMORY 196 #define WB_RID WB_PCI_LOMEM 197 #endif 198 199 static device_method_t wb_methods[] = { 200 /* Device interface */ 201 DEVMETHOD(device_probe, wb_probe), 202 DEVMETHOD(device_attach, wb_attach), 203 DEVMETHOD(device_detach, wb_detach), 204 DEVMETHOD(device_shutdown, wb_shutdown), 205 206 /* bus interface, for miibus */ 207 DEVMETHOD(bus_print_child, bus_generic_print_child), 208 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 209 210 /* MII interface */ 211 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 212 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 213 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 214 { 0, 0 } 215 }; 216 217 static driver_t wb_driver = { 218 "wb", 219 wb_methods, 220 sizeof(struct wb_softc) 221 }; 222 223 static devclass_t wb_devclass; 224 225 DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0); 226 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 227 228 #define WB_SETBIT(sc, reg, x) \ 229 CSR_WRITE_4(sc, reg, \ 230 CSR_READ_4(sc, reg) | x) 231 232 #define WB_CLRBIT(sc, reg, x) \ 233 CSR_WRITE_4(sc, reg, \ 234 CSR_READ_4(sc, reg) & ~x) 235 236 #define SIO_SET(x) \ 237 CSR_WRITE_4(sc, WB_SIO, \ 238 CSR_READ_4(sc, WB_SIO) | x) 239 240 #define SIO_CLR(x) \ 241 CSR_WRITE_4(sc, WB_SIO, \ 242 CSR_READ_4(sc, WB_SIO) & ~x) 243 244 /* 245 * Send a read command and address to the EEPROM, check for ACK. 246 */ 247 static void wb_eeprom_putbyte(sc, addr) 248 struct wb_softc *sc; 249 int addr; 250 { 251 register int d, i; 252 253 d = addr | WB_EECMD_READ; 254 255 /* 256 * Feed in each bit and stobe the clock. 257 */ 258 for (i = 0x400; i; i >>= 1) { 259 if (d & i) { 260 SIO_SET(WB_SIO_EE_DATAIN); 261 } else { 262 SIO_CLR(WB_SIO_EE_DATAIN); 263 } 264 DELAY(100); 265 SIO_SET(WB_SIO_EE_CLK); 266 DELAY(150); 267 SIO_CLR(WB_SIO_EE_CLK); 268 DELAY(100); 269 } 270 271 return; 272 } 273 274 /* 275 * Read a word of data stored in the EEPROM at address 'addr.' 276 */ 277 static void wb_eeprom_getword(sc, addr, dest) 278 struct wb_softc *sc; 279 int addr; 280 u_int16_t *dest; 281 { 282 register int i; 283 u_int16_t word = 0; 284 285 /* Enter EEPROM access mode. */ 286 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 287 288 /* 289 * Send address of word we want to read. 290 */ 291 wb_eeprom_putbyte(sc, addr); 292 293 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 294 295 /* 296 * Start reading bits from EEPROM. 297 */ 298 for (i = 0x8000; i; i >>= 1) { 299 SIO_SET(WB_SIO_EE_CLK); 300 DELAY(100); 301 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 302 word |= i; 303 SIO_CLR(WB_SIO_EE_CLK); 304 DELAY(100); 305 } 306 307 /* Turn off EEPROM access mode. */ 308 CSR_WRITE_4(sc, WB_SIO, 0); 309 310 *dest = word; 311 312 return; 313 } 314 315 /* 316 * Read a sequence of words from the EEPROM. 317 */ 318 static void wb_read_eeprom(sc, dest, off, cnt, swap) 319 struct wb_softc *sc; 320 caddr_t dest; 321 int off; 322 int cnt; 323 int swap; 324 { 325 int i; 326 u_int16_t word = 0, *ptr; 327 328 for (i = 0; i < cnt; i++) { 329 wb_eeprom_getword(sc, off + i, &word); 330 ptr = (u_int16_t *)(dest + (i * 2)); 331 if (swap) 332 *ptr = ntohs(word); 333 else 334 *ptr = word; 335 } 336 337 return; 338 } 339 340 /* 341 * Sync the PHYs by setting data bit and strobing the clock 32 times. 342 */ 343 static void wb_mii_sync(sc) 344 struct wb_softc *sc; 345 { 346 register int i; 347 348 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 349 350 for (i = 0; i < 32; i++) { 351 SIO_SET(WB_SIO_MII_CLK); 352 DELAY(1); 353 SIO_CLR(WB_SIO_MII_CLK); 354 DELAY(1); 355 } 356 357 return; 358 } 359 360 /* 361 * Clock a series of bits through the MII. 362 */ 363 static void wb_mii_send(sc, bits, cnt) 364 struct wb_softc *sc; 365 u_int32_t bits; 366 int cnt; 367 { 368 int i; 369 370 SIO_CLR(WB_SIO_MII_CLK); 371 372 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 373 if (bits & i) { 374 SIO_SET(WB_SIO_MII_DATAIN); 375 } else { 376 SIO_CLR(WB_SIO_MII_DATAIN); 377 } 378 DELAY(1); 379 SIO_CLR(WB_SIO_MII_CLK); 380 DELAY(1); 381 SIO_SET(WB_SIO_MII_CLK); 382 } 383 } 384 385 /* 386 * Read an PHY register through the MII. 387 */ 388 static int wb_mii_readreg(sc, frame) 389 struct wb_softc *sc; 390 struct wb_mii_frame *frame; 391 392 { 393 int i, ack, s; 394 395 s = splimp(); 396 397 /* 398 * Set up frame for RX. 399 */ 400 frame->mii_stdelim = WB_MII_STARTDELIM; 401 frame->mii_opcode = WB_MII_READOP; 402 frame->mii_turnaround = 0; 403 frame->mii_data = 0; 404 405 CSR_WRITE_4(sc, WB_SIO, 0); 406 407 /* 408 * Turn on data xmit. 409 */ 410 SIO_SET(WB_SIO_MII_DIR); 411 412 wb_mii_sync(sc); 413 414 /* 415 * Send command/address info. 416 */ 417 wb_mii_send(sc, frame->mii_stdelim, 2); 418 wb_mii_send(sc, frame->mii_opcode, 2); 419 wb_mii_send(sc, frame->mii_phyaddr, 5); 420 wb_mii_send(sc, frame->mii_regaddr, 5); 421 422 /* Idle bit */ 423 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 424 DELAY(1); 425 SIO_SET(WB_SIO_MII_CLK); 426 DELAY(1); 427 428 /* Turn off xmit. */ 429 SIO_CLR(WB_SIO_MII_DIR); 430 /* Check for ack */ 431 SIO_CLR(WB_SIO_MII_CLK); 432 DELAY(1); 433 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 434 SIO_SET(WB_SIO_MII_CLK); 435 DELAY(1); 436 SIO_CLR(WB_SIO_MII_CLK); 437 DELAY(1); 438 SIO_SET(WB_SIO_MII_CLK); 439 DELAY(1); 440 441 /* 442 * Now try reading data bits. If the ack failed, we still 443 * need to clock through 16 cycles to keep the PHY(s) in sync. 444 */ 445 if (ack) { 446 for(i = 0; i < 16; i++) { 447 SIO_CLR(WB_SIO_MII_CLK); 448 DELAY(1); 449 SIO_SET(WB_SIO_MII_CLK); 450 DELAY(1); 451 } 452 goto fail; 453 } 454 455 for (i = 0x8000; i; i >>= 1) { 456 SIO_CLR(WB_SIO_MII_CLK); 457 DELAY(1); 458 if (!ack) { 459 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 460 frame->mii_data |= i; 461 DELAY(1); 462 } 463 SIO_SET(WB_SIO_MII_CLK); 464 DELAY(1); 465 } 466 467 fail: 468 469 SIO_CLR(WB_SIO_MII_CLK); 470 DELAY(1); 471 SIO_SET(WB_SIO_MII_CLK); 472 DELAY(1); 473 474 splx(s); 475 476 if (ack) 477 return(1); 478 return(0); 479 } 480 481 /* 482 * Write to a PHY register through the MII. 483 */ 484 static int wb_mii_writereg(sc, frame) 485 struct wb_softc *sc; 486 struct wb_mii_frame *frame; 487 488 { 489 int s; 490 491 s = splimp(); 492 /* 493 * Set up frame for TX. 494 */ 495 496 frame->mii_stdelim = WB_MII_STARTDELIM; 497 frame->mii_opcode = WB_MII_WRITEOP; 498 frame->mii_turnaround = WB_MII_TURNAROUND; 499 500 /* 501 * Turn on data output. 502 */ 503 SIO_SET(WB_SIO_MII_DIR); 504 505 wb_mii_sync(sc); 506 507 wb_mii_send(sc, frame->mii_stdelim, 2); 508 wb_mii_send(sc, frame->mii_opcode, 2); 509 wb_mii_send(sc, frame->mii_phyaddr, 5); 510 wb_mii_send(sc, frame->mii_regaddr, 5); 511 wb_mii_send(sc, frame->mii_turnaround, 2); 512 wb_mii_send(sc, frame->mii_data, 16); 513 514 /* Idle bit. */ 515 SIO_SET(WB_SIO_MII_CLK); 516 DELAY(1); 517 SIO_CLR(WB_SIO_MII_CLK); 518 DELAY(1); 519 520 /* 521 * Turn off xmit. 522 */ 523 SIO_CLR(WB_SIO_MII_DIR); 524 525 splx(s); 526 527 return(0); 528 } 529 530 static int wb_miibus_readreg(dev, phy, reg) 531 device_t dev; 532 int phy, reg; 533 { 534 struct wb_softc *sc; 535 struct wb_mii_frame frame; 536 537 sc = device_get_softc(dev); 538 539 bzero((char *)&frame, sizeof(frame)); 540 541 frame.mii_phyaddr = phy; 542 frame.mii_regaddr = reg; 543 wb_mii_readreg(sc, &frame); 544 545 return(frame.mii_data); 546 } 547 548 static int wb_miibus_writereg(dev, phy, reg, data) 549 device_t dev; 550 int phy, reg, data; 551 { 552 struct wb_softc *sc; 553 struct wb_mii_frame frame; 554 555 sc = device_get_softc(dev); 556 557 bzero((char *)&frame, sizeof(frame)); 558 559 frame.mii_phyaddr = phy; 560 frame.mii_regaddr = reg; 561 frame.mii_data = data; 562 563 wb_mii_writereg(sc, &frame); 564 565 return(0); 566 } 567 568 static void wb_miibus_statchg(dev) 569 device_t dev; 570 { 571 struct wb_softc *sc; 572 struct mii_data *mii; 573 574 sc = device_get_softc(dev); 575 mii = device_get_softc(sc->wb_miibus); 576 wb_setcfg(sc, mii->mii_media_active); 577 578 return; 579 } 580 581 static u_int8_t wb_calchash(addr) 582 caddr_t addr; 583 { 584 u_int32_t crc, carry; 585 int i, j; 586 u_int8_t c; 587 588 /* Compute CRC for the address value. */ 589 crc = 0xFFFFFFFF; /* initial value */ 590 591 for (i = 0; i < 6; i++) { 592 c = *(addr + i); 593 for (j = 0; j < 8; j++) { 594 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 595 crc <<= 1; 596 c >>= 1; 597 if (carry) 598 crc = (crc ^ 0x04c11db6) | carry; 599 } 600 } 601 602 /* 603 * return the filter bit position 604 * Note: I arrived at the following nonsense 605 * through experimentation. It's not the usual way to 606 * generate the bit position but it's the only thing 607 * I could come up with that works. 608 */ 609 return(~(crc >> 26) & 0x0000003F); 610 } 611 612 /* 613 * Program the 64-bit multicast hash filter. 614 */ 615 static void wb_setmulti(sc) 616 struct wb_softc *sc; 617 { 618 struct ifnet *ifp; 619 int h = 0; 620 u_int32_t hashes[2] = { 0, 0 }; 621 struct ifmultiaddr *ifma; 622 u_int32_t rxfilt; 623 int mcnt = 0; 624 625 ifp = &sc->arpcom.ac_if; 626 627 rxfilt = CSR_READ_4(sc, WB_NETCFG); 628 629 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 630 rxfilt |= WB_NETCFG_RX_MULTI; 631 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 632 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 633 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 634 return; 635 } 636 637 /* first, zot all the existing hash bits */ 638 CSR_WRITE_4(sc, WB_MAR0, 0); 639 CSR_WRITE_4(sc, WB_MAR1, 0); 640 641 /* now program new ones */ 642 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 643 ifma = ifma->ifma_link.le_next) { 644 if (ifma->ifma_addr->sa_family != AF_LINK) 645 continue; 646 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 647 if (h < 32) 648 hashes[0] |= (1 << h); 649 else 650 hashes[1] |= (1 << (h - 32)); 651 mcnt++; 652 } 653 654 if (mcnt) 655 rxfilt |= WB_NETCFG_RX_MULTI; 656 else 657 rxfilt &= ~WB_NETCFG_RX_MULTI; 658 659 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 660 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 661 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 662 663 return; 664 } 665 666 /* 667 * The Winbond manual states that in order to fiddle with the 668 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 669 * first have to put the transmit and/or receive logic in the idle state. 670 */ 671 static void wb_setcfg(sc, media) 672 struct wb_softc *sc; 673 u_int32_t media; 674 { 675 int i, restart = 0; 676 677 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 678 restart = 1; 679 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 680 681 for (i = 0; i < WB_TIMEOUT; i++) { 682 DELAY(10); 683 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 684 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 685 break; 686 } 687 688 if (i == WB_TIMEOUT) 689 printf("wb%d: failed to force tx and " 690 "rx to idle state\n", sc->wb_unit); 691 } 692 693 if (IFM_SUBTYPE(media) == IFM_10_T) 694 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 695 else 696 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 697 698 if ((media & IFM_GMASK) == IFM_FDX) 699 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 700 else 701 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 702 703 if (restart) 704 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 705 706 return; 707 } 708 709 static void wb_reset(sc) 710 struct wb_softc *sc; 711 { 712 register int i; 713 struct mii_data *mii; 714 715 CSR_WRITE_4(sc, WB_NETCFG, 0); 716 CSR_WRITE_4(sc, WB_BUSCTL, 0); 717 CSR_WRITE_4(sc, WB_TXADDR, 0); 718 CSR_WRITE_4(sc, WB_RXADDR, 0); 719 720 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 721 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 722 723 for (i = 0; i < WB_TIMEOUT; i++) { 724 DELAY(10); 725 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 726 break; 727 } 728 if (i == WB_TIMEOUT) 729 printf("wb%d: reset never completed!\n", sc->wb_unit); 730 731 /* Wait a little while for the chip to get its brains in order. */ 732 DELAY(1000); 733 734 if (sc->wb_miibus == NULL) 735 return; 736 737 mii = device_get_softc(sc->wb_miibus); 738 if (mii == NULL) 739 return; 740 741 if (mii->mii_instance) { 742 struct mii_softc *miisc; 743 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 744 miisc = LIST_NEXT(miisc, mii_list)) 745 mii_phy_reset(miisc); 746 } 747 748 return; 749 } 750 751 static void wb_fixmedia(sc) 752 struct wb_softc *sc; 753 { 754 struct mii_data *mii = NULL; 755 struct ifnet *ifp; 756 u_int32_t media; 757 758 if (sc->wb_miibus == NULL) 759 return; 760 761 mii = device_get_softc(sc->wb_miibus); 762 ifp = &sc->arpcom.ac_if; 763 764 mii_pollstat(mii); 765 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 766 media = mii->mii_media_active & ~IFM_10_T; 767 media |= IFM_100_TX; 768 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 769 media = mii->mii_media_active & ~IFM_100_TX; 770 media |= IFM_10_T; 771 } else 772 return; 773 774 ifmedia_set(&mii->mii_media, media); 775 776 return; 777 } 778 779 /* 780 * Probe for a Winbond chip. Check the PCI vendor and device 781 * IDs against our list and return a device name if we find a match. 782 */ 783 static int wb_probe(dev) 784 device_t dev; 785 { 786 struct wb_type *t; 787 788 t = wb_devs; 789 790 while(t->wb_name != NULL) { 791 if ((pci_get_vendor(dev) == t->wb_vid) && 792 (pci_get_device(dev) == t->wb_did)) { 793 device_set_desc(dev, t->wb_name); 794 return(0); 795 } 796 t++; 797 } 798 799 return(ENXIO); 800 } 801 802 /* 803 * Attach the interface. Allocate softc structures, do ifmedia 804 * setup and ethernet/BPF attach. 805 */ 806 static int wb_attach(dev) 807 device_t dev; 808 { 809 int s; 810 u_char eaddr[ETHER_ADDR_LEN]; 811 u_int32_t command; 812 struct wb_softc *sc; 813 struct ifnet *ifp; 814 int unit, error = 0, rid; 815 816 s = splimp(); 817 818 sc = device_get_softc(dev); 819 unit = device_get_unit(dev); 820 821 /* 822 * Handle power management nonsense. 823 */ 824 825 command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF; 826 if (command == 0x01) { 827 828 command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4); 829 if (command & WB_PSTATE_MASK) { 830 u_int32_t iobase, membase, irq; 831 832 /* Save important PCI config data. */ 833 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 834 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 835 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 836 837 /* Reset the power state. */ 838 printf("wb%d: chip is in D%d power mode " 839 "-- setting to D0\n", unit, command & WB_PSTATE_MASK); 840 command &= 0xFFFFFFFC; 841 pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4); 842 843 /* Restore PCI config data. */ 844 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 845 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 846 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 847 } 848 } 849 850 /* 851 * Map control/status registers. 852 */ 853 command = pci_read_config(dev, PCIR_COMMAND, 4); 854 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 855 pci_write_config(dev, PCIR_COMMAND, command, 4); 856 command = pci_read_config(dev, PCIR_COMMAND, 4); 857 858 #ifdef WB_USEIOSPACE 859 if (!(command & PCIM_CMD_PORTEN)) { 860 printf("wb%d: failed to enable I/O ports!\n", unit); 861 error = ENXIO; 862 goto fail; 863 } 864 #else 865 if (!(command & PCIM_CMD_MEMEN)) { 866 printf("wb%d: failed to enable memory mapping!\n", unit); 867 error = ENXIO; 868 goto fail; 869 } 870 #endif 871 872 rid = WB_RID; 873 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 874 0, ~0, 1, RF_ACTIVE); 875 876 if (sc->wb_res == NULL) { 877 printf("wb%d: couldn't map ports/memory\n", unit); 878 error = ENXIO; 879 goto fail; 880 } 881 882 sc->wb_btag = rman_get_bustag(sc->wb_res); 883 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 884 885 /* Allocate interrupt */ 886 rid = 0; 887 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 888 RF_SHAREABLE | RF_ACTIVE); 889 890 if (sc->wb_irq == NULL) { 891 printf("wb%d: couldn't map interrupt\n", unit); 892 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 893 error = ENXIO; 894 goto fail; 895 } 896 897 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 898 wb_intr, sc, &sc->wb_intrhand); 899 900 if (error) { 901 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 902 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 903 printf("wb%d: couldn't set up irq\n", unit); 904 goto fail; 905 } 906 907 /* Save the cache line size. */ 908 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 909 910 /* Reset the adapter. */ 911 wb_reset(sc); 912 913 /* 914 * Get station address from the EEPROM. 915 */ 916 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 917 918 /* 919 * A Winbond chip was detected. Inform the world. 920 */ 921 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 922 923 sc->wb_unit = unit; 924 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 925 926 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 927 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 928 929 if (sc->wb_ldata == NULL) { 930 printf("wb%d: no memory for list buffers!\n", unit); 931 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 932 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 933 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 934 error = ENXIO; 935 goto fail; 936 } 937 938 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 939 940 ifp = &sc->arpcom.ac_if; 941 ifp->if_softc = sc; 942 ifp->if_unit = unit; 943 ifp->if_name = "wb"; 944 ifp->if_mtu = ETHERMTU; 945 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 946 ifp->if_ioctl = wb_ioctl; 947 ifp->if_output = ether_output; 948 ifp->if_start = wb_start; 949 ifp->if_watchdog = wb_watchdog; 950 ifp->if_init = wb_init; 951 ifp->if_baudrate = 10000000; 952 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 953 954 /* 955 * Do MII setup. 956 */ 957 if (mii_phy_probe(dev, &sc->wb_miibus, 958 wb_ifmedia_upd, wb_ifmedia_sts)) { 959 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8, 960 M_DEVBUF); 961 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 962 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 963 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 964 error = ENXIO; 965 goto fail; 966 } 967 968 /* 969 * Call MI attach routine. 970 */ 971 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 972 973 fail: 974 if (error) 975 device_delete_child(dev, sc->wb_miibus); 976 splx(s); 977 978 return(error); 979 } 980 981 static int wb_detach(dev) 982 device_t dev; 983 { 984 struct wb_softc *sc; 985 struct ifnet *ifp; 986 int s; 987 988 s = splimp(); 989 990 sc = device_get_softc(dev); 991 ifp = &sc->arpcom.ac_if; 992 993 wb_stop(sc); 994 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 995 996 /* Delete any miibus and phy devices attached to this interface */ 997 bus_generic_detach(dev); 998 device_delete_child(dev, sc->wb_miibus); 999 1000 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 1001 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 1002 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 1003 1004 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8, 1005 M_DEVBUF); 1006 1007 splx(s); 1008 1009 return(0); 1010 } 1011 1012 /* 1013 * Initialize the transmit descriptors. 1014 */ 1015 static int wb_list_tx_init(sc) 1016 struct wb_softc *sc; 1017 { 1018 struct wb_chain_data *cd; 1019 struct wb_list_data *ld; 1020 int i; 1021 1022 cd = &sc->wb_cdata; 1023 ld = sc->wb_ldata; 1024 1025 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1026 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1027 if (i == (WB_TX_LIST_CNT - 1)) { 1028 cd->wb_tx_chain[i].wb_nextdesc = 1029 &cd->wb_tx_chain[0]; 1030 } else { 1031 cd->wb_tx_chain[i].wb_nextdesc = 1032 &cd->wb_tx_chain[i + 1]; 1033 } 1034 } 1035 1036 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1037 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1038 1039 return(0); 1040 } 1041 1042 1043 /* 1044 * Initialize the RX descriptors and allocate mbufs for them. Note that 1045 * we arrange the descriptors in a closed ring, so that the last descriptor 1046 * points back to the first. 1047 */ 1048 static int wb_list_rx_init(sc) 1049 struct wb_softc *sc; 1050 { 1051 struct wb_chain_data *cd; 1052 struct wb_list_data *ld; 1053 int i; 1054 1055 cd = &sc->wb_cdata; 1056 ld = sc->wb_ldata; 1057 1058 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1059 cd->wb_rx_chain[i].wb_ptr = 1060 (struct wb_desc *)&ld->wb_rx_list[i]; 1061 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1062 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1063 return(ENOBUFS); 1064 if (i == (WB_RX_LIST_CNT - 1)) { 1065 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1066 ld->wb_rx_list[i].wb_next = 1067 vtophys(&ld->wb_rx_list[0]); 1068 } else { 1069 cd->wb_rx_chain[i].wb_nextdesc = 1070 &cd->wb_rx_chain[i + 1]; 1071 ld->wb_rx_list[i].wb_next = 1072 vtophys(&ld->wb_rx_list[i + 1]); 1073 } 1074 } 1075 1076 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1077 1078 return(0); 1079 } 1080 1081 static void wb_bfree(buf, size) 1082 caddr_t buf; 1083 u_int size; 1084 { 1085 return; 1086 } 1087 1088 /* 1089 * Initialize an RX descriptor and attach an MBUF cluster. 1090 */ 1091 static int wb_newbuf(sc, c, m) 1092 struct wb_softc *sc; 1093 struct wb_chain_onefrag *c; 1094 struct mbuf *m; 1095 { 1096 struct mbuf *m_new = NULL; 1097 1098 if (m == NULL) { 1099 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1100 if (m_new == NULL) 1101 return(ENOBUFS); 1102 1103 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf; 1104 m_new->m_flags |= M_EXT; 1105 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 1106 m_new->m_len = WB_BUFBYTES; 1107 m_new->m_ext.ext_free = wb_bfree; 1108 m_new->m_ext.ext_ref = wb_bfree; 1109 } else { 1110 m_new = m; 1111 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1112 m_new->m_data = m_new->m_ext.ext_buf; 1113 } 1114 1115 m_adj(m_new, sizeof(u_int64_t)); 1116 1117 c->wb_mbuf = m_new; 1118 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1119 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1120 c->wb_ptr->wb_status = WB_RXSTAT; 1121 1122 return(0); 1123 } 1124 1125 /* 1126 * A frame has been uploaded: pass the resulting mbuf chain up to 1127 * the higher level protocols. 1128 */ 1129 static void wb_rxeof(sc) 1130 struct wb_softc *sc; 1131 { 1132 struct ether_header *eh; 1133 struct mbuf *m = NULL; 1134 struct ifnet *ifp; 1135 struct wb_chain_onefrag *cur_rx; 1136 int total_len = 0; 1137 u_int32_t rxstat; 1138 1139 ifp = &sc->arpcom.ac_if; 1140 1141 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1142 WB_RXSTAT_OWN)) { 1143 struct mbuf *m0 = NULL; 1144 1145 cur_rx = sc->wb_cdata.wb_rx_head; 1146 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1147 1148 m = cur_rx->wb_mbuf; 1149 1150 if ((rxstat & WB_RXSTAT_MIIERR) || 1151 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1152 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1153 !(rxstat & WB_RXSTAT_LASTFRAG) || 1154 !(rxstat & WB_RXSTAT_RXCMP)) { 1155 ifp->if_ierrors++; 1156 wb_newbuf(sc, cur_rx, m); 1157 printf("wb%x: receiver babbling: possible chip " 1158 "bug, forcing reset\n", sc->wb_unit); 1159 wb_fixmedia(sc); 1160 wb_reset(sc); 1161 wb_init(sc); 1162 return; 1163 } 1164 1165 if (rxstat & WB_RXSTAT_RXERR) { 1166 ifp->if_ierrors++; 1167 wb_newbuf(sc, cur_rx, m); 1168 break; 1169 } 1170 1171 /* No errors; receive the packet. */ 1172 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1173 1174 /* 1175 * XXX The Winbond chip includes the CRC with every 1176 * received frame, and there's no way to turn this 1177 * behavior off (at least, I can't find anything in 1178 * the manual that explains how to do it) so we have 1179 * to trim off the CRC manually. 1180 */ 1181 total_len -= ETHER_CRC_LEN; 1182 1183 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1184 total_len + ETHER_ALIGN, 0, ifp, NULL); 1185 wb_newbuf(sc, cur_rx, m); 1186 if (m0 == NULL) { 1187 ifp->if_ierrors++; 1188 break; 1189 } 1190 m_adj(m0, ETHER_ALIGN); 1191 m = m0; 1192 1193 ifp->if_ipackets++; 1194 eh = mtod(m, struct ether_header *); 1195 1196 /* Remove header from mbuf and pass it on. */ 1197 m_adj(m, sizeof(struct ether_header)); 1198 ether_input(ifp, eh, m); 1199 } 1200 } 1201 1202 void wb_rxeoc(sc) 1203 struct wb_softc *sc; 1204 { 1205 wb_rxeof(sc); 1206 1207 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1208 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1209 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1210 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1211 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1212 1213 return; 1214 } 1215 1216 /* 1217 * A frame was downloaded to the chip. It's safe for us to clean up 1218 * the list buffers. 1219 */ 1220 static void wb_txeof(sc) 1221 struct wb_softc *sc; 1222 { 1223 struct wb_chain *cur_tx; 1224 struct ifnet *ifp; 1225 1226 ifp = &sc->arpcom.ac_if; 1227 1228 /* Clear the timeout timer. */ 1229 ifp->if_timer = 0; 1230 1231 if (sc->wb_cdata.wb_tx_head == NULL) 1232 return; 1233 1234 /* 1235 * Go through our tx list and free mbufs for those 1236 * frames that have been transmitted. 1237 */ 1238 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1239 u_int32_t txstat; 1240 1241 cur_tx = sc->wb_cdata.wb_tx_head; 1242 txstat = WB_TXSTATUS(cur_tx); 1243 1244 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1245 break; 1246 1247 if (txstat & WB_TXSTAT_TXERR) { 1248 ifp->if_oerrors++; 1249 if (txstat & WB_TXSTAT_ABORT) 1250 ifp->if_collisions++; 1251 if (txstat & WB_TXSTAT_LATECOLL) 1252 ifp->if_collisions++; 1253 } 1254 1255 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1256 1257 ifp->if_opackets++; 1258 m_freem(cur_tx->wb_mbuf); 1259 cur_tx->wb_mbuf = NULL; 1260 1261 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1262 sc->wb_cdata.wb_tx_head = NULL; 1263 sc->wb_cdata.wb_tx_tail = NULL; 1264 break; 1265 } 1266 1267 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1268 } 1269 1270 return; 1271 } 1272 1273 /* 1274 * TX 'end of channel' interrupt handler. 1275 */ 1276 static void wb_txeoc(sc) 1277 struct wb_softc *sc; 1278 { 1279 struct ifnet *ifp; 1280 1281 ifp = &sc->arpcom.ac_if; 1282 1283 ifp->if_timer = 0; 1284 1285 if (sc->wb_cdata.wb_tx_head == NULL) { 1286 ifp->if_flags &= ~IFF_OACTIVE; 1287 sc->wb_cdata.wb_tx_tail = NULL; 1288 } else { 1289 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1290 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1291 ifp->if_timer = 5; 1292 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1293 } 1294 } 1295 1296 return; 1297 } 1298 1299 static void wb_intr(arg) 1300 void *arg; 1301 { 1302 struct wb_softc *sc; 1303 struct ifnet *ifp; 1304 u_int32_t status; 1305 1306 sc = arg; 1307 ifp = &sc->arpcom.ac_if; 1308 1309 if (!(ifp->if_flags & IFF_UP)) 1310 return; 1311 1312 /* Disable interrupts. */ 1313 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1314 1315 for (;;) { 1316 1317 status = CSR_READ_4(sc, WB_ISR); 1318 if (status) 1319 CSR_WRITE_4(sc, WB_ISR, status); 1320 1321 if ((status & WB_INTRS) == 0) 1322 break; 1323 1324 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1325 ifp->if_ierrors++; 1326 wb_reset(sc); 1327 if (status & WB_ISR_RX_ERR) 1328 wb_fixmedia(sc); 1329 wb_init(sc); 1330 continue; 1331 } 1332 1333 if (status & WB_ISR_RX_OK) 1334 wb_rxeof(sc); 1335 1336 if (status & WB_ISR_RX_IDLE) 1337 wb_rxeoc(sc); 1338 1339 if (status & WB_ISR_TX_OK) 1340 wb_txeof(sc); 1341 1342 if (status & WB_ISR_TX_NOBUF) 1343 wb_txeoc(sc); 1344 1345 if (status & WB_ISR_TX_IDLE) { 1346 wb_txeof(sc); 1347 if (sc->wb_cdata.wb_tx_head != NULL) { 1348 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1349 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1350 } 1351 } 1352 1353 if (status & WB_ISR_TX_UNDERRUN) { 1354 ifp->if_oerrors++; 1355 wb_txeof(sc); 1356 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1357 /* Jack up TX threshold */ 1358 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1359 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1360 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1361 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1362 } 1363 1364 if (status & WB_ISR_BUS_ERR) { 1365 wb_reset(sc); 1366 wb_init(sc); 1367 } 1368 1369 } 1370 1371 /* Re-enable interrupts. */ 1372 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1373 1374 if (ifp->if_snd.ifq_head != NULL) { 1375 wb_start(ifp); 1376 } 1377 1378 return; 1379 } 1380 1381 static void wb_tick(xsc) 1382 void *xsc; 1383 { 1384 struct wb_softc *sc; 1385 struct mii_data *mii; 1386 int s; 1387 1388 s = splimp(); 1389 1390 sc = xsc; 1391 mii = device_get_softc(sc->wb_miibus); 1392 1393 mii_tick(mii); 1394 1395 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1396 1397 splx(s); 1398 1399 return; 1400 } 1401 1402 /* 1403 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1404 * pointers to the fragment pointers. 1405 */ 1406 static int wb_encap(sc, c, m_head) 1407 struct wb_softc *sc; 1408 struct wb_chain *c; 1409 struct mbuf *m_head; 1410 { 1411 int frag = 0; 1412 struct wb_desc *f = NULL; 1413 int total_len; 1414 struct mbuf *m; 1415 1416 /* 1417 * Start packing the mbufs in this chain into 1418 * the fragment pointers. Stop when we run out 1419 * of fragments or hit the end of the mbuf chain. 1420 */ 1421 m = m_head; 1422 total_len = 0; 1423 1424 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1425 if (m->m_len != 0) { 1426 if (frag == WB_MAXFRAGS) 1427 break; 1428 total_len += m->m_len; 1429 f = &c->wb_ptr->wb_frag[frag]; 1430 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1431 if (frag == 0) { 1432 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1433 f->wb_status = 0; 1434 } else 1435 f->wb_status = WB_TXSTAT_OWN; 1436 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1437 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1438 frag++; 1439 } 1440 } 1441 1442 /* 1443 * Handle special case: we used up all 16 fragments, 1444 * but we have more mbufs left in the chain. Copy the 1445 * data into an mbuf cluster. Note that we don't 1446 * bother clearing the values in the other fragment 1447 * pointers/counters; it wouldn't gain us anything, 1448 * and would waste cycles. 1449 */ 1450 if (m != NULL) { 1451 struct mbuf *m_new = NULL; 1452 1453 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1454 if (m_new == NULL) 1455 return(1); 1456 if (m_head->m_pkthdr.len > MHLEN) { 1457 MCLGET(m_new, M_DONTWAIT); 1458 if (!(m_new->m_flags & M_EXT)) { 1459 m_freem(m_new); 1460 return(1); 1461 } 1462 } 1463 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1464 mtod(m_new, caddr_t)); 1465 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1466 m_freem(m_head); 1467 m_head = m_new; 1468 f = &c->wb_ptr->wb_frag[0]; 1469 f->wb_status = 0; 1470 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1471 f->wb_ctl = total_len = m_new->m_len; 1472 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1473 frag = 1; 1474 } 1475 1476 if (total_len < WB_MIN_FRAMELEN) { 1477 f = &c->wb_ptr->wb_frag[frag]; 1478 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1479 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1480 f->wb_ctl |= WB_TXCTL_TLINK; 1481 f->wb_status = WB_TXSTAT_OWN; 1482 frag++; 1483 } 1484 1485 c->wb_mbuf = m_head; 1486 c->wb_lastdesc = frag - 1; 1487 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1488 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1489 1490 return(0); 1491 } 1492 1493 /* 1494 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1495 * to the mbuf data regions directly in the transmit lists. We also save a 1496 * copy of the pointers since the transmit list fragment pointers are 1497 * physical addresses. 1498 */ 1499 1500 static void wb_start(ifp) 1501 struct ifnet *ifp; 1502 { 1503 struct wb_softc *sc; 1504 struct mbuf *m_head = NULL; 1505 struct wb_chain *cur_tx = NULL, *start_tx; 1506 1507 sc = ifp->if_softc; 1508 1509 /* 1510 * Check for an available queue slot. If there are none, 1511 * punt. 1512 */ 1513 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1514 ifp->if_flags |= IFF_OACTIVE; 1515 return; 1516 } 1517 1518 start_tx = sc->wb_cdata.wb_tx_free; 1519 1520 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1521 IF_DEQUEUE(&ifp->if_snd, m_head); 1522 if (m_head == NULL) 1523 break; 1524 1525 /* Pick a descriptor off the free list. */ 1526 cur_tx = sc->wb_cdata.wb_tx_free; 1527 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1528 1529 /* Pack the data into the descriptor. */ 1530 wb_encap(sc, cur_tx, m_head); 1531 1532 if (cur_tx != start_tx) 1533 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1534 1535 /* 1536 * If there's a BPF listener, bounce a copy of this frame 1537 * to him. 1538 */ 1539 if (ifp->if_bpf) 1540 bpf_mtap(ifp, cur_tx->wb_mbuf); 1541 } 1542 1543 /* 1544 * If there are no packets queued, bail. 1545 */ 1546 if (cur_tx == NULL) 1547 return; 1548 1549 /* 1550 * Place the request for the upload interrupt 1551 * in the last descriptor in the chain. This way, if 1552 * we're chaining several packets at once, we'll only 1553 * get an interupt once for the whole chain rather than 1554 * once for each packet. 1555 */ 1556 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1557 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1558 sc->wb_cdata.wb_tx_tail = cur_tx; 1559 1560 if (sc->wb_cdata.wb_tx_head == NULL) { 1561 sc->wb_cdata.wb_tx_head = start_tx; 1562 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1563 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1564 } else { 1565 /* 1566 * We need to distinguish between the case where 1567 * the own bit is clear because the chip cleared it 1568 * and where the own bit is clear because we haven't 1569 * set it yet. The magic value WB_UNSET is just some 1570 * ramdomly chosen number which doesn't have the own 1571 * bit set. When we actually transmit the frame, the 1572 * status word will have _only_ the own bit set, so 1573 * the txeoc handler will be able to tell if it needs 1574 * to initiate another transmission to flush out pending 1575 * frames. 1576 */ 1577 WB_TXOWN(start_tx) = WB_UNSENT; 1578 } 1579 1580 /* 1581 * Set a timeout in case the chip goes out to lunch. 1582 */ 1583 ifp->if_timer = 5; 1584 1585 return; 1586 } 1587 1588 static void wb_init(xsc) 1589 void *xsc; 1590 { 1591 struct wb_softc *sc = xsc; 1592 struct ifnet *ifp = &sc->arpcom.ac_if; 1593 int s, i; 1594 struct mii_data *mii; 1595 1596 s = splimp(); 1597 1598 mii = device_get_softc(sc->wb_miibus); 1599 1600 /* 1601 * Cancel pending I/O and free all RX/TX buffers. 1602 */ 1603 wb_stop(sc); 1604 wb_reset(sc); 1605 1606 sc->wb_txthresh = WB_TXTHRESH_INIT; 1607 1608 /* 1609 * Set cache alignment and burst length. 1610 */ 1611 #ifdef foo 1612 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1613 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1614 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1615 #endif 1616 1617 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1618 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1619 switch(sc->wb_cachesize) { 1620 case 32: 1621 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1622 break; 1623 case 16: 1624 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1625 break; 1626 case 8: 1627 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1628 break; 1629 case 0: 1630 default: 1631 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1632 break; 1633 } 1634 1635 /* This doesn't tend to work too well at 100Mbps. */ 1636 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1637 1638 /* Init our MAC address */ 1639 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1640 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1641 } 1642 1643 /* Init circular RX list. */ 1644 if (wb_list_rx_init(sc) == ENOBUFS) { 1645 printf("wb%d: initialization failed: no " 1646 "memory for rx buffers\n", sc->wb_unit); 1647 wb_stop(sc); 1648 (void)splx(s); 1649 return; 1650 } 1651 1652 /* Init TX descriptors. */ 1653 wb_list_tx_init(sc); 1654 1655 /* If we want promiscuous mode, set the allframes bit. */ 1656 if (ifp->if_flags & IFF_PROMISC) { 1657 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1658 } else { 1659 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1660 } 1661 1662 /* 1663 * Set capture broadcast bit to capture broadcast frames. 1664 */ 1665 if (ifp->if_flags & IFF_BROADCAST) { 1666 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1667 } else { 1668 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1669 } 1670 1671 /* 1672 * Program the multicast filter, if necessary. 1673 */ 1674 wb_setmulti(sc); 1675 1676 /* 1677 * Load the address of the RX list. 1678 */ 1679 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1680 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1681 1682 /* 1683 * Enable interrupts. 1684 */ 1685 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1686 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1687 1688 /* Enable receiver and transmitter. */ 1689 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1690 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1691 1692 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1693 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1694 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1695 1696 mii_mediachg(mii); 1697 1698 ifp->if_flags |= IFF_RUNNING; 1699 ifp->if_flags &= ~IFF_OACTIVE; 1700 1701 (void)splx(s); 1702 1703 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1704 1705 return; 1706 } 1707 1708 /* 1709 * Set media options. 1710 */ 1711 static int wb_ifmedia_upd(ifp) 1712 struct ifnet *ifp; 1713 { 1714 struct wb_softc *sc; 1715 1716 sc = ifp->if_softc; 1717 1718 if (ifp->if_flags & IFF_UP) 1719 wb_init(sc); 1720 1721 return(0); 1722 } 1723 1724 /* 1725 * Report current media status. 1726 */ 1727 static void wb_ifmedia_sts(ifp, ifmr) 1728 struct ifnet *ifp; 1729 struct ifmediareq *ifmr; 1730 { 1731 struct wb_softc *sc; 1732 struct mii_data *mii; 1733 1734 sc = ifp->if_softc; 1735 1736 mii = device_get_softc(sc->wb_miibus); 1737 1738 mii_pollstat(mii); 1739 ifmr->ifm_active = mii->mii_media_active; 1740 ifmr->ifm_status = mii->mii_media_status; 1741 1742 return; 1743 } 1744 1745 static int wb_ioctl(ifp, command, data) 1746 struct ifnet *ifp; 1747 u_long command; 1748 caddr_t data; 1749 { 1750 struct wb_softc *sc = ifp->if_softc; 1751 struct mii_data *mii; 1752 struct ifreq *ifr = (struct ifreq *) data; 1753 int s, error = 0; 1754 1755 s = splimp(); 1756 1757 switch(command) { 1758 case SIOCSIFADDR: 1759 case SIOCGIFADDR: 1760 case SIOCSIFMTU: 1761 error = ether_ioctl(ifp, command, data); 1762 break; 1763 case SIOCSIFFLAGS: 1764 if (ifp->if_flags & IFF_UP) { 1765 wb_init(sc); 1766 } else { 1767 if (ifp->if_flags & IFF_RUNNING) 1768 wb_stop(sc); 1769 } 1770 error = 0; 1771 break; 1772 case SIOCADDMULTI: 1773 case SIOCDELMULTI: 1774 wb_setmulti(sc); 1775 error = 0; 1776 break; 1777 case SIOCGIFMEDIA: 1778 case SIOCSIFMEDIA: 1779 mii = device_get_softc(sc->wb_miibus); 1780 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1781 break; 1782 default: 1783 error = EINVAL; 1784 break; 1785 } 1786 1787 (void)splx(s); 1788 1789 return(error); 1790 } 1791 1792 static void wb_watchdog(ifp) 1793 struct ifnet *ifp; 1794 { 1795 struct wb_softc *sc; 1796 1797 sc = ifp->if_softc; 1798 1799 ifp->if_oerrors++; 1800 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1801 #ifdef foo 1802 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1803 printf("wb%d: no carrier - transceiver cable problem?\n", 1804 sc->wb_unit); 1805 #endif 1806 wb_stop(sc); 1807 wb_reset(sc); 1808 wb_init(sc); 1809 1810 if (ifp->if_snd.ifq_head != NULL) 1811 wb_start(ifp); 1812 1813 return; 1814 } 1815 1816 /* 1817 * Stop the adapter and free any mbufs allocated to the 1818 * RX and TX lists. 1819 */ 1820 static void wb_stop(sc) 1821 struct wb_softc *sc; 1822 { 1823 register int i; 1824 struct ifnet *ifp; 1825 1826 ifp = &sc->arpcom.ac_if; 1827 ifp->if_timer = 0; 1828 1829 untimeout(wb_tick, sc, sc->wb_stat_ch); 1830 1831 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1832 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1833 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1834 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1835 1836 /* 1837 * Free data in the RX lists. 1838 */ 1839 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1840 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1841 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1842 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1843 } 1844 } 1845 bzero((char *)&sc->wb_ldata->wb_rx_list, 1846 sizeof(sc->wb_ldata->wb_rx_list)); 1847 1848 /* 1849 * Free the TX list buffers. 1850 */ 1851 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1852 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1853 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1854 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1855 } 1856 } 1857 1858 bzero((char *)&sc->wb_ldata->wb_tx_list, 1859 sizeof(sc->wb_ldata->wb_tx_list)); 1860 1861 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1862 1863 return; 1864 } 1865 1866 /* 1867 * Stop all chip I/O so that the kernel's probe routines don't 1868 * get confused by errant DMAs when rebooting. 1869 */ 1870 static void wb_shutdown(dev) 1871 device_t dev; 1872 { 1873 struct wb_softc *sc; 1874 1875 sc = device_get_softc(dev); 1876 wb_stop(sc); 1877 1878 return; 1879 }
Cache object: d670246de856f453f873347dd20a5004
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