FreeBSD/Linux Kernel Cross Reference
sys/pci/if_wb.c
1 /*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: releng/5.0/sys/pci/if_wb.c 106936 2002-11-14 23:49:09Z sam $
33 */
34
35 /*
36 * Winbond fast ethernet PCI NIC driver
37 *
38 * Supports various cheap network adapters based on the Winbond W89C840F
39 * fast ethernet controller chip. This includes adapters manufactured by
40 * Winbond itself and some made by Linksys.
41 *
42 * Written by Bill Paul <wpaul@ctr.columbia.edu>
43 * Electrical Engineering Department
44 * Columbia University, New York City
45 */
46
47 /*
48 * The Winbond W89C840F chip is a bus master; in some ways it resembles
49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
50 * one major difference which is that while the registers do many of
51 * the same things as a tulip adapter, the offsets are different: where
52 * tulip registers are typically spaced 8 bytes apart, the Winbond
53 * registers are spaced 4 bytes apart. The receiver filter is also
54 * programmed differently.
55 *
56 * Like the tulip, the Winbond chip uses small descriptors containing
57 * a status word, a control word and 32-bit areas that can either be used
58 * to point to two external data blocks, or to point to a single block
59 * and another descriptor in a linked list. Descriptors can be grouped
60 * together in blocks to form fixed length rings or can be chained
61 * together in linked lists. A single packet may be spread out over
62 * several descriptors if necessary.
63 *
64 * For the receive ring, this driver uses a linked list of descriptors,
65 * each pointing to a single mbuf cluster buffer, which us large enough
66 * to hold an entire packet. The link list is looped back to created a
67 * closed ring.
68 *
69 * For transmission, the driver creates a linked list of 'super descriptors'
70 * which each contain several individual descriptors linked toghether.
71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
72 * abuse as fragment pointers. This allows us to use a buffer managment
73 * scheme very similar to that used in the ThunderLAN and Etherlink XL
74 * drivers.
75 *
76 * Autonegotiation is performed using the external PHY via the MII bus.
77 * The sample boards I have all use a Davicom PHY.
78 *
79 * Note: the author of the Linux driver for the Winbond chip alludes
80 * to some sort of flaw in the chip's design that seems to mandate some
81 * drastic workaround which signigicantly impairs transmit performance.
82 * I have no idea what he's on about: transmit performance with all
83 * three of my test boards seems fine.
84 */
85
86 #include "opt_bdg.h"
87
88 #include <sys/param.h>
89 #include <sys/systm.h>
90 #include <sys/sockio.h>
91 #include <sys/mbuf.h>
92 #include <sys/malloc.h>
93 #include <sys/kernel.h>
94 #include <sys/socket.h>
95 #include <sys/queue.h>
96
97 #include <net/if.h>
98 #include <net/if_arp.h>
99 #include <net/ethernet.h>
100 #include <net/if_dl.h>
101 #include <net/if_media.h>
102
103 #include <net/bpf.h>
104
105 #include <vm/vm.h> /* for vtophys */
106 #include <vm/pmap.h> /* for vtophys */
107 #include <machine/bus_memio.h>
108 #include <machine/bus_pio.h>
109 #include <machine/bus.h>
110 #include <machine/resource.h>
111 #include <sys/bus.h>
112 #include <sys/rman.h>
113
114 #include <pci/pcireg.h>
115 #include <pci/pcivar.h>
116
117 #include <dev/mii/mii.h>
118 #include <dev/mii/miivar.h>
119
120 /* "controller miibus0" required. See GENERIC if you get errors here. */
121 #include "miibus_if.h"
122
123 #define WB_USEIOSPACE
124
125 #include <pci/if_wbreg.h>
126
127 MODULE_DEPEND(wb, miibus, 1, 1, 1);
128
129 #ifndef lint
130 static const char rcsid[] =
131 "$FreeBSD: releng/5.0/sys/pci/if_wb.c 106936 2002-11-14 23:49:09Z sam $";
132 #endif
133
134 /*
135 * Various supported device vendors/types and their names.
136 */
137 static struct wb_type wb_devs[] = {
138 { WB_VENDORID, WB_DEVICEID_840F,
139 "Winbond W89C840F 10/100BaseTX" },
140 { CP_VENDORID, CP_DEVICEID_RL100,
141 "Compex RL100-ATX 10/100baseTX" },
142 { 0, 0, NULL }
143 };
144
145 static int wb_probe (device_t);
146 static int wb_attach (device_t);
147 static int wb_detach (device_t);
148
149 static void wb_bfree (void *addr, void *args);
150 static int wb_newbuf (struct wb_softc *,
151 struct wb_chain_onefrag *,
152 struct mbuf *);
153 static int wb_encap (struct wb_softc *, struct wb_chain *,
154 struct mbuf *);
155
156 static void wb_rxeof (struct wb_softc *);
157 static void wb_rxeoc (struct wb_softc *);
158 static void wb_txeof (struct wb_softc *);
159 static void wb_txeoc (struct wb_softc *);
160 static void wb_intr (void *);
161 static void wb_tick (void *);
162 static void wb_start (struct ifnet *);
163 static int wb_ioctl (struct ifnet *, u_long, caddr_t);
164 static void wb_init (void *);
165 static void wb_stop (struct wb_softc *);
166 static void wb_watchdog (struct ifnet *);
167 static void wb_shutdown (device_t);
168 static int wb_ifmedia_upd (struct ifnet *);
169 static void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *);
170
171 static void wb_eeprom_putbyte (struct wb_softc *, int);
172 static void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *);
173 static void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int);
174 static void wb_mii_sync (struct wb_softc *);
175 static void wb_mii_send (struct wb_softc *, u_int32_t, int);
176 static int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *);
177 static int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *);
178
179 static void wb_setcfg (struct wb_softc *, u_int32_t);
180 static u_int8_t wb_calchash (caddr_t);
181 static void wb_setmulti (struct wb_softc *);
182 static void wb_reset (struct wb_softc *);
183 static void wb_fixmedia (struct wb_softc *);
184 static int wb_list_rx_init (struct wb_softc *);
185 static int wb_list_tx_init (struct wb_softc *);
186
187 static int wb_miibus_readreg (device_t, int, int);
188 static int wb_miibus_writereg (device_t, int, int, int);
189 static void wb_miibus_statchg (device_t);
190
191 #ifdef WB_USEIOSPACE
192 #define WB_RES SYS_RES_IOPORT
193 #define WB_RID WB_PCI_LOIO
194 #else
195 #define WB_RES SYS_RES_MEMORY
196 #define WB_RID WB_PCI_LOMEM
197 #endif
198
199 static device_method_t wb_methods[] = {
200 /* Device interface */
201 DEVMETHOD(device_probe, wb_probe),
202 DEVMETHOD(device_attach, wb_attach),
203 DEVMETHOD(device_detach, wb_detach),
204 DEVMETHOD(device_shutdown, wb_shutdown),
205
206 /* bus interface, for miibus */
207 DEVMETHOD(bus_print_child, bus_generic_print_child),
208 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
209
210 /* MII interface */
211 DEVMETHOD(miibus_readreg, wb_miibus_readreg),
212 DEVMETHOD(miibus_writereg, wb_miibus_writereg),
213 DEVMETHOD(miibus_statchg, wb_miibus_statchg),
214 { 0, 0 }
215 };
216
217 static driver_t wb_driver = {
218 "wb",
219 wb_methods,
220 sizeof(struct wb_softc)
221 };
222
223 static devclass_t wb_devclass;
224
225 DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0);
226 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
227
228 #define WB_SETBIT(sc, reg, x) \
229 CSR_WRITE_4(sc, reg, \
230 CSR_READ_4(sc, reg) | (x))
231
232 #define WB_CLRBIT(sc, reg, x) \
233 CSR_WRITE_4(sc, reg, \
234 CSR_READ_4(sc, reg) & ~(x))
235
236 #define SIO_SET(x) \
237 CSR_WRITE_4(sc, WB_SIO, \
238 CSR_READ_4(sc, WB_SIO) | (x))
239
240 #define SIO_CLR(x) \
241 CSR_WRITE_4(sc, WB_SIO, \
242 CSR_READ_4(sc, WB_SIO) & ~(x))
243
244 /*
245 * Send a read command and address to the EEPROM, check for ACK.
246 */
247 static void
248 wb_eeprom_putbyte(sc, addr)
249 struct wb_softc *sc;
250 int addr;
251 {
252 register int d, i;
253
254 d = addr | WB_EECMD_READ;
255
256 /*
257 * Feed in each bit and stobe the clock.
258 */
259 for (i = 0x400; i; i >>= 1) {
260 if (d & i) {
261 SIO_SET(WB_SIO_EE_DATAIN);
262 } else {
263 SIO_CLR(WB_SIO_EE_DATAIN);
264 }
265 DELAY(100);
266 SIO_SET(WB_SIO_EE_CLK);
267 DELAY(150);
268 SIO_CLR(WB_SIO_EE_CLK);
269 DELAY(100);
270 }
271
272 return;
273 }
274
275 /*
276 * Read a word of data stored in the EEPROM at address 'addr.'
277 */
278 static void
279 wb_eeprom_getword(sc, addr, dest)
280 struct wb_softc *sc;
281 int addr;
282 u_int16_t *dest;
283 {
284 register int i;
285 u_int16_t word = 0;
286
287 /* Enter EEPROM access mode. */
288 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
289
290 /*
291 * Send address of word we want to read.
292 */
293 wb_eeprom_putbyte(sc, addr);
294
295 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
296
297 /*
298 * Start reading bits from EEPROM.
299 */
300 for (i = 0x8000; i; i >>= 1) {
301 SIO_SET(WB_SIO_EE_CLK);
302 DELAY(100);
303 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
304 word |= i;
305 SIO_CLR(WB_SIO_EE_CLK);
306 DELAY(100);
307 }
308
309 /* Turn off EEPROM access mode. */
310 CSR_WRITE_4(sc, WB_SIO, 0);
311
312 *dest = word;
313
314 return;
315 }
316
317 /*
318 * Read a sequence of words from the EEPROM.
319 */
320 static void
321 wb_read_eeprom(sc, dest, off, cnt, swap)
322 struct wb_softc *sc;
323 caddr_t dest;
324 int off;
325 int cnt;
326 int swap;
327 {
328 int i;
329 u_int16_t word = 0, *ptr;
330
331 for (i = 0; i < cnt; i++) {
332 wb_eeprom_getword(sc, off + i, &word);
333 ptr = (u_int16_t *)(dest + (i * 2));
334 if (swap)
335 *ptr = ntohs(word);
336 else
337 *ptr = word;
338 }
339
340 return;
341 }
342
343 /*
344 * Sync the PHYs by setting data bit and strobing the clock 32 times.
345 */
346 static void
347 wb_mii_sync(sc)
348 struct wb_softc *sc;
349 {
350 register int i;
351
352 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN);
353
354 for (i = 0; i < 32; i++) {
355 SIO_SET(WB_SIO_MII_CLK);
356 DELAY(1);
357 SIO_CLR(WB_SIO_MII_CLK);
358 DELAY(1);
359 }
360
361 return;
362 }
363
364 /*
365 * Clock a series of bits through the MII.
366 */
367 static void
368 wb_mii_send(sc, bits, cnt)
369 struct wb_softc *sc;
370 u_int32_t bits;
371 int cnt;
372 {
373 int i;
374
375 SIO_CLR(WB_SIO_MII_CLK);
376
377 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
378 if (bits & i) {
379 SIO_SET(WB_SIO_MII_DATAIN);
380 } else {
381 SIO_CLR(WB_SIO_MII_DATAIN);
382 }
383 DELAY(1);
384 SIO_CLR(WB_SIO_MII_CLK);
385 DELAY(1);
386 SIO_SET(WB_SIO_MII_CLK);
387 }
388 }
389
390 /*
391 * Read an PHY register through the MII.
392 */
393 static int
394 wb_mii_readreg(sc, frame)
395 struct wb_softc *sc;
396 struct wb_mii_frame *frame;
397
398 {
399 int i, ack;
400
401 WB_LOCK(sc);
402
403 /*
404 * Set up frame for RX.
405 */
406 frame->mii_stdelim = WB_MII_STARTDELIM;
407 frame->mii_opcode = WB_MII_READOP;
408 frame->mii_turnaround = 0;
409 frame->mii_data = 0;
410
411 CSR_WRITE_4(sc, WB_SIO, 0);
412
413 /*
414 * Turn on data xmit.
415 */
416 SIO_SET(WB_SIO_MII_DIR);
417
418 wb_mii_sync(sc);
419
420 /*
421 * Send command/address info.
422 */
423 wb_mii_send(sc, frame->mii_stdelim, 2);
424 wb_mii_send(sc, frame->mii_opcode, 2);
425 wb_mii_send(sc, frame->mii_phyaddr, 5);
426 wb_mii_send(sc, frame->mii_regaddr, 5);
427
428 /* Idle bit */
429 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN));
430 DELAY(1);
431 SIO_SET(WB_SIO_MII_CLK);
432 DELAY(1);
433
434 /* Turn off xmit. */
435 SIO_CLR(WB_SIO_MII_DIR);
436 /* Check for ack */
437 SIO_CLR(WB_SIO_MII_CLK);
438 DELAY(1);
439 SIO_SET(WB_SIO_MII_CLK);
440 DELAY(1);
441 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
442 SIO_CLR(WB_SIO_MII_CLK);
443 DELAY(1);
444 SIO_SET(WB_SIO_MII_CLK);
445 DELAY(1);
446
447 /*
448 * Now try reading data bits. If the ack failed, we still
449 * need to clock through 16 cycles to keep the PHY(s) in sync.
450 */
451 if (ack) {
452 for(i = 0; i < 16; i++) {
453 SIO_CLR(WB_SIO_MII_CLK);
454 DELAY(1);
455 SIO_SET(WB_SIO_MII_CLK);
456 DELAY(1);
457 }
458 goto fail;
459 }
460
461 for (i = 0x8000; i; i >>= 1) {
462 SIO_CLR(WB_SIO_MII_CLK);
463 DELAY(1);
464 if (!ack) {
465 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
466 frame->mii_data |= i;
467 DELAY(1);
468 }
469 SIO_SET(WB_SIO_MII_CLK);
470 DELAY(1);
471 }
472
473 fail:
474
475 SIO_CLR(WB_SIO_MII_CLK);
476 DELAY(1);
477 SIO_SET(WB_SIO_MII_CLK);
478 DELAY(1);
479
480 WB_UNLOCK(sc);
481
482 if (ack)
483 return(1);
484 return(0);
485 }
486
487 /*
488 * Write to a PHY register through the MII.
489 */
490 static int
491 wb_mii_writereg(sc, frame)
492 struct wb_softc *sc;
493 struct wb_mii_frame *frame;
494
495 {
496 WB_LOCK(sc);
497
498 /*
499 * Set up frame for TX.
500 */
501
502 frame->mii_stdelim = WB_MII_STARTDELIM;
503 frame->mii_opcode = WB_MII_WRITEOP;
504 frame->mii_turnaround = WB_MII_TURNAROUND;
505
506 /*
507 * Turn on data output.
508 */
509 SIO_SET(WB_SIO_MII_DIR);
510
511 wb_mii_sync(sc);
512
513 wb_mii_send(sc, frame->mii_stdelim, 2);
514 wb_mii_send(sc, frame->mii_opcode, 2);
515 wb_mii_send(sc, frame->mii_phyaddr, 5);
516 wb_mii_send(sc, frame->mii_regaddr, 5);
517 wb_mii_send(sc, frame->mii_turnaround, 2);
518 wb_mii_send(sc, frame->mii_data, 16);
519
520 /* Idle bit. */
521 SIO_SET(WB_SIO_MII_CLK);
522 DELAY(1);
523 SIO_CLR(WB_SIO_MII_CLK);
524 DELAY(1);
525
526 /*
527 * Turn off xmit.
528 */
529 SIO_CLR(WB_SIO_MII_DIR);
530
531 WB_UNLOCK(sc);
532
533 return(0);
534 }
535
536 static int
537 wb_miibus_readreg(dev, phy, reg)
538 device_t dev;
539 int phy, reg;
540 {
541 struct wb_softc *sc;
542 struct wb_mii_frame frame;
543
544 sc = device_get_softc(dev);
545
546 bzero((char *)&frame, sizeof(frame));
547
548 frame.mii_phyaddr = phy;
549 frame.mii_regaddr = reg;
550 wb_mii_readreg(sc, &frame);
551
552 return(frame.mii_data);
553 }
554
555 static int
556 wb_miibus_writereg(dev, phy, reg, data)
557 device_t dev;
558 int phy, reg, data;
559 {
560 struct wb_softc *sc;
561 struct wb_mii_frame frame;
562
563 sc = device_get_softc(dev);
564
565 bzero((char *)&frame, sizeof(frame));
566
567 frame.mii_phyaddr = phy;
568 frame.mii_regaddr = reg;
569 frame.mii_data = data;
570
571 wb_mii_writereg(sc, &frame);
572
573 return(0);
574 }
575
576 static void
577 wb_miibus_statchg(dev)
578 device_t dev;
579 {
580 struct wb_softc *sc;
581 struct mii_data *mii;
582
583 sc = device_get_softc(dev);
584 WB_LOCK(sc);
585 mii = device_get_softc(sc->wb_miibus);
586 wb_setcfg(sc, mii->mii_media_active);
587 WB_UNLOCK(sc);
588
589 return;
590 }
591
592 static u_int8_t wb_calchash(addr)
593 caddr_t addr;
594 {
595 u_int32_t crc, carry;
596 int i, j;
597 u_int8_t c;
598
599 /* Compute CRC for the address value. */
600 crc = 0xFFFFFFFF; /* initial value */
601
602 for (i = 0; i < 6; i++) {
603 c = *(addr + i);
604 for (j = 0; j < 8; j++) {
605 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
606 crc <<= 1;
607 c >>= 1;
608 if (carry)
609 crc = (crc ^ 0x04c11db6) | carry;
610 }
611 }
612
613 /*
614 * return the filter bit position
615 * Note: I arrived at the following nonsense
616 * through experimentation. It's not the usual way to
617 * generate the bit position but it's the only thing
618 * I could come up with that works.
619 */
620 return(~(crc >> 26) & 0x0000003F);
621 }
622
623 /*
624 * Program the 64-bit multicast hash filter.
625 */
626 static void
627 wb_setmulti(sc)
628 struct wb_softc *sc;
629 {
630 struct ifnet *ifp;
631 int h = 0;
632 u_int32_t hashes[2] = { 0, 0 };
633 struct ifmultiaddr *ifma;
634 u_int32_t rxfilt;
635 int mcnt = 0;
636
637 ifp = &sc->arpcom.ac_if;
638
639 rxfilt = CSR_READ_4(sc, WB_NETCFG);
640
641 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
642 rxfilt |= WB_NETCFG_RX_MULTI;
643 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
644 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
645 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
646 return;
647 }
648
649 /* first, zot all the existing hash bits */
650 CSR_WRITE_4(sc, WB_MAR0, 0);
651 CSR_WRITE_4(sc, WB_MAR1, 0);
652
653 /* now program new ones */
654 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
655 if (ifma->ifma_addr->sa_family != AF_LINK)
656 continue;
657 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
658 if (h < 32)
659 hashes[0] |= (1 << h);
660 else
661 hashes[1] |= (1 << (h - 32));
662 mcnt++;
663 }
664
665 if (mcnt)
666 rxfilt |= WB_NETCFG_RX_MULTI;
667 else
668 rxfilt &= ~WB_NETCFG_RX_MULTI;
669
670 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
671 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
672 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
673
674 return;
675 }
676
677 /*
678 * The Winbond manual states that in order to fiddle with the
679 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
680 * first have to put the transmit and/or receive logic in the idle state.
681 */
682 static void
683 wb_setcfg(sc, media)
684 struct wb_softc *sc;
685 u_int32_t media;
686 {
687 int i, restart = 0;
688
689 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
690 restart = 1;
691 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
692
693 for (i = 0; i < WB_TIMEOUT; i++) {
694 DELAY(10);
695 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
696 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
697 break;
698 }
699
700 if (i == WB_TIMEOUT)
701 printf("wb%d: failed to force tx and "
702 "rx to idle state\n", sc->wb_unit);
703 }
704
705 if (IFM_SUBTYPE(media) == IFM_10_T)
706 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
707 else
708 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
709
710 if ((media & IFM_GMASK) == IFM_FDX)
711 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
712 else
713 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
714
715 if (restart)
716 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
717
718 return;
719 }
720
721 static void
722 wb_reset(sc)
723 struct wb_softc *sc;
724 {
725 register int i;
726 struct mii_data *mii;
727
728 CSR_WRITE_4(sc, WB_NETCFG, 0);
729 CSR_WRITE_4(sc, WB_BUSCTL, 0);
730 CSR_WRITE_4(sc, WB_TXADDR, 0);
731 CSR_WRITE_4(sc, WB_RXADDR, 0);
732
733 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
734 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
735
736 for (i = 0; i < WB_TIMEOUT; i++) {
737 DELAY(10);
738 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
739 break;
740 }
741 if (i == WB_TIMEOUT)
742 printf("wb%d: reset never completed!\n", sc->wb_unit);
743
744 /* Wait a little while for the chip to get its brains in order. */
745 DELAY(1000);
746
747 if (sc->wb_miibus == NULL)
748 return;
749
750 mii = device_get_softc(sc->wb_miibus);
751 if (mii == NULL)
752 return;
753
754 if (mii->mii_instance) {
755 struct mii_softc *miisc;
756 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
757 mii_phy_reset(miisc);
758 }
759
760 return;
761 }
762
763 static void
764 wb_fixmedia(sc)
765 struct wb_softc *sc;
766 {
767 struct mii_data *mii = NULL;
768 struct ifnet *ifp;
769 u_int32_t media;
770
771 if (sc->wb_miibus == NULL)
772 return;
773
774 mii = device_get_softc(sc->wb_miibus);
775 ifp = &sc->arpcom.ac_if;
776
777 mii_pollstat(mii);
778 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
779 media = mii->mii_media_active & ~IFM_10_T;
780 media |= IFM_100_TX;
781 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
782 media = mii->mii_media_active & ~IFM_100_TX;
783 media |= IFM_10_T;
784 } else
785 return;
786
787 ifmedia_set(&mii->mii_media, media);
788
789 return;
790 }
791
792 /*
793 * Probe for a Winbond chip. Check the PCI vendor and device
794 * IDs against our list and return a device name if we find a match.
795 */
796 static int
797 wb_probe(dev)
798 device_t dev;
799 {
800 struct wb_type *t;
801
802 t = wb_devs;
803
804 while(t->wb_name != NULL) {
805 if ((pci_get_vendor(dev) == t->wb_vid) &&
806 (pci_get_device(dev) == t->wb_did)) {
807 device_set_desc(dev, t->wb_name);
808 return(0);
809 }
810 t++;
811 }
812
813 return(ENXIO);
814 }
815
816 /*
817 * Attach the interface. Allocate softc structures, do ifmedia
818 * setup and ethernet/BPF attach.
819 */
820 static int
821 wb_attach(dev)
822 device_t dev;
823 {
824 u_char eaddr[ETHER_ADDR_LEN];
825 u_int32_t command;
826 struct wb_softc *sc;
827 struct ifnet *ifp;
828 int unit, error = 0, rid;
829
830 sc = device_get_softc(dev);
831 unit = device_get_unit(dev);
832
833 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
834 MTX_DEF | MTX_RECURSE);
835 WB_LOCK(sc);
836
837 /*
838 * Handle power management nonsense.
839 */
840
841 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
842 u_int32_t iobase, membase, irq;
843
844 /* Save important PCI config data. */
845 iobase = pci_read_config(dev, WB_PCI_LOIO, 4);
846 membase = pci_read_config(dev, WB_PCI_LOMEM, 4);
847 irq = pci_read_config(dev, WB_PCI_INTLINE, 4);
848
849 /* Reset the power state. */
850 printf("wb%d: chip is in D%d power mode "
851 "-- setting to D0\n", unit,
852 pci_get_powerstate(dev));
853 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
854
855 /* Restore PCI config data. */
856 pci_write_config(dev, WB_PCI_LOIO, iobase, 4);
857 pci_write_config(dev, WB_PCI_LOMEM, membase, 4);
858 pci_write_config(dev, WB_PCI_INTLINE, irq, 4);
859 }
860
861 /*
862 * Map control/status registers.
863 */
864 pci_enable_busmaster(dev);
865 pci_enable_io(dev, SYS_RES_IOPORT);
866 pci_enable_io(dev, SYS_RES_MEMORY);
867 command = pci_read_config(dev, PCIR_COMMAND, 4);
868
869 #ifdef WB_USEIOSPACE
870 if (!(command & PCIM_CMD_PORTEN)) {
871 printf("wb%d: failed to enable I/O ports!\n", unit);
872 error = ENXIO;
873 goto fail;
874 }
875 #else
876 if (!(command & PCIM_CMD_MEMEN)) {
877 printf("wb%d: failed to enable memory mapping!\n", unit);
878 error = ENXIO;
879 goto fail;
880 }
881 #endif
882
883 rid = WB_RID;
884 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid,
885 0, ~0, 1, RF_ACTIVE);
886
887 if (sc->wb_res == NULL) {
888 printf("wb%d: couldn't map ports/memory\n", unit);
889 error = ENXIO;
890 goto fail;
891 }
892
893 sc->wb_btag = rman_get_bustag(sc->wb_res);
894 sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
895
896 /* Allocate interrupt */
897 rid = 0;
898 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
899 RF_SHAREABLE | RF_ACTIVE);
900
901 if (sc->wb_irq == NULL) {
902 printf("wb%d: couldn't map interrupt\n", unit);
903 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
904 error = ENXIO;
905 goto fail;
906 }
907
908 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET,
909 wb_intr, sc, &sc->wb_intrhand);
910
911 if (error) {
912 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
913 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
914 printf("wb%d: couldn't set up irq\n", unit);
915 goto fail;
916 }
917
918 /* Save the cache line size. */
919 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
920
921 /* Reset the adapter. */
922 wb_reset(sc);
923
924 /*
925 * Get station address from the EEPROM.
926 */
927 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0);
928
929 /*
930 * A Winbond chip was detected. Inform the world.
931 */
932 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":");
933
934 sc->wb_unit = unit;
935 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
936
937 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
938 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
939
940 if (sc->wb_ldata == NULL) {
941 printf("wb%d: no memory for list buffers!\n", unit);
942 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
943 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
944 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
945 error = ENXIO;
946 goto fail;
947 }
948
949 bzero(sc->wb_ldata, sizeof(struct wb_list_data));
950
951 ifp = &sc->arpcom.ac_if;
952 ifp->if_softc = sc;
953 ifp->if_unit = unit;
954 ifp->if_name = "wb";
955 ifp->if_mtu = ETHERMTU;
956 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
957 ifp->if_ioctl = wb_ioctl;
958 ifp->if_output = ether_output;
959 ifp->if_start = wb_start;
960 ifp->if_watchdog = wb_watchdog;
961 ifp->if_init = wb_init;
962 ifp->if_baudrate = 10000000;
963 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1;
964
965 /*
966 * Do MII setup.
967 */
968 if (mii_phy_probe(dev, &sc->wb_miibus,
969 wb_ifmedia_upd, wb_ifmedia_sts)) {
970 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
971 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
972 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
973 free(sc->wb_ldata_ptr, M_DEVBUF);
974 error = ENXIO;
975 goto fail;
976 }
977
978 /*
979 * Call MI attach routine.
980 */
981 ether_ifattach(ifp, eaddr);
982 WB_UNLOCK(sc);
983 return(0);
984
985 fail:
986 if (error)
987 device_delete_child(dev, sc->wb_miibus);
988 WB_UNLOCK(sc);
989 mtx_destroy(&sc->wb_mtx);
990
991 return(error);
992 }
993
994 static int
995 wb_detach(dev)
996 device_t dev;
997 {
998 struct wb_softc *sc;
999 struct ifnet *ifp;
1000
1001 sc = device_get_softc(dev);
1002 WB_LOCK(sc);
1003 ifp = &sc->arpcom.ac_if;
1004
1005 wb_stop(sc);
1006 ether_ifdetach(ifp);
1007
1008 /* Delete any miibus and phy devices attached to this interface */
1009 bus_generic_detach(dev);
1010 device_delete_child(dev, sc->wb_miibus);
1011
1012 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
1013 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
1014 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
1015
1016 free(sc->wb_ldata_ptr, M_DEVBUF);
1017
1018 WB_UNLOCK(sc);
1019 mtx_destroy(&sc->wb_mtx);
1020
1021 return(0);
1022 }
1023
1024 /*
1025 * Initialize the transmit descriptors.
1026 */
1027 static int
1028 wb_list_tx_init(sc)
1029 struct wb_softc *sc;
1030 {
1031 struct wb_chain_data *cd;
1032 struct wb_list_data *ld;
1033 int i;
1034
1035 cd = &sc->wb_cdata;
1036 ld = sc->wb_ldata;
1037
1038 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1039 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
1040 if (i == (WB_TX_LIST_CNT - 1)) {
1041 cd->wb_tx_chain[i].wb_nextdesc =
1042 &cd->wb_tx_chain[0];
1043 } else {
1044 cd->wb_tx_chain[i].wb_nextdesc =
1045 &cd->wb_tx_chain[i + 1];
1046 }
1047 }
1048
1049 cd->wb_tx_free = &cd->wb_tx_chain[0];
1050 cd->wb_tx_tail = cd->wb_tx_head = NULL;
1051
1052 return(0);
1053 }
1054
1055
1056 /*
1057 * Initialize the RX descriptors and allocate mbufs for them. Note that
1058 * we arrange the descriptors in a closed ring, so that the last descriptor
1059 * points back to the first.
1060 */
1061 static int
1062 wb_list_rx_init(sc)
1063 struct wb_softc *sc;
1064 {
1065 struct wb_chain_data *cd;
1066 struct wb_list_data *ld;
1067 int i;
1068
1069 cd = &sc->wb_cdata;
1070 ld = sc->wb_ldata;
1071
1072 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1073 cd->wb_rx_chain[i].wb_ptr =
1074 (struct wb_desc *)&ld->wb_rx_list[i];
1075 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i];
1076 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
1077 return(ENOBUFS);
1078 if (i == (WB_RX_LIST_CNT - 1)) {
1079 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
1080 ld->wb_rx_list[i].wb_next =
1081 vtophys(&ld->wb_rx_list[0]);
1082 } else {
1083 cd->wb_rx_chain[i].wb_nextdesc =
1084 &cd->wb_rx_chain[i + 1];
1085 ld->wb_rx_list[i].wb_next =
1086 vtophys(&ld->wb_rx_list[i + 1]);
1087 }
1088 }
1089
1090 cd->wb_rx_head = &cd->wb_rx_chain[0];
1091
1092 return(0);
1093 }
1094
1095 static void
1096 wb_bfree(buf, args)
1097 void *buf;
1098 void *args;
1099 {
1100 return;
1101 }
1102
1103 /*
1104 * Initialize an RX descriptor and attach an MBUF cluster.
1105 */
1106 static int
1107 wb_newbuf(sc, c, m)
1108 struct wb_softc *sc;
1109 struct wb_chain_onefrag *c;
1110 struct mbuf *m;
1111 {
1112 struct mbuf *m_new = NULL;
1113
1114 if (m == NULL) {
1115 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1116 if (m_new == NULL)
1117 return(ENOBUFS);
1118 m_new->m_data = c->wb_buf;
1119 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES;
1120 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0,
1121 EXT_NET_DRV);
1122 } else {
1123 m_new = m;
1124 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
1125 m_new->m_data = m_new->m_ext.ext_buf;
1126 }
1127
1128 m_adj(m_new, sizeof(u_int64_t));
1129
1130 c->wb_mbuf = m_new;
1131 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
1132 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
1133 c->wb_ptr->wb_status = WB_RXSTAT;
1134
1135 return(0);
1136 }
1137
1138 /*
1139 * A frame has been uploaded: pass the resulting mbuf chain up to
1140 * the higher level protocols.
1141 */
1142 static void
1143 wb_rxeof(sc)
1144 struct wb_softc *sc;
1145 {
1146 struct mbuf *m = NULL;
1147 struct ifnet *ifp;
1148 struct wb_chain_onefrag *cur_rx;
1149 int total_len = 0;
1150 u_int32_t rxstat;
1151
1152 ifp = &sc->arpcom.ac_if;
1153
1154 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
1155 WB_RXSTAT_OWN)) {
1156 struct mbuf *m0 = NULL;
1157
1158 cur_rx = sc->wb_cdata.wb_rx_head;
1159 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
1160
1161 m = cur_rx->wb_mbuf;
1162
1163 if ((rxstat & WB_RXSTAT_MIIERR) ||
1164 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
1165 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
1166 !(rxstat & WB_RXSTAT_LASTFRAG) ||
1167 !(rxstat & WB_RXSTAT_RXCMP)) {
1168 ifp->if_ierrors++;
1169 wb_newbuf(sc, cur_rx, m);
1170 printf("wb%x: receiver babbling: possible chip "
1171 "bug, forcing reset\n", sc->wb_unit);
1172 wb_fixmedia(sc);
1173 wb_reset(sc);
1174 wb_init(sc);
1175 return;
1176 }
1177
1178 if (rxstat & WB_RXSTAT_RXERR) {
1179 ifp->if_ierrors++;
1180 wb_newbuf(sc, cur_rx, m);
1181 break;
1182 }
1183
1184 /* No errors; receive the packet. */
1185 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
1186
1187 /*
1188 * XXX The Winbond chip includes the CRC with every
1189 * received frame, and there's no way to turn this
1190 * behavior off (at least, I can't find anything in
1191 * the manual that explains how to do it) so we have
1192 * to trim off the CRC manually.
1193 */
1194 total_len -= ETHER_CRC_LEN;
1195
1196 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp,
1197 NULL);
1198 wb_newbuf(sc, cur_rx, m);
1199 if (m0 == NULL) {
1200 ifp->if_ierrors++;
1201 break;
1202 }
1203 m = m0;
1204
1205 ifp->if_ipackets++;
1206 (*ifp->if_input)(ifp, m);
1207 }
1208 }
1209
1210 static void
1211 wb_rxeoc(sc)
1212 struct wb_softc *sc;
1213 {
1214 wb_rxeof(sc);
1215
1216 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1217 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1218 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1219 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
1220 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1221
1222 return;
1223 }
1224
1225 /*
1226 * A frame was downloaded to the chip. It's safe for us to clean up
1227 * the list buffers.
1228 */
1229 static void
1230 wb_txeof(sc)
1231 struct wb_softc *sc;
1232 {
1233 struct wb_chain *cur_tx;
1234 struct ifnet *ifp;
1235
1236 ifp = &sc->arpcom.ac_if;
1237
1238 /* Clear the timeout timer. */
1239 ifp->if_timer = 0;
1240
1241 if (sc->wb_cdata.wb_tx_head == NULL)
1242 return;
1243
1244 /*
1245 * Go through our tx list and free mbufs for those
1246 * frames that have been transmitted.
1247 */
1248 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
1249 u_int32_t txstat;
1250
1251 cur_tx = sc->wb_cdata.wb_tx_head;
1252 txstat = WB_TXSTATUS(cur_tx);
1253
1254 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
1255 break;
1256
1257 if (txstat & WB_TXSTAT_TXERR) {
1258 ifp->if_oerrors++;
1259 if (txstat & WB_TXSTAT_ABORT)
1260 ifp->if_collisions++;
1261 if (txstat & WB_TXSTAT_LATECOLL)
1262 ifp->if_collisions++;
1263 }
1264
1265 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1266
1267 ifp->if_opackets++;
1268 m_freem(cur_tx->wb_mbuf);
1269 cur_tx->wb_mbuf = NULL;
1270
1271 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1272 sc->wb_cdata.wb_tx_head = NULL;
1273 sc->wb_cdata.wb_tx_tail = NULL;
1274 break;
1275 }
1276
1277 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1278 }
1279
1280 return;
1281 }
1282
1283 /*
1284 * TX 'end of channel' interrupt handler.
1285 */
1286 static void
1287 wb_txeoc(sc)
1288 struct wb_softc *sc;
1289 {
1290 struct ifnet *ifp;
1291
1292 ifp = &sc->arpcom.ac_if;
1293
1294 ifp->if_timer = 0;
1295
1296 if (sc->wb_cdata.wb_tx_head == NULL) {
1297 ifp->if_flags &= ~IFF_OACTIVE;
1298 sc->wb_cdata.wb_tx_tail = NULL;
1299 } else {
1300 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1301 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1302 ifp->if_timer = 5;
1303 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1304 }
1305 }
1306
1307 return;
1308 }
1309
1310 static void
1311 wb_intr(arg)
1312 void *arg;
1313 {
1314 struct wb_softc *sc;
1315 struct ifnet *ifp;
1316 u_int32_t status;
1317
1318 sc = arg;
1319 WB_LOCK(sc);
1320 ifp = &sc->arpcom.ac_if;
1321
1322 if (!(ifp->if_flags & IFF_UP)) {
1323 WB_UNLOCK(sc);
1324 return;
1325 }
1326
1327 /* Disable interrupts. */
1328 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1329
1330 for (;;) {
1331
1332 status = CSR_READ_4(sc, WB_ISR);
1333 if (status)
1334 CSR_WRITE_4(sc, WB_ISR, status);
1335
1336 if ((status & WB_INTRS) == 0)
1337 break;
1338
1339 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1340 ifp->if_ierrors++;
1341 wb_reset(sc);
1342 if (status & WB_ISR_RX_ERR)
1343 wb_fixmedia(sc);
1344 wb_init(sc);
1345 continue;
1346 }
1347
1348 if (status & WB_ISR_RX_OK)
1349 wb_rxeof(sc);
1350
1351 if (status & WB_ISR_RX_IDLE)
1352 wb_rxeoc(sc);
1353
1354 if (status & WB_ISR_TX_OK)
1355 wb_txeof(sc);
1356
1357 if (status & WB_ISR_TX_NOBUF)
1358 wb_txeoc(sc);
1359
1360 if (status & WB_ISR_TX_IDLE) {
1361 wb_txeof(sc);
1362 if (sc->wb_cdata.wb_tx_head != NULL) {
1363 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1364 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1365 }
1366 }
1367
1368 if (status & WB_ISR_TX_UNDERRUN) {
1369 ifp->if_oerrors++;
1370 wb_txeof(sc);
1371 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1372 /* Jack up TX threshold */
1373 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1374 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1375 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1376 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1377 }
1378
1379 if (status & WB_ISR_BUS_ERR) {
1380 wb_reset(sc);
1381 wb_init(sc);
1382 }
1383
1384 }
1385
1386 /* Re-enable interrupts. */
1387 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1388
1389 if (ifp->if_snd.ifq_head != NULL) {
1390 wb_start(ifp);
1391 }
1392
1393 WB_UNLOCK(sc);
1394
1395 return;
1396 }
1397
1398 static void
1399 wb_tick(xsc)
1400 void *xsc;
1401 {
1402 struct wb_softc *sc;
1403 struct mii_data *mii;
1404
1405 sc = xsc;
1406 WB_LOCK(sc);
1407 mii = device_get_softc(sc->wb_miibus);
1408
1409 mii_tick(mii);
1410
1411 sc->wb_stat_ch = timeout(wb_tick, sc, hz);
1412
1413 WB_UNLOCK(sc);
1414
1415 return;
1416 }
1417
1418 /*
1419 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1420 * pointers to the fragment pointers.
1421 */
1422 static int
1423 wb_encap(sc, c, m_head)
1424 struct wb_softc *sc;
1425 struct wb_chain *c;
1426 struct mbuf *m_head;
1427 {
1428 int frag = 0;
1429 struct wb_desc *f = NULL;
1430 int total_len;
1431 struct mbuf *m;
1432
1433 /*
1434 * Start packing the mbufs in this chain into
1435 * the fragment pointers. Stop when we run out
1436 * of fragments or hit the end of the mbuf chain.
1437 */
1438 m = m_head;
1439 total_len = 0;
1440
1441 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1442 if (m->m_len != 0) {
1443 if (frag == WB_MAXFRAGS)
1444 break;
1445 total_len += m->m_len;
1446 f = &c->wb_ptr->wb_frag[frag];
1447 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1448 if (frag == 0) {
1449 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1450 f->wb_status = 0;
1451 } else
1452 f->wb_status = WB_TXSTAT_OWN;
1453 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1454 f->wb_data = vtophys(mtod(m, vm_offset_t));
1455 frag++;
1456 }
1457 }
1458
1459 /*
1460 * Handle special case: we used up all 16 fragments,
1461 * but we have more mbufs left in the chain. Copy the
1462 * data into an mbuf cluster. Note that we don't
1463 * bother clearing the values in the other fragment
1464 * pointers/counters; it wouldn't gain us anything,
1465 * and would waste cycles.
1466 */
1467 if (m != NULL) {
1468 struct mbuf *m_new = NULL;
1469
1470 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1471 if (m_new == NULL)
1472 return(1);
1473 if (m_head->m_pkthdr.len > MHLEN) {
1474 MCLGET(m_new, M_DONTWAIT);
1475 if (!(m_new->m_flags & M_EXT)) {
1476 m_freem(m_new);
1477 return(1);
1478 }
1479 }
1480 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1481 mtod(m_new, caddr_t));
1482 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1483 m_freem(m_head);
1484 m_head = m_new;
1485 f = &c->wb_ptr->wb_frag[0];
1486 f->wb_status = 0;
1487 f->wb_data = vtophys(mtod(m_new, caddr_t));
1488 f->wb_ctl = total_len = m_new->m_len;
1489 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1490 frag = 1;
1491 }
1492
1493 if (total_len < WB_MIN_FRAMELEN) {
1494 f = &c->wb_ptr->wb_frag[frag];
1495 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1496 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1497 f->wb_ctl |= WB_TXCTL_TLINK;
1498 f->wb_status = WB_TXSTAT_OWN;
1499 frag++;
1500 }
1501
1502 c->wb_mbuf = m_head;
1503 c->wb_lastdesc = frag - 1;
1504 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1505 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1506
1507 return(0);
1508 }
1509
1510 /*
1511 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1512 * to the mbuf data regions directly in the transmit lists. We also save a
1513 * copy of the pointers since the transmit list fragment pointers are
1514 * physical addresses.
1515 */
1516
1517 static void
1518 wb_start(ifp)
1519 struct ifnet *ifp;
1520 {
1521 struct wb_softc *sc;
1522 struct mbuf *m_head = NULL;
1523 struct wb_chain *cur_tx = NULL, *start_tx;
1524
1525 sc = ifp->if_softc;
1526 WB_LOCK(sc);
1527
1528 /*
1529 * Check for an available queue slot. If there are none,
1530 * punt.
1531 */
1532 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1533 ifp->if_flags |= IFF_OACTIVE;
1534 WB_UNLOCK(sc);
1535 return;
1536 }
1537
1538 start_tx = sc->wb_cdata.wb_tx_free;
1539
1540 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1541 IF_DEQUEUE(&ifp->if_snd, m_head);
1542 if (m_head == NULL)
1543 break;
1544
1545 /* Pick a descriptor off the free list. */
1546 cur_tx = sc->wb_cdata.wb_tx_free;
1547 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1548
1549 /* Pack the data into the descriptor. */
1550 wb_encap(sc, cur_tx, m_head);
1551
1552 if (cur_tx != start_tx)
1553 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1554
1555 /*
1556 * If there's a BPF listener, bounce a copy of this frame
1557 * to him.
1558 */
1559 BPF_MTAP(ifp, cur_tx->wb_mbuf);
1560 }
1561
1562 /*
1563 * If there are no packets queued, bail.
1564 */
1565 if (cur_tx == NULL) {
1566 WB_UNLOCK(sc);
1567 return;
1568 }
1569
1570 /*
1571 * Place the request for the upload interrupt
1572 * in the last descriptor in the chain. This way, if
1573 * we're chaining several packets at once, we'll only
1574 * get an interupt once for the whole chain rather than
1575 * once for each packet.
1576 */
1577 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1578 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1579 sc->wb_cdata.wb_tx_tail = cur_tx;
1580
1581 if (sc->wb_cdata.wb_tx_head == NULL) {
1582 sc->wb_cdata.wb_tx_head = start_tx;
1583 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1584 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1585 } else {
1586 /*
1587 * We need to distinguish between the case where
1588 * the own bit is clear because the chip cleared it
1589 * and where the own bit is clear because we haven't
1590 * set it yet. The magic value WB_UNSET is just some
1591 * ramdomly chosen number which doesn't have the own
1592 * bit set. When we actually transmit the frame, the
1593 * status word will have _only_ the own bit set, so
1594 * the txeoc handler will be able to tell if it needs
1595 * to initiate another transmission to flush out pending
1596 * frames.
1597 */
1598 WB_TXOWN(start_tx) = WB_UNSENT;
1599 }
1600
1601 /*
1602 * Set a timeout in case the chip goes out to lunch.
1603 */
1604 ifp->if_timer = 5;
1605 WB_UNLOCK(sc);
1606
1607 return;
1608 }
1609
1610 static void
1611 wb_init(xsc)
1612 void *xsc;
1613 {
1614 struct wb_softc *sc = xsc;
1615 struct ifnet *ifp = &sc->arpcom.ac_if;
1616 int i;
1617 struct mii_data *mii;
1618
1619 WB_LOCK(sc);
1620 mii = device_get_softc(sc->wb_miibus);
1621
1622 /*
1623 * Cancel pending I/O and free all RX/TX buffers.
1624 */
1625 wb_stop(sc);
1626 wb_reset(sc);
1627
1628 sc->wb_txthresh = WB_TXTHRESH_INIT;
1629
1630 /*
1631 * Set cache alignment and burst length.
1632 */
1633 #ifdef foo
1634 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1635 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1636 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1637 #endif
1638
1639 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION);
1640 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
1641 switch(sc->wb_cachesize) {
1642 case 32:
1643 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
1644 break;
1645 case 16:
1646 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
1647 break;
1648 case 8:
1649 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
1650 break;
1651 case 0:
1652 default:
1653 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
1654 break;
1655 }
1656
1657 /* This doesn't tend to work too well at 100Mbps. */
1658 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1659
1660 /* Init our MAC address */
1661 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1662 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]);
1663 }
1664
1665 /* Init circular RX list. */
1666 if (wb_list_rx_init(sc) == ENOBUFS) {
1667 printf("wb%d: initialization failed: no "
1668 "memory for rx buffers\n", sc->wb_unit);
1669 wb_stop(sc);
1670 WB_UNLOCK(sc);
1671 return;
1672 }
1673
1674 /* Init TX descriptors. */
1675 wb_list_tx_init(sc);
1676
1677 /* If we want promiscuous mode, set the allframes bit. */
1678 if (ifp->if_flags & IFF_PROMISC) {
1679 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1680 } else {
1681 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1682 }
1683
1684 /*
1685 * Set capture broadcast bit to capture broadcast frames.
1686 */
1687 if (ifp->if_flags & IFF_BROADCAST) {
1688 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1689 } else {
1690 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1691 }
1692
1693 /*
1694 * Program the multicast filter, if necessary.
1695 */
1696 wb_setmulti(sc);
1697
1698 /*
1699 * Load the address of the RX list.
1700 */
1701 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1702 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1703
1704 /*
1705 * Enable interrupts.
1706 */
1707 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1708 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1709
1710 /* Enable receiver and transmitter. */
1711 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1712 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1713
1714 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1715 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1716 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1717
1718 mii_mediachg(mii);
1719
1720 ifp->if_flags |= IFF_RUNNING;
1721 ifp->if_flags &= ~IFF_OACTIVE;
1722
1723 sc->wb_stat_ch = timeout(wb_tick, sc, hz);
1724 WB_UNLOCK(sc);
1725
1726 return;
1727 }
1728
1729 /*
1730 * Set media options.
1731 */
1732 static int
1733 wb_ifmedia_upd(ifp)
1734 struct ifnet *ifp;
1735 {
1736 struct wb_softc *sc;
1737
1738 sc = ifp->if_softc;
1739
1740 if (ifp->if_flags & IFF_UP)
1741 wb_init(sc);
1742
1743 return(0);
1744 }
1745
1746 /*
1747 * Report current media status.
1748 */
1749 static void
1750 wb_ifmedia_sts(ifp, ifmr)
1751 struct ifnet *ifp;
1752 struct ifmediareq *ifmr;
1753 {
1754 struct wb_softc *sc;
1755 struct mii_data *mii;
1756
1757 sc = ifp->if_softc;
1758
1759 mii = device_get_softc(sc->wb_miibus);
1760
1761 mii_pollstat(mii);
1762 ifmr->ifm_active = mii->mii_media_active;
1763 ifmr->ifm_status = mii->mii_media_status;
1764
1765 return;
1766 }
1767
1768 static int
1769 wb_ioctl(ifp, command, data)
1770 struct ifnet *ifp;
1771 u_long command;
1772 caddr_t data;
1773 {
1774 struct wb_softc *sc = ifp->if_softc;
1775 struct mii_data *mii;
1776 struct ifreq *ifr = (struct ifreq *) data;
1777 int error = 0;
1778
1779 WB_LOCK(sc);
1780
1781 switch(command) {
1782 case SIOCSIFFLAGS:
1783 if (ifp->if_flags & IFF_UP) {
1784 wb_init(sc);
1785 } else {
1786 if (ifp->if_flags & IFF_RUNNING)
1787 wb_stop(sc);
1788 }
1789 error = 0;
1790 break;
1791 case SIOCADDMULTI:
1792 case SIOCDELMULTI:
1793 wb_setmulti(sc);
1794 error = 0;
1795 break;
1796 case SIOCGIFMEDIA:
1797 case SIOCSIFMEDIA:
1798 mii = device_get_softc(sc->wb_miibus);
1799 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1800 break;
1801 default:
1802 error = ether_ioctl(ifp, command, data);
1803 break;
1804 }
1805
1806 WB_UNLOCK(sc);
1807
1808 return(error);
1809 }
1810
1811 static void
1812 wb_watchdog(ifp)
1813 struct ifnet *ifp;
1814 {
1815 struct wb_softc *sc;
1816
1817 sc = ifp->if_softc;
1818
1819 WB_LOCK(sc);
1820 ifp->if_oerrors++;
1821 printf("wb%d: watchdog timeout\n", sc->wb_unit);
1822 #ifdef foo
1823 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1824 printf("wb%d: no carrier - transceiver cable problem?\n",
1825 sc->wb_unit);
1826 #endif
1827 wb_stop(sc);
1828 wb_reset(sc);
1829 wb_init(sc);
1830
1831 if (ifp->if_snd.ifq_head != NULL)
1832 wb_start(ifp);
1833 WB_UNLOCK(sc);
1834
1835 return;
1836 }
1837
1838 /*
1839 * Stop the adapter and free any mbufs allocated to the
1840 * RX and TX lists.
1841 */
1842 static void
1843 wb_stop(sc)
1844 struct wb_softc *sc;
1845 {
1846 register int i;
1847 struct ifnet *ifp;
1848
1849 WB_LOCK(sc);
1850 ifp = &sc->arpcom.ac_if;
1851 ifp->if_timer = 0;
1852
1853 untimeout(wb_tick, sc, sc->wb_stat_ch);
1854
1855 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
1856 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1857 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
1858 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
1859
1860 /*
1861 * Free data in the RX lists.
1862 */
1863 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1864 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
1865 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
1866 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
1867 }
1868 }
1869 bzero((char *)&sc->wb_ldata->wb_rx_list,
1870 sizeof(sc->wb_ldata->wb_rx_list));
1871
1872 /*
1873 * Free the TX list buffers.
1874 */
1875 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1876 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
1877 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
1878 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
1879 }
1880 }
1881
1882 bzero((char *)&sc->wb_ldata->wb_tx_list,
1883 sizeof(sc->wb_ldata->wb_tx_list));
1884
1885 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1886 WB_UNLOCK(sc);
1887
1888 return;
1889 }
1890
1891 /*
1892 * Stop all chip I/O so that the kernel's probe routines don't
1893 * get confused by errant DMAs when rebooting.
1894 */
1895 static void
1896 wb_shutdown(dev)
1897 device_t dev;
1898 {
1899 struct wb_softc *sc;
1900
1901 sc = device_get_softc(dev);
1902 wb_stop(sc);
1903
1904 return;
1905 }
Cache object: d023907540a117ce0287a4f099b3e4e8
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