Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_wb.c
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1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Winbond fast ethernet PCI NIC driver 35 * 36 * Supports various cheap network adapters based on the Winbond W89C840F 37 * fast ethernet controller chip. This includes adapters manufactured by 38 * Winbond itself and some made by Linksys. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45 /* 46 * The Winbond W89C840F chip is a bus master; in some ways it resembles 47 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 48 * one major difference which is that while the registers do many of 49 * the same things as a tulip adapter, the offsets are different: where 50 * tulip registers are typically spaced 8 bytes apart, the Winbond 51 * registers are spaced 4 bytes apart. The receiver filter is also 52 * programmed differently. 53 * 54 * Like the tulip, the Winbond chip uses small descriptors containing 55 * a status word, a control word and 32-bit areas that can either be used 56 * to point to two external data blocks, or to point to a single block 57 * and another descriptor in a linked list. Descriptors can be grouped 58 * together in blocks to form fixed length rings or can be chained 59 * together in linked lists. A single packet may be spread out over 60 * several descriptors if necessary. 61 * 62 * For the receive ring, this driver uses a linked list of descriptors, 63 * each pointing to a single mbuf cluster buffer, which us large enough 64 * to hold an entire packet. The link list is looped back to created a 65 * closed ring. 66 * 67 * For transmission, the driver creates a linked list of 'super descriptors' 68 * which each contain several individual descriptors linked toghether. 69 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 70 * abuse as fragment pointers. This allows us to use a buffer managment 71 * scheme very similar to that used in the ThunderLAN and Etherlink XL 72 * drivers. 73 * 74 * Autonegotiation is performed using the external PHY via the MII bus. 75 * The sample boards I have all use a Davicom PHY. 76 * 77 * Note: the author of the Linux driver for the Winbond chip alludes 78 * to some sort of flaw in the chip's design that seems to mandate some 79 * drastic workaround which signigicantly impairs transmit performance. 80 * I have no idea what he's on about: transmit performance with all 81 * three of my test boards seems fine. 82 */ 83 84 #include <sys/cdefs.h> 85 __FBSDID("$FreeBSD: releng/5.1/sys/pci/if_wb.c 113812 2003-04-21 18:34:04Z imp $"); 86 87 #include "opt_bdg.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/queue.h> 97 98 #include <net/if.h> 99 #include <net/if_arp.h> 100 #include <net/ethernet.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 104 #include <net/bpf.h> 105 106 #include <vm/vm.h> /* for vtophys */ 107 #include <vm/pmap.h> /* for vtophys */ 108 #include <machine/bus_memio.h> 109 #include <machine/bus_pio.h> 110 #include <machine/bus.h> 111 #include <machine/resource.h> 112 #include <sys/bus.h> 113 #include <sys/rman.h> 114 115 #include <pci/pcireg.h> 116 #include <pci/pcivar.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 121 /* "controller miibus0" required. See GENERIC if you get errors here. */ 122 #include "miibus_if.h" 123 124 #define WB_USEIOSPACE 125 126 #include <pci/if_wbreg.h> 127 128 MODULE_DEPEND(wb, pci, 1, 1, 1); 129 MODULE_DEPEND(wb, ether, 1, 1, 1); 130 MODULE_DEPEND(wb, miibus, 1, 1, 1); 131 132 /* 133 * Various supported device vendors/types and their names. 134 */ 135 static struct wb_type wb_devs[] = { 136 { WB_VENDORID, WB_DEVICEID_840F, 137 "Winbond W89C840F 10/100BaseTX" }, 138 { CP_VENDORID, CP_DEVICEID_RL100, 139 "Compex RL100-ATX 10/100baseTX" }, 140 { 0, 0, NULL } 141 }; 142 143 static int wb_probe (device_t); 144 static int wb_attach (device_t); 145 static int wb_detach (device_t); 146 147 static void wb_bfree (void *addr, void *args); 148 static int wb_newbuf (struct wb_softc *, 149 struct wb_chain_onefrag *, 150 struct mbuf *); 151 static int wb_encap (struct wb_softc *, struct wb_chain *, 152 struct mbuf *); 153 154 static void wb_rxeof (struct wb_softc *); 155 static void wb_rxeoc (struct wb_softc *); 156 static void wb_txeof (struct wb_softc *); 157 static void wb_txeoc (struct wb_softc *); 158 static void wb_intr (void *); 159 static void wb_tick (void *); 160 static void wb_start (struct ifnet *); 161 static int wb_ioctl (struct ifnet *, u_long, caddr_t); 162 static void wb_init (void *); 163 static void wb_stop (struct wb_softc *); 164 static void wb_watchdog (struct ifnet *); 165 static void wb_shutdown (device_t); 166 static int wb_ifmedia_upd (struct ifnet *); 167 static void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 168 169 static void wb_eeprom_putbyte (struct wb_softc *, int); 170 static void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 171 static void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int); 172 static void wb_mii_sync (struct wb_softc *); 173 static void wb_mii_send (struct wb_softc *, u_int32_t, int); 174 static int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 175 static int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 176 177 static void wb_setcfg (struct wb_softc *, u_int32_t); 178 static u_int8_t wb_calchash (caddr_t); 179 static void wb_setmulti (struct wb_softc *); 180 static void wb_reset (struct wb_softc *); 181 static void wb_fixmedia (struct wb_softc *); 182 static int wb_list_rx_init (struct wb_softc *); 183 static int wb_list_tx_init (struct wb_softc *); 184 185 static int wb_miibus_readreg (device_t, int, int); 186 static int wb_miibus_writereg (device_t, int, int, int); 187 static void wb_miibus_statchg (device_t); 188 189 #ifdef WB_USEIOSPACE 190 #define WB_RES SYS_RES_IOPORT 191 #define WB_RID WB_PCI_LOIO 192 #else 193 #define WB_RES SYS_RES_MEMORY 194 #define WB_RID WB_PCI_LOMEM 195 #endif 196 197 static device_method_t wb_methods[] = { 198 /* Device interface */ 199 DEVMETHOD(device_probe, wb_probe), 200 DEVMETHOD(device_attach, wb_attach), 201 DEVMETHOD(device_detach, wb_detach), 202 DEVMETHOD(device_shutdown, wb_shutdown), 203 204 /* bus interface, for miibus */ 205 DEVMETHOD(bus_print_child, bus_generic_print_child), 206 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 207 208 /* MII interface */ 209 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 210 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 211 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 212 { 0, 0 } 213 }; 214 215 static driver_t wb_driver = { 216 "wb", 217 wb_methods, 218 sizeof(struct wb_softc) 219 }; 220 221 static devclass_t wb_devclass; 222 223 DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 224 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 225 226 #define WB_SETBIT(sc, reg, x) \ 227 CSR_WRITE_4(sc, reg, \ 228 CSR_READ_4(sc, reg) | (x)) 229 230 #define WB_CLRBIT(sc, reg, x) \ 231 CSR_WRITE_4(sc, reg, \ 232 CSR_READ_4(sc, reg) & ~(x)) 233 234 #define SIO_SET(x) \ 235 CSR_WRITE_4(sc, WB_SIO, \ 236 CSR_READ_4(sc, WB_SIO) | (x)) 237 238 #define SIO_CLR(x) \ 239 CSR_WRITE_4(sc, WB_SIO, \ 240 CSR_READ_4(sc, WB_SIO) & ~(x)) 241 242 /* 243 * Send a read command and address to the EEPROM, check for ACK. 244 */ 245 static void 246 wb_eeprom_putbyte(sc, addr) 247 struct wb_softc *sc; 248 int addr; 249 { 250 register int d, i; 251 252 d = addr | WB_EECMD_READ; 253 254 /* 255 * Feed in each bit and stobe the clock. 256 */ 257 for (i = 0x400; i; i >>= 1) { 258 if (d & i) { 259 SIO_SET(WB_SIO_EE_DATAIN); 260 } else { 261 SIO_CLR(WB_SIO_EE_DATAIN); 262 } 263 DELAY(100); 264 SIO_SET(WB_SIO_EE_CLK); 265 DELAY(150); 266 SIO_CLR(WB_SIO_EE_CLK); 267 DELAY(100); 268 } 269 270 return; 271 } 272 273 /* 274 * Read a word of data stored in the EEPROM at address 'addr.' 275 */ 276 static void 277 wb_eeprom_getword(sc, addr, dest) 278 struct wb_softc *sc; 279 int addr; 280 u_int16_t *dest; 281 { 282 register int i; 283 u_int16_t word = 0; 284 285 /* Enter EEPROM access mode. */ 286 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 287 288 /* 289 * Send address of word we want to read. 290 */ 291 wb_eeprom_putbyte(sc, addr); 292 293 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 294 295 /* 296 * Start reading bits from EEPROM. 297 */ 298 for (i = 0x8000; i; i >>= 1) { 299 SIO_SET(WB_SIO_EE_CLK); 300 DELAY(100); 301 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 302 word |= i; 303 SIO_CLR(WB_SIO_EE_CLK); 304 DELAY(100); 305 } 306 307 /* Turn off EEPROM access mode. */ 308 CSR_WRITE_4(sc, WB_SIO, 0); 309 310 *dest = word; 311 312 return; 313 } 314 315 /* 316 * Read a sequence of words from the EEPROM. 317 */ 318 static void 319 wb_read_eeprom(sc, dest, off, cnt, swap) 320 struct wb_softc *sc; 321 caddr_t dest; 322 int off; 323 int cnt; 324 int swap; 325 { 326 int i; 327 u_int16_t word = 0, *ptr; 328 329 for (i = 0; i < cnt; i++) { 330 wb_eeprom_getword(sc, off + i, &word); 331 ptr = (u_int16_t *)(dest + (i * 2)); 332 if (swap) 333 *ptr = ntohs(word); 334 else 335 *ptr = word; 336 } 337 338 return; 339 } 340 341 /* 342 * Sync the PHYs by setting data bit and strobing the clock 32 times. 343 */ 344 static void 345 wb_mii_sync(sc) 346 struct wb_softc *sc; 347 { 348 register int i; 349 350 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 351 352 for (i = 0; i < 32; i++) { 353 SIO_SET(WB_SIO_MII_CLK); 354 DELAY(1); 355 SIO_CLR(WB_SIO_MII_CLK); 356 DELAY(1); 357 } 358 359 return; 360 } 361 362 /* 363 * Clock a series of bits through the MII. 364 */ 365 static void 366 wb_mii_send(sc, bits, cnt) 367 struct wb_softc *sc; 368 u_int32_t bits; 369 int cnt; 370 { 371 int i; 372 373 SIO_CLR(WB_SIO_MII_CLK); 374 375 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 376 if (bits & i) { 377 SIO_SET(WB_SIO_MII_DATAIN); 378 } else { 379 SIO_CLR(WB_SIO_MII_DATAIN); 380 } 381 DELAY(1); 382 SIO_CLR(WB_SIO_MII_CLK); 383 DELAY(1); 384 SIO_SET(WB_SIO_MII_CLK); 385 } 386 } 387 388 /* 389 * Read an PHY register through the MII. 390 */ 391 static int 392 wb_mii_readreg(sc, frame) 393 struct wb_softc *sc; 394 struct wb_mii_frame *frame; 395 396 { 397 int i, ack; 398 399 WB_LOCK(sc); 400 401 /* 402 * Set up frame for RX. 403 */ 404 frame->mii_stdelim = WB_MII_STARTDELIM; 405 frame->mii_opcode = WB_MII_READOP; 406 frame->mii_turnaround = 0; 407 frame->mii_data = 0; 408 409 CSR_WRITE_4(sc, WB_SIO, 0); 410 411 /* 412 * Turn on data xmit. 413 */ 414 SIO_SET(WB_SIO_MII_DIR); 415 416 wb_mii_sync(sc); 417 418 /* 419 * Send command/address info. 420 */ 421 wb_mii_send(sc, frame->mii_stdelim, 2); 422 wb_mii_send(sc, frame->mii_opcode, 2); 423 wb_mii_send(sc, frame->mii_phyaddr, 5); 424 wb_mii_send(sc, frame->mii_regaddr, 5); 425 426 /* Idle bit */ 427 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 428 DELAY(1); 429 SIO_SET(WB_SIO_MII_CLK); 430 DELAY(1); 431 432 /* Turn off xmit. */ 433 SIO_CLR(WB_SIO_MII_DIR); 434 /* Check for ack */ 435 SIO_CLR(WB_SIO_MII_CLK); 436 DELAY(1); 437 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 438 SIO_SET(WB_SIO_MII_CLK); 439 DELAY(1); 440 SIO_CLR(WB_SIO_MII_CLK); 441 DELAY(1); 442 SIO_SET(WB_SIO_MII_CLK); 443 DELAY(1); 444 445 /* 446 * Now try reading data bits. If the ack failed, we still 447 * need to clock through 16 cycles to keep the PHY(s) in sync. 448 */ 449 if (ack) { 450 for(i = 0; i < 16; i++) { 451 SIO_CLR(WB_SIO_MII_CLK); 452 DELAY(1); 453 SIO_SET(WB_SIO_MII_CLK); 454 DELAY(1); 455 } 456 goto fail; 457 } 458 459 for (i = 0x8000; i; i >>= 1) { 460 SIO_CLR(WB_SIO_MII_CLK); 461 DELAY(1); 462 if (!ack) { 463 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 464 frame->mii_data |= i; 465 DELAY(1); 466 } 467 SIO_SET(WB_SIO_MII_CLK); 468 DELAY(1); 469 } 470 471 fail: 472 473 SIO_CLR(WB_SIO_MII_CLK); 474 DELAY(1); 475 SIO_SET(WB_SIO_MII_CLK); 476 DELAY(1); 477 478 WB_UNLOCK(sc); 479 480 if (ack) 481 return(1); 482 return(0); 483 } 484 485 /* 486 * Write to a PHY register through the MII. 487 */ 488 static int 489 wb_mii_writereg(sc, frame) 490 struct wb_softc *sc; 491 struct wb_mii_frame *frame; 492 493 { 494 WB_LOCK(sc); 495 496 /* 497 * Set up frame for TX. 498 */ 499 500 frame->mii_stdelim = WB_MII_STARTDELIM; 501 frame->mii_opcode = WB_MII_WRITEOP; 502 frame->mii_turnaround = WB_MII_TURNAROUND; 503 504 /* 505 * Turn on data output. 506 */ 507 SIO_SET(WB_SIO_MII_DIR); 508 509 wb_mii_sync(sc); 510 511 wb_mii_send(sc, frame->mii_stdelim, 2); 512 wb_mii_send(sc, frame->mii_opcode, 2); 513 wb_mii_send(sc, frame->mii_phyaddr, 5); 514 wb_mii_send(sc, frame->mii_regaddr, 5); 515 wb_mii_send(sc, frame->mii_turnaround, 2); 516 wb_mii_send(sc, frame->mii_data, 16); 517 518 /* Idle bit. */ 519 SIO_SET(WB_SIO_MII_CLK); 520 DELAY(1); 521 SIO_CLR(WB_SIO_MII_CLK); 522 DELAY(1); 523 524 /* 525 * Turn off xmit. 526 */ 527 SIO_CLR(WB_SIO_MII_DIR); 528 529 WB_UNLOCK(sc); 530 531 return(0); 532 } 533 534 static int 535 wb_miibus_readreg(dev, phy, reg) 536 device_t dev; 537 int phy, reg; 538 { 539 struct wb_softc *sc; 540 struct wb_mii_frame frame; 541 542 sc = device_get_softc(dev); 543 544 bzero((char *)&frame, sizeof(frame)); 545 546 frame.mii_phyaddr = phy; 547 frame.mii_regaddr = reg; 548 wb_mii_readreg(sc, &frame); 549 550 return(frame.mii_data); 551 } 552 553 static int 554 wb_miibus_writereg(dev, phy, reg, data) 555 device_t dev; 556 int phy, reg, data; 557 { 558 struct wb_softc *sc; 559 struct wb_mii_frame frame; 560 561 sc = device_get_softc(dev); 562 563 bzero((char *)&frame, sizeof(frame)); 564 565 frame.mii_phyaddr = phy; 566 frame.mii_regaddr = reg; 567 frame.mii_data = data; 568 569 wb_mii_writereg(sc, &frame); 570 571 return(0); 572 } 573 574 static void 575 wb_miibus_statchg(dev) 576 device_t dev; 577 { 578 struct wb_softc *sc; 579 struct mii_data *mii; 580 581 sc = device_get_softc(dev); 582 WB_LOCK(sc); 583 mii = device_get_softc(sc->wb_miibus); 584 wb_setcfg(sc, mii->mii_media_active); 585 WB_UNLOCK(sc); 586 587 return; 588 } 589 590 static u_int8_t wb_calchash(addr) 591 caddr_t addr; 592 { 593 u_int32_t crc, carry; 594 int i, j; 595 u_int8_t c; 596 597 /* Compute CRC for the address value. */ 598 crc = 0xFFFFFFFF; /* initial value */ 599 600 for (i = 0; i < 6; i++) { 601 c = *(addr + i); 602 for (j = 0; j < 8; j++) { 603 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 604 crc <<= 1; 605 c >>= 1; 606 if (carry) 607 crc = (crc ^ 0x04c11db6) | carry; 608 } 609 } 610 611 /* 612 * return the filter bit position 613 * Note: I arrived at the following nonsense 614 * through experimentation. It's not the usual way to 615 * generate the bit position but it's the only thing 616 * I could come up with that works. 617 */ 618 return(~(crc >> 26) & 0x0000003F); 619 } 620 621 /* 622 * Program the 64-bit multicast hash filter. 623 */ 624 static void 625 wb_setmulti(sc) 626 struct wb_softc *sc; 627 { 628 struct ifnet *ifp; 629 int h = 0; 630 u_int32_t hashes[2] = { 0, 0 }; 631 struct ifmultiaddr *ifma; 632 u_int32_t rxfilt; 633 int mcnt = 0; 634 635 ifp = &sc->arpcom.ac_if; 636 637 rxfilt = CSR_READ_4(sc, WB_NETCFG); 638 639 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 640 rxfilt |= WB_NETCFG_RX_MULTI; 641 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 642 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 643 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 644 return; 645 } 646 647 /* first, zot all the existing hash bits */ 648 CSR_WRITE_4(sc, WB_MAR0, 0); 649 CSR_WRITE_4(sc, WB_MAR1, 0); 650 651 /* now program new ones */ 652 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 653 if (ifma->ifma_addr->sa_family != AF_LINK) 654 continue; 655 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 656 if (h < 32) 657 hashes[0] |= (1 << h); 658 else 659 hashes[1] |= (1 << (h - 32)); 660 mcnt++; 661 } 662 663 if (mcnt) 664 rxfilt |= WB_NETCFG_RX_MULTI; 665 else 666 rxfilt &= ~WB_NETCFG_RX_MULTI; 667 668 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 669 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 670 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 671 672 return; 673 } 674 675 /* 676 * The Winbond manual states that in order to fiddle with the 677 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 678 * first have to put the transmit and/or receive logic in the idle state. 679 */ 680 static void 681 wb_setcfg(sc, media) 682 struct wb_softc *sc; 683 u_int32_t media; 684 { 685 int i, restart = 0; 686 687 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 688 restart = 1; 689 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 690 691 for (i = 0; i < WB_TIMEOUT; i++) { 692 DELAY(10); 693 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 694 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 695 break; 696 } 697 698 if (i == WB_TIMEOUT) 699 printf("wb%d: failed to force tx and " 700 "rx to idle state\n", sc->wb_unit); 701 } 702 703 if (IFM_SUBTYPE(media) == IFM_10_T) 704 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 705 else 706 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 707 708 if ((media & IFM_GMASK) == IFM_FDX) 709 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 710 else 711 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 712 713 if (restart) 714 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 715 716 return; 717 } 718 719 static void 720 wb_reset(sc) 721 struct wb_softc *sc; 722 { 723 register int i; 724 struct mii_data *mii; 725 726 CSR_WRITE_4(sc, WB_NETCFG, 0); 727 CSR_WRITE_4(sc, WB_BUSCTL, 0); 728 CSR_WRITE_4(sc, WB_TXADDR, 0); 729 CSR_WRITE_4(sc, WB_RXADDR, 0); 730 731 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 732 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 733 734 for (i = 0; i < WB_TIMEOUT; i++) { 735 DELAY(10); 736 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 737 break; 738 } 739 if (i == WB_TIMEOUT) 740 printf("wb%d: reset never completed!\n", sc->wb_unit); 741 742 /* Wait a little while for the chip to get its brains in order. */ 743 DELAY(1000); 744 745 if (sc->wb_miibus == NULL) 746 return; 747 748 mii = device_get_softc(sc->wb_miibus); 749 if (mii == NULL) 750 return; 751 752 if (mii->mii_instance) { 753 struct mii_softc *miisc; 754 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 755 mii_phy_reset(miisc); 756 } 757 758 return; 759 } 760 761 static void 762 wb_fixmedia(sc) 763 struct wb_softc *sc; 764 { 765 struct mii_data *mii = NULL; 766 struct ifnet *ifp; 767 u_int32_t media; 768 769 if (sc->wb_miibus == NULL) 770 return; 771 772 mii = device_get_softc(sc->wb_miibus); 773 ifp = &sc->arpcom.ac_if; 774 775 mii_pollstat(mii); 776 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 777 media = mii->mii_media_active & ~IFM_10_T; 778 media |= IFM_100_TX; 779 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 780 media = mii->mii_media_active & ~IFM_100_TX; 781 media |= IFM_10_T; 782 } else 783 return; 784 785 ifmedia_set(&mii->mii_media, media); 786 787 return; 788 } 789 790 /* 791 * Probe for a Winbond chip. Check the PCI vendor and device 792 * IDs against our list and return a device name if we find a match. 793 */ 794 static int 795 wb_probe(dev) 796 device_t dev; 797 { 798 struct wb_type *t; 799 800 t = wb_devs; 801 802 while(t->wb_name != NULL) { 803 if ((pci_get_vendor(dev) == t->wb_vid) && 804 (pci_get_device(dev) == t->wb_did)) { 805 device_set_desc(dev, t->wb_name); 806 return(0); 807 } 808 t++; 809 } 810 811 return(ENXIO); 812 } 813 814 /* 815 * Attach the interface. Allocate softc structures, do ifmedia 816 * setup and ethernet/BPF attach. 817 */ 818 static int 819 wb_attach(dev) 820 device_t dev; 821 { 822 u_char eaddr[ETHER_ADDR_LEN]; 823 struct wb_softc *sc; 824 struct ifnet *ifp; 825 int unit, error = 0, rid; 826 827 sc = device_get_softc(dev); 828 unit = device_get_unit(dev); 829 830 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 831 MTX_DEF | MTX_RECURSE); 832 833 /* 834 * Handle power management nonsense. 835 */ 836 837 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 838 u_int32_t iobase, membase, irq; 839 840 /* Save important PCI config data. */ 841 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 842 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 843 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 844 845 /* Reset the power state. */ 846 printf("wb%d: chip is in D%d power mode " 847 "-- setting to D0\n", unit, 848 pci_get_powerstate(dev)); 849 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 850 851 /* Restore PCI config data. */ 852 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 853 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 854 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 855 } 856 857 /* 858 * Map control/status registers. 859 */ 860 pci_enable_busmaster(dev); 861 862 rid = WB_RID; 863 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 864 0, ~0, 1, RF_ACTIVE); 865 866 if (sc->wb_res == NULL) { 867 printf("wb%d: couldn't map ports/memory\n", unit); 868 error = ENXIO; 869 goto fail; 870 } 871 872 sc->wb_btag = rman_get_bustag(sc->wb_res); 873 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 874 875 /* Allocate interrupt */ 876 rid = 0; 877 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 878 RF_SHAREABLE | RF_ACTIVE); 879 880 if (sc->wb_irq == NULL) { 881 printf("wb%d: couldn't map interrupt\n", unit); 882 error = ENXIO; 883 goto fail; 884 } 885 886 /* Save the cache line size. */ 887 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 888 889 /* Reset the adapter. */ 890 wb_reset(sc); 891 892 /* 893 * Get station address from the EEPROM. 894 */ 895 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 896 897 /* 898 * A Winbond chip was detected. Inform the world. 899 */ 900 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 901 902 sc->wb_unit = unit; 903 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 904 905 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 906 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 907 908 if (sc->wb_ldata == NULL) { 909 printf("wb%d: no memory for list buffers!\n", unit); 910 error = ENXIO; 911 goto fail; 912 } 913 914 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 915 916 ifp = &sc->arpcom.ac_if; 917 ifp->if_softc = sc; 918 ifp->if_unit = unit; 919 ifp->if_name = "wb"; 920 ifp->if_mtu = ETHERMTU; 921 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 922 ifp->if_ioctl = wb_ioctl; 923 ifp->if_output = ether_output; 924 ifp->if_start = wb_start; 925 ifp->if_watchdog = wb_watchdog; 926 ifp->if_init = wb_init; 927 ifp->if_baudrate = 10000000; 928 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 929 930 /* 931 * Do MII setup. 932 */ 933 if (mii_phy_probe(dev, &sc->wb_miibus, 934 wb_ifmedia_upd, wb_ifmedia_sts)) { 935 error = ENXIO; 936 goto fail; 937 } 938 939 /* 940 * Call MI attach routine. 941 */ 942 ether_ifattach(ifp, eaddr); 943 944 /* Hook interrupt last to avoid having to lock softc */ 945 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 946 wb_intr, sc, &sc->wb_intrhand); 947 948 if (error) { 949 printf("wb%d: couldn't set up irq\n", unit); 950 ether_ifdetach(ifp); 951 goto fail; 952 } 953 954 fail: 955 if (error) 956 wb_detach(dev); 957 958 return(error); 959 } 960 961 /* 962 * Shutdown hardware and free up resources. This can be called any 963 * time after the mutex has been initialized. It is called in both 964 * the error case in attach and the normal detach case so it needs 965 * to be careful about only freeing resources that have actually been 966 * allocated. 967 */ 968 static int 969 wb_detach(dev) 970 device_t dev; 971 { 972 struct wb_softc *sc; 973 struct ifnet *ifp; 974 975 sc = device_get_softc(dev); 976 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 977 WB_LOCK(sc); 978 ifp = &sc->arpcom.ac_if; 979 980 /* 981 * Delete any miibus and phy devices attached to this interface. 982 * This should only be done if attach succeeded. 983 */ 984 if (device_is_attached(dev)) { 985 wb_stop(sc); 986 ether_ifdetach(ifp); 987 } 988 if (sc->wb_miibus) 989 device_delete_child(dev, sc->wb_miibus); 990 bus_generic_detach(dev); 991 992 if (sc->wb_intrhand) 993 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 994 if (sc->wb_irq) 995 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 996 if (sc->wb_res) 997 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 998 999 if (sc->wb_ldata) { 1000 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 1001 M_DEVBUF); 1002 } 1003 1004 WB_UNLOCK(sc); 1005 mtx_destroy(&sc->wb_mtx); 1006 1007 return(0); 1008 } 1009 1010 /* 1011 * Initialize the transmit descriptors. 1012 */ 1013 static int 1014 wb_list_tx_init(sc) 1015 struct wb_softc *sc; 1016 { 1017 struct wb_chain_data *cd; 1018 struct wb_list_data *ld; 1019 int i; 1020 1021 cd = &sc->wb_cdata; 1022 ld = sc->wb_ldata; 1023 1024 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1025 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1026 if (i == (WB_TX_LIST_CNT - 1)) { 1027 cd->wb_tx_chain[i].wb_nextdesc = 1028 &cd->wb_tx_chain[0]; 1029 } else { 1030 cd->wb_tx_chain[i].wb_nextdesc = 1031 &cd->wb_tx_chain[i + 1]; 1032 } 1033 } 1034 1035 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1036 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1037 1038 return(0); 1039 } 1040 1041 1042 /* 1043 * Initialize the RX descriptors and allocate mbufs for them. Note that 1044 * we arrange the descriptors in a closed ring, so that the last descriptor 1045 * points back to the first. 1046 */ 1047 static int 1048 wb_list_rx_init(sc) 1049 struct wb_softc *sc; 1050 { 1051 struct wb_chain_data *cd; 1052 struct wb_list_data *ld; 1053 int i; 1054 1055 cd = &sc->wb_cdata; 1056 ld = sc->wb_ldata; 1057 1058 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1059 cd->wb_rx_chain[i].wb_ptr = 1060 (struct wb_desc *)&ld->wb_rx_list[i]; 1061 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1062 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1063 return(ENOBUFS); 1064 if (i == (WB_RX_LIST_CNT - 1)) { 1065 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1066 ld->wb_rx_list[i].wb_next = 1067 vtophys(&ld->wb_rx_list[0]); 1068 } else { 1069 cd->wb_rx_chain[i].wb_nextdesc = 1070 &cd->wb_rx_chain[i + 1]; 1071 ld->wb_rx_list[i].wb_next = 1072 vtophys(&ld->wb_rx_list[i + 1]); 1073 } 1074 } 1075 1076 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1077 1078 return(0); 1079 } 1080 1081 static void 1082 wb_bfree(buf, args) 1083 void *buf; 1084 void *args; 1085 { 1086 return; 1087 } 1088 1089 /* 1090 * Initialize an RX descriptor and attach an MBUF cluster. 1091 */ 1092 static int 1093 wb_newbuf(sc, c, m) 1094 struct wb_softc *sc; 1095 struct wb_chain_onefrag *c; 1096 struct mbuf *m; 1097 { 1098 struct mbuf *m_new = NULL; 1099 1100 if (m == NULL) { 1101 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1102 if (m_new == NULL) 1103 return(ENOBUFS); 1104 m_new->m_data = c->wb_buf; 1105 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1106 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 1107 EXT_NET_DRV); 1108 } else { 1109 m_new = m; 1110 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1111 m_new->m_data = m_new->m_ext.ext_buf; 1112 } 1113 1114 m_adj(m_new, sizeof(u_int64_t)); 1115 1116 c->wb_mbuf = m_new; 1117 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1118 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1119 c->wb_ptr->wb_status = WB_RXSTAT; 1120 1121 return(0); 1122 } 1123 1124 /* 1125 * A frame has been uploaded: pass the resulting mbuf chain up to 1126 * the higher level protocols. 1127 */ 1128 static void 1129 wb_rxeof(sc) 1130 struct wb_softc *sc; 1131 { 1132 struct mbuf *m = NULL; 1133 struct ifnet *ifp; 1134 struct wb_chain_onefrag *cur_rx; 1135 int total_len = 0; 1136 u_int32_t rxstat; 1137 1138 ifp = &sc->arpcom.ac_if; 1139 1140 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1141 WB_RXSTAT_OWN)) { 1142 struct mbuf *m0 = NULL; 1143 1144 cur_rx = sc->wb_cdata.wb_rx_head; 1145 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1146 1147 m = cur_rx->wb_mbuf; 1148 1149 if ((rxstat & WB_RXSTAT_MIIERR) || 1150 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1151 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1152 !(rxstat & WB_RXSTAT_LASTFRAG) || 1153 !(rxstat & WB_RXSTAT_RXCMP)) { 1154 ifp->if_ierrors++; 1155 wb_newbuf(sc, cur_rx, m); 1156 printf("wb%x: receiver babbling: possible chip " 1157 "bug, forcing reset\n", sc->wb_unit); 1158 wb_fixmedia(sc); 1159 wb_reset(sc); 1160 wb_init(sc); 1161 return; 1162 } 1163 1164 if (rxstat & WB_RXSTAT_RXERR) { 1165 ifp->if_ierrors++; 1166 wb_newbuf(sc, cur_rx, m); 1167 break; 1168 } 1169 1170 /* No errors; receive the packet. */ 1171 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1172 1173 /* 1174 * XXX The Winbond chip includes the CRC with every 1175 * received frame, and there's no way to turn this 1176 * behavior off (at least, I can't find anything in 1177 * the manual that explains how to do it) so we have 1178 * to trim off the CRC manually. 1179 */ 1180 total_len -= ETHER_CRC_LEN; 1181 1182 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1183 NULL); 1184 wb_newbuf(sc, cur_rx, m); 1185 if (m0 == NULL) { 1186 ifp->if_ierrors++; 1187 break; 1188 } 1189 m = m0; 1190 1191 ifp->if_ipackets++; 1192 (*ifp->if_input)(ifp, m); 1193 } 1194 } 1195 1196 static void 1197 wb_rxeoc(sc) 1198 struct wb_softc *sc; 1199 { 1200 wb_rxeof(sc); 1201 1202 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1203 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1204 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1205 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1206 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1207 1208 return; 1209 } 1210 1211 /* 1212 * A frame was downloaded to the chip. It's safe for us to clean up 1213 * the list buffers. 1214 */ 1215 static void 1216 wb_txeof(sc) 1217 struct wb_softc *sc; 1218 { 1219 struct wb_chain *cur_tx; 1220 struct ifnet *ifp; 1221 1222 ifp = &sc->arpcom.ac_if; 1223 1224 /* Clear the timeout timer. */ 1225 ifp->if_timer = 0; 1226 1227 if (sc->wb_cdata.wb_tx_head == NULL) 1228 return; 1229 1230 /* 1231 * Go through our tx list and free mbufs for those 1232 * frames that have been transmitted. 1233 */ 1234 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1235 u_int32_t txstat; 1236 1237 cur_tx = sc->wb_cdata.wb_tx_head; 1238 txstat = WB_TXSTATUS(cur_tx); 1239 1240 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1241 break; 1242 1243 if (txstat & WB_TXSTAT_TXERR) { 1244 ifp->if_oerrors++; 1245 if (txstat & WB_TXSTAT_ABORT) 1246 ifp->if_collisions++; 1247 if (txstat & WB_TXSTAT_LATECOLL) 1248 ifp->if_collisions++; 1249 } 1250 1251 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1252 1253 ifp->if_opackets++; 1254 m_freem(cur_tx->wb_mbuf); 1255 cur_tx->wb_mbuf = NULL; 1256 1257 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1258 sc->wb_cdata.wb_tx_head = NULL; 1259 sc->wb_cdata.wb_tx_tail = NULL; 1260 break; 1261 } 1262 1263 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1264 } 1265 1266 return; 1267 } 1268 1269 /* 1270 * TX 'end of channel' interrupt handler. 1271 */ 1272 static void 1273 wb_txeoc(sc) 1274 struct wb_softc *sc; 1275 { 1276 struct ifnet *ifp; 1277 1278 ifp = &sc->arpcom.ac_if; 1279 1280 ifp->if_timer = 0; 1281 1282 if (sc->wb_cdata.wb_tx_head == NULL) { 1283 ifp->if_flags &= ~IFF_OACTIVE; 1284 sc->wb_cdata.wb_tx_tail = NULL; 1285 } else { 1286 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1287 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1288 ifp->if_timer = 5; 1289 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1290 } 1291 } 1292 1293 return; 1294 } 1295 1296 static void 1297 wb_intr(arg) 1298 void *arg; 1299 { 1300 struct wb_softc *sc; 1301 struct ifnet *ifp; 1302 u_int32_t status; 1303 1304 sc = arg; 1305 WB_LOCK(sc); 1306 ifp = &sc->arpcom.ac_if; 1307 1308 if (!(ifp->if_flags & IFF_UP)) { 1309 WB_UNLOCK(sc); 1310 return; 1311 } 1312 1313 /* Disable interrupts. */ 1314 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1315 1316 for (;;) { 1317 1318 status = CSR_READ_4(sc, WB_ISR); 1319 if (status) 1320 CSR_WRITE_4(sc, WB_ISR, status); 1321 1322 if ((status & WB_INTRS) == 0) 1323 break; 1324 1325 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1326 ifp->if_ierrors++; 1327 wb_reset(sc); 1328 if (status & WB_ISR_RX_ERR) 1329 wb_fixmedia(sc); 1330 wb_init(sc); 1331 continue; 1332 } 1333 1334 if (status & WB_ISR_RX_OK) 1335 wb_rxeof(sc); 1336 1337 if (status & WB_ISR_RX_IDLE) 1338 wb_rxeoc(sc); 1339 1340 if (status & WB_ISR_TX_OK) 1341 wb_txeof(sc); 1342 1343 if (status & WB_ISR_TX_NOBUF) 1344 wb_txeoc(sc); 1345 1346 if (status & WB_ISR_TX_IDLE) { 1347 wb_txeof(sc); 1348 if (sc->wb_cdata.wb_tx_head != NULL) { 1349 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1350 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1351 } 1352 } 1353 1354 if (status & WB_ISR_TX_UNDERRUN) { 1355 ifp->if_oerrors++; 1356 wb_txeof(sc); 1357 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1358 /* Jack up TX threshold */ 1359 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1360 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1361 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1362 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1363 } 1364 1365 if (status & WB_ISR_BUS_ERR) { 1366 wb_reset(sc); 1367 wb_init(sc); 1368 } 1369 1370 } 1371 1372 /* Re-enable interrupts. */ 1373 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1374 1375 if (ifp->if_snd.ifq_head != NULL) { 1376 wb_start(ifp); 1377 } 1378 1379 WB_UNLOCK(sc); 1380 1381 return; 1382 } 1383 1384 static void 1385 wb_tick(xsc) 1386 void *xsc; 1387 { 1388 struct wb_softc *sc; 1389 struct mii_data *mii; 1390 1391 sc = xsc; 1392 WB_LOCK(sc); 1393 mii = device_get_softc(sc->wb_miibus); 1394 1395 mii_tick(mii); 1396 1397 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1398 1399 WB_UNLOCK(sc); 1400 1401 return; 1402 } 1403 1404 /* 1405 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1406 * pointers to the fragment pointers. 1407 */ 1408 static int 1409 wb_encap(sc, c, m_head) 1410 struct wb_softc *sc; 1411 struct wb_chain *c; 1412 struct mbuf *m_head; 1413 { 1414 int frag = 0; 1415 struct wb_desc *f = NULL; 1416 int total_len; 1417 struct mbuf *m; 1418 1419 /* 1420 * Start packing the mbufs in this chain into 1421 * the fragment pointers. Stop when we run out 1422 * of fragments or hit the end of the mbuf chain. 1423 */ 1424 m = m_head; 1425 total_len = 0; 1426 1427 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1428 if (m->m_len != 0) { 1429 if (frag == WB_MAXFRAGS) 1430 break; 1431 total_len += m->m_len; 1432 f = &c->wb_ptr->wb_frag[frag]; 1433 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1434 if (frag == 0) { 1435 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1436 f->wb_status = 0; 1437 } else 1438 f->wb_status = WB_TXSTAT_OWN; 1439 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1440 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1441 frag++; 1442 } 1443 } 1444 1445 /* 1446 * Handle special case: we used up all 16 fragments, 1447 * but we have more mbufs left in the chain. Copy the 1448 * data into an mbuf cluster. Note that we don't 1449 * bother clearing the values in the other fragment 1450 * pointers/counters; it wouldn't gain us anything, 1451 * and would waste cycles. 1452 */ 1453 if (m != NULL) { 1454 struct mbuf *m_new = NULL; 1455 1456 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1457 if (m_new == NULL) 1458 return(1); 1459 if (m_head->m_pkthdr.len > MHLEN) { 1460 MCLGET(m_new, M_DONTWAIT); 1461 if (!(m_new->m_flags & M_EXT)) { 1462 m_freem(m_new); 1463 return(1); 1464 } 1465 } 1466 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1467 mtod(m_new, caddr_t)); 1468 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1469 m_freem(m_head); 1470 m_head = m_new; 1471 f = &c->wb_ptr->wb_frag[0]; 1472 f->wb_status = 0; 1473 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1474 f->wb_ctl = total_len = m_new->m_len; 1475 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1476 frag = 1; 1477 } 1478 1479 if (total_len < WB_MIN_FRAMELEN) { 1480 f = &c->wb_ptr->wb_frag[frag]; 1481 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1482 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1483 f->wb_ctl |= WB_TXCTL_TLINK; 1484 f->wb_status = WB_TXSTAT_OWN; 1485 frag++; 1486 } 1487 1488 c->wb_mbuf = m_head; 1489 c->wb_lastdesc = frag - 1; 1490 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1491 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1492 1493 return(0); 1494 } 1495 1496 /* 1497 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1498 * to the mbuf data regions directly in the transmit lists. We also save a 1499 * copy of the pointers since the transmit list fragment pointers are 1500 * physical addresses. 1501 */ 1502 1503 static void 1504 wb_start(ifp) 1505 struct ifnet *ifp; 1506 { 1507 struct wb_softc *sc; 1508 struct mbuf *m_head = NULL; 1509 struct wb_chain *cur_tx = NULL, *start_tx; 1510 1511 sc = ifp->if_softc; 1512 WB_LOCK(sc); 1513 1514 /* 1515 * Check for an available queue slot. If there are none, 1516 * punt. 1517 */ 1518 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1519 ifp->if_flags |= IFF_OACTIVE; 1520 WB_UNLOCK(sc); 1521 return; 1522 } 1523 1524 start_tx = sc->wb_cdata.wb_tx_free; 1525 1526 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1527 IF_DEQUEUE(&ifp->if_snd, m_head); 1528 if (m_head == NULL) 1529 break; 1530 1531 /* Pick a descriptor off the free list. */ 1532 cur_tx = sc->wb_cdata.wb_tx_free; 1533 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1534 1535 /* Pack the data into the descriptor. */ 1536 wb_encap(sc, cur_tx, m_head); 1537 1538 if (cur_tx != start_tx) 1539 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1540 1541 /* 1542 * If there's a BPF listener, bounce a copy of this frame 1543 * to him. 1544 */ 1545 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1546 } 1547 1548 /* 1549 * If there are no packets queued, bail. 1550 */ 1551 if (cur_tx == NULL) { 1552 WB_UNLOCK(sc); 1553 return; 1554 } 1555 1556 /* 1557 * Place the request for the upload interrupt 1558 * in the last descriptor in the chain. This way, if 1559 * we're chaining several packets at once, we'll only 1560 * get an interupt once for the whole chain rather than 1561 * once for each packet. 1562 */ 1563 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1564 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1565 sc->wb_cdata.wb_tx_tail = cur_tx; 1566 1567 if (sc->wb_cdata.wb_tx_head == NULL) { 1568 sc->wb_cdata.wb_tx_head = start_tx; 1569 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1570 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1571 } else { 1572 /* 1573 * We need to distinguish between the case where 1574 * the own bit is clear because the chip cleared it 1575 * and where the own bit is clear because we haven't 1576 * set it yet. The magic value WB_UNSET is just some 1577 * ramdomly chosen number which doesn't have the own 1578 * bit set. When we actually transmit the frame, the 1579 * status word will have _only_ the own bit set, so 1580 * the txeoc handler will be able to tell if it needs 1581 * to initiate another transmission to flush out pending 1582 * frames. 1583 */ 1584 WB_TXOWN(start_tx) = WB_UNSENT; 1585 } 1586 1587 /* 1588 * Set a timeout in case the chip goes out to lunch. 1589 */ 1590 ifp->if_timer = 5; 1591 WB_UNLOCK(sc); 1592 1593 return; 1594 } 1595 1596 static void 1597 wb_init(xsc) 1598 void *xsc; 1599 { 1600 struct wb_softc *sc = xsc; 1601 struct ifnet *ifp = &sc->arpcom.ac_if; 1602 int i; 1603 struct mii_data *mii; 1604 1605 WB_LOCK(sc); 1606 mii = device_get_softc(sc->wb_miibus); 1607 1608 /* 1609 * Cancel pending I/O and free all RX/TX buffers. 1610 */ 1611 wb_stop(sc); 1612 wb_reset(sc); 1613 1614 sc->wb_txthresh = WB_TXTHRESH_INIT; 1615 1616 /* 1617 * Set cache alignment and burst length. 1618 */ 1619 #ifdef foo 1620 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1621 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1622 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1623 #endif 1624 1625 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1626 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1627 switch(sc->wb_cachesize) { 1628 case 32: 1629 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1630 break; 1631 case 16: 1632 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1633 break; 1634 case 8: 1635 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1636 break; 1637 case 0: 1638 default: 1639 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1640 break; 1641 } 1642 1643 /* This doesn't tend to work too well at 100Mbps. */ 1644 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1645 1646 /* Init our MAC address */ 1647 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1648 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1649 } 1650 1651 /* Init circular RX list. */ 1652 if (wb_list_rx_init(sc) == ENOBUFS) { 1653 printf("wb%d: initialization failed: no " 1654 "memory for rx buffers\n", sc->wb_unit); 1655 wb_stop(sc); 1656 WB_UNLOCK(sc); 1657 return; 1658 } 1659 1660 /* Init TX descriptors. */ 1661 wb_list_tx_init(sc); 1662 1663 /* If we want promiscuous mode, set the allframes bit. */ 1664 if (ifp->if_flags & IFF_PROMISC) { 1665 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1666 } else { 1667 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1668 } 1669 1670 /* 1671 * Set capture broadcast bit to capture broadcast frames. 1672 */ 1673 if (ifp->if_flags & IFF_BROADCAST) { 1674 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1675 } else { 1676 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1677 } 1678 1679 /* 1680 * Program the multicast filter, if necessary. 1681 */ 1682 wb_setmulti(sc); 1683 1684 /* 1685 * Load the address of the RX list. 1686 */ 1687 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1688 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1689 1690 /* 1691 * Enable interrupts. 1692 */ 1693 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1694 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1695 1696 /* Enable receiver and transmitter. */ 1697 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1698 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1699 1700 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1701 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1702 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1703 1704 mii_mediachg(mii); 1705 1706 ifp->if_flags |= IFF_RUNNING; 1707 ifp->if_flags &= ~IFF_OACTIVE; 1708 1709 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1710 WB_UNLOCK(sc); 1711 1712 return; 1713 } 1714 1715 /* 1716 * Set media options. 1717 */ 1718 static int 1719 wb_ifmedia_upd(ifp) 1720 struct ifnet *ifp; 1721 { 1722 struct wb_softc *sc; 1723 1724 sc = ifp->if_softc; 1725 1726 if (ifp->if_flags & IFF_UP) 1727 wb_init(sc); 1728 1729 return(0); 1730 } 1731 1732 /* 1733 * Report current media status. 1734 */ 1735 static void 1736 wb_ifmedia_sts(ifp, ifmr) 1737 struct ifnet *ifp; 1738 struct ifmediareq *ifmr; 1739 { 1740 struct wb_softc *sc; 1741 struct mii_data *mii; 1742 1743 sc = ifp->if_softc; 1744 1745 mii = device_get_softc(sc->wb_miibus); 1746 1747 mii_pollstat(mii); 1748 ifmr->ifm_active = mii->mii_media_active; 1749 ifmr->ifm_status = mii->mii_media_status; 1750 1751 return; 1752 } 1753 1754 static int 1755 wb_ioctl(ifp, command, data) 1756 struct ifnet *ifp; 1757 u_long command; 1758 caddr_t data; 1759 { 1760 struct wb_softc *sc = ifp->if_softc; 1761 struct mii_data *mii; 1762 struct ifreq *ifr = (struct ifreq *) data; 1763 int error = 0; 1764 1765 WB_LOCK(sc); 1766 1767 switch(command) { 1768 case SIOCSIFFLAGS: 1769 if (ifp->if_flags & IFF_UP) { 1770 wb_init(sc); 1771 } else { 1772 if (ifp->if_flags & IFF_RUNNING) 1773 wb_stop(sc); 1774 } 1775 error = 0; 1776 break; 1777 case SIOCADDMULTI: 1778 case SIOCDELMULTI: 1779 wb_setmulti(sc); 1780 error = 0; 1781 break; 1782 case SIOCGIFMEDIA: 1783 case SIOCSIFMEDIA: 1784 mii = device_get_softc(sc->wb_miibus); 1785 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1786 break; 1787 default: 1788 error = ether_ioctl(ifp, command, data); 1789 break; 1790 } 1791 1792 WB_UNLOCK(sc); 1793 1794 return(error); 1795 } 1796 1797 static void 1798 wb_watchdog(ifp) 1799 struct ifnet *ifp; 1800 { 1801 struct wb_softc *sc; 1802 1803 sc = ifp->if_softc; 1804 1805 WB_LOCK(sc); 1806 ifp->if_oerrors++; 1807 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1808 #ifdef foo 1809 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1810 printf("wb%d: no carrier - transceiver cable problem?\n", 1811 sc->wb_unit); 1812 #endif 1813 wb_stop(sc); 1814 wb_reset(sc); 1815 wb_init(sc); 1816 1817 if (ifp->if_snd.ifq_head != NULL) 1818 wb_start(ifp); 1819 WB_UNLOCK(sc); 1820 1821 return; 1822 } 1823 1824 /* 1825 * Stop the adapter and free any mbufs allocated to the 1826 * RX and TX lists. 1827 */ 1828 static void 1829 wb_stop(sc) 1830 struct wb_softc *sc; 1831 { 1832 register int i; 1833 struct ifnet *ifp; 1834 1835 WB_LOCK(sc); 1836 ifp = &sc->arpcom.ac_if; 1837 ifp->if_timer = 0; 1838 1839 untimeout(wb_tick, sc, sc->wb_stat_ch); 1840 1841 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1842 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1843 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1844 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1845 1846 /* 1847 * Free data in the RX lists. 1848 */ 1849 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1850 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1851 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1852 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1853 } 1854 } 1855 bzero((char *)&sc->wb_ldata->wb_rx_list, 1856 sizeof(sc->wb_ldata->wb_rx_list)); 1857 1858 /* 1859 * Free the TX list buffers. 1860 */ 1861 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1862 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1863 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1864 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1865 } 1866 } 1867 1868 bzero((char *)&sc->wb_ldata->wb_tx_list, 1869 sizeof(sc->wb_ldata->wb_tx_list)); 1870 1871 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1872 WB_UNLOCK(sc); 1873 1874 return; 1875 } 1876 1877 /* 1878 * Stop all chip I/O so that the kernel's probe routines don't 1879 * get confused by errant DMAs when rebooting. 1880 */ 1881 static void 1882 wb_shutdown(dev) 1883 device_t dev; 1884 { 1885 struct wb_softc *sc; 1886 1887 sc = device_get_softc(dev); 1888 wb_stop(sc); 1889 1890 return; 1891 }
Cache object: 4e47b18899f1c77c291776504a3a75f3
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