Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/pci/if_wb.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/5.2/sys/pci/if_wb.c 122689 2003-11-14 19:00:32Z sam $"); 35 36 /* 37 * Winbond fast ethernet PCI NIC driver 38 * 39 * Supports various cheap network adapters based on the Winbond W89C840F 40 * fast ethernet controller chip. This includes adapters manufactured by 41 * Winbond itself and some made by Linksys. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 /* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86 #include "opt_bdg.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/queue.h> 96 97 #include <net/if.h> 98 #include <net/if_arp.h> 99 #include <net/ethernet.h> 100 #include <net/if_dl.h> 101 #include <net/if_media.h> 102 103 #include <net/bpf.h> 104 105 #include <vm/vm.h> /* for vtophys */ 106 #include <vm/pmap.h> /* for vtophys */ 107 #include <machine/bus_memio.h> 108 #include <machine/bus_pio.h> 109 #include <machine/bus.h> 110 #include <machine/resource.h> 111 #include <sys/bus.h> 112 #include <sys/rman.h> 113 114 #include <dev/pci/pcireg.h> 115 #include <dev/pci/pcivar.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 120 /* "controller miibus0" required. See GENERIC if you get errors here. */ 121 #include "miibus_if.h" 122 123 #define WB_USEIOSPACE 124 125 #include <pci/if_wbreg.h> 126 127 MODULE_DEPEND(wb, pci, 1, 1, 1); 128 MODULE_DEPEND(wb, ether, 1, 1, 1); 129 MODULE_DEPEND(wb, miibus, 1, 1, 1); 130 131 /* 132 * Various supported device vendors/types and their names. 133 */ 134 static struct wb_type wb_devs[] = { 135 { WB_VENDORID, WB_DEVICEID_840F, 136 "Winbond W89C840F 10/100BaseTX" }, 137 { CP_VENDORID, CP_DEVICEID_RL100, 138 "Compex RL100-ATX 10/100baseTX" }, 139 { 0, 0, NULL } 140 }; 141 142 static int wb_probe (device_t); 143 static int wb_attach (device_t); 144 static int wb_detach (device_t); 145 146 static void wb_bfree (void *addr, void *args); 147 static int wb_newbuf (struct wb_softc *, 148 struct wb_chain_onefrag *, 149 struct mbuf *); 150 static int wb_encap (struct wb_softc *, struct wb_chain *, 151 struct mbuf *); 152 153 static void wb_rxeof (struct wb_softc *); 154 static void wb_rxeoc (struct wb_softc *); 155 static void wb_txeof (struct wb_softc *); 156 static void wb_txeoc (struct wb_softc *); 157 static void wb_intr (void *); 158 static void wb_tick (void *); 159 static void wb_start (struct ifnet *); 160 static int wb_ioctl (struct ifnet *, u_long, caddr_t); 161 static void wb_init (void *); 162 static void wb_stop (struct wb_softc *); 163 static void wb_watchdog (struct ifnet *); 164 static void wb_shutdown (device_t); 165 static int wb_ifmedia_upd (struct ifnet *); 166 static void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 167 168 static void wb_eeprom_putbyte (struct wb_softc *, int); 169 static void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 170 static void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int); 171 static void wb_mii_sync (struct wb_softc *); 172 static void wb_mii_send (struct wb_softc *, u_int32_t, int); 173 static int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 174 static int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 175 176 static void wb_setcfg (struct wb_softc *, u_int32_t); 177 static u_int32_t wb_mchash (caddr_t); 178 static void wb_setmulti (struct wb_softc *); 179 static void wb_reset (struct wb_softc *); 180 static void wb_fixmedia (struct wb_softc *); 181 static int wb_list_rx_init (struct wb_softc *); 182 static int wb_list_tx_init (struct wb_softc *); 183 184 static int wb_miibus_readreg (device_t, int, int); 185 static int wb_miibus_writereg (device_t, int, int, int); 186 static void wb_miibus_statchg (device_t); 187 188 #ifdef WB_USEIOSPACE 189 #define WB_RES SYS_RES_IOPORT 190 #define WB_RID WB_PCI_LOIO 191 #else 192 #define WB_RES SYS_RES_MEMORY 193 #define WB_RID WB_PCI_LOMEM 194 #endif 195 196 static device_method_t wb_methods[] = { 197 /* Device interface */ 198 DEVMETHOD(device_probe, wb_probe), 199 DEVMETHOD(device_attach, wb_attach), 200 DEVMETHOD(device_detach, wb_detach), 201 DEVMETHOD(device_shutdown, wb_shutdown), 202 203 /* bus interface, for miibus */ 204 DEVMETHOD(bus_print_child, bus_generic_print_child), 205 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 206 207 /* MII interface */ 208 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 209 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 210 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 211 { 0, 0 } 212 }; 213 214 static driver_t wb_driver = { 215 "wb", 216 wb_methods, 217 sizeof(struct wb_softc) 218 }; 219 220 static devclass_t wb_devclass; 221 222 DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 223 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 224 225 #define WB_SETBIT(sc, reg, x) \ 226 CSR_WRITE_4(sc, reg, \ 227 CSR_READ_4(sc, reg) | (x)) 228 229 #define WB_CLRBIT(sc, reg, x) \ 230 CSR_WRITE_4(sc, reg, \ 231 CSR_READ_4(sc, reg) & ~(x)) 232 233 #define SIO_SET(x) \ 234 CSR_WRITE_4(sc, WB_SIO, \ 235 CSR_READ_4(sc, WB_SIO) | (x)) 236 237 #define SIO_CLR(x) \ 238 CSR_WRITE_4(sc, WB_SIO, \ 239 CSR_READ_4(sc, WB_SIO) & ~(x)) 240 241 /* 242 * Send a read command and address to the EEPROM, check for ACK. 243 */ 244 static void 245 wb_eeprom_putbyte(sc, addr) 246 struct wb_softc *sc; 247 int addr; 248 { 249 register int d, i; 250 251 d = addr | WB_EECMD_READ; 252 253 /* 254 * Feed in each bit and stobe the clock. 255 */ 256 for (i = 0x400; i; i >>= 1) { 257 if (d & i) { 258 SIO_SET(WB_SIO_EE_DATAIN); 259 } else { 260 SIO_CLR(WB_SIO_EE_DATAIN); 261 } 262 DELAY(100); 263 SIO_SET(WB_SIO_EE_CLK); 264 DELAY(150); 265 SIO_CLR(WB_SIO_EE_CLK); 266 DELAY(100); 267 } 268 269 return; 270 } 271 272 /* 273 * Read a word of data stored in the EEPROM at address 'addr.' 274 */ 275 static void 276 wb_eeprom_getword(sc, addr, dest) 277 struct wb_softc *sc; 278 int addr; 279 u_int16_t *dest; 280 { 281 register int i; 282 u_int16_t word = 0; 283 284 /* Enter EEPROM access mode. */ 285 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 286 287 /* 288 * Send address of word we want to read. 289 */ 290 wb_eeprom_putbyte(sc, addr); 291 292 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 293 294 /* 295 * Start reading bits from EEPROM. 296 */ 297 for (i = 0x8000; i; i >>= 1) { 298 SIO_SET(WB_SIO_EE_CLK); 299 DELAY(100); 300 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 301 word |= i; 302 SIO_CLR(WB_SIO_EE_CLK); 303 DELAY(100); 304 } 305 306 /* Turn off EEPROM access mode. */ 307 CSR_WRITE_4(sc, WB_SIO, 0); 308 309 *dest = word; 310 311 return; 312 } 313 314 /* 315 * Read a sequence of words from the EEPROM. 316 */ 317 static void 318 wb_read_eeprom(sc, dest, off, cnt, swap) 319 struct wb_softc *sc; 320 caddr_t dest; 321 int off; 322 int cnt; 323 int swap; 324 { 325 int i; 326 u_int16_t word = 0, *ptr; 327 328 for (i = 0; i < cnt; i++) { 329 wb_eeprom_getword(sc, off + i, &word); 330 ptr = (u_int16_t *)(dest + (i * 2)); 331 if (swap) 332 *ptr = ntohs(word); 333 else 334 *ptr = word; 335 } 336 337 return; 338 } 339 340 /* 341 * Sync the PHYs by setting data bit and strobing the clock 32 times. 342 */ 343 static void 344 wb_mii_sync(sc) 345 struct wb_softc *sc; 346 { 347 register int i; 348 349 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 350 351 for (i = 0; i < 32; i++) { 352 SIO_SET(WB_SIO_MII_CLK); 353 DELAY(1); 354 SIO_CLR(WB_SIO_MII_CLK); 355 DELAY(1); 356 } 357 358 return; 359 } 360 361 /* 362 * Clock a series of bits through the MII. 363 */ 364 static void 365 wb_mii_send(sc, bits, cnt) 366 struct wb_softc *sc; 367 u_int32_t bits; 368 int cnt; 369 { 370 int i; 371 372 SIO_CLR(WB_SIO_MII_CLK); 373 374 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 375 if (bits & i) { 376 SIO_SET(WB_SIO_MII_DATAIN); 377 } else { 378 SIO_CLR(WB_SIO_MII_DATAIN); 379 } 380 DELAY(1); 381 SIO_CLR(WB_SIO_MII_CLK); 382 DELAY(1); 383 SIO_SET(WB_SIO_MII_CLK); 384 } 385 } 386 387 /* 388 * Read an PHY register through the MII. 389 */ 390 static int 391 wb_mii_readreg(sc, frame) 392 struct wb_softc *sc; 393 struct wb_mii_frame *frame; 394 395 { 396 int i, ack; 397 398 WB_LOCK(sc); 399 400 /* 401 * Set up frame for RX. 402 */ 403 frame->mii_stdelim = WB_MII_STARTDELIM; 404 frame->mii_opcode = WB_MII_READOP; 405 frame->mii_turnaround = 0; 406 frame->mii_data = 0; 407 408 CSR_WRITE_4(sc, WB_SIO, 0); 409 410 /* 411 * Turn on data xmit. 412 */ 413 SIO_SET(WB_SIO_MII_DIR); 414 415 wb_mii_sync(sc); 416 417 /* 418 * Send command/address info. 419 */ 420 wb_mii_send(sc, frame->mii_stdelim, 2); 421 wb_mii_send(sc, frame->mii_opcode, 2); 422 wb_mii_send(sc, frame->mii_phyaddr, 5); 423 wb_mii_send(sc, frame->mii_regaddr, 5); 424 425 /* Idle bit */ 426 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 427 DELAY(1); 428 SIO_SET(WB_SIO_MII_CLK); 429 DELAY(1); 430 431 /* Turn off xmit. */ 432 SIO_CLR(WB_SIO_MII_DIR); 433 /* Check for ack */ 434 SIO_CLR(WB_SIO_MII_CLK); 435 DELAY(1); 436 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 437 SIO_SET(WB_SIO_MII_CLK); 438 DELAY(1); 439 SIO_CLR(WB_SIO_MII_CLK); 440 DELAY(1); 441 SIO_SET(WB_SIO_MII_CLK); 442 DELAY(1); 443 444 /* 445 * Now try reading data bits. If the ack failed, we still 446 * need to clock through 16 cycles to keep the PHY(s) in sync. 447 */ 448 if (ack) { 449 for(i = 0; i < 16; i++) { 450 SIO_CLR(WB_SIO_MII_CLK); 451 DELAY(1); 452 SIO_SET(WB_SIO_MII_CLK); 453 DELAY(1); 454 } 455 goto fail; 456 } 457 458 for (i = 0x8000; i; i >>= 1) { 459 SIO_CLR(WB_SIO_MII_CLK); 460 DELAY(1); 461 if (!ack) { 462 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 463 frame->mii_data |= i; 464 DELAY(1); 465 } 466 SIO_SET(WB_SIO_MII_CLK); 467 DELAY(1); 468 } 469 470 fail: 471 472 SIO_CLR(WB_SIO_MII_CLK); 473 DELAY(1); 474 SIO_SET(WB_SIO_MII_CLK); 475 DELAY(1); 476 477 WB_UNLOCK(sc); 478 479 if (ack) 480 return(1); 481 return(0); 482 } 483 484 /* 485 * Write to a PHY register through the MII. 486 */ 487 static int 488 wb_mii_writereg(sc, frame) 489 struct wb_softc *sc; 490 struct wb_mii_frame *frame; 491 492 { 493 WB_LOCK(sc); 494 495 /* 496 * Set up frame for TX. 497 */ 498 499 frame->mii_stdelim = WB_MII_STARTDELIM; 500 frame->mii_opcode = WB_MII_WRITEOP; 501 frame->mii_turnaround = WB_MII_TURNAROUND; 502 503 /* 504 * Turn on data output. 505 */ 506 SIO_SET(WB_SIO_MII_DIR); 507 508 wb_mii_sync(sc); 509 510 wb_mii_send(sc, frame->mii_stdelim, 2); 511 wb_mii_send(sc, frame->mii_opcode, 2); 512 wb_mii_send(sc, frame->mii_phyaddr, 5); 513 wb_mii_send(sc, frame->mii_regaddr, 5); 514 wb_mii_send(sc, frame->mii_turnaround, 2); 515 wb_mii_send(sc, frame->mii_data, 16); 516 517 /* Idle bit. */ 518 SIO_SET(WB_SIO_MII_CLK); 519 DELAY(1); 520 SIO_CLR(WB_SIO_MII_CLK); 521 DELAY(1); 522 523 /* 524 * Turn off xmit. 525 */ 526 SIO_CLR(WB_SIO_MII_DIR); 527 528 WB_UNLOCK(sc); 529 530 return(0); 531 } 532 533 static int 534 wb_miibus_readreg(dev, phy, reg) 535 device_t dev; 536 int phy, reg; 537 { 538 struct wb_softc *sc; 539 struct wb_mii_frame frame; 540 541 sc = device_get_softc(dev); 542 543 bzero((char *)&frame, sizeof(frame)); 544 545 frame.mii_phyaddr = phy; 546 frame.mii_regaddr = reg; 547 wb_mii_readreg(sc, &frame); 548 549 return(frame.mii_data); 550 } 551 552 static int 553 wb_miibus_writereg(dev, phy, reg, data) 554 device_t dev; 555 int phy, reg, data; 556 { 557 struct wb_softc *sc; 558 struct wb_mii_frame frame; 559 560 sc = device_get_softc(dev); 561 562 bzero((char *)&frame, sizeof(frame)); 563 564 frame.mii_phyaddr = phy; 565 frame.mii_regaddr = reg; 566 frame.mii_data = data; 567 568 wb_mii_writereg(sc, &frame); 569 570 return(0); 571 } 572 573 static void 574 wb_miibus_statchg(dev) 575 device_t dev; 576 { 577 struct wb_softc *sc; 578 struct mii_data *mii; 579 580 sc = device_get_softc(dev); 581 WB_LOCK(sc); 582 mii = device_get_softc(sc->wb_miibus); 583 wb_setcfg(sc, mii->mii_media_active); 584 WB_UNLOCK(sc); 585 586 return; 587 } 588 589 static u_int32_t 590 wb_mchash(addr) 591 caddr_t addr; 592 { 593 u_int32_t crc, carry; 594 int idx, bit; 595 u_int8_t data; 596 597 /* Compute CRC for the address value. */ 598 crc = 0xFFFFFFFF; /* initial value */ 599 600 for (idx = 0; idx < 6; idx++) { 601 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 602 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 603 crc <<= 1; 604 if (carry) 605 crc = (crc ^ 0x04c11db6) | carry; 606 } 607 } 608 609 /* 610 * return the filter bit position 611 * Note: I arrived at the following nonsense 612 * through experimentation. It's not the usual way to 613 * generate the bit position but it's the only thing 614 * I could come up with that works. 615 */ 616 return(~(crc >> 26) & 0x0000003F); 617 } 618 619 /* 620 * Program the 64-bit multicast hash filter. 621 */ 622 static void 623 wb_setmulti(sc) 624 struct wb_softc *sc; 625 { 626 struct ifnet *ifp; 627 int h = 0; 628 u_int32_t hashes[2] = { 0, 0 }; 629 struct ifmultiaddr *ifma; 630 u_int32_t rxfilt; 631 int mcnt = 0; 632 633 ifp = &sc->arpcom.ac_if; 634 635 rxfilt = CSR_READ_4(sc, WB_NETCFG); 636 637 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 638 rxfilt |= WB_NETCFG_RX_MULTI; 639 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 640 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 641 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 642 return; 643 } 644 645 /* first, zot all the existing hash bits */ 646 CSR_WRITE_4(sc, WB_MAR0, 0); 647 CSR_WRITE_4(sc, WB_MAR1, 0); 648 649 /* now program new ones */ 650 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 651 if (ifma->ifma_addr->sa_family != AF_LINK) 652 continue; 653 h = wb_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 654 if (h < 32) 655 hashes[0] |= (1 << h); 656 else 657 hashes[1] |= (1 << (h - 32)); 658 mcnt++; 659 } 660 661 if (mcnt) 662 rxfilt |= WB_NETCFG_RX_MULTI; 663 else 664 rxfilt &= ~WB_NETCFG_RX_MULTI; 665 666 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 667 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 668 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 669 670 return; 671 } 672 673 /* 674 * The Winbond manual states that in order to fiddle with the 675 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 676 * first have to put the transmit and/or receive logic in the idle state. 677 */ 678 static void 679 wb_setcfg(sc, media) 680 struct wb_softc *sc; 681 u_int32_t media; 682 { 683 int i, restart = 0; 684 685 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 686 restart = 1; 687 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 688 689 for (i = 0; i < WB_TIMEOUT; i++) { 690 DELAY(10); 691 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 692 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 693 break; 694 } 695 696 if (i == WB_TIMEOUT) 697 printf("wb%d: failed to force tx and " 698 "rx to idle state\n", sc->wb_unit); 699 } 700 701 if (IFM_SUBTYPE(media) == IFM_10_T) 702 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 703 else 704 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 705 706 if ((media & IFM_GMASK) == IFM_FDX) 707 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 708 else 709 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 710 711 if (restart) 712 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 713 714 return; 715 } 716 717 static void 718 wb_reset(sc) 719 struct wb_softc *sc; 720 { 721 register int i; 722 struct mii_data *mii; 723 724 CSR_WRITE_4(sc, WB_NETCFG, 0); 725 CSR_WRITE_4(sc, WB_BUSCTL, 0); 726 CSR_WRITE_4(sc, WB_TXADDR, 0); 727 CSR_WRITE_4(sc, WB_RXADDR, 0); 728 729 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 730 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 731 732 for (i = 0; i < WB_TIMEOUT; i++) { 733 DELAY(10); 734 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 735 break; 736 } 737 if (i == WB_TIMEOUT) 738 printf("wb%d: reset never completed!\n", sc->wb_unit); 739 740 /* Wait a little while for the chip to get its brains in order. */ 741 DELAY(1000); 742 743 if (sc->wb_miibus == NULL) 744 return; 745 746 mii = device_get_softc(sc->wb_miibus); 747 if (mii == NULL) 748 return; 749 750 if (mii->mii_instance) { 751 struct mii_softc *miisc; 752 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 753 mii_phy_reset(miisc); 754 } 755 756 return; 757 } 758 759 static void 760 wb_fixmedia(sc) 761 struct wb_softc *sc; 762 { 763 struct mii_data *mii = NULL; 764 struct ifnet *ifp; 765 u_int32_t media; 766 767 if (sc->wb_miibus == NULL) 768 return; 769 770 mii = device_get_softc(sc->wb_miibus); 771 ifp = &sc->arpcom.ac_if; 772 773 mii_pollstat(mii); 774 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 775 media = mii->mii_media_active & ~IFM_10_T; 776 media |= IFM_100_TX; 777 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 778 media = mii->mii_media_active & ~IFM_100_TX; 779 media |= IFM_10_T; 780 } else 781 return; 782 783 ifmedia_set(&mii->mii_media, media); 784 785 return; 786 } 787 788 /* 789 * Probe for a Winbond chip. Check the PCI vendor and device 790 * IDs against our list and return a device name if we find a match. 791 */ 792 static int 793 wb_probe(dev) 794 device_t dev; 795 { 796 struct wb_type *t; 797 798 t = wb_devs; 799 800 while(t->wb_name != NULL) { 801 if ((pci_get_vendor(dev) == t->wb_vid) && 802 (pci_get_device(dev) == t->wb_did)) { 803 device_set_desc(dev, t->wb_name); 804 return(0); 805 } 806 t++; 807 } 808 809 return(ENXIO); 810 } 811 812 /* 813 * Attach the interface. Allocate softc structures, do ifmedia 814 * setup and ethernet/BPF attach. 815 */ 816 static int 817 wb_attach(dev) 818 device_t dev; 819 { 820 u_char eaddr[ETHER_ADDR_LEN]; 821 struct wb_softc *sc; 822 struct ifnet *ifp; 823 int unit, error = 0, rid; 824 825 sc = device_get_softc(dev); 826 unit = device_get_unit(dev); 827 828 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 829 MTX_DEF | MTX_RECURSE); 830 #ifndef BURN_BRIDGES 831 /* 832 * Handle power management nonsense. 833 */ 834 835 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 836 u_int32_t iobase, membase, irq; 837 838 /* Save important PCI config data. */ 839 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 840 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 841 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 842 843 /* Reset the power state. */ 844 printf("wb%d: chip is in D%d power mode " 845 "-- setting to D0\n", unit, 846 pci_get_powerstate(dev)); 847 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 848 849 /* Restore PCI config data. */ 850 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 851 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 852 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 853 } 854 #endif 855 /* 856 * Map control/status registers. 857 */ 858 pci_enable_busmaster(dev); 859 860 rid = WB_RID; 861 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 862 0, ~0, 1, RF_ACTIVE); 863 864 if (sc->wb_res == NULL) { 865 printf("wb%d: couldn't map ports/memory\n", unit); 866 error = ENXIO; 867 goto fail; 868 } 869 870 sc->wb_btag = rman_get_bustag(sc->wb_res); 871 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 872 873 /* Allocate interrupt */ 874 rid = 0; 875 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 876 RF_SHAREABLE | RF_ACTIVE); 877 878 if (sc->wb_irq == NULL) { 879 printf("wb%d: couldn't map interrupt\n", unit); 880 error = ENXIO; 881 goto fail; 882 } 883 884 /* Save the cache line size. */ 885 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 886 887 /* Reset the adapter. */ 888 wb_reset(sc); 889 890 /* 891 * Get station address from the EEPROM. 892 */ 893 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 894 895 /* 896 * A Winbond chip was detected. Inform the world. 897 */ 898 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 899 900 sc->wb_unit = unit; 901 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 902 903 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 904 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 905 906 if (sc->wb_ldata == NULL) { 907 printf("wb%d: no memory for list buffers!\n", unit); 908 error = ENXIO; 909 goto fail; 910 } 911 912 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 913 914 ifp = &sc->arpcom.ac_if; 915 ifp->if_softc = sc; 916 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 917 ifp->if_mtu = ETHERMTU; 918 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 919 ifp->if_ioctl = wb_ioctl; 920 ifp->if_output = ether_output; 921 ifp->if_start = wb_start; 922 ifp->if_watchdog = wb_watchdog; 923 ifp->if_init = wb_init; 924 ifp->if_baudrate = 10000000; 925 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 926 927 /* 928 * Do MII setup. 929 */ 930 if (mii_phy_probe(dev, &sc->wb_miibus, 931 wb_ifmedia_upd, wb_ifmedia_sts)) { 932 error = ENXIO; 933 goto fail; 934 } 935 936 /* 937 * Call MI attach routine. 938 */ 939 ether_ifattach(ifp, eaddr); 940 941 /* Hook interrupt last to avoid having to lock softc */ 942 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 943 wb_intr, sc, &sc->wb_intrhand); 944 945 if (error) { 946 printf("wb%d: couldn't set up irq\n", unit); 947 ether_ifdetach(ifp); 948 goto fail; 949 } 950 951 fail: 952 if (error) 953 wb_detach(dev); 954 955 return(error); 956 } 957 958 /* 959 * Shutdown hardware and free up resources. This can be called any 960 * time after the mutex has been initialized. It is called in both 961 * the error case in attach and the normal detach case so it needs 962 * to be careful about only freeing resources that have actually been 963 * allocated. 964 */ 965 static int 966 wb_detach(dev) 967 device_t dev; 968 { 969 struct wb_softc *sc; 970 struct ifnet *ifp; 971 972 sc = device_get_softc(dev); 973 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 974 WB_LOCK(sc); 975 ifp = &sc->arpcom.ac_if; 976 977 /* 978 * Delete any miibus and phy devices attached to this interface. 979 * This should only be done if attach succeeded. 980 */ 981 if (device_is_attached(dev)) { 982 wb_stop(sc); 983 ether_ifdetach(ifp); 984 } 985 if (sc->wb_miibus) 986 device_delete_child(dev, sc->wb_miibus); 987 bus_generic_detach(dev); 988 989 if (sc->wb_intrhand) 990 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 991 if (sc->wb_irq) 992 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 993 if (sc->wb_res) 994 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 995 996 if (sc->wb_ldata) { 997 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 998 M_DEVBUF); 999 } 1000 1001 WB_UNLOCK(sc); 1002 mtx_destroy(&sc->wb_mtx); 1003 1004 return(0); 1005 } 1006 1007 /* 1008 * Initialize the transmit descriptors. 1009 */ 1010 static int 1011 wb_list_tx_init(sc) 1012 struct wb_softc *sc; 1013 { 1014 struct wb_chain_data *cd; 1015 struct wb_list_data *ld; 1016 int i; 1017 1018 cd = &sc->wb_cdata; 1019 ld = sc->wb_ldata; 1020 1021 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1022 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1023 if (i == (WB_TX_LIST_CNT - 1)) { 1024 cd->wb_tx_chain[i].wb_nextdesc = 1025 &cd->wb_tx_chain[0]; 1026 } else { 1027 cd->wb_tx_chain[i].wb_nextdesc = 1028 &cd->wb_tx_chain[i + 1]; 1029 } 1030 } 1031 1032 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1033 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1034 1035 return(0); 1036 } 1037 1038 1039 /* 1040 * Initialize the RX descriptors and allocate mbufs for them. Note that 1041 * we arrange the descriptors in a closed ring, so that the last descriptor 1042 * points back to the first. 1043 */ 1044 static int 1045 wb_list_rx_init(sc) 1046 struct wb_softc *sc; 1047 { 1048 struct wb_chain_data *cd; 1049 struct wb_list_data *ld; 1050 int i; 1051 1052 cd = &sc->wb_cdata; 1053 ld = sc->wb_ldata; 1054 1055 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1056 cd->wb_rx_chain[i].wb_ptr = 1057 (struct wb_desc *)&ld->wb_rx_list[i]; 1058 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1059 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1060 return(ENOBUFS); 1061 if (i == (WB_RX_LIST_CNT - 1)) { 1062 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1063 ld->wb_rx_list[i].wb_next = 1064 vtophys(&ld->wb_rx_list[0]); 1065 } else { 1066 cd->wb_rx_chain[i].wb_nextdesc = 1067 &cd->wb_rx_chain[i + 1]; 1068 ld->wb_rx_list[i].wb_next = 1069 vtophys(&ld->wb_rx_list[i + 1]); 1070 } 1071 } 1072 1073 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1074 1075 return(0); 1076 } 1077 1078 static void 1079 wb_bfree(buf, args) 1080 void *buf; 1081 void *args; 1082 { 1083 return; 1084 } 1085 1086 /* 1087 * Initialize an RX descriptor and attach an MBUF cluster. 1088 */ 1089 static int 1090 wb_newbuf(sc, c, m) 1091 struct wb_softc *sc; 1092 struct wb_chain_onefrag *c; 1093 struct mbuf *m; 1094 { 1095 struct mbuf *m_new = NULL; 1096 1097 if (m == NULL) { 1098 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1099 if (m_new == NULL) 1100 return(ENOBUFS); 1101 m_new->m_data = c->wb_buf; 1102 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1103 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 1104 EXT_NET_DRV); 1105 } else { 1106 m_new = m; 1107 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1108 m_new->m_data = m_new->m_ext.ext_buf; 1109 } 1110 1111 m_adj(m_new, sizeof(u_int64_t)); 1112 1113 c->wb_mbuf = m_new; 1114 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1115 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1116 c->wb_ptr->wb_status = WB_RXSTAT; 1117 1118 return(0); 1119 } 1120 1121 /* 1122 * A frame has been uploaded: pass the resulting mbuf chain up to 1123 * the higher level protocols. 1124 */ 1125 static void 1126 wb_rxeof(sc) 1127 struct wb_softc *sc; 1128 { 1129 struct mbuf *m = NULL; 1130 struct ifnet *ifp; 1131 struct wb_chain_onefrag *cur_rx; 1132 int total_len = 0; 1133 u_int32_t rxstat; 1134 1135 WB_LOCK_ASSERT(sc); 1136 1137 ifp = &sc->arpcom.ac_if; 1138 1139 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1140 WB_RXSTAT_OWN)) { 1141 struct mbuf *m0 = NULL; 1142 1143 cur_rx = sc->wb_cdata.wb_rx_head; 1144 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1145 1146 m = cur_rx->wb_mbuf; 1147 1148 if ((rxstat & WB_RXSTAT_MIIERR) || 1149 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1150 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1151 !(rxstat & WB_RXSTAT_LASTFRAG) || 1152 !(rxstat & WB_RXSTAT_RXCMP)) { 1153 ifp->if_ierrors++; 1154 wb_newbuf(sc, cur_rx, m); 1155 printf("wb%x: receiver babbling: possible chip " 1156 "bug, forcing reset\n", sc->wb_unit); 1157 wb_fixmedia(sc); 1158 wb_reset(sc); 1159 wb_init(sc); 1160 return; 1161 } 1162 1163 if (rxstat & WB_RXSTAT_RXERR) { 1164 ifp->if_ierrors++; 1165 wb_newbuf(sc, cur_rx, m); 1166 break; 1167 } 1168 1169 /* No errors; receive the packet. */ 1170 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1171 1172 /* 1173 * XXX The Winbond chip includes the CRC with every 1174 * received frame, and there's no way to turn this 1175 * behavior off (at least, I can't find anything in 1176 * the manual that explains how to do it) so we have 1177 * to trim off the CRC manually. 1178 */ 1179 total_len -= ETHER_CRC_LEN; 1180 1181 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1182 NULL); 1183 wb_newbuf(sc, cur_rx, m); 1184 if (m0 == NULL) { 1185 ifp->if_ierrors++; 1186 break; 1187 } 1188 m = m0; 1189 1190 ifp->if_ipackets++; 1191 WB_UNLOCK(sc); 1192 (*ifp->if_input)(ifp, m); 1193 WB_LOCK(sc); 1194 } 1195 } 1196 1197 static void 1198 wb_rxeoc(sc) 1199 struct wb_softc *sc; 1200 { 1201 wb_rxeof(sc); 1202 1203 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1204 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1205 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1206 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1207 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1208 1209 return; 1210 } 1211 1212 /* 1213 * A frame was downloaded to the chip. It's safe for us to clean up 1214 * the list buffers. 1215 */ 1216 static void 1217 wb_txeof(sc) 1218 struct wb_softc *sc; 1219 { 1220 struct wb_chain *cur_tx; 1221 struct ifnet *ifp; 1222 1223 ifp = &sc->arpcom.ac_if; 1224 1225 /* Clear the timeout timer. */ 1226 ifp->if_timer = 0; 1227 1228 if (sc->wb_cdata.wb_tx_head == NULL) 1229 return; 1230 1231 /* 1232 * Go through our tx list and free mbufs for those 1233 * frames that have been transmitted. 1234 */ 1235 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1236 u_int32_t txstat; 1237 1238 cur_tx = sc->wb_cdata.wb_tx_head; 1239 txstat = WB_TXSTATUS(cur_tx); 1240 1241 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1242 break; 1243 1244 if (txstat & WB_TXSTAT_TXERR) { 1245 ifp->if_oerrors++; 1246 if (txstat & WB_TXSTAT_ABORT) 1247 ifp->if_collisions++; 1248 if (txstat & WB_TXSTAT_LATECOLL) 1249 ifp->if_collisions++; 1250 } 1251 1252 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1253 1254 ifp->if_opackets++; 1255 m_freem(cur_tx->wb_mbuf); 1256 cur_tx->wb_mbuf = NULL; 1257 1258 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1259 sc->wb_cdata.wb_tx_head = NULL; 1260 sc->wb_cdata.wb_tx_tail = NULL; 1261 break; 1262 } 1263 1264 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1265 } 1266 1267 return; 1268 } 1269 1270 /* 1271 * TX 'end of channel' interrupt handler. 1272 */ 1273 static void 1274 wb_txeoc(sc) 1275 struct wb_softc *sc; 1276 { 1277 struct ifnet *ifp; 1278 1279 ifp = &sc->arpcom.ac_if; 1280 1281 ifp->if_timer = 0; 1282 1283 if (sc->wb_cdata.wb_tx_head == NULL) { 1284 ifp->if_flags &= ~IFF_OACTIVE; 1285 sc->wb_cdata.wb_tx_tail = NULL; 1286 } else { 1287 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1288 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1289 ifp->if_timer = 5; 1290 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1291 } 1292 } 1293 1294 return; 1295 } 1296 1297 static void 1298 wb_intr(arg) 1299 void *arg; 1300 { 1301 struct wb_softc *sc; 1302 struct ifnet *ifp; 1303 u_int32_t status; 1304 1305 sc = arg; 1306 WB_LOCK(sc); 1307 ifp = &sc->arpcom.ac_if; 1308 1309 if (!(ifp->if_flags & IFF_UP)) { 1310 WB_UNLOCK(sc); 1311 return; 1312 } 1313 1314 /* Disable interrupts. */ 1315 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1316 1317 for (;;) { 1318 1319 status = CSR_READ_4(sc, WB_ISR); 1320 if (status) 1321 CSR_WRITE_4(sc, WB_ISR, status); 1322 1323 if ((status & WB_INTRS) == 0) 1324 break; 1325 1326 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1327 ifp->if_ierrors++; 1328 wb_reset(sc); 1329 if (status & WB_ISR_RX_ERR) 1330 wb_fixmedia(sc); 1331 wb_init(sc); 1332 continue; 1333 } 1334 1335 if (status & WB_ISR_RX_OK) 1336 wb_rxeof(sc); 1337 1338 if (status & WB_ISR_RX_IDLE) 1339 wb_rxeoc(sc); 1340 1341 if (status & WB_ISR_TX_OK) 1342 wb_txeof(sc); 1343 1344 if (status & WB_ISR_TX_NOBUF) 1345 wb_txeoc(sc); 1346 1347 if (status & WB_ISR_TX_IDLE) { 1348 wb_txeof(sc); 1349 if (sc->wb_cdata.wb_tx_head != NULL) { 1350 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1351 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1352 } 1353 } 1354 1355 if (status & WB_ISR_TX_UNDERRUN) { 1356 ifp->if_oerrors++; 1357 wb_txeof(sc); 1358 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1359 /* Jack up TX threshold */ 1360 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1361 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1362 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1363 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1364 } 1365 1366 if (status & WB_ISR_BUS_ERR) { 1367 wb_reset(sc); 1368 wb_init(sc); 1369 } 1370 1371 } 1372 1373 /* Re-enable interrupts. */ 1374 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1375 1376 if (ifp->if_snd.ifq_head != NULL) { 1377 wb_start(ifp); 1378 } 1379 1380 WB_UNLOCK(sc); 1381 1382 return; 1383 } 1384 1385 static void 1386 wb_tick(xsc) 1387 void *xsc; 1388 { 1389 struct wb_softc *sc; 1390 struct mii_data *mii; 1391 1392 sc = xsc; 1393 WB_LOCK(sc); 1394 mii = device_get_softc(sc->wb_miibus); 1395 1396 mii_tick(mii); 1397 1398 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1399 1400 WB_UNLOCK(sc); 1401 1402 return; 1403 } 1404 1405 /* 1406 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1407 * pointers to the fragment pointers. 1408 */ 1409 static int 1410 wb_encap(sc, c, m_head) 1411 struct wb_softc *sc; 1412 struct wb_chain *c; 1413 struct mbuf *m_head; 1414 { 1415 int frag = 0; 1416 struct wb_desc *f = NULL; 1417 int total_len; 1418 struct mbuf *m; 1419 1420 /* 1421 * Start packing the mbufs in this chain into 1422 * the fragment pointers. Stop when we run out 1423 * of fragments or hit the end of the mbuf chain. 1424 */ 1425 m = m_head; 1426 total_len = 0; 1427 1428 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1429 if (m->m_len != 0) { 1430 if (frag == WB_MAXFRAGS) 1431 break; 1432 total_len += m->m_len; 1433 f = &c->wb_ptr->wb_frag[frag]; 1434 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1435 if (frag == 0) { 1436 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1437 f->wb_status = 0; 1438 } else 1439 f->wb_status = WB_TXSTAT_OWN; 1440 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1441 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1442 frag++; 1443 } 1444 } 1445 1446 /* 1447 * Handle special case: we used up all 16 fragments, 1448 * but we have more mbufs left in the chain. Copy the 1449 * data into an mbuf cluster. Note that we don't 1450 * bother clearing the values in the other fragment 1451 * pointers/counters; it wouldn't gain us anything, 1452 * and would waste cycles. 1453 */ 1454 if (m != NULL) { 1455 struct mbuf *m_new = NULL; 1456 1457 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1458 if (m_new == NULL) 1459 return(1); 1460 if (m_head->m_pkthdr.len > MHLEN) { 1461 MCLGET(m_new, M_DONTWAIT); 1462 if (!(m_new->m_flags & M_EXT)) { 1463 m_freem(m_new); 1464 return(1); 1465 } 1466 } 1467 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1468 mtod(m_new, caddr_t)); 1469 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1470 m_freem(m_head); 1471 m_head = m_new; 1472 f = &c->wb_ptr->wb_frag[0]; 1473 f->wb_status = 0; 1474 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1475 f->wb_ctl = total_len = m_new->m_len; 1476 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1477 frag = 1; 1478 } 1479 1480 if (total_len < WB_MIN_FRAMELEN) { 1481 f = &c->wb_ptr->wb_frag[frag]; 1482 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1483 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1484 f->wb_ctl |= WB_TXCTL_TLINK; 1485 f->wb_status = WB_TXSTAT_OWN; 1486 frag++; 1487 } 1488 1489 c->wb_mbuf = m_head; 1490 c->wb_lastdesc = frag - 1; 1491 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1492 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1493 1494 return(0); 1495 } 1496 1497 /* 1498 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1499 * to the mbuf data regions directly in the transmit lists. We also save a 1500 * copy of the pointers since the transmit list fragment pointers are 1501 * physical addresses. 1502 */ 1503 1504 static void 1505 wb_start(ifp) 1506 struct ifnet *ifp; 1507 { 1508 struct wb_softc *sc; 1509 struct mbuf *m_head = NULL; 1510 struct wb_chain *cur_tx = NULL, *start_tx; 1511 1512 sc = ifp->if_softc; 1513 WB_LOCK(sc); 1514 1515 /* 1516 * Check for an available queue slot. If there are none, 1517 * punt. 1518 */ 1519 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1520 ifp->if_flags |= IFF_OACTIVE; 1521 WB_UNLOCK(sc); 1522 return; 1523 } 1524 1525 start_tx = sc->wb_cdata.wb_tx_free; 1526 1527 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1528 IF_DEQUEUE(&ifp->if_snd, m_head); 1529 if (m_head == NULL) 1530 break; 1531 1532 /* Pick a descriptor off the free list. */ 1533 cur_tx = sc->wb_cdata.wb_tx_free; 1534 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1535 1536 /* Pack the data into the descriptor. */ 1537 wb_encap(sc, cur_tx, m_head); 1538 1539 if (cur_tx != start_tx) 1540 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1541 1542 /* 1543 * If there's a BPF listener, bounce a copy of this frame 1544 * to him. 1545 */ 1546 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1547 } 1548 1549 /* 1550 * If there are no packets queued, bail. 1551 */ 1552 if (cur_tx == NULL) { 1553 WB_UNLOCK(sc); 1554 return; 1555 } 1556 1557 /* 1558 * Place the request for the upload interrupt 1559 * in the last descriptor in the chain. This way, if 1560 * we're chaining several packets at once, we'll only 1561 * get an interupt once for the whole chain rather than 1562 * once for each packet. 1563 */ 1564 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1565 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1566 sc->wb_cdata.wb_tx_tail = cur_tx; 1567 1568 if (sc->wb_cdata.wb_tx_head == NULL) { 1569 sc->wb_cdata.wb_tx_head = start_tx; 1570 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1571 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1572 } else { 1573 /* 1574 * We need to distinguish between the case where 1575 * the own bit is clear because the chip cleared it 1576 * and where the own bit is clear because we haven't 1577 * set it yet. The magic value WB_UNSET is just some 1578 * ramdomly chosen number which doesn't have the own 1579 * bit set. When we actually transmit the frame, the 1580 * status word will have _only_ the own bit set, so 1581 * the txeoc handler will be able to tell if it needs 1582 * to initiate another transmission to flush out pending 1583 * frames. 1584 */ 1585 WB_TXOWN(start_tx) = WB_UNSENT; 1586 } 1587 1588 /* 1589 * Set a timeout in case the chip goes out to lunch. 1590 */ 1591 ifp->if_timer = 5; 1592 WB_UNLOCK(sc); 1593 1594 return; 1595 } 1596 1597 static void 1598 wb_init(xsc) 1599 void *xsc; 1600 { 1601 struct wb_softc *sc = xsc; 1602 struct ifnet *ifp = &sc->arpcom.ac_if; 1603 int i; 1604 struct mii_data *mii; 1605 1606 WB_LOCK(sc); 1607 mii = device_get_softc(sc->wb_miibus); 1608 1609 /* 1610 * Cancel pending I/O and free all RX/TX buffers. 1611 */ 1612 wb_stop(sc); 1613 wb_reset(sc); 1614 1615 sc->wb_txthresh = WB_TXTHRESH_INIT; 1616 1617 /* 1618 * Set cache alignment and burst length. 1619 */ 1620 #ifdef foo 1621 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1622 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1623 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1624 #endif 1625 1626 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1627 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1628 switch(sc->wb_cachesize) { 1629 case 32: 1630 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1631 break; 1632 case 16: 1633 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1634 break; 1635 case 8: 1636 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1637 break; 1638 case 0: 1639 default: 1640 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1641 break; 1642 } 1643 1644 /* This doesn't tend to work too well at 100Mbps. */ 1645 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1646 1647 /* Init our MAC address */ 1648 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1649 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1650 } 1651 1652 /* Init circular RX list. */ 1653 if (wb_list_rx_init(sc) == ENOBUFS) { 1654 printf("wb%d: initialization failed: no " 1655 "memory for rx buffers\n", sc->wb_unit); 1656 wb_stop(sc); 1657 WB_UNLOCK(sc); 1658 return; 1659 } 1660 1661 /* Init TX descriptors. */ 1662 wb_list_tx_init(sc); 1663 1664 /* If we want promiscuous mode, set the allframes bit. */ 1665 if (ifp->if_flags & IFF_PROMISC) { 1666 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1667 } else { 1668 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1669 } 1670 1671 /* 1672 * Set capture broadcast bit to capture broadcast frames. 1673 */ 1674 if (ifp->if_flags & IFF_BROADCAST) { 1675 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1676 } else { 1677 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1678 } 1679 1680 /* 1681 * Program the multicast filter, if necessary. 1682 */ 1683 wb_setmulti(sc); 1684 1685 /* 1686 * Load the address of the RX list. 1687 */ 1688 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1689 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1690 1691 /* 1692 * Enable interrupts. 1693 */ 1694 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1695 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1696 1697 /* Enable receiver and transmitter. */ 1698 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1699 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1700 1701 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1702 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1703 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1704 1705 mii_mediachg(mii); 1706 1707 ifp->if_flags |= IFF_RUNNING; 1708 ifp->if_flags &= ~IFF_OACTIVE; 1709 1710 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1711 WB_UNLOCK(sc); 1712 1713 return; 1714 } 1715 1716 /* 1717 * Set media options. 1718 */ 1719 static int 1720 wb_ifmedia_upd(ifp) 1721 struct ifnet *ifp; 1722 { 1723 struct wb_softc *sc; 1724 1725 sc = ifp->if_softc; 1726 1727 if (ifp->if_flags & IFF_UP) 1728 wb_init(sc); 1729 1730 return(0); 1731 } 1732 1733 /* 1734 * Report current media status. 1735 */ 1736 static void 1737 wb_ifmedia_sts(ifp, ifmr) 1738 struct ifnet *ifp; 1739 struct ifmediareq *ifmr; 1740 { 1741 struct wb_softc *sc; 1742 struct mii_data *mii; 1743 1744 sc = ifp->if_softc; 1745 1746 mii = device_get_softc(sc->wb_miibus); 1747 1748 mii_pollstat(mii); 1749 ifmr->ifm_active = mii->mii_media_active; 1750 ifmr->ifm_status = mii->mii_media_status; 1751 1752 return; 1753 } 1754 1755 static int 1756 wb_ioctl(ifp, command, data) 1757 struct ifnet *ifp; 1758 u_long command; 1759 caddr_t data; 1760 { 1761 struct wb_softc *sc = ifp->if_softc; 1762 struct mii_data *mii; 1763 struct ifreq *ifr = (struct ifreq *) data; 1764 int error = 0; 1765 1766 WB_LOCK(sc); 1767 1768 switch(command) { 1769 case SIOCSIFFLAGS: 1770 if (ifp->if_flags & IFF_UP) { 1771 wb_init(sc); 1772 } else { 1773 if (ifp->if_flags & IFF_RUNNING) 1774 wb_stop(sc); 1775 } 1776 error = 0; 1777 break; 1778 case SIOCADDMULTI: 1779 case SIOCDELMULTI: 1780 wb_setmulti(sc); 1781 error = 0; 1782 break; 1783 case SIOCGIFMEDIA: 1784 case SIOCSIFMEDIA: 1785 mii = device_get_softc(sc->wb_miibus); 1786 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1787 break; 1788 default: 1789 error = ether_ioctl(ifp, command, data); 1790 break; 1791 } 1792 1793 WB_UNLOCK(sc); 1794 1795 return(error); 1796 } 1797 1798 static void 1799 wb_watchdog(ifp) 1800 struct ifnet *ifp; 1801 { 1802 struct wb_softc *sc; 1803 1804 sc = ifp->if_softc; 1805 1806 WB_LOCK(sc); 1807 ifp->if_oerrors++; 1808 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1809 #ifdef foo 1810 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1811 printf("wb%d: no carrier - transceiver cable problem?\n", 1812 sc->wb_unit); 1813 #endif 1814 wb_stop(sc); 1815 wb_reset(sc); 1816 wb_init(sc); 1817 1818 if (ifp->if_snd.ifq_head != NULL) 1819 wb_start(ifp); 1820 WB_UNLOCK(sc); 1821 1822 return; 1823 } 1824 1825 /* 1826 * Stop the adapter and free any mbufs allocated to the 1827 * RX and TX lists. 1828 */ 1829 static void 1830 wb_stop(sc) 1831 struct wb_softc *sc; 1832 { 1833 register int i; 1834 struct ifnet *ifp; 1835 1836 WB_LOCK(sc); 1837 ifp = &sc->arpcom.ac_if; 1838 ifp->if_timer = 0; 1839 1840 untimeout(wb_tick, sc, sc->wb_stat_ch); 1841 1842 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1843 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1844 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1845 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1846 1847 /* 1848 * Free data in the RX lists. 1849 */ 1850 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1851 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1852 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1853 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1854 } 1855 } 1856 bzero((char *)&sc->wb_ldata->wb_rx_list, 1857 sizeof(sc->wb_ldata->wb_rx_list)); 1858 1859 /* 1860 * Free the TX list buffers. 1861 */ 1862 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1863 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1864 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1865 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1866 } 1867 } 1868 1869 bzero((char *)&sc->wb_ldata->wb_tx_list, 1870 sizeof(sc->wb_ldata->wb_tx_list)); 1871 1872 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1873 WB_UNLOCK(sc); 1874 1875 return; 1876 } 1877 1878 /* 1879 * Stop all chip I/O so that the kernel's probe routines don't 1880 * get confused by errant DMAs when rebooting. 1881 */ 1882 static void 1883 wb_shutdown(dev) 1884 device_t dev; 1885 { 1886 struct wb_softc *sc; 1887 1888 sc = device_get_softc(dev); 1889 wb_stop(sc); 1890 1891 return; 1892 }
Cache object: 31663d17584acc9d4bc0e6fc0c36f16a
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]