Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/pci/if_wb.c
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1 /*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/5.4/sys/pci/if_wb.c 142884 2005-03-01 08:11:52Z imp $"); 35 36 /* 37 * Winbond fast ethernet PCI NIC driver 38 * 39 * Supports various cheap network adapters based on the Winbond W89C840F 40 * fast ethernet controller chip. This includes adapters manufactured by 41 * Winbond itself and some made by Linksys. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 /* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86 #include "opt_bdg.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/module.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/queue.h> 97 98 #include <net/if.h> 99 #include <net/if_arp.h> 100 #include <net/ethernet.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 104 #include <net/bpf.h> 105 106 #include <vm/vm.h> /* for vtophys */ 107 #include <vm/pmap.h> /* for vtophys */ 108 #include <machine/bus_memio.h> 109 #include <machine/bus_pio.h> 110 #include <machine/bus.h> 111 #include <machine/resource.h> 112 #include <sys/bus.h> 113 #include <sys/rman.h> 114 115 #include <dev/pci/pcireg.h> 116 #include <dev/pci/pcivar.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 121 /* "controller miibus0" required. See GENERIC if you get errors here. */ 122 #include "miibus_if.h" 123 124 #define WB_USEIOSPACE 125 126 #include <pci/if_wbreg.h> 127 128 MODULE_DEPEND(wb, pci, 1, 1, 1); 129 MODULE_DEPEND(wb, ether, 1, 1, 1); 130 MODULE_DEPEND(wb, miibus, 1, 1, 1); 131 132 /* 133 * Various supported device vendors/types and their names. 134 */ 135 static struct wb_type wb_devs[] = { 136 { WB_VENDORID, WB_DEVICEID_840F, 137 "Winbond W89C840F 10/100BaseTX" }, 138 { CP_VENDORID, CP_DEVICEID_RL100, 139 "Compex RL100-ATX 10/100baseTX" }, 140 { 0, 0, NULL } 141 }; 142 143 static int wb_probe(device_t); 144 static int wb_attach(device_t); 145 static int wb_detach(device_t); 146 147 static void wb_bfree(void *addr, void *args); 148 static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *, 149 struct mbuf *); 150 static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *); 151 152 static void wb_rxeof(struct wb_softc *); 153 static void wb_rxeoc(struct wb_softc *); 154 static void wb_txeof(struct wb_softc *); 155 static void wb_txeoc(struct wb_softc *); 156 static void wb_intr(void *); 157 static void wb_tick(void *); 158 static void wb_start(struct ifnet *); 159 static int wb_ioctl(struct ifnet *, u_long, caddr_t); 160 static void wb_init(void *); 161 static void wb_stop(struct wb_softc *); 162 static void wb_watchdog(struct ifnet *); 163 static void wb_shutdown(device_t); 164 static int wb_ifmedia_upd(struct ifnet *); 165 static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 166 167 static void wb_eeprom_putbyte(struct wb_softc *, int); 168 static void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *); 169 static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int); 170 static void wb_mii_sync(struct wb_softc *); 171 static void wb_mii_send(struct wb_softc *, u_int32_t, int); 172 static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *); 173 static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *); 174 175 static void wb_setcfg(struct wb_softc *, u_int32_t); 176 static void wb_setmulti(struct wb_softc *); 177 static void wb_reset(struct wb_softc *); 178 static void wb_fixmedia(struct wb_softc *); 179 static int wb_list_rx_init(struct wb_softc *); 180 static int wb_list_tx_init(struct wb_softc *); 181 182 static int wb_miibus_readreg(device_t, int, int); 183 static int wb_miibus_writereg(device_t, int, int, int); 184 static void wb_miibus_statchg(device_t); 185 186 #ifdef WB_USEIOSPACE 187 #define WB_RES SYS_RES_IOPORT 188 #define WB_RID WB_PCI_LOIO 189 #else 190 #define WB_RES SYS_RES_MEMORY 191 #define WB_RID WB_PCI_LOMEM 192 #endif 193 194 static device_method_t wb_methods[] = { 195 /* Device interface */ 196 DEVMETHOD(device_probe, wb_probe), 197 DEVMETHOD(device_attach, wb_attach), 198 DEVMETHOD(device_detach, wb_detach), 199 DEVMETHOD(device_shutdown, wb_shutdown), 200 201 /* bus interface, for miibus */ 202 DEVMETHOD(bus_print_child, bus_generic_print_child), 203 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 204 205 /* MII interface */ 206 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 207 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 208 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 209 { 0, 0 } 210 }; 211 212 static driver_t wb_driver = { 213 "wb", 214 wb_methods, 215 sizeof(struct wb_softc) 216 }; 217 218 static devclass_t wb_devclass; 219 220 DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 221 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 222 223 #define WB_SETBIT(sc, reg, x) \ 224 CSR_WRITE_4(sc, reg, \ 225 CSR_READ_4(sc, reg) | (x)) 226 227 #define WB_CLRBIT(sc, reg, x) \ 228 CSR_WRITE_4(sc, reg, \ 229 CSR_READ_4(sc, reg) & ~(x)) 230 231 #define SIO_SET(x) \ 232 CSR_WRITE_4(sc, WB_SIO, \ 233 CSR_READ_4(sc, WB_SIO) | (x)) 234 235 #define SIO_CLR(x) \ 236 CSR_WRITE_4(sc, WB_SIO, \ 237 CSR_READ_4(sc, WB_SIO) & ~(x)) 238 239 /* 240 * Send a read command and address to the EEPROM, check for ACK. 241 */ 242 static void 243 wb_eeprom_putbyte(sc, addr) 244 struct wb_softc *sc; 245 int addr; 246 { 247 register int d, i; 248 249 d = addr | WB_EECMD_READ; 250 251 /* 252 * Feed in each bit and stobe the clock. 253 */ 254 for (i = 0x400; i; i >>= 1) { 255 if (d & i) { 256 SIO_SET(WB_SIO_EE_DATAIN); 257 } else { 258 SIO_CLR(WB_SIO_EE_DATAIN); 259 } 260 DELAY(100); 261 SIO_SET(WB_SIO_EE_CLK); 262 DELAY(150); 263 SIO_CLR(WB_SIO_EE_CLK); 264 DELAY(100); 265 } 266 267 return; 268 } 269 270 /* 271 * Read a word of data stored in the EEPROM at address 'addr.' 272 */ 273 static void 274 wb_eeprom_getword(sc, addr, dest) 275 struct wb_softc *sc; 276 int addr; 277 u_int16_t *dest; 278 { 279 register int i; 280 u_int16_t word = 0; 281 282 /* Enter EEPROM access mode. */ 283 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 284 285 /* 286 * Send address of word we want to read. 287 */ 288 wb_eeprom_putbyte(sc, addr); 289 290 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 291 292 /* 293 * Start reading bits from EEPROM. 294 */ 295 for (i = 0x8000; i; i >>= 1) { 296 SIO_SET(WB_SIO_EE_CLK); 297 DELAY(100); 298 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 299 word |= i; 300 SIO_CLR(WB_SIO_EE_CLK); 301 DELAY(100); 302 } 303 304 /* Turn off EEPROM access mode. */ 305 CSR_WRITE_4(sc, WB_SIO, 0); 306 307 *dest = word; 308 309 return; 310 } 311 312 /* 313 * Read a sequence of words from the EEPROM. 314 */ 315 static void 316 wb_read_eeprom(sc, dest, off, cnt, swap) 317 struct wb_softc *sc; 318 caddr_t dest; 319 int off; 320 int cnt; 321 int swap; 322 { 323 int i; 324 u_int16_t word = 0, *ptr; 325 326 for (i = 0; i < cnt; i++) { 327 wb_eeprom_getword(sc, off + i, &word); 328 ptr = (u_int16_t *)(dest + (i * 2)); 329 if (swap) 330 *ptr = ntohs(word); 331 else 332 *ptr = word; 333 } 334 335 return; 336 } 337 338 /* 339 * Sync the PHYs by setting data bit and strobing the clock 32 times. 340 */ 341 static void 342 wb_mii_sync(sc) 343 struct wb_softc *sc; 344 { 345 register int i; 346 347 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 348 349 for (i = 0; i < 32; i++) { 350 SIO_SET(WB_SIO_MII_CLK); 351 DELAY(1); 352 SIO_CLR(WB_SIO_MII_CLK); 353 DELAY(1); 354 } 355 356 return; 357 } 358 359 /* 360 * Clock a series of bits through the MII. 361 */ 362 static void 363 wb_mii_send(sc, bits, cnt) 364 struct wb_softc *sc; 365 u_int32_t bits; 366 int cnt; 367 { 368 int i; 369 370 SIO_CLR(WB_SIO_MII_CLK); 371 372 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 373 if (bits & i) { 374 SIO_SET(WB_SIO_MII_DATAIN); 375 } else { 376 SIO_CLR(WB_SIO_MII_DATAIN); 377 } 378 DELAY(1); 379 SIO_CLR(WB_SIO_MII_CLK); 380 DELAY(1); 381 SIO_SET(WB_SIO_MII_CLK); 382 } 383 } 384 385 /* 386 * Read an PHY register through the MII. 387 */ 388 static int 389 wb_mii_readreg(sc, frame) 390 struct wb_softc *sc; 391 struct wb_mii_frame *frame; 392 393 { 394 int i, ack; 395 396 WB_LOCK(sc); 397 398 /* 399 * Set up frame for RX. 400 */ 401 frame->mii_stdelim = WB_MII_STARTDELIM; 402 frame->mii_opcode = WB_MII_READOP; 403 frame->mii_turnaround = 0; 404 frame->mii_data = 0; 405 406 CSR_WRITE_4(sc, WB_SIO, 0); 407 408 /* 409 * Turn on data xmit. 410 */ 411 SIO_SET(WB_SIO_MII_DIR); 412 413 wb_mii_sync(sc); 414 415 /* 416 * Send command/address info. 417 */ 418 wb_mii_send(sc, frame->mii_stdelim, 2); 419 wb_mii_send(sc, frame->mii_opcode, 2); 420 wb_mii_send(sc, frame->mii_phyaddr, 5); 421 wb_mii_send(sc, frame->mii_regaddr, 5); 422 423 /* Idle bit */ 424 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 425 DELAY(1); 426 SIO_SET(WB_SIO_MII_CLK); 427 DELAY(1); 428 429 /* Turn off xmit. */ 430 SIO_CLR(WB_SIO_MII_DIR); 431 /* Check for ack */ 432 SIO_CLR(WB_SIO_MII_CLK); 433 DELAY(1); 434 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 435 SIO_SET(WB_SIO_MII_CLK); 436 DELAY(1); 437 SIO_CLR(WB_SIO_MII_CLK); 438 DELAY(1); 439 SIO_SET(WB_SIO_MII_CLK); 440 DELAY(1); 441 442 /* 443 * Now try reading data bits. If the ack failed, we still 444 * need to clock through 16 cycles to keep the PHY(s) in sync. 445 */ 446 if (ack) { 447 for(i = 0; i < 16; i++) { 448 SIO_CLR(WB_SIO_MII_CLK); 449 DELAY(1); 450 SIO_SET(WB_SIO_MII_CLK); 451 DELAY(1); 452 } 453 goto fail; 454 } 455 456 for (i = 0x8000; i; i >>= 1) { 457 SIO_CLR(WB_SIO_MII_CLK); 458 DELAY(1); 459 if (!ack) { 460 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 461 frame->mii_data |= i; 462 DELAY(1); 463 } 464 SIO_SET(WB_SIO_MII_CLK); 465 DELAY(1); 466 } 467 468 fail: 469 470 SIO_CLR(WB_SIO_MII_CLK); 471 DELAY(1); 472 SIO_SET(WB_SIO_MII_CLK); 473 DELAY(1); 474 475 WB_UNLOCK(sc); 476 477 if (ack) 478 return(1); 479 return(0); 480 } 481 482 /* 483 * Write to a PHY register through the MII. 484 */ 485 static int 486 wb_mii_writereg(sc, frame) 487 struct wb_softc *sc; 488 struct wb_mii_frame *frame; 489 490 { 491 WB_LOCK(sc); 492 493 /* 494 * Set up frame for TX. 495 */ 496 497 frame->mii_stdelim = WB_MII_STARTDELIM; 498 frame->mii_opcode = WB_MII_WRITEOP; 499 frame->mii_turnaround = WB_MII_TURNAROUND; 500 501 /* 502 * Turn on data output. 503 */ 504 SIO_SET(WB_SIO_MII_DIR); 505 506 wb_mii_sync(sc); 507 508 wb_mii_send(sc, frame->mii_stdelim, 2); 509 wb_mii_send(sc, frame->mii_opcode, 2); 510 wb_mii_send(sc, frame->mii_phyaddr, 5); 511 wb_mii_send(sc, frame->mii_regaddr, 5); 512 wb_mii_send(sc, frame->mii_turnaround, 2); 513 wb_mii_send(sc, frame->mii_data, 16); 514 515 /* Idle bit. */ 516 SIO_SET(WB_SIO_MII_CLK); 517 DELAY(1); 518 SIO_CLR(WB_SIO_MII_CLK); 519 DELAY(1); 520 521 /* 522 * Turn off xmit. 523 */ 524 SIO_CLR(WB_SIO_MII_DIR); 525 526 WB_UNLOCK(sc); 527 528 return(0); 529 } 530 531 static int 532 wb_miibus_readreg(dev, phy, reg) 533 device_t dev; 534 int phy, reg; 535 { 536 struct wb_softc *sc; 537 struct wb_mii_frame frame; 538 539 sc = device_get_softc(dev); 540 541 bzero((char *)&frame, sizeof(frame)); 542 543 frame.mii_phyaddr = phy; 544 frame.mii_regaddr = reg; 545 wb_mii_readreg(sc, &frame); 546 547 return(frame.mii_data); 548 } 549 550 static int 551 wb_miibus_writereg(dev, phy, reg, data) 552 device_t dev; 553 int phy, reg, data; 554 { 555 struct wb_softc *sc; 556 struct wb_mii_frame frame; 557 558 sc = device_get_softc(dev); 559 560 bzero((char *)&frame, sizeof(frame)); 561 562 frame.mii_phyaddr = phy; 563 frame.mii_regaddr = reg; 564 frame.mii_data = data; 565 566 wb_mii_writereg(sc, &frame); 567 568 return(0); 569 } 570 571 static void 572 wb_miibus_statchg(dev) 573 device_t dev; 574 { 575 struct wb_softc *sc; 576 struct mii_data *mii; 577 578 sc = device_get_softc(dev); 579 WB_LOCK(sc); 580 mii = device_get_softc(sc->wb_miibus); 581 wb_setcfg(sc, mii->mii_media_active); 582 WB_UNLOCK(sc); 583 584 return; 585 } 586 587 /* 588 * Program the 64-bit multicast hash filter. 589 */ 590 static void 591 wb_setmulti(sc) 592 struct wb_softc *sc; 593 { 594 struct ifnet *ifp; 595 int h = 0; 596 u_int32_t hashes[2] = { 0, 0 }; 597 struct ifmultiaddr *ifma; 598 u_int32_t rxfilt; 599 int mcnt = 0; 600 601 ifp = &sc->arpcom.ac_if; 602 603 rxfilt = CSR_READ_4(sc, WB_NETCFG); 604 605 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 606 rxfilt |= WB_NETCFG_RX_MULTI; 607 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 608 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 609 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 610 return; 611 } 612 613 /* first, zot all the existing hash bits */ 614 CSR_WRITE_4(sc, WB_MAR0, 0); 615 CSR_WRITE_4(sc, WB_MAR1, 0); 616 617 /* now program new ones */ 618 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 619 if (ifma->ifma_addr->sa_family != AF_LINK) 620 continue; 621 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 622 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 623 if (h < 32) 624 hashes[0] |= (1 << h); 625 else 626 hashes[1] |= (1 << (h - 32)); 627 mcnt++; 628 } 629 630 if (mcnt) 631 rxfilt |= WB_NETCFG_RX_MULTI; 632 else 633 rxfilt &= ~WB_NETCFG_RX_MULTI; 634 635 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 636 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 637 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 638 639 return; 640 } 641 642 /* 643 * The Winbond manual states that in order to fiddle with the 644 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 645 * first have to put the transmit and/or receive logic in the idle state. 646 */ 647 static void 648 wb_setcfg(sc, media) 649 struct wb_softc *sc; 650 u_int32_t media; 651 { 652 int i, restart = 0; 653 654 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 655 restart = 1; 656 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 657 658 for (i = 0; i < WB_TIMEOUT; i++) { 659 DELAY(10); 660 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 661 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 662 break; 663 } 664 665 if (i == WB_TIMEOUT) 666 printf("wb%d: failed to force tx and " 667 "rx to idle state\n", sc->wb_unit); 668 } 669 670 if (IFM_SUBTYPE(media) == IFM_10_T) 671 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 672 else 673 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 674 675 if ((media & IFM_GMASK) == IFM_FDX) 676 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 677 else 678 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 679 680 if (restart) 681 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 682 683 return; 684 } 685 686 static void 687 wb_reset(sc) 688 struct wb_softc *sc; 689 { 690 register int i; 691 struct mii_data *mii; 692 693 CSR_WRITE_4(sc, WB_NETCFG, 0); 694 CSR_WRITE_4(sc, WB_BUSCTL, 0); 695 CSR_WRITE_4(sc, WB_TXADDR, 0); 696 CSR_WRITE_4(sc, WB_RXADDR, 0); 697 698 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 699 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 700 701 for (i = 0; i < WB_TIMEOUT; i++) { 702 DELAY(10); 703 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 704 break; 705 } 706 if (i == WB_TIMEOUT) 707 printf("wb%d: reset never completed!\n", sc->wb_unit); 708 709 /* Wait a little while for the chip to get its brains in order. */ 710 DELAY(1000); 711 712 if (sc->wb_miibus == NULL) 713 return; 714 715 mii = device_get_softc(sc->wb_miibus); 716 if (mii == NULL) 717 return; 718 719 if (mii->mii_instance) { 720 struct mii_softc *miisc; 721 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 722 mii_phy_reset(miisc); 723 } 724 725 return; 726 } 727 728 static void 729 wb_fixmedia(sc) 730 struct wb_softc *sc; 731 { 732 struct mii_data *mii = NULL; 733 struct ifnet *ifp; 734 u_int32_t media; 735 736 if (sc->wb_miibus == NULL) 737 return; 738 739 mii = device_get_softc(sc->wb_miibus); 740 ifp = &sc->arpcom.ac_if; 741 742 mii_pollstat(mii); 743 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 744 media = mii->mii_media_active & ~IFM_10_T; 745 media |= IFM_100_TX; 746 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 747 media = mii->mii_media_active & ~IFM_100_TX; 748 media |= IFM_10_T; 749 } else 750 return; 751 752 ifmedia_set(&mii->mii_media, media); 753 754 return; 755 } 756 757 /* 758 * Probe for a Winbond chip. Check the PCI vendor and device 759 * IDs against our list and return a device name if we find a match. 760 */ 761 static int 762 wb_probe(dev) 763 device_t dev; 764 { 765 struct wb_type *t; 766 767 t = wb_devs; 768 769 while(t->wb_name != NULL) { 770 if ((pci_get_vendor(dev) == t->wb_vid) && 771 (pci_get_device(dev) == t->wb_did)) { 772 device_set_desc(dev, t->wb_name); 773 return (BUS_PROBE_DEFAULT); 774 } 775 t++; 776 } 777 778 return(ENXIO); 779 } 780 781 /* 782 * Attach the interface. Allocate softc structures, do ifmedia 783 * setup and ethernet/BPF attach. 784 */ 785 static int 786 wb_attach(dev) 787 device_t dev; 788 { 789 u_char eaddr[ETHER_ADDR_LEN]; 790 struct wb_softc *sc; 791 struct ifnet *ifp; 792 int unit, error = 0, rid; 793 794 sc = device_get_softc(dev); 795 unit = device_get_unit(dev); 796 797 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 798 MTX_DEF | MTX_RECURSE); 799 /* 800 * Map control/status registers. 801 */ 802 pci_enable_busmaster(dev); 803 804 rid = WB_RID; 805 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 806 807 if (sc->wb_res == NULL) { 808 printf("wb%d: couldn't map ports/memory\n", unit); 809 error = ENXIO; 810 goto fail; 811 } 812 813 sc->wb_btag = rman_get_bustag(sc->wb_res); 814 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 815 816 /* Allocate interrupt */ 817 rid = 0; 818 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 819 RF_SHAREABLE | RF_ACTIVE); 820 821 if (sc->wb_irq == NULL) { 822 printf("wb%d: couldn't map interrupt\n", unit); 823 error = ENXIO; 824 goto fail; 825 } 826 827 /* Save the cache line size. */ 828 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 829 830 /* Reset the adapter. */ 831 wb_reset(sc); 832 833 /* 834 * Get station address from the EEPROM. 835 */ 836 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 837 838 sc->wb_unit = unit; 839 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 840 841 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 842 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 843 844 if (sc->wb_ldata == NULL) { 845 printf("wb%d: no memory for list buffers!\n", unit); 846 error = ENXIO; 847 goto fail; 848 } 849 850 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 851 852 ifp = &sc->arpcom.ac_if; 853 ifp->if_softc = sc; 854 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 855 ifp->if_mtu = ETHERMTU; 856 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 857 IFF_NEEDSGIANT; 858 ifp->if_ioctl = wb_ioctl; 859 ifp->if_start = wb_start; 860 ifp->if_watchdog = wb_watchdog; 861 ifp->if_init = wb_init; 862 ifp->if_baudrate = 10000000; 863 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 864 865 /* 866 * Do MII setup. 867 */ 868 if (mii_phy_probe(dev, &sc->wb_miibus, 869 wb_ifmedia_upd, wb_ifmedia_sts)) { 870 error = ENXIO; 871 goto fail; 872 } 873 874 /* 875 * Call MI attach routine. 876 */ 877 ether_ifattach(ifp, eaddr); 878 879 /* Hook interrupt last to avoid having to lock softc */ 880 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 881 wb_intr, sc, &sc->wb_intrhand); 882 883 if (error) { 884 printf("wb%d: couldn't set up irq\n", unit); 885 ether_ifdetach(ifp); 886 goto fail; 887 } 888 889 fail: 890 if (error) 891 wb_detach(dev); 892 893 return(error); 894 } 895 896 /* 897 * Shutdown hardware and free up resources. This can be called any 898 * time after the mutex has been initialized. It is called in both 899 * the error case in attach and the normal detach case so it needs 900 * to be careful about only freeing resources that have actually been 901 * allocated. 902 */ 903 static int 904 wb_detach(dev) 905 device_t dev; 906 { 907 struct wb_softc *sc; 908 struct ifnet *ifp; 909 910 sc = device_get_softc(dev); 911 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 912 WB_LOCK(sc); 913 ifp = &sc->arpcom.ac_if; 914 915 /* 916 * Delete any miibus and phy devices attached to this interface. 917 * This should only be done if attach succeeded. 918 */ 919 if (device_is_attached(dev)) { 920 wb_stop(sc); 921 ether_ifdetach(ifp); 922 } 923 if (sc->wb_miibus) 924 device_delete_child(dev, sc->wb_miibus); 925 bus_generic_detach(dev); 926 927 if (sc->wb_intrhand) 928 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 929 if (sc->wb_irq) 930 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 931 if (sc->wb_res) 932 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 933 934 if (sc->wb_ldata) { 935 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 936 M_DEVBUF); 937 } 938 939 WB_UNLOCK(sc); 940 mtx_destroy(&sc->wb_mtx); 941 942 return(0); 943 } 944 945 /* 946 * Initialize the transmit descriptors. 947 */ 948 static int 949 wb_list_tx_init(sc) 950 struct wb_softc *sc; 951 { 952 struct wb_chain_data *cd; 953 struct wb_list_data *ld; 954 int i; 955 956 cd = &sc->wb_cdata; 957 ld = sc->wb_ldata; 958 959 for (i = 0; i < WB_TX_LIST_CNT; i++) { 960 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 961 if (i == (WB_TX_LIST_CNT - 1)) { 962 cd->wb_tx_chain[i].wb_nextdesc = 963 &cd->wb_tx_chain[0]; 964 } else { 965 cd->wb_tx_chain[i].wb_nextdesc = 966 &cd->wb_tx_chain[i + 1]; 967 } 968 } 969 970 cd->wb_tx_free = &cd->wb_tx_chain[0]; 971 cd->wb_tx_tail = cd->wb_tx_head = NULL; 972 973 return(0); 974 } 975 976 977 /* 978 * Initialize the RX descriptors and allocate mbufs for them. Note that 979 * we arrange the descriptors in a closed ring, so that the last descriptor 980 * points back to the first. 981 */ 982 static int 983 wb_list_rx_init(sc) 984 struct wb_softc *sc; 985 { 986 struct wb_chain_data *cd; 987 struct wb_list_data *ld; 988 int i; 989 990 cd = &sc->wb_cdata; 991 ld = sc->wb_ldata; 992 993 for (i = 0; i < WB_RX_LIST_CNT; i++) { 994 cd->wb_rx_chain[i].wb_ptr = 995 (struct wb_desc *)&ld->wb_rx_list[i]; 996 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 997 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 998 return(ENOBUFS); 999 if (i == (WB_RX_LIST_CNT - 1)) { 1000 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1001 ld->wb_rx_list[i].wb_next = 1002 vtophys(&ld->wb_rx_list[0]); 1003 } else { 1004 cd->wb_rx_chain[i].wb_nextdesc = 1005 &cd->wb_rx_chain[i + 1]; 1006 ld->wb_rx_list[i].wb_next = 1007 vtophys(&ld->wb_rx_list[i + 1]); 1008 } 1009 } 1010 1011 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1012 1013 return(0); 1014 } 1015 1016 static void 1017 wb_bfree(buf, args) 1018 void *buf; 1019 void *args; 1020 { 1021 return; 1022 } 1023 1024 /* 1025 * Initialize an RX descriptor and attach an MBUF cluster. 1026 */ 1027 static int 1028 wb_newbuf(sc, c, m) 1029 struct wb_softc *sc; 1030 struct wb_chain_onefrag *c; 1031 struct mbuf *m; 1032 { 1033 struct mbuf *m_new = NULL; 1034 1035 if (m == NULL) { 1036 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1037 if (m_new == NULL) 1038 return(ENOBUFS); 1039 m_new->m_data = c->wb_buf; 1040 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1041 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 1042 EXT_NET_DRV); 1043 } else { 1044 m_new = m; 1045 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1046 m_new->m_data = m_new->m_ext.ext_buf; 1047 } 1048 1049 m_adj(m_new, sizeof(u_int64_t)); 1050 1051 c->wb_mbuf = m_new; 1052 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1053 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1054 c->wb_ptr->wb_status = WB_RXSTAT; 1055 1056 return(0); 1057 } 1058 1059 /* 1060 * A frame has been uploaded: pass the resulting mbuf chain up to 1061 * the higher level protocols. 1062 */ 1063 static void 1064 wb_rxeof(sc) 1065 struct wb_softc *sc; 1066 { 1067 struct mbuf *m = NULL; 1068 struct ifnet *ifp; 1069 struct wb_chain_onefrag *cur_rx; 1070 int total_len = 0; 1071 u_int32_t rxstat; 1072 1073 WB_LOCK_ASSERT(sc); 1074 1075 ifp = &sc->arpcom.ac_if; 1076 1077 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1078 WB_RXSTAT_OWN)) { 1079 struct mbuf *m0 = NULL; 1080 1081 cur_rx = sc->wb_cdata.wb_rx_head; 1082 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1083 1084 m = cur_rx->wb_mbuf; 1085 1086 if ((rxstat & WB_RXSTAT_MIIERR) || 1087 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1088 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1089 !(rxstat & WB_RXSTAT_LASTFRAG) || 1090 !(rxstat & WB_RXSTAT_RXCMP)) { 1091 ifp->if_ierrors++; 1092 wb_newbuf(sc, cur_rx, m); 1093 printf("wb%x: receiver babbling: possible chip " 1094 "bug, forcing reset\n", sc->wb_unit); 1095 wb_fixmedia(sc); 1096 wb_reset(sc); 1097 wb_init(sc); 1098 return; 1099 } 1100 1101 if (rxstat & WB_RXSTAT_RXERR) { 1102 ifp->if_ierrors++; 1103 wb_newbuf(sc, cur_rx, m); 1104 break; 1105 } 1106 1107 /* No errors; receive the packet. */ 1108 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1109 1110 /* 1111 * XXX The Winbond chip includes the CRC with every 1112 * received frame, and there's no way to turn this 1113 * behavior off (at least, I can't find anything in 1114 * the manual that explains how to do it) so we have 1115 * to trim off the CRC manually. 1116 */ 1117 total_len -= ETHER_CRC_LEN; 1118 1119 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1120 NULL); 1121 wb_newbuf(sc, cur_rx, m); 1122 if (m0 == NULL) { 1123 ifp->if_ierrors++; 1124 break; 1125 } 1126 m = m0; 1127 1128 ifp->if_ipackets++; 1129 WB_UNLOCK(sc); 1130 (*ifp->if_input)(ifp, m); 1131 WB_LOCK(sc); 1132 } 1133 } 1134 1135 static void 1136 wb_rxeoc(sc) 1137 struct wb_softc *sc; 1138 { 1139 wb_rxeof(sc); 1140 1141 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1142 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1143 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1144 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1145 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1146 1147 return; 1148 } 1149 1150 /* 1151 * A frame was downloaded to the chip. It's safe for us to clean up 1152 * the list buffers. 1153 */ 1154 static void 1155 wb_txeof(sc) 1156 struct wb_softc *sc; 1157 { 1158 struct wb_chain *cur_tx; 1159 struct ifnet *ifp; 1160 1161 ifp = &sc->arpcom.ac_if; 1162 1163 /* Clear the timeout timer. */ 1164 ifp->if_timer = 0; 1165 1166 if (sc->wb_cdata.wb_tx_head == NULL) 1167 return; 1168 1169 /* 1170 * Go through our tx list and free mbufs for those 1171 * frames that have been transmitted. 1172 */ 1173 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1174 u_int32_t txstat; 1175 1176 cur_tx = sc->wb_cdata.wb_tx_head; 1177 txstat = WB_TXSTATUS(cur_tx); 1178 1179 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1180 break; 1181 1182 if (txstat & WB_TXSTAT_TXERR) { 1183 ifp->if_oerrors++; 1184 if (txstat & WB_TXSTAT_ABORT) 1185 ifp->if_collisions++; 1186 if (txstat & WB_TXSTAT_LATECOLL) 1187 ifp->if_collisions++; 1188 } 1189 1190 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1191 1192 ifp->if_opackets++; 1193 m_freem(cur_tx->wb_mbuf); 1194 cur_tx->wb_mbuf = NULL; 1195 1196 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1197 sc->wb_cdata.wb_tx_head = NULL; 1198 sc->wb_cdata.wb_tx_tail = NULL; 1199 break; 1200 } 1201 1202 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1203 } 1204 1205 return; 1206 } 1207 1208 /* 1209 * TX 'end of channel' interrupt handler. 1210 */ 1211 static void 1212 wb_txeoc(sc) 1213 struct wb_softc *sc; 1214 { 1215 struct ifnet *ifp; 1216 1217 ifp = &sc->arpcom.ac_if; 1218 1219 ifp->if_timer = 0; 1220 1221 if (sc->wb_cdata.wb_tx_head == NULL) { 1222 ifp->if_flags &= ~IFF_OACTIVE; 1223 sc->wb_cdata.wb_tx_tail = NULL; 1224 } else { 1225 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1226 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1227 ifp->if_timer = 5; 1228 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1229 } 1230 } 1231 1232 return; 1233 } 1234 1235 static void 1236 wb_intr(arg) 1237 void *arg; 1238 { 1239 struct wb_softc *sc; 1240 struct ifnet *ifp; 1241 u_int32_t status; 1242 1243 sc = arg; 1244 WB_LOCK(sc); 1245 ifp = &sc->arpcom.ac_if; 1246 1247 if (!(ifp->if_flags & IFF_UP)) { 1248 WB_UNLOCK(sc); 1249 return; 1250 } 1251 1252 /* Disable interrupts. */ 1253 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1254 1255 for (;;) { 1256 1257 status = CSR_READ_4(sc, WB_ISR); 1258 if (status) 1259 CSR_WRITE_4(sc, WB_ISR, status); 1260 1261 if ((status & WB_INTRS) == 0) 1262 break; 1263 1264 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1265 ifp->if_ierrors++; 1266 wb_reset(sc); 1267 if (status & WB_ISR_RX_ERR) 1268 wb_fixmedia(sc); 1269 wb_init(sc); 1270 continue; 1271 } 1272 1273 if (status & WB_ISR_RX_OK) 1274 wb_rxeof(sc); 1275 1276 if (status & WB_ISR_RX_IDLE) 1277 wb_rxeoc(sc); 1278 1279 if (status & WB_ISR_TX_OK) 1280 wb_txeof(sc); 1281 1282 if (status & WB_ISR_TX_NOBUF) 1283 wb_txeoc(sc); 1284 1285 if (status & WB_ISR_TX_IDLE) { 1286 wb_txeof(sc); 1287 if (sc->wb_cdata.wb_tx_head != NULL) { 1288 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1289 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1290 } 1291 } 1292 1293 if (status & WB_ISR_TX_UNDERRUN) { 1294 ifp->if_oerrors++; 1295 wb_txeof(sc); 1296 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1297 /* Jack up TX threshold */ 1298 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1299 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1300 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1301 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1302 } 1303 1304 if (status & WB_ISR_BUS_ERR) { 1305 wb_reset(sc); 1306 wb_init(sc); 1307 } 1308 1309 } 1310 1311 /* Re-enable interrupts. */ 1312 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1313 1314 if (ifp->if_snd.ifq_head != NULL) { 1315 wb_start(ifp); 1316 } 1317 1318 WB_UNLOCK(sc); 1319 1320 return; 1321 } 1322 1323 static void 1324 wb_tick(xsc) 1325 void *xsc; 1326 { 1327 struct wb_softc *sc; 1328 struct mii_data *mii; 1329 1330 sc = xsc; 1331 WB_LOCK(sc); 1332 mii = device_get_softc(sc->wb_miibus); 1333 1334 mii_tick(mii); 1335 1336 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1337 1338 WB_UNLOCK(sc); 1339 1340 return; 1341 } 1342 1343 /* 1344 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1345 * pointers to the fragment pointers. 1346 */ 1347 static int 1348 wb_encap(sc, c, m_head) 1349 struct wb_softc *sc; 1350 struct wb_chain *c; 1351 struct mbuf *m_head; 1352 { 1353 int frag = 0; 1354 struct wb_desc *f = NULL; 1355 int total_len; 1356 struct mbuf *m; 1357 1358 /* 1359 * Start packing the mbufs in this chain into 1360 * the fragment pointers. Stop when we run out 1361 * of fragments or hit the end of the mbuf chain. 1362 */ 1363 m = m_head; 1364 total_len = 0; 1365 1366 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1367 if (m->m_len != 0) { 1368 if (frag == WB_MAXFRAGS) 1369 break; 1370 total_len += m->m_len; 1371 f = &c->wb_ptr->wb_frag[frag]; 1372 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1373 if (frag == 0) { 1374 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1375 f->wb_status = 0; 1376 } else 1377 f->wb_status = WB_TXSTAT_OWN; 1378 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1379 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1380 frag++; 1381 } 1382 } 1383 1384 /* 1385 * Handle special case: we used up all 16 fragments, 1386 * but we have more mbufs left in the chain. Copy the 1387 * data into an mbuf cluster. Note that we don't 1388 * bother clearing the values in the other fragment 1389 * pointers/counters; it wouldn't gain us anything, 1390 * and would waste cycles. 1391 */ 1392 if (m != NULL) { 1393 struct mbuf *m_new = NULL; 1394 1395 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1396 if (m_new == NULL) 1397 return(1); 1398 if (m_head->m_pkthdr.len > MHLEN) { 1399 MCLGET(m_new, M_DONTWAIT); 1400 if (!(m_new->m_flags & M_EXT)) { 1401 m_freem(m_new); 1402 return(1); 1403 } 1404 } 1405 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1406 mtod(m_new, caddr_t)); 1407 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1408 m_freem(m_head); 1409 m_head = m_new; 1410 f = &c->wb_ptr->wb_frag[0]; 1411 f->wb_status = 0; 1412 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1413 f->wb_ctl = total_len = m_new->m_len; 1414 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1415 frag = 1; 1416 } 1417 1418 if (total_len < WB_MIN_FRAMELEN) { 1419 f = &c->wb_ptr->wb_frag[frag]; 1420 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1421 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1422 f->wb_ctl |= WB_TXCTL_TLINK; 1423 f->wb_status = WB_TXSTAT_OWN; 1424 frag++; 1425 } 1426 1427 c->wb_mbuf = m_head; 1428 c->wb_lastdesc = frag - 1; 1429 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1430 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1431 1432 return(0); 1433 } 1434 1435 /* 1436 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1437 * to the mbuf data regions directly in the transmit lists. We also save a 1438 * copy of the pointers since the transmit list fragment pointers are 1439 * physical addresses. 1440 */ 1441 1442 static void 1443 wb_start(ifp) 1444 struct ifnet *ifp; 1445 { 1446 struct wb_softc *sc; 1447 struct mbuf *m_head = NULL; 1448 struct wb_chain *cur_tx = NULL, *start_tx; 1449 1450 sc = ifp->if_softc; 1451 WB_LOCK(sc); 1452 1453 /* 1454 * Check for an available queue slot. If there are none, 1455 * punt. 1456 */ 1457 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1458 ifp->if_flags |= IFF_OACTIVE; 1459 WB_UNLOCK(sc); 1460 return; 1461 } 1462 1463 start_tx = sc->wb_cdata.wb_tx_free; 1464 1465 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1466 IF_DEQUEUE(&ifp->if_snd, m_head); 1467 if (m_head == NULL) 1468 break; 1469 1470 /* Pick a descriptor off the free list. */ 1471 cur_tx = sc->wb_cdata.wb_tx_free; 1472 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1473 1474 /* Pack the data into the descriptor. */ 1475 wb_encap(sc, cur_tx, m_head); 1476 1477 if (cur_tx != start_tx) 1478 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1479 1480 /* 1481 * If there's a BPF listener, bounce a copy of this frame 1482 * to him. 1483 */ 1484 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1485 } 1486 1487 /* 1488 * If there are no packets queued, bail. 1489 */ 1490 if (cur_tx == NULL) { 1491 WB_UNLOCK(sc); 1492 return; 1493 } 1494 1495 /* 1496 * Place the request for the upload interrupt 1497 * in the last descriptor in the chain. This way, if 1498 * we're chaining several packets at once, we'll only 1499 * get an interupt once for the whole chain rather than 1500 * once for each packet. 1501 */ 1502 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1503 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1504 sc->wb_cdata.wb_tx_tail = cur_tx; 1505 1506 if (sc->wb_cdata.wb_tx_head == NULL) { 1507 sc->wb_cdata.wb_tx_head = start_tx; 1508 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1509 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1510 } else { 1511 /* 1512 * We need to distinguish between the case where 1513 * the own bit is clear because the chip cleared it 1514 * and where the own bit is clear because we haven't 1515 * set it yet. The magic value WB_UNSET is just some 1516 * ramdomly chosen number which doesn't have the own 1517 * bit set. When we actually transmit the frame, the 1518 * status word will have _only_ the own bit set, so 1519 * the txeoc handler will be able to tell if it needs 1520 * to initiate another transmission to flush out pending 1521 * frames. 1522 */ 1523 WB_TXOWN(start_tx) = WB_UNSENT; 1524 } 1525 1526 /* 1527 * Set a timeout in case the chip goes out to lunch. 1528 */ 1529 ifp->if_timer = 5; 1530 WB_UNLOCK(sc); 1531 1532 return; 1533 } 1534 1535 static void 1536 wb_init(xsc) 1537 void *xsc; 1538 { 1539 struct wb_softc *sc = xsc; 1540 struct ifnet *ifp = &sc->arpcom.ac_if; 1541 int i; 1542 struct mii_data *mii; 1543 1544 WB_LOCK(sc); 1545 mii = device_get_softc(sc->wb_miibus); 1546 1547 /* 1548 * Cancel pending I/O and free all RX/TX buffers. 1549 */ 1550 wb_stop(sc); 1551 wb_reset(sc); 1552 1553 sc->wb_txthresh = WB_TXTHRESH_INIT; 1554 1555 /* 1556 * Set cache alignment and burst length. 1557 */ 1558 #ifdef foo 1559 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1560 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1561 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1562 #endif 1563 1564 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1565 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1566 switch(sc->wb_cachesize) { 1567 case 32: 1568 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1569 break; 1570 case 16: 1571 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1572 break; 1573 case 8: 1574 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1575 break; 1576 case 0: 1577 default: 1578 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1579 break; 1580 } 1581 1582 /* This doesn't tend to work too well at 100Mbps. */ 1583 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1584 1585 /* Init our MAC address */ 1586 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1587 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1588 } 1589 1590 /* Init circular RX list. */ 1591 if (wb_list_rx_init(sc) == ENOBUFS) { 1592 printf("wb%d: initialization failed: no " 1593 "memory for rx buffers\n", sc->wb_unit); 1594 wb_stop(sc); 1595 WB_UNLOCK(sc); 1596 return; 1597 } 1598 1599 /* Init TX descriptors. */ 1600 wb_list_tx_init(sc); 1601 1602 /* If we want promiscuous mode, set the allframes bit. */ 1603 if (ifp->if_flags & IFF_PROMISC) { 1604 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1605 } else { 1606 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1607 } 1608 1609 /* 1610 * Set capture broadcast bit to capture broadcast frames. 1611 */ 1612 if (ifp->if_flags & IFF_BROADCAST) { 1613 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1614 } else { 1615 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1616 } 1617 1618 /* 1619 * Program the multicast filter, if necessary. 1620 */ 1621 wb_setmulti(sc); 1622 1623 /* 1624 * Load the address of the RX list. 1625 */ 1626 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1627 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1628 1629 /* 1630 * Enable interrupts. 1631 */ 1632 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1633 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1634 1635 /* Enable receiver and transmitter. */ 1636 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1637 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1638 1639 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1640 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1641 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1642 1643 mii_mediachg(mii); 1644 1645 ifp->if_flags |= IFF_RUNNING; 1646 ifp->if_flags &= ~IFF_OACTIVE; 1647 1648 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1649 WB_UNLOCK(sc); 1650 1651 return; 1652 } 1653 1654 /* 1655 * Set media options. 1656 */ 1657 static int 1658 wb_ifmedia_upd(ifp) 1659 struct ifnet *ifp; 1660 { 1661 struct wb_softc *sc; 1662 1663 sc = ifp->if_softc; 1664 1665 if (ifp->if_flags & IFF_UP) 1666 wb_init(sc); 1667 1668 return(0); 1669 } 1670 1671 /* 1672 * Report current media status. 1673 */ 1674 static void 1675 wb_ifmedia_sts(ifp, ifmr) 1676 struct ifnet *ifp; 1677 struct ifmediareq *ifmr; 1678 { 1679 struct wb_softc *sc; 1680 struct mii_data *mii; 1681 1682 sc = ifp->if_softc; 1683 1684 mii = device_get_softc(sc->wb_miibus); 1685 1686 mii_pollstat(mii); 1687 ifmr->ifm_active = mii->mii_media_active; 1688 ifmr->ifm_status = mii->mii_media_status; 1689 1690 return; 1691 } 1692 1693 static int 1694 wb_ioctl(ifp, command, data) 1695 struct ifnet *ifp; 1696 u_long command; 1697 caddr_t data; 1698 { 1699 struct wb_softc *sc = ifp->if_softc; 1700 struct mii_data *mii; 1701 struct ifreq *ifr = (struct ifreq *) data; 1702 int error = 0; 1703 1704 WB_LOCK(sc); 1705 1706 switch(command) { 1707 case SIOCSIFFLAGS: 1708 if (ifp->if_flags & IFF_UP) { 1709 wb_init(sc); 1710 } else { 1711 if (ifp->if_flags & IFF_RUNNING) 1712 wb_stop(sc); 1713 } 1714 error = 0; 1715 break; 1716 case SIOCADDMULTI: 1717 case SIOCDELMULTI: 1718 wb_setmulti(sc); 1719 error = 0; 1720 break; 1721 case SIOCGIFMEDIA: 1722 case SIOCSIFMEDIA: 1723 mii = device_get_softc(sc->wb_miibus); 1724 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1725 break; 1726 default: 1727 error = ether_ioctl(ifp, command, data); 1728 break; 1729 } 1730 1731 WB_UNLOCK(sc); 1732 1733 return(error); 1734 } 1735 1736 static void 1737 wb_watchdog(ifp) 1738 struct ifnet *ifp; 1739 { 1740 struct wb_softc *sc; 1741 1742 sc = ifp->if_softc; 1743 1744 WB_LOCK(sc); 1745 ifp->if_oerrors++; 1746 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1747 #ifdef foo 1748 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1749 printf("wb%d: no carrier - transceiver cable problem?\n", 1750 sc->wb_unit); 1751 #endif 1752 wb_stop(sc); 1753 wb_reset(sc); 1754 wb_init(sc); 1755 1756 if (ifp->if_snd.ifq_head != NULL) 1757 wb_start(ifp); 1758 WB_UNLOCK(sc); 1759 1760 return; 1761 } 1762 1763 /* 1764 * Stop the adapter and free any mbufs allocated to the 1765 * RX and TX lists. 1766 */ 1767 static void 1768 wb_stop(sc) 1769 struct wb_softc *sc; 1770 { 1771 register int i; 1772 struct ifnet *ifp; 1773 1774 WB_LOCK(sc); 1775 ifp = &sc->arpcom.ac_if; 1776 ifp->if_timer = 0; 1777 1778 untimeout(wb_tick, sc, sc->wb_stat_ch); 1779 1780 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1781 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1782 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1783 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1784 1785 /* 1786 * Free data in the RX lists. 1787 */ 1788 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1789 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1790 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1791 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1792 } 1793 } 1794 bzero((char *)&sc->wb_ldata->wb_rx_list, 1795 sizeof(sc->wb_ldata->wb_rx_list)); 1796 1797 /* 1798 * Free the TX list buffers. 1799 */ 1800 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1801 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1802 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1803 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1804 } 1805 } 1806 1807 bzero((char *)&sc->wb_ldata->wb_tx_list, 1808 sizeof(sc->wb_ldata->wb_tx_list)); 1809 1810 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1811 WB_UNLOCK(sc); 1812 1813 return; 1814 } 1815 1816 /* 1817 * Stop all chip I/O so that the kernel's probe routines don't 1818 * get confused by errant DMAs when rebooting. 1819 */ 1820 static void 1821 wb_shutdown(dev) 1822 device_t dev; 1823 { 1824 struct wb_softc *sc; 1825 1826 sc = device_get_softc(dev); 1827 wb_stop(sc); 1828 1829 return; 1830 }
Cache object: da87319eda82d29c30f1c5491cfdcda4
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