Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/pci/if_wb.c
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1 /*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Winbond fast ethernet PCI NIC driver 38 * 39 * Supports various cheap network adapters based on the Winbond W89C840F 40 * fast ethernet controller chip. This includes adapters manufactured by 41 * Winbond itself and some made by Linksys. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 /* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86 #include "opt_bdg.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/module.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/queue.h> 97 98 #include <net/if.h> 99 #include <net/if_arp.h> 100 #include <net/ethernet.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 104 #include <net/bpf.h> 105 106 #include <vm/vm.h> /* for vtophys */ 107 #include <vm/pmap.h> /* for vtophys */ 108 #include <machine/bus_memio.h> 109 #include <machine/bus_pio.h> 110 #include <machine/bus.h> 111 #include <machine/resource.h> 112 #include <sys/bus.h> 113 #include <sys/rman.h> 114 115 #include <dev/pci/pcireg.h> 116 #include <dev/pci/pcivar.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 121 /* "controller miibus0" required. See GENERIC if you get errors here. */ 122 #include "miibus_if.h" 123 124 #define WB_USEIOSPACE 125 126 #include <pci/if_wbreg.h> 127 128 MODULE_DEPEND(wb, pci, 1, 1, 1); 129 MODULE_DEPEND(wb, ether, 1, 1, 1); 130 MODULE_DEPEND(wb, miibus, 1, 1, 1); 131 132 /* 133 * Various supported device vendors/types and their names. 134 */ 135 static struct wb_type wb_devs[] = { 136 { WB_VENDORID, WB_DEVICEID_840F, 137 "Winbond W89C840F 10/100BaseTX" }, 138 { CP_VENDORID, CP_DEVICEID_RL100, 139 "Compex RL100-ATX 10/100baseTX" }, 140 { 0, 0, NULL } 141 }; 142 143 static int wb_probe(device_t); 144 static int wb_attach(device_t); 145 static int wb_detach(device_t); 146 147 static void wb_bfree(void *addr, void *args); 148 static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *, 149 struct mbuf *); 150 static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *); 151 152 static void wb_rxeof(struct wb_softc *); 153 static void wb_rxeoc(struct wb_softc *); 154 static void wb_txeof(struct wb_softc *); 155 static void wb_txeoc(struct wb_softc *); 156 static void wb_intr(void *); 157 static void wb_tick(void *); 158 static void wb_start(struct ifnet *); 159 static int wb_ioctl(struct ifnet *, u_long, caddr_t); 160 static void wb_init(void *); 161 static void wb_stop(struct wb_softc *); 162 static void wb_watchdog(struct ifnet *); 163 static void wb_shutdown(device_t); 164 static int wb_ifmedia_upd(struct ifnet *); 165 static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 166 167 static void wb_eeprom_putbyte(struct wb_softc *, int); 168 static void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *); 169 static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int); 170 static void wb_mii_sync(struct wb_softc *); 171 static void wb_mii_send(struct wb_softc *, u_int32_t, int); 172 static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *); 173 static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *); 174 175 static void wb_setcfg(struct wb_softc *, u_int32_t); 176 static void wb_setmulti(struct wb_softc *); 177 static void wb_reset(struct wb_softc *); 178 static void wb_fixmedia(struct wb_softc *); 179 static int wb_list_rx_init(struct wb_softc *); 180 static int wb_list_tx_init(struct wb_softc *); 181 182 static int wb_miibus_readreg(device_t, int, int); 183 static int wb_miibus_writereg(device_t, int, int, int); 184 static void wb_miibus_statchg(device_t); 185 186 #ifdef WB_USEIOSPACE 187 #define WB_RES SYS_RES_IOPORT 188 #define WB_RID WB_PCI_LOIO 189 #else 190 #define WB_RES SYS_RES_MEMORY 191 #define WB_RID WB_PCI_LOMEM 192 #endif 193 194 static device_method_t wb_methods[] = { 195 /* Device interface */ 196 DEVMETHOD(device_probe, wb_probe), 197 DEVMETHOD(device_attach, wb_attach), 198 DEVMETHOD(device_detach, wb_detach), 199 DEVMETHOD(device_shutdown, wb_shutdown), 200 201 /* bus interface, for miibus */ 202 DEVMETHOD(bus_print_child, bus_generic_print_child), 203 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 204 205 /* MII interface */ 206 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 207 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 208 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 209 { 0, 0 } 210 }; 211 212 static driver_t wb_driver = { 213 "wb", 214 wb_methods, 215 sizeof(struct wb_softc) 216 }; 217 218 static devclass_t wb_devclass; 219 220 DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 221 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 222 223 #define WB_SETBIT(sc, reg, x) \ 224 CSR_WRITE_4(sc, reg, \ 225 CSR_READ_4(sc, reg) | (x)) 226 227 #define WB_CLRBIT(sc, reg, x) \ 228 CSR_WRITE_4(sc, reg, \ 229 CSR_READ_4(sc, reg) & ~(x)) 230 231 #define SIO_SET(x) \ 232 CSR_WRITE_4(sc, WB_SIO, \ 233 CSR_READ_4(sc, WB_SIO) | (x)) 234 235 #define SIO_CLR(x) \ 236 CSR_WRITE_4(sc, WB_SIO, \ 237 CSR_READ_4(sc, WB_SIO) & ~(x)) 238 239 /* 240 * Send a read command and address to the EEPROM, check for ACK. 241 */ 242 static void 243 wb_eeprom_putbyte(sc, addr) 244 struct wb_softc *sc; 245 int addr; 246 { 247 register int d, i; 248 249 d = addr | WB_EECMD_READ; 250 251 /* 252 * Feed in each bit and stobe the clock. 253 */ 254 for (i = 0x400; i; i >>= 1) { 255 if (d & i) { 256 SIO_SET(WB_SIO_EE_DATAIN); 257 } else { 258 SIO_CLR(WB_SIO_EE_DATAIN); 259 } 260 DELAY(100); 261 SIO_SET(WB_SIO_EE_CLK); 262 DELAY(150); 263 SIO_CLR(WB_SIO_EE_CLK); 264 DELAY(100); 265 } 266 267 return; 268 } 269 270 /* 271 * Read a word of data stored in the EEPROM at address 'addr.' 272 */ 273 static void 274 wb_eeprom_getword(sc, addr, dest) 275 struct wb_softc *sc; 276 int addr; 277 u_int16_t *dest; 278 { 279 register int i; 280 u_int16_t word = 0; 281 282 /* Enter EEPROM access mode. */ 283 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 284 285 /* 286 * Send address of word we want to read. 287 */ 288 wb_eeprom_putbyte(sc, addr); 289 290 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 291 292 /* 293 * Start reading bits from EEPROM. 294 */ 295 for (i = 0x8000; i; i >>= 1) { 296 SIO_SET(WB_SIO_EE_CLK); 297 DELAY(100); 298 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 299 word |= i; 300 SIO_CLR(WB_SIO_EE_CLK); 301 DELAY(100); 302 } 303 304 /* Turn off EEPROM access mode. */ 305 CSR_WRITE_4(sc, WB_SIO, 0); 306 307 *dest = word; 308 309 return; 310 } 311 312 /* 313 * Read a sequence of words from the EEPROM. 314 */ 315 static void 316 wb_read_eeprom(sc, dest, off, cnt, swap) 317 struct wb_softc *sc; 318 caddr_t dest; 319 int off; 320 int cnt; 321 int swap; 322 { 323 int i; 324 u_int16_t word = 0, *ptr; 325 326 for (i = 0; i < cnt; i++) { 327 wb_eeprom_getword(sc, off + i, &word); 328 ptr = (u_int16_t *)(dest + (i * 2)); 329 if (swap) 330 *ptr = ntohs(word); 331 else 332 *ptr = word; 333 } 334 335 return; 336 } 337 338 /* 339 * Sync the PHYs by setting data bit and strobing the clock 32 times. 340 */ 341 static void 342 wb_mii_sync(sc) 343 struct wb_softc *sc; 344 { 345 register int i; 346 347 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 348 349 for (i = 0; i < 32; i++) { 350 SIO_SET(WB_SIO_MII_CLK); 351 DELAY(1); 352 SIO_CLR(WB_SIO_MII_CLK); 353 DELAY(1); 354 } 355 356 return; 357 } 358 359 /* 360 * Clock a series of bits through the MII. 361 */ 362 static void 363 wb_mii_send(sc, bits, cnt) 364 struct wb_softc *sc; 365 u_int32_t bits; 366 int cnt; 367 { 368 int i; 369 370 SIO_CLR(WB_SIO_MII_CLK); 371 372 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 373 if (bits & i) { 374 SIO_SET(WB_SIO_MII_DATAIN); 375 } else { 376 SIO_CLR(WB_SIO_MII_DATAIN); 377 } 378 DELAY(1); 379 SIO_CLR(WB_SIO_MII_CLK); 380 DELAY(1); 381 SIO_SET(WB_SIO_MII_CLK); 382 } 383 } 384 385 /* 386 * Read an PHY register through the MII. 387 */ 388 static int 389 wb_mii_readreg(sc, frame) 390 struct wb_softc *sc; 391 struct wb_mii_frame *frame; 392 393 { 394 int i, ack; 395 396 WB_LOCK(sc); 397 398 /* 399 * Set up frame for RX. 400 */ 401 frame->mii_stdelim = WB_MII_STARTDELIM; 402 frame->mii_opcode = WB_MII_READOP; 403 frame->mii_turnaround = 0; 404 frame->mii_data = 0; 405 406 CSR_WRITE_4(sc, WB_SIO, 0); 407 408 /* 409 * Turn on data xmit. 410 */ 411 SIO_SET(WB_SIO_MII_DIR); 412 413 wb_mii_sync(sc); 414 415 /* 416 * Send command/address info. 417 */ 418 wb_mii_send(sc, frame->mii_stdelim, 2); 419 wb_mii_send(sc, frame->mii_opcode, 2); 420 wb_mii_send(sc, frame->mii_phyaddr, 5); 421 wb_mii_send(sc, frame->mii_regaddr, 5); 422 423 /* Idle bit */ 424 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 425 DELAY(1); 426 SIO_SET(WB_SIO_MII_CLK); 427 DELAY(1); 428 429 /* Turn off xmit. */ 430 SIO_CLR(WB_SIO_MII_DIR); 431 /* Check for ack */ 432 SIO_CLR(WB_SIO_MII_CLK); 433 DELAY(1); 434 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 435 SIO_SET(WB_SIO_MII_CLK); 436 DELAY(1); 437 SIO_CLR(WB_SIO_MII_CLK); 438 DELAY(1); 439 SIO_SET(WB_SIO_MII_CLK); 440 DELAY(1); 441 442 /* 443 * Now try reading data bits. If the ack failed, we still 444 * need to clock through 16 cycles to keep the PHY(s) in sync. 445 */ 446 if (ack) { 447 for(i = 0; i < 16; i++) { 448 SIO_CLR(WB_SIO_MII_CLK); 449 DELAY(1); 450 SIO_SET(WB_SIO_MII_CLK); 451 DELAY(1); 452 } 453 goto fail; 454 } 455 456 for (i = 0x8000; i; i >>= 1) { 457 SIO_CLR(WB_SIO_MII_CLK); 458 DELAY(1); 459 if (!ack) { 460 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 461 frame->mii_data |= i; 462 DELAY(1); 463 } 464 SIO_SET(WB_SIO_MII_CLK); 465 DELAY(1); 466 } 467 468 fail: 469 470 SIO_CLR(WB_SIO_MII_CLK); 471 DELAY(1); 472 SIO_SET(WB_SIO_MII_CLK); 473 DELAY(1); 474 475 WB_UNLOCK(sc); 476 477 if (ack) 478 return(1); 479 return(0); 480 } 481 482 /* 483 * Write to a PHY register through the MII. 484 */ 485 static int 486 wb_mii_writereg(sc, frame) 487 struct wb_softc *sc; 488 struct wb_mii_frame *frame; 489 490 { 491 WB_LOCK(sc); 492 493 /* 494 * Set up frame for TX. 495 */ 496 497 frame->mii_stdelim = WB_MII_STARTDELIM; 498 frame->mii_opcode = WB_MII_WRITEOP; 499 frame->mii_turnaround = WB_MII_TURNAROUND; 500 501 /* 502 * Turn on data output. 503 */ 504 SIO_SET(WB_SIO_MII_DIR); 505 506 wb_mii_sync(sc); 507 508 wb_mii_send(sc, frame->mii_stdelim, 2); 509 wb_mii_send(sc, frame->mii_opcode, 2); 510 wb_mii_send(sc, frame->mii_phyaddr, 5); 511 wb_mii_send(sc, frame->mii_regaddr, 5); 512 wb_mii_send(sc, frame->mii_turnaround, 2); 513 wb_mii_send(sc, frame->mii_data, 16); 514 515 /* Idle bit. */ 516 SIO_SET(WB_SIO_MII_CLK); 517 DELAY(1); 518 SIO_CLR(WB_SIO_MII_CLK); 519 DELAY(1); 520 521 /* 522 * Turn off xmit. 523 */ 524 SIO_CLR(WB_SIO_MII_DIR); 525 526 WB_UNLOCK(sc); 527 528 return(0); 529 } 530 531 static int 532 wb_miibus_readreg(dev, phy, reg) 533 device_t dev; 534 int phy, reg; 535 { 536 struct wb_softc *sc; 537 struct wb_mii_frame frame; 538 539 sc = device_get_softc(dev); 540 541 bzero((char *)&frame, sizeof(frame)); 542 543 frame.mii_phyaddr = phy; 544 frame.mii_regaddr = reg; 545 wb_mii_readreg(sc, &frame); 546 547 return(frame.mii_data); 548 } 549 550 static int 551 wb_miibus_writereg(dev, phy, reg, data) 552 device_t dev; 553 int phy, reg, data; 554 { 555 struct wb_softc *sc; 556 struct wb_mii_frame frame; 557 558 sc = device_get_softc(dev); 559 560 bzero((char *)&frame, sizeof(frame)); 561 562 frame.mii_phyaddr = phy; 563 frame.mii_regaddr = reg; 564 frame.mii_data = data; 565 566 wb_mii_writereg(sc, &frame); 567 568 return(0); 569 } 570 571 static void 572 wb_miibus_statchg(dev) 573 device_t dev; 574 { 575 struct wb_softc *sc; 576 struct mii_data *mii; 577 578 sc = device_get_softc(dev); 579 WB_LOCK(sc); 580 mii = device_get_softc(sc->wb_miibus); 581 wb_setcfg(sc, mii->mii_media_active); 582 WB_UNLOCK(sc); 583 584 return; 585 } 586 587 /* 588 * Program the 64-bit multicast hash filter. 589 */ 590 static void 591 wb_setmulti(sc) 592 struct wb_softc *sc; 593 { 594 struct ifnet *ifp; 595 int h = 0; 596 u_int32_t hashes[2] = { 0, 0 }; 597 struct ifmultiaddr *ifma; 598 u_int32_t rxfilt; 599 int mcnt = 0; 600 601 ifp = &sc->arpcom.ac_if; 602 603 rxfilt = CSR_READ_4(sc, WB_NETCFG); 604 605 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 606 rxfilt |= WB_NETCFG_RX_MULTI; 607 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 608 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 609 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 610 return; 611 } 612 613 /* first, zot all the existing hash bits */ 614 CSR_WRITE_4(sc, WB_MAR0, 0); 615 CSR_WRITE_4(sc, WB_MAR1, 0); 616 617 /* now program new ones */ 618 IF_ADDR_LOCK(ifp); 619 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 620 if (ifma->ifma_addr->sa_family != AF_LINK) 621 continue; 622 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 623 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 624 if (h < 32) 625 hashes[0] |= (1 << h); 626 else 627 hashes[1] |= (1 << (h - 32)); 628 mcnt++; 629 } 630 IF_ADDR_UNLOCK(ifp); 631 632 if (mcnt) 633 rxfilt |= WB_NETCFG_RX_MULTI; 634 else 635 rxfilt &= ~WB_NETCFG_RX_MULTI; 636 637 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 638 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 639 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 640 641 return; 642 } 643 644 /* 645 * The Winbond manual states that in order to fiddle with the 646 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 647 * first have to put the transmit and/or receive logic in the idle state. 648 */ 649 static void 650 wb_setcfg(sc, media) 651 struct wb_softc *sc; 652 u_int32_t media; 653 { 654 int i, restart = 0; 655 656 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 657 restart = 1; 658 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 659 660 for (i = 0; i < WB_TIMEOUT; i++) { 661 DELAY(10); 662 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 663 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 664 break; 665 } 666 667 if (i == WB_TIMEOUT) 668 printf("wb%d: failed to force tx and " 669 "rx to idle state\n", sc->wb_unit); 670 } 671 672 if (IFM_SUBTYPE(media) == IFM_10_T) 673 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 674 else 675 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 676 677 if ((media & IFM_GMASK) == IFM_FDX) 678 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 679 else 680 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 681 682 if (restart) 683 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 684 685 return; 686 } 687 688 static void 689 wb_reset(sc) 690 struct wb_softc *sc; 691 { 692 register int i; 693 struct mii_data *mii; 694 695 CSR_WRITE_4(sc, WB_NETCFG, 0); 696 CSR_WRITE_4(sc, WB_BUSCTL, 0); 697 CSR_WRITE_4(sc, WB_TXADDR, 0); 698 CSR_WRITE_4(sc, WB_RXADDR, 0); 699 700 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 701 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 702 703 for (i = 0; i < WB_TIMEOUT; i++) { 704 DELAY(10); 705 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 706 break; 707 } 708 if (i == WB_TIMEOUT) 709 printf("wb%d: reset never completed!\n", sc->wb_unit); 710 711 /* Wait a little while for the chip to get its brains in order. */ 712 DELAY(1000); 713 714 if (sc->wb_miibus == NULL) 715 return; 716 717 mii = device_get_softc(sc->wb_miibus); 718 if (mii == NULL) 719 return; 720 721 if (mii->mii_instance) { 722 struct mii_softc *miisc; 723 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 724 mii_phy_reset(miisc); 725 } 726 727 return; 728 } 729 730 static void 731 wb_fixmedia(sc) 732 struct wb_softc *sc; 733 { 734 struct mii_data *mii = NULL; 735 struct ifnet *ifp; 736 u_int32_t media; 737 738 if (sc->wb_miibus == NULL) 739 return; 740 741 mii = device_get_softc(sc->wb_miibus); 742 ifp = &sc->arpcom.ac_if; 743 744 mii_pollstat(mii); 745 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 746 media = mii->mii_media_active & ~IFM_10_T; 747 media |= IFM_100_TX; 748 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 749 media = mii->mii_media_active & ~IFM_100_TX; 750 media |= IFM_10_T; 751 } else 752 return; 753 754 ifmedia_set(&mii->mii_media, media); 755 756 return; 757 } 758 759 /* 760 * Probe for a Winbond chip. Check the PCI vendor and device 761 * IDs against our list and return a device name if we find a match. 762 */ 763 static int 764 wb_probe(dev) 765 device_t dev; 766 { 767 struct wb_type *t; 768 769 t = wb_devs; 770 771 while(t->wb_name != NULL) { 772 if ((pci_get_vendor(dev) == t->wb_vid) && 773 (pci_get_device(dev) == t->wb_did)) { 774 device_set_desc(dev, t->wb_name); 775 return (BUS_PROBE_DEFAULT); 776 } 777 t++; 778 } 779 780 return(ENXIO); 781 } 782 783 /* 784 * Attach the interface. Allocate softc structures, do ifmedia 785 * setup and ethernet/BPF attach. 786 */ 787 static int 788 wb_attach(dev) 789 device_t dev; 790 { 791 u_char eaddr[ETHER_ADDR_LEN]; 792 struct wb_softc *sc; 793 struct ifnet *ifp; 794 int unit, error = 0, rid; 795 796 sc = device_get_softc(dev); 797 unit = device_get_unit(dev); 798 799 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 800 MTX_DEF | MTX_RECURSE); 801 /* 802 * Map control/status registers. 803 */ 804 pci_enable_busmaster(dev); 805 806 rid = WB_RID; 807 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 808 809 if (sc->wb_res == NULL) { 810 printf("wb%d: couldn't map ports/memory\n", unit); 811 error = ENXIO; 812 goto fail; 813 } 814 815 sc->wb_btag = rman_get_bustag(sc->wb_res); 816 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 817 818 /* Allocate interrupt */ 819 rid = 0; 820 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 821 RF_SHAREABLE | RF_ACTIVE); 822 823 if (sc->wb_irq == NULL) { 824 printf("wb%d: couldn't map interrupt\n", unit); 825 error = ENXIO; 826 goto fail; 827 } 828 829 /* Save the cache line size. */ 830 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 831 832 /* Reset the adapter. */ 833 wb_reset(sc); 834 835 /* 836 * Get station address from the EEPROM. 837 */ 838 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 839 840 sc->wb_unit = unit; 841 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 842 843 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 844 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 845 846 if (sc->wb_ldata == NULL) { 847 printf("wb%d: no memory for list buffers!\n", unit); 848 error = ENXIO; 849 goto fail; 850 } 851 852 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 853 854 ifp = &sc->arpcom.ac_if; 855 ifp->if_softc = sc; 856 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 857 ifp->if_mtu = ETHERMTU; 858 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 859 IFF_NEEDSGIANT; 860 ifp->if_ioctl = wb_ioctl; 861 ifp->if_start = wb_start; 862 ifp->if_watchdog = wb_watchdog; 863 ifp->if_init = wb_init; 864 ifp->if_baudrate = 10000000; 865 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 866 867 /* 868 * Do MII setup. 869 */ 870 if (mii_phy_probe(dev, &sc->wb_miibus, 871 wb_ifmedia_upd, wb_ifmedia_sts)) { 872 error = ENXIO; 873 goto fail; 874 } 875 876 /* 877 * Call MI attach routine. 878 */ 879 ether_ifattach(ifp, eaddr); 880 881 /* Hook interrupt last to avoid having to lock softc */ 882 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 883 wb_intr, sc, &sc->wb_intrhand); 884 885 if (error) { 886 printf("wb%d: couldn't set up irq\n", unit); 887 ether_ifdetach(ifp); 888 goto fail; 889 } 890 891 fail: 892 if (error) 893 wb_detach(dev); 894 895 return(error); 896 } 897 898 /* 899 * Shutdown hardware and free up resources. This can be called any 900 * time after the mutex has been initialized. It is called in both 901 * the error case in attach and the normal detach case so it needs 902 * to be careful about only freeing resources that have actually been 903 * allocated. 904 */ 905 static int 906 wb_detach(dev) 907 device_t dev; 908 { 909 struct wb_softc *sc; 910 struct ifnet *ifp; 911 912 sc = device_get_softc(dev); 913 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 914 WB_LOCK(sc); 915 ifp = &sc->arpcom.ac_if; 916 917 /* 918 * Delete any miibus and phy devices attached to this interface. 919 * This should only be done if attach succeeded. 920 */ 921 if (device_is_attached(dev)) { 922 wb_stop(sc); 923 ether_ifdetach(ifp); 924 } 925 if (sc->wb_miibus) 926 device_delete_child(dev, sc->wb_miibus); 927 bus_generic_detach(dev); 928 929 if (sc->wb_intrhand) 930 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 931 if (sc->wb_irq) 932 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 933 if (sc->wb_res) 934 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 935 936 if (sc->wb_ldata) { 937 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 938 M_DEVBUF); 939 } 940 941 WB_UNLOCK(sc); 942 mtx_destroy(&sc->wb_mtx); 943 944 return(0); 945 } 946 947 /* 948 * Initialize the transmit descriptors. 949 */ 950 static int 951 wb_list_tx_init(sc) 952 struct wb_softc *sc; 953 { 954 struct wb_chain_data *cd; 955 struct wb_list_data *ld; 956 int i; 957 958 cd = &sc->wb_cdata; 959 ld = sc->wb_ldata; 960 961 for (i = 0; i < WB_TX_LIST_CNT; i++) { 962 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 963 if (i == (WB_TX_LIST_CNT - 1)) { 964 cd->wb_tx_chain[i].wb_nextdesc = 965 &cd->wb_tx_chain[0]; 966 } else { 967 cd->wb_tx_chain[i].wb_nextdesc = 968 &cd->wb_tx_chain[i + 1]; 969 } 970 } 971 972 cd->wb_tx_free = &cd->wb_tx_chain[0]; 973 cd->wb_tx_tail = cd->wb_tx_head = NULL; 974 975 return(0); 976 } 977 978 979 /* 980 * Initialize the RX descriptors and allocate mbufs for them. Note that 981 * we arrange the descriptors in a closed ring, so that the last descriptor 982 * points back to the first. 983 */ 984 static int 985 wb_list_rx_init(sc) 986 struct wb_softc *sc; 987 { 988 struct wb_chain_data *cd; 989 struct wb_list_data *ld; 990 int i; 991 992 cd = &sc->wb_cdata; 993 ld = sc->wb_ldata; 994 995 for (i = 0; i < WB_RX_LIST_CNT; i++) { 996 cd->wb_rx_chain[i].wb_ptr = 997 (struct wb_desc *)&ld->wb_rx_list[i]; 998 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 999 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1000 return(ENOBUFS); 1001 if (i == (WB_RX_LIST_CNT - 1)) { 1002 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1003 ld->wb_rx_list[i].wb_next = 1004 vtophys(&ld->wb_rx_list[0]); 1005 } else { 1006 cd->wb_rx_chain[i].wb_nextdesc = 1007 &cd->wb_rx_chain[i + 1]; 1008 ld->wb_rx_list[i].wb_next = 1009 vtophys(&ld->wb_rx_list[i + 1]); 1010 } 1011 } 1012 1013 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1014 1015 return(0); 1016 } 1017 1018 static void 1019 wb_bfree(buf, args) 1020 void *buf; 1021 void *args; 1022 { 1023 return; 1024 } 1025 1026 /* 1027 * Initialize an RX descriptor and attach an MBUF cluster. 1028 */ 1029 static int 1030 wb_newbuf(sc, c, m) 1031 struct wb_softc *sc; 1032 struct wb_chain_onefrag *c; 1033 struct mbuf *m; 1034 { 1035 struct mbuf *m_new = NULL; 1036 1037 if (m == NULL) { 1038 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1039 if (m_new == NULL) 1040 return(ENOBUFS); 1041 m_new->m_data = c->wb_buf; 1042 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1043 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 1044 EXT_NET_DRV); 1045 } else { 1046 m_new = m; 1047 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1048 m_new->m_data = m_new->m_ext.ext_buf; 1049 } 1050 1051 m_adj(m_new, sizeof(u_int64_t)); 1052 1053 c->wb_mbuf = m_new; 1054 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1055 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1056 c->wb_ptr->wb_status = WB_RXSTAT; 1057 1058 return(0); 1059 } 1060 1061 /* 1062 * A frame has been uploaded: pass the resulting mbuf chain up to 1063 * the higher level protocols. 1064 */ 1065 static void 1066 wb_rxeof(sc) 1067 struct wb_softc *sc; 1068 { 1069 struct mbuf *m = NULL; 1070 struct ifnet *ifp; 1071 struct wb_chain_onefrag *cur_rx; 1072 int total_len = 0; 1073 u_int32_t rxstat; 1074 1075 WB_LOCK_ASSERT(sc); 1076 1077 ifp = &sc->arpcom.ac_if; 1078 1079 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1080 WB_RXSTAT_OWN)) { 1081 struct mbuf *m0 = NULL; 1082 1083 cur_rx = sc->wb_cdata.wb_rx_head; 1084 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1085 1086 m = cur_rx->wb_mbuf; 1087 1088 if ((rxstat & WB_RXSTAT_MIIERR) || 1089 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1090 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1091 !(rxstat & WB_RXSTAT_LASTFRAG) || 1092 !(rxstat & WB_RXSTAT_RXCMP)) { 1093 ifp->if_ierrors++; 1094 wb_newbuf(sc, cur_rx, m); 1095 printf("wb%x: receiver babbling: possible chip " 1096 "bug, forcing reset\n", sc->wb_unit); 1097 wb_fixmedia(sc); 1098 wb_reset(sc); 1099 wb_init(sc); 1100 return; 1101 } 1102 1103 if (rxstat & WB_RXSTAT_RXERR) { 1104 ifp->if_ierrors++; 1105 wb_newbuf(sc, cur_rx, m); 1106 break; 1107 } 1108 1109 /* No errors; receive the packet. */ 1110 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1111 1112 /* 1113 * XXX The Winbond chip includes the CRC with every 1114 * received frame, and there's no way to turn this 1115 * behavior off (at least, I can't find anything in 1116 * the manual that explains how to do it) so we have 1117 * to trim off the CRC manually. 1118 */ 1119 total_len -= ETHER_CRC_LEN; 1120 1121 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1122 NULL); 1123 wb_newbuf(sc, cur_rx, m); 1124 if (m0 == NULL) { 1125 ifp->if_ierrors++; 1126 break; 1127 } 1128 m = m0; 1129 1130 ifp->if_ipackets++; 1131 WB_UNLOCK(sc); 1132 (*ifp->if_input)(ifp, m); 1133 WB_LOCK(sc); 1134 } 1135 } 1136 1137 static void 1138 wb_rxeoc(sc) 1139 struct wb_softc *sc; 1140 { 1141 wb_rxeof(sc); 1142 1143 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1144 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1145 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1146 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1147 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1148 1149 return; 1150 } 1151 1152 /* 1153 * A frame was downloaded to the chip. It's safe for us to clean up 1154 * the list buffers. 1155 */ 1156 static void 1157 wb_txeof(sc) 1158 struct wb_softc *sc; 1159 { 1160 struct wb_chain *cur_tx; 1161 struct ifnet *ifp; 1162 1163 ifp = &sc->arpcom.ac_if; 1164 1165 /* Clear the timeout timer. */ 1166 ifp->if_timer = 0; 1167 1168 if (sc->wb_cdata.wb_tx_head == NULL) 1169 return; 1170 1171 /* 1172 * Go through our tx list and free mbufs for those 1173 * frames that have been transmitted. 1174 */ 1175 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1176 u_int32_t txstat; 1177 1178 cur_tx = sc->wb_cdata.wb_tx_head; 1179 txstat = WB_TXSTATUS(cur_tx); 1180 1181 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1182 break; 1183 1184 if (txstat & WB_TXSTAT_TXERR) { 1185 ifp->if_oerrors++; 1186 if (txstat & WB_TXSTAT_ABORT) 1187 ifp->if_collisions++; 1188 if (txstat & WB_TXSTAT_LATECOLL) 1189 ifp->if_collisions++; 1190 } 1191 1192 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1193 1194 ifp->if_opackets++; 1195 m_freem(cur_tx->wb_mbuf); 1196 cur_tx->wb_mbuf = NULL; 1197 1198 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1199 sc->wb_cdata.wb_tx_head = NULL; 1200 sc->wb_cdata.wb_tx_tail = NULL; 1201 break; 1202 } 1203 1204 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1205 } 1206 1207 return; 1208 } 1209 1210 /* 1211 * TX 'end of channel' interrupt handler. 1212 */ 1213 static void 1214 wb_txeoc(sc) 1215 struct wb_softc *sc; 1216 { 1217 struct ifnet *ifp; 1218 1219 ifp = &sc->arpcom.ac_if; 1220 1221 ifp->if_timer = 0; 1222 1223 if (sc->wb_cdata.wb_tx_head == NULL) { 1224 ifp->if_flags &= ~IFF_OACTIVE; 1225 sc->wb_cdata.wb_tx_tail = NULL; 1226 } else { 1227 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1228 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1229 ifp->if_timer = 5; 1230 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1231 } 1232 } 1233 1234 return; 1235 } 1236 1237 static void 1238 wb_intr(arg) 1239 void *arg; 1240 { 1241 struct wb_softc *sc; 1242 struct ifnet *ifp; 1243 u_int32_t status; 1244 1245 sc = arg; 1246 WB_LOCK(sc); 1247 ifp = &sc->arpcom.ac_if; 1248 1249 if (!(ifp->if_flags & IFF_UP)) { 1250 WB_UNLOCK(sc); 1251 return; 1252 } 1253 1254 /* Disable interrupts. */ 1255 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1256 1257 for (;;) { 1258 1259 status = CSR_READ_4(sc, WB_ISR); 1260 if (status) 1261 CSR_WRITE_4(sc, WB_ISR, status); 1262 1263 if ((status & WB_INTRS) == 0) 1264 break; 1265 1266 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1267 ifp->if_ierrors++; 1268 wb_reset(sc); 1269 if (status & WB_ISR_RX_ERR) 1270 wb_fixmedia(sc); 1271 wb_init(sc); 1272 continue; 1273 } 1274 1275 if (status & WB_ISR_RX_OK) 1276 wb_rxeof(sc); 1277 1278 if (status & WB_ISR_RX_IDLE) 1279 wb_rxeoc(sc); 1280 1281 if (status & WB_ISR_TX_OK) 1282 wb_txeof(sc); 1283 1284 if (status & WB_ISR_TX_NOBUF) 1285 wb_txeoc(sc); 1286 1287 if (status & WB_ISR_TX_IDLE) { 1288 wb_txeof(sc); 1289 if (sc->wb_cdata.wb_tx_head != NULL) { 1290 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1291 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1292 } 1293 } 1294 1295 if (status & WB_ISR_TX_UNDERRUN) { 1296 ifp->if_oerrors++; 1297 wb_txeof(sc); 1298 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1299 /* Jack up TX threshold */ 1300 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1301 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1302 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1303 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1304 } 1305 1306 if (status & WB_ISR_BUS_ERR) { 1307 wb_reset(sc); 1308 wb_init(sc); 1309 } 1310 1311 } 1312 1313 /* Re-enable interrupts. */ 1314 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1315 1316 if (ifp->if_snd.ifq_head != NULL) { 1317 wb_start(ifp); 1318 } 1319 1320 WB_UNLOCK(sc); 1321 1322 return; 1323 } 1324 1325 static void 1326 wb_tick(xsc) 1327 void *xsc; 1328 { 1329 struct wb_softc *sc; 1330 struct mii_data *mii; 1331 1332 sc = xsc; 1333 WB_LOCK(sc); 1334 mii = device_get_softc(sc->wb_miibus); 1335 1336 mii_tick(mii); 1337 1338 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1339 1340 WB_UNLOCK(sc); 1341 1342 return; 1343 } 1344 1345 /* 1346 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1347 * pointers to the fragment pointers. 1348 */ 1349 static int 1350 wb_encap(sc, c, m_head) 1351 struct wb_softc *sc; 1352 struct wb_chain *c; 1353 struct mbuf *m_head; 1354 { 1355 int frag = 0; 1356 struct wb_desc *f = NULL; 1357 int total_len; 1358 struct mbuf *m; 1359 1360 /* 1361 * Start packing the mbufs in this chain into 1362 * the fragment pointers. Stop when we run out 1363 * of fragments or hit the end of the mbuf chain. 1364 */ 1365 m = m_head; 1366 total_len = 0; 1367 1368 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1369 if (m->m_len != 0) { 1370 if (frag == WB_MAXFRAGS) 1371 break; 1372 total_len += m->m_len; 1373 f = &c->wb_ptr->wb_frag[frag]; 1374 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1375 if (frag == 0) { 1376 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1377 f->wb_status = 0; 1378 } else 1379 f->wb_status = WB_TXSTAT_OWN; 1380 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1381 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1382 frag++; 1383 } 1384 } 1385 1386 /* 1387 * Handle special case: we used up all 16 fragments, 1388 * but we have more mbufs left in the chain. Copy the 1389 * data into an mbuf cluster. Note that we don't 1390 * bother clearing the values in the other fragment 1391 * pointers/counters; it wouldn't gain us anything, 1392 * and would waste cycles. 1393 */ 1394 if (m != NULL) { 1395 struct mbuf *m_new = NULL; 1396 1397 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1398 if (m_new == NULL) 1399 return(1); 1400 if (m_head->m_pkthdr.len > MHLEN) { 1401 MCLGET(m_new, M_DONTWAIT); 1402 if (!(m_new->m_flags & M_EXT)) { 1403 m_freem(m_new); 1404 return(1); 1405 } 1406 } 1407 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1408 mtod(m_new, caddr_t)); 1409 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1410 m_freem(m_head); 1411 m_head = m_new; 1412 f = &c->wb_ptr->wb_frag[0]; 1413 f->wb_status = 0; 1414 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1415 f->wb_ctl = total_len = m_new->m_len; 1416 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1417 frag = 1; 1418 } 1419 1420 if (total_len < WB_MIN_FRAMELEN) { 1421 f = &c->wb_ptr->wb_frag[frag]; 1422 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1423 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1424 f->wb_ctl |= WB_TXCTL_TLINK; 1425 f->wb_status = WB_TXSTAT_OWN; 1426 frag++; 1427 } 1428 1429 c->wb_mbuf = m_head; 1430 c->wb_lastdesc = frag - 1; 1431 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1432 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1433 1434 return(0); 1435 } 1436 1437 /* 1438 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1439 * to the mbuf data regions directly in the transmit lists. We also save a 1440 * copy of the pointers since the transmit list fragment pointers are 1441 * physical addresses. 1442 */ 1443 1444 static void 1445 wb_start(ifp) 1446 struct ifnet *ifp; 1447 { 1448 struct wb_softc *sc; 1449 struct mbuf *m_head = NULL; 1450 struct wb_chain *cur_tx = NULL, *start_tx; 1451 1452 sc = ifp->if_softc; 1453 WB_LOCK(sc); 1454 1455 /* 1456 * Check for an available queue slot. If there are none, 1457 * punt. 1458 */ 1459 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1460 ifp->if_flags |= IFF_OACTIVE; 1461 WB_UNLOCK(sc); 1462 return; 1463 } 1464 1465 start_tx = sc->wb_cdata.wb_tx_free; 1466 1467 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1468 IF_DEQUEUE(&ifp->if_snd, m_head); 1469 if (m_head == NULL) 1470 break; 1471 1472 /* Pick a descriptor off the free list. */ 1473 cur_tx = sc->wb_cdata.wb_tx_free; 1474 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1475 1476 /* Pack the data into the descriptor. */ 1477 wb_encap(sc, cur_tx, m_head); 1478 1479 if (cur_tx != start_tx) 1480 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1481 1482 /* 1483 * If there's a BPF listener, bounce a copy of this frame 1484 * to him. 1485 */ 1486 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1487 } 1488 1489 /* 1490 * If there are no packets queued, bail. 1491 */ 1492 if (cur_tx == NULL) { 1493 WB_UNLOCK(sc); 1494 return; 1495 } 1496 1497 /* 1498 * Place the request for the upload interrupt 1499 * in the last descriptor in the chain. This way, if 1500 * we're chaining several packets at once, we'll only 1501 * get an interupt once for the whole chain rather than 1502 * once for each packet. 1503 */ 1504 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1505 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1506 sc->wb_cdata.wb_tx_tail = cur_tx; 1507 1508 if (sc->wb_cdata.wb_tx_head == NULL) { 1509 sc->wb_cdata.wb_tx_head = start_tx; 1510 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1511 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1512 } else { 1513 /* 1514 * We need to distinguish between the case where 1515 * the own bit is clear because the chip cleared it 1516 * and where the own bit is clear because we haven't 1517 * set it yet. The magic value WB_UNSET is just some 1518 * ramdomly chosen number which doesn't have the own 1519 * bit set. When we actually transmit the frame, the 1520 * status word will have _only_ the own bit set, so 1521 * the txeoc handler will be able to tell if it needs 1522 * to initiate another transmission to flush out pending 1523 * frames. 1524 */ 1525 WB_TXOWN(start_tx) = WB_UNSENT; 1526 } 1527 1528 /* 1529 * Set a timeout in case the chip goes out to lunch. 1530 */ 1531 ifp->if_timer = 5; 1532 WB_UNLOCK(sc); 1533 1534 return; 1535 } 1536 1537 static void 1538 wb_init(xsc) 1539 void *xsc; 1540 { 1541 struct wb_softc *sc = xsc; 1542 struct ifnet *ifp = &sc->arpcom.ac_if; 1543 int i; 1544 struct mii_data *mii; 1545 1546 WB_LOCK(sc); 1547 mii = device_get_softc(sc->wb_miibus); 1548 1549 /* 1550 * Cancel pending I/O and free all RX/TX buffers. 1551 */ 1552 wb_stop(sc); 1553 wb_reset(sc); 1554 1555 sc->wb_txthresh = WB_TXTHRESH_INIT; 1556 1557 /* 1558 * Set cache alignment and burst length. 1559 */ 1560 #ifdef foo 1561 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1562 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1563 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1564 #endif 1565 1566 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1567 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1568 switch(sc->wb_cachesize) { 1569 case 32: 1570 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1571 break; 1572 case 16: 1573 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1574 break; 1575 case 8: 1576 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1577 break; 1578 case 0: 1579 default: 1580 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1581 break; 1582 } 1583 1584 /* This doesn't tend to work too well at 100Mbps. */ 1585 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1586 1587 /* Init our MAC address */ 1588 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1589 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1590 } 1591 1592 /* Init circular RX list. */ 1593 if (wb_list_rx_init(sc) == ENOBUFS) { 1594 printf("wb%d: initialization failed: no " 1595 "memory for rx buffers\n", sc->wb_unit); 1596 wb_stop(sc); 1597 WB_UNLOCK(sc); 1598 return; 1599 } 1600 1601 /* Init TX descriptors. */ 1602 wb_list_tx_init(sc); 1603 1604 /* If we want promiscuous mode, set the allframes bit. */ 1605 if (ifp->if_flags & IFF_PROMISC) { 1606 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1607 } else { 1608 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1609 } 1610 1611 /* 1612 * Set capture broadcast bit to capture broadcast frames. 1613 */ 1614 if (ifp->if_flags & IFF_BROADCAST) { 1615 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1616 } else { 1617 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1618 } 1619 1620 /* 1621 * Program the multicast filter, if necessary. 1622 */ 1623 wb_setmulti(sc); 1624 1625 /* 1626 * Load the address of the RX list. 1627 */ 1628 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1629 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1630 1631 /* 1632 * Enable interrupts. 1633 */ 1634 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1635 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1636 1637 /* Enable receiver and transmitter. */ 1638 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1639 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1640 1641 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1642 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1643 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1644 1645 mii_mediachg(mii); 1646 1647 ifp->if_flags |= IFF_RUNNING; 1648 ifp->if_flags &= ~IFF_OACTIVE; 1649 1650 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1651 WB_UNLOCK(sc); 1652 1653 return; 1654 } 1655 1656 /* 1657 * Set media options. 1658 */ 1659 static int 1660 wb_ifmedia_upd(ifp) 1661 struct ifnet *ifp; 1662 { 1663 struct wb_softc *sc; 1664 1665 sc = ifp->if_softc; 1666 1667 if (ifp->if_flags & IFF_UP) 1668 wb_init(sc); 1669 1670 return(0); 1671 } 1672 1673 /* 1674 * Report current media status. 1675 */ 1676 static void 1677 wb_ifmedia_sts(ifp, ifmr) 1678 struct ifnet *ifp; 1679 struct ifmediareq *ifmr; 1680 { 1681 struct wb_softc *sc; 1682 struct mii_data *mii; 1683 1684 sc = ifp->if_softc; 1685 1686 mii = device_get_softc(sc->wb_miibus); 1687 1688 mii_pollstat(mii); 1689 ifmr->ifm_active = mii->mii_media_active; 1690 ifmr->ifm_status = mii->mii_media_status; 1691 1692 return; 1693 } 1694 1695 static int 1696 wb_ioctl(ifp, command, data) 1697 struct ifnet *ifp; 1698 u_long command; 1699 caddr_t data; 1700 { 1701 struct wb_softc *sc = ifp->if_softc; 1702 struct mii_data *mii; 1703 struct ifreq *ifr = (struct ifreq *) data; 1704 int error = 0; 1705 1706 WB_LOCK(sc); 1707 1708 switch(command) { 1709 case SIOCSIFFLAGS: 1710 if (ifp->if_flags & IFF_UP) { 1711 wb_init(sc); 1712 } else { 1713 if (ifp->if_flags & IFF_RUNNING) 1714 wb_stop(sc); 1715 } 1716 error = 0; 1717 break; 1718 case SIOCADDMULTI: 1719 case SIOCDELMULTI: 1720 wb_setmulti(sc); 1721 error = 0; 1722 break; 1723 case SIOCGIFMEDIA: 1724 case SIOCSIFMEDIA: 1725 mii = device_get_softc(sc->wb_miibus); 1726 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1727 break; 1728 default: 1729 error = ether_ioctl(ifp, command, data); 1730 break; 1731 } 1732 1733 WB_UNLOCK(sc); 1734 1735 return(error); 1736 } 1737 1738 static void 1739 wb_watchdog(ifp) 1740 struct ifnet *ifp; 1741 { 1742 struct wb_softc *sc; 1743 1744 sc = ifp->if_softc; 1745 1746 WB_LOCK(sc); 1747 ifp->if_oerrors++; 1748 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1749 #ifdef foo 1750 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1751 printf("wb%d: no carrier - transceiver cable problem?\n", 1752 sc->wb_unit); 1753 #endif 1754 wb_stop(sc); 1755 wb_reset(sc); 1756 wb_init(sc); 1757 1758 if (ifp->if_snd.ifq_head != NULL) 1759 wb_start(ifp); 1760 WB_UNLOCK(sc); 1761 1762 return; 1763 } 1764 1765 /* 1766 * Stop the adapter and free any mbufs allocated to the 1767 * RX and TX lists. 1768 */ 1769 static void 1770 wb_stop(sc) 1771 struct wb_softc *sc; 1772 { 1773 register int i; 1774 struct ifnet *ifp; 1775 1776 WB_LOCK(sc); 1777 ifp = &sc->arpcom.ac_if; 1778 ifp->if_timer = 0; 1779 1780 untimeout(wb_tick, sc, sc->wb_stat_ch); 1781 1782 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1783 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1784 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1785 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1786 1787 /* 1788 * Free data in the RX lists. 1789 */ 1790 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1791 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1792 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1793 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1794 } 1795 } 1796 bzero((char *)&sc->wb_ldata->wb_rx_list, 1797 sizeof(sc->wb_ldata->wb_rx_list)); 1798 1799 /* 1800 * Free the TX list buffers. 1801 */ 1802 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1803 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1804 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1805 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1806 } 1807 } 1808 1809 bzero((char *)&sc->wb_ldata->wb_tx_list, 1810 sizeof(sc->wb_ldata->wb_tx_list)); 1811 1812 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1813 WB_UNLOCK(sc); 1814 1815 return; 1816 } 1817 1818 /* 1819 * Stop all chip I/O so that the kernel's probe routines don't 1820 * get confused by errant DMAs when rebooting. 1821 */ 1822 static void 1823 wb_shutdown(dev) 1824 device_t dev; 1825 { 1826 struct wb_softc *sc; 1827 1828 sc = device_get_softc(dev); 1829 wb_stop(sc); 1830 1831 return; 1832 }
Cache object: 4c497ca51fb1d51da569f834294506e8
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