FreeBSD/Linux Kernel Cross Reference
sys/pci/if_wb.c
1 /*-
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: releng/6.0/sys/pci/if_wb.c 151140 2005-10-09 04:11:20Z delphij $");
35
36 /*
37 * Winbond fast ethernet PCI NIC driver
38 *
39 * Supports various cheap network adapters based on the Winbond W89C840F
40 * fast ethernet controller chip. This includes adapters manufactured by
41 * Winbond itself and some made by Linksys.
42 *
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
46 */
47 /*
48 * The Winbond W89C840F chip is a bus master; in some ways it resembles
49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
50 * one major difference which is that while the registers do many of
51 * the same things as a tulip adapter, the offsets are different: where
52 * tulip registers are typically spaced 8 bytes apart, the Winbond
53 * registers are spaced 4 bytes apart. The receiver filter is also
54 * programmed differently.
55 *
56 * Like the tulip, the Winbond chip uses small descriptors containing
57 * a status word, a control word and 32-bit areas that can either be used
58 * to point to two external data blocks, or to point to a single block
59 * and another descriptor in a linked list. Descriptors can be grouped
60 * together in blocks to form fixed length rings or can be chained
61 * together in linked lists. A single packet may be spread out over
62 * several descriptors if necessary.
63 *
64 * For the receive ring, this driver uses a linked list of descriptors,
65 * each pointing to a single mbuf cluster buffer, which us large enough
66 * to hold an entire packet. The link list is looped back to created a
67 * closed ring.
68 *
69 * For transmission, the driver creates a linked list of 'super descriptors'
70 * which each contain several individual descriptors linked toghether.
71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
72 * abuse as fragment pointers. This allows us to use a buffer managment
73 * scheme very similar to that used in the ThunderLAN and Etherlink XL
74 * drivers.
75 *
76 * Autonegotiation is performed using the external PHY via the MII bus.
77 * The sample boards I have all use a Davicom PHY.
78 *
79 * Note: the author of the Linux driver for the Winbond chip alludes
80 * to some sort of flaw in the chip's design that seems to mandate some
81 * drastic workaround which signigicantly impairs transmit performance.
82 * I have no idea what he's on about: transmit performance with all
83 * three of my test boards seems fine.
84 */
85
86 #include "opt_bdg.h"
87
88 #include <sys/param.h>
89 #include <sys/systm.h>
90 #include <sys/sockio.h>
91 #include <sys/mbuf.h>
92 #include <sys/malloc.h>
93 #include <sys/module.h>
94 #include <sys/kernel.h>
95 #include <sys/socket.h>
96 #include <sys/queue.h>
97
98 #include <net/if.h>
99 #include <net/if_arp.h>
100 #include <net/ethernet.h>
101 #include <net/if_dl.h>
102 #include <net/if_media.h>
103 #include <net/if_types.h>
104
105 #include <net/bpf.h>
106
107 #include <vm/vm.h> /* for vtophys */
108 #include <vm/pmap.h> /* for vtophys */
109 #include <machine/bus.h>
110 #include <machine/resource.h>
111 #include <sys/bus.h>
112 #include <sys/rman.h>
113
114 #include <dev/pci/pcireg.h>
115 #include <dev/pci/pcivar.h>
116
117 #include <dev/mii/mii.h>
118 #include <dev/mii/miivar.h>
119
120 /* "controller miibus0" required. See GENERIC if you get errors here. */
121 #include "miibus_if.h"
122
123 #define WB_USEIOSPACE
124
125 #include <pci/if_wbreg.h>
126
127 MODULE_DEPEND(wb, pci, 1, 1, 1);
128 MODULE_DEPEND(wb, ether, 1, 1, 1);
129 MODULE_DEPEND(wb, miibus, 1, 1, 1);
130
131 /*
132 * Various supported device vendors/types and their names.
133 */
134 static struct wb_type wb_devs[] = {
135 { WB_VENDORID, WB_DEVICEID_840F,
136 "Winbond W89C840F 10/100BaseTX" },
137 { CP_VENDORID, CP_DEVICEID_RL100,
138 "Compex RL100-ATX 10/100baseTX" },
139 { 0, 0, NULL }
140 };
141
142 static int wb_probe(device_t);
143 static int wb_attach(device_t);
144 static int wb_detach(device_t);
145
146 static void wb_bfree(void *addr, void *args);
147 static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *,
148 struct mbuf *);
149 static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *);
150
151 static void wb_rxeof(struct wb_softc *);
152 static void wb_rxeoc(struct wb_softc *);
153 static void wb_txeof(struct wb_softc *);
154 static void wb_txeoc(struct wb_softc *);
155 static void wb_intr(void *);
156 static void wb_tick(void *);
157 static void wb_start(struct ifnet *);
158 static int wb_ioctl(struct ifnet *, u_long, caddr_t);
159 static void wb_init(void *);
160 static void wb_stop(struct wb_softc *);
161 static void wb_watchdog(struct ifnet *);
162 static void wb_shutdown(device_t);
163 static int wb_ifmedia_upd(struct ifnet *);
164 static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *);
165
166 static void wb_eeprom_putbyte(struct wb_softc *, int);
167 static void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *);
168 static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int);
169 static void wb_mii_sync(struct wb_softc *);
170 static void wb_mii_send(struct wb_softc *, u_int32_t, int);
171 static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *);
172 static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *);
173
174 static void wb_setcfg(struct wb_softc *, u_int32_t);
175 static void wb_setmulti(struct wb_softc *);
176 static void wb_reset(struct wb_softc *);
177 static void wb_fixmedia(struct wb_softc *);
178 static int wb_list_rx_init(struct wb_softc *);
179 static int wb_list_tx_init(struct wb_softc *);
180
181 static int wb_miibus_readreg(device_t, int, int);
182 static int wb_miibus_writereg(device_t, int, int, int);
183 static void wb_miibus_statchg(device_t);
184
185 #ifdef WB_USEIOSPACE
186 #define WB_RES SYS_RES_IOPORT
187 #define WB_RID WB_PCI_LOIO
188 #else
189 #define WB_RES SYS_RES_MEMORY
190 #define WB_RID WB_PCI_LOMEM
191 #endif
192
193 static device_method_t wb_methods[] = {
194 /* Device interface */
195 DEVMETHOD(device_probe, wb_probe),
196 DEVMETHOD(device_attach, wb_attach),
197 DEVMETHOD(device_detach, wb_detach),
198 DEVMETHOD(device_shutdown, wb_shutdown),
199
200 /* bus interface, for miibus */
201 DEVMETHOD(bus_print_child, bus_generic_print_child),
202 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
203
204 /* MII interface */
205 DEVMETHOD(miibus_readreg, wb_miibus_readreg),
206 DEVMETHOD(miibus_writereg, wb_miibus_writereg),
207 DEVMETHOD(miibus_statchg, wb_miibus_statchg),
208 { 0, 0 }
209 };
210
211 static driver_t wb_driver = {
212 "wb",
213 wb_methods,
214 sizeof(struct wb_softc)
215 };
216
217 static devclass_t wb_devclass;
218
219 DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0);
220 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
221
222 #define WB_SETBIT(sc, reg, x) \
223 CSR_WRITE_4(sc, reg, \
224 CSR_READ_4(sc, reg) | (x))
225
226 #define WB_CLRBIT(sc, reg, x) \
227 CSR_WRITE_4(sc, reg, \
228 CSR_READ_4(sc, reg) & ~(x))
229
230 #define SIO_SET(x) \
231 CSR_WRITE_4(sc, WB_SIO, \
232 CSR_READ_4(sc, WB_SIO) | (x))
233
234 #define SIO_CLR(x) \
235 CSR_WRITE_4(sc, WB_SIO, \
236 CSR_READ_4(sc, WB_SIO) & ~(x))
237
238 /*
239 * Send a read command and address to the EEPROM, check for ACK.
240 */
241 static void
242 wb_eeprom_putbyte(sc, addr)
243 struct wb_softc *sc;
244 int addr;
245 {
246 register int d, i;
247
248 d = addr | WB_EECMD_READ;
249
250 /*
251 * Feed in each bit and stobe the clock.
252 */
253 for (i = 0x400; i; i >>= 1) {
254 if (d & i) {
255 SIO_SET(WB_SIO_EE_DATAIN);
256 } else {
257 SIO_CLR(WB_SIO_EE_DATAIN);
258 }
259 DELAY(100);
260 SIO_SET(WB_SIO_EE_CLK);
261 DELAY(150);
262 SIO_CLR(WB_SIO_EE_CLK);
263 DELAY(100);
264 }
265
266 return;
267 }
268
269 /*
270 * Read a word of data stored in the EEPROM at address 'addr.'
271 */
272 static void
273 wb_eeprom_getword(sc, addr, dest)
274 struct wb_softc *sc;
275 int addr;
276 u_int16_t *dest;
277 {
278 register int i;
279 u_int16_t word = 0;
280
281 /* Enter EEPROM access mode. */
282 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
283
284 /*
285 * Send address of word we want to read.
286 */
287 wb_eeprom_putbyte(sc, addr);
288
289 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
290
291 /*
292 * Start reading bits from EEPROM.
293 */
294 for (i = 0x8000; i; i >>= 1) {
295 SIO_SET(WB_SIO_EE_CLK);
296 DELAY(100);
297 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
298 word |= i;
299 SIO_CLR(WB_SIO_EE_CLK);
300 DELAY(100);
301 }
302
303 /* Turn off EEPROM access mode. */
304 CSR_WRITE_4(sc, WB_SIO, 0);
305
306 *dest = word;
307
308 return;
309 }
310
311 /*
312 * Read a sequence of words from the EEPROM.
313 */
314 static void
315 wb_read_eeprom(sc, dest, off, cnt, swap)
316 struct wb_softc *sc;
317 caddr_t dest;
318 int off;
319 int cnt;
320 int swap;
321 {
322 int i;
323 u_int16_t word = 0, *ptr;
324
325 for (i = 0; i < cnt; i++) {
326 wb_eeprom_getword(sc, off + i, &word);
327 ptr = (u_int16_t *)(dest + (i * 2));
328 if (swap)
329 *ptr = ntohs(word);
330 else
331 *ptr = word;
332 }
333
334 return;
335 }
336
337 /*
338 * Sync the PHYs by setting data bit and strobing the clock 32 times.
339 */
340 static void
341 wb_mii_sync(sc)
342 struct wb_softc *sc;
343 {
344 register int i;
345
346 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN);
347
348 for (i = 0; i < 32; i++) {
349 SIO_SET(WB_SIO_MII_CLK);
350 DELAY(1);
351 SIO_CLR(WB_SIO_MII_CLK);
352 DELAY(1);
353 }
354
355 return;
356 }
357
358 /*
359 * Clock a series of bits through the MII.
360 */
361 static void
362 wb_mii_send(sc, bits, cnt)
363 struct wb_softc *sc;
364 u_int32_t bits;
365 int cnt;
366 {
367 int i;
368
369 SIO_CLR(WB_SIO_MII_CLK);
370
371 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
372 if (bits & i) {
373 SIO_SET(WB_SIO_MII_DATAIN);
374 } else {
375 SIO_CLR(WB_SIO_MII_DATAIN);
376 }
377 DELAY(1);
378 SIO_CLR(WB_SIO_MII_CLK);
379 DELAY(1);
380 SIO_SET(WB_SIO_MII_CLK);
381 }
382 }
383
384 /*
385 * Read an PHY register through the MII.
386 */
387 static int
388 wb_mii_readreg(sc, frame)
389 struct wb_softc *sc;
390 struct wb_mii_frame *frame;
391
392 {
393 int i, ack;
394
395 WB_LOCK(sc);
396
397 /*
398 * Set up frame for RX.
399 */
400 frame->mii_stdelim = WB_MII_STARTDELIM;
401 frame->mii_opcode = WB_MII_READOP;
402 frame->mii_turnaround = 0;
403 frame->mii_data = 0;
404
405 CSR_WRITE_4(sc, WB_SIO, 0);
406
407 /*
408 * Turn on data xmit.
409 */
410 SIO_SET(WB_SIO_MII_DIR);
411
412 wb_mii_sync(sc);
413
414 /*
415 * Send command/address info.
416 */
417 wb_mii_send(sc, frame->mii_stdelim, 2);
418 wb_mii_send(sc, frame->mii_opcode, 2);
419 wb_mii_send(sc, frame->mii_phyaddr, 5);
420 wb_mii_send(sc, frame->mii_regaddr, 5);
421
422 /* Idle bit */
423 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN));
424 DELAY(1);
425 SIO_SET(WB_SIO_MII_CLK);
426 DELAY(1);
427
428 /* Turn off xmit. */
429 SIO_CLR(WB_SIO_MII_DIR);
430 /* Check for ack */
431 SIO_CLR(WB_SIO_MII_CLK);
432 DELAY(1);
433 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
434 SIO_SET(WB_SIO_MII_CLK);
435 DELAY(1);
436 SIO_CLR(WB_SIO_MII_CLK);
437 DELAY(1);
438 SIO_SET(WB_SIO_MII_CLK);
439 DELAY(1);
440
441 /*
442 * Now try reading data bits. If the ack failed, we still
443 * need to clock through 16 cycles to keep the PHY(s) in sync.
444 */
445 if (ack) {
446 for(i = 0; i < 16; i++) {
447 SIO_CLR(WB_SIO_MII_CLK);
448 DELAY(1);
449 SIO_SET(WB_SIO_MII_CLK);
450 DELAY(1);
451 }
452 goto fail;
453 }
454
455 for (i = 0x8000; i; i >>= 1) {
456 SIO_CLR(WB_SIO_MII_CLK);
457 DELAY(1);
458 if (!ack) {
459 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
460 frame->mii_data |= i;
461 DELAY(1);
462 }
463 SIO_SET(WB_SIO_MII_CLK);
464 DELAY(1);
465 }
466
467 fail:
468
469 SIO_CLR(WB_SIO_MII_CLK);
470 DELAY(1);
471 SIO_SET(WB_SIO_MII_CLK);
472 DELAY(1);
473
474 WB_UNLOCK(sc);
475
476 if (ack)
477 return(1);
478 return(0);
479 }
480
481 /*
482 * Write to a PHY register through the MII.
483 */
484 static int
485 wb_mii_writereg(sc, frame)
486 struct wb_softc *sc;
487 struct wb_mii_frame *frame;
488
489 {
490 WB_LOCK(sc);
491
492 /*
493 * Set up frame for TX.
494 */
495
496 frame->mii_stdelim = WB_MII_STARTDELIM;
497 frame->mii_opcode = WB_MII_WRITEOP;
498 frame->mii_turnaround = WB_MII_TURNAROUND;
499
500 /*
501 * Turn on data output.
502 */
503 SIO_SET(WB_SIO_MII_DIR);
504
505 wb_mii_sync(sc);
506
507 wb_mii_send(sc, frame->mii_stdelim, 2);
508 wb_mii_send(sc, frame->mii_opcode, 2);
509 wb_mii_send(sc, frame->mii_phyaddr, 5);
510 wb_mii_send(sc, frame->mii_regaddr, 5);
511 wb_mii_send(sc, frame->mii_turnaround, 2);
512 wb_mii_send(sc, frame->mii_data, 16);
513
514 /* Idle bit. */
515 SIO_SET(WB_SIO_MII_CLK);
516 DELAY(1);
517 SIO_CLR(WB_SIO_MII_CLK);
518 DELAY(1);
519
520 /*
521 * Turn off xmit.
522 */
523 SIO_CLR(WB_SIO_MII_DIR);
524
525 WB_UNLOCK(sc);
526
527 return(0);
528 }
529
530 static int
531 wb_miibus_readreg(dev, phy, reg)
532 device_t dev;
533 int phy, reg;
534 {
535 struct wb_softc *sc;
536 struct wb_mii_frame frame;
537
538 sc = device_get_softc(dev);
539
540 bzero((char *)&frame, sizeof(frame));
541
542 frame.mii_phyaddr = phy;
543 frame.mii_regaddr = reg;
544 wb_mii_readreg(sc, &frame);
545
546 return(frame.mii_data);
547 }
548
549 static int
550 wb_miibus_writereg(dev, phy, reg, data)
551 device_t dev;
552 int phy, reg, data;
553 {
554 struct wb_softc *sc;
555 struct wb_mii_frame frame;
556
557 sc = device_get_softc(dev);
558
559 bzero((char *)&frame, sizeof(frame));
560
561 frame.mii_phyaddr = phy;
562 frame.mii_regaddr = reg;
563 frame.mii_data = data;
564
565 wb_mii_writereg(sc, &frame);
566
567 return(0);
568 }
569
570 static void
571 wb_miibus_statchg(dev)
572 device_t dev;
573 {
574 struct wb_softc *sc;
575 struct mii_data *mii;
576
577 sc = device_get_softc(dev);
578 WB_LOCK(sc);
579 mii = device_get_softc(sc->wb_miibus);
580 wb_setcfg(sc, mii->mii_media_active);
581 WB_UNLOCK(sc);
582
583 return;
584 }
585
586 /*
587 * Program the 64-bit multicast hash filter.
588 */
589 static void
590 wb_setmulti(sc)
591 struct wb_softc *sc;
592 {
593 struct ifnet *ifp;
594 int h = 0;
595 u_int32_t hashes[2] = { 0, 0 };
596 struct ifmultiaddr *ifma;
597 u_int32_t rxfilt;
598 int mcnt = 0;
599
600 ifp = sc->wb_ifp;
601
602 rxfilt = CSR_READ_4(sc, WB_NETCFG);
603
604 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
605 rxfilt |= WB_NETCFG_RX_MULTI;
606 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
607 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
608 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
609 return;
610 }
611
612 /* first, zot all the existing hash bits */
613 CSR_WRITE_4(sc, WB_MAR0, 0);
614 CSR_WRITE_4(sc, WB_MAR1, 0);
615
616 /* now program new ones */
617 IF_ADDR_LOCK(ifp);
618 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
619 if (ifma->ifma_addr->sa_family != AF_LINK)
620 continue;
621 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
622 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
623 if (h < 32)
624 hashes[0] |= (1 << h);
625 else
626 hashes[1] |= (1 << (h - 32));
627 mcnt++;
628 }
629 IF_ADDR_UNLOCK(ifp);
630
631 if (mcnt)
632 rxfilt |= WB_NETCFG_RX_MULTI;
633 else
634 rxfilt &= ~WB_NETCFG_RX_MULTI;
635
636 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
637 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
638 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
639
640 return;
641 }
642
643 /*
644 * The Winbond manual states that in order to fiddle with the
645 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
646 * first have to put the transmit and/or receive logic in the idle state.
647 */
648 static void
649 wb_setcfg(sc, media)
650 struct wb_softc *sc;
651 u_int32_t media;
652 {
653 int i, restart = 0;
654
655 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
656 restart = 1;
657 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
658
659 for (i = 0; i < WB_TIMEOUT; i++) {
660 DELAY(10);
661 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
662 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
663 break;
664 }
665
666 if (i == WB_TIMEOUT)
667 if_printf(sc->wb_ifp,
668 "failed to force tx and rx to idle state\n");
669 }
670
671 if (IFM_SUBTYPE(media) == IFM_10_T)
672 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
673 else
674 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
675
676 if ((media & IFM_GMASK) == IFM_FDX)
677 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
678 else
679 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
680
681 if (restart)
682 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
683
684 return;
685 }
686
687 static void
688 wb_reset(sc)
689 struct wb_softc *sc;
690 {
691 register int i;
692 struct mii_data *mii;
693
694 CSR_WRITE_4(sc, WB_NETCFG, 0);
695 CSR_WRITE_4(sc, WB_BUSCTL, 0);
696 CSR_WRITE_4(sc, WB_TXADDR, 0);
697 CSR_WRITE_4(sc, WB_RXADDR, 0);
698
699 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
700 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
701
702 for (i = 0; i < WB_TIMEOUT; i++) {
703 DELAY(10);
704 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
705 break;
706 }
707 if (i == WB_TIMEOUT)
708 if_printf(sc->wb_ifp, "reset never completed!\n");
709
710 /* Wait a little while for the chip to get its brains in order. */
711 DELAY(1000);
712
713 if (sc->wb_miibus == NULL)
714 return;
715
716 mii = device_get_softc(sc->wb_miibus);
717 if (mii == NULL)
718 return;
719
720 if (mii->mii_instance) {
721 struct mii_softc *miisc;
722 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
723 mii_phy_reset(miisc);
724 }
725
726 return;
727 }
728
729 static void
730 wb_fixmedia(sc)
731 struct wb_softc *sc;
732 {
733 struct mii_data *mii = NULL;
734 struct ifnet *ifp;
735 u_int32_t media;
736
737 if (sc->wb_miibus == NULL)
738 return;
739
740 mii = device_get_softc(sc->wb_miibus);
741 ifp = sc->wb_ifp;
742
743 mii_pollstat(mii);
744 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
745 media = mii->mii_media_active & ~IFM_10_T;
746 media |= IFM_100_TX;
747 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
748 media = mii->mii_media_active & ~IFM_100_TX;
749 media |= IFM_10_T;
750 } else
751 return;
752
753 ifmedia_set(&mii->mii_media, media);
754
755 return;
756 }
757
758 /*
759 * Probe for a Winbond chip. Check the PCI vendor and device
760 * IDs against our list and return a device name if we find a match.
761 */
762 static int
763 wb_probe(dev)
764 device_t dev;
765 {
766 struct wb_type *t;
767
768 t = wb_devs;
769
770 while(t->wb_name != NULL) {
771 if ((pci_get_vendor(dev) == t->wb_vid) &&
772 (pci_get_device(dev) == t->wb_did)) {
773 device_set_desc(dev, t->wb_name);
774 return (BUS_PROBE_DEFAULT);
775 }
776 t++;
777 }
778
779 return(ENXIO);
780 }
781
782 /*
783 * Attach the interface. Allocate softc structures, do ifmedia
784 * setup and ethernet/BPF attach.
785 */
786 static int
787 wb_attach(dev)
788 device_t dev;
789 {
790 u_char eaddr[ETHER_ADDR_LEN];
791 struct wb_softc *sc;
792 struct ifnet *ifp;
793 int error = 0, rid;
794
795 sc = device_get_softc(dev);
796
797 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
798 MTX_DEF | MTX_RECURSE);
799 /*
800 * Map control/status registers.
801 */
802 pci_enable_busmaster(dev);
803
804 rid = WB_RID;
805 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE);
806
807 if (sc->wb_res == NULL) {
808 device_printf(dev, "couldn't map ports/memory\n");
809 error = ENXIO;
810 goto fail;
811 }
812
813 sc->wb_btag = rman_get_bustag(sc->wb_res);
814 sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
815
816 /* Allocate interrupt */
817 rid = 0;
818 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
819 RF_SHAREABLE | RF_ACTIVE);
820
821 if (sc->wb_irq == NULL) {
822 device_printf(dev, "couldn't map interrupt\n");
823 error = ENXIO;
824 goto fail;
825 }
826
827 /* Save the cache line size. */
828 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
829
830 /* Reset the adapter. */
831 wb_reset(sc);
832
833 /*
834 * Get station address from the EEPROM.
835 */
836 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0);
837
838 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
839 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
840
841 if (sc->wb_ldata == NULL) {
842 device_printf(dev, "no memory for list buffers!\n");
843 error = ENXIO;
844 goto fail;
845 }
846
847 bzero(sc->wb_ldata, sizeof(struct wb_list_data));
848
849 ifp = sc->wb_ifp = if_alloc(IFT_ETHER);
850 if (ifp == NULL) {
851 device_printf(dev, "can not if_alloc()\n");
852 error = ENOSPC;
853 goto fail;
854 }
855 ifp->if_softc = sc;
856 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
857 ifp->if_mtu = ETHERMTU;
858 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST |
859 IFF_NEEDSGIANT;
860 ifp->if_ioctl = wb_ioctl;
861 ifp->if_start = wb_start;
862 ifp->if_watchdog = wb_watchdog;
863 ifp->if_init = wb_init;
864 ifp->if_baudrate = 10000000;
865 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1;
866
867 /*
868 * Do MII setup.
869 */
870 if (mii_phy_probe(dev, &sc->wb_miibus,
871 wb_ifmedia_upd, wb_ifmedia_sts)) {
872 error = ENXIO;
873 goto fail;
874 }
875
876 /*
877 * Call MI attach routine.
878 */
879 ether_ifattach(ifp, eaddr);
880
881 /* Hook interrupt last to avoid having to lock softc */
882 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET,
883 wb_intr, sc, &sc->wb_intrhand);
884
885 if (error) {
886 device_printf(dev, "couldn't set up irq\n");
887 ether_ifdetach(ifp);
888 goto fail;
889 }
890
891 fail:
892 if (error)
893 wb_detach(dev);
894
895 return(error);
896 }
897
898 /*
899 * Shutdown hardware and free up resources. This can be called any
900 * time after the mutex has been initialized. It is called in both
901 * the error case in attach and the normal detach case so it needs
902 * to be careful about only freeing resources that have actually been
903 * allocated.
904 */
905 static int
906 wb_detach(dev)
907 device_t dev;
908 {
909 struct wb_softc *sc;
910 struct ifnet *ifp;
911
912 sc = device_get_softc(dev);
913 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized"));
914 WB_LOCK(sc);
915 ifp = sc->wb_ifp;
916
917 /*
918 * Delete any miibus and phy devices attached to this interface.
919 * This should only be done if attach succeeded.
920 */
921 if (device_is_attached(dev)) {
922 wb_stop(sc);
923 ether_ifdetach(ifp);
924 }
925 if (ifp)
926 if_free(ifp);
927 if (sc->wb_miibus)
928 device_delete_child(dev, sc->wb_miibus);
929 bus_generic_detach(dev);
930
931 if (sc->wb_intrhand)
932 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
933 if (sc->wb_irq)
934 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
935 if (sc->wb_res)
936 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
937
938 if (sc->wb_ldata) {
939 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8,
940 M_DEVBUF);
941 }
942
943 WB_UNLOCK(sc);
944 mtx_destroy(&sc->wb_mtx);
945
946 return(0);
947 }
948
949 /*
950 * Initialize the transmit descriptors.
951 */
952 static int
953 wb_list_tx_init(sc)
954 struct wb_softc *sc;
955 {
956 struct wb_chain_data *cd;
957 struct wb_list_data *ld;
958 int i;
959
960 cd = &sc->wb_cdata;
961 ld = sc->wb_ldata;
962
963 for (i = 0; i < WB_TX_LIST_CNT; i++) {
964 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
965 if (i == (WB_TX_LIST_CNT - 1)) {
966 cd->wb_tx_chain[i].wb_nextdesc =
967 &cd->wb_tx_chain[0];
968 } else {
969 cd->wb_tx_chain[i].wb_nextdesc =
970 &cd->wb_tx_chain[i + 1];
971 }
972 }
973
974 cd->wb_tx_free = &cd->wb_tx_chain[0];
975 cd->wb_tx_tail = cd->wb_tx_head = NULL;
976
977 return(0);
978 }
979
980
981 /*
982 * Initialize the RX descriptors and allocate mbufs for them. Note that
983 * we arrange the descriptors in a closed ring, so that the last descriptor
984 * points back to the first.
985 */
986 static int
987 wb_list_rx_init(sc)
988 struct wb_softc *sc;
989 {
990 struct wb_chain_data *cd;
991 struct wb_list_data *ld;
992 int i;
993
994 cd = &sc->wb_cdata;
995 ld = sc->wb_ldata;
996
997 for (i = 0; i < WB_RX_LIST_CNT; i++) {
998 cd->wb_rx_chain[i].wb_ptr =
999 (struct wb_desc *)&ld->wb_rx_list[i];
1000 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i];
1001 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
1002 return(ENOBUFS);
1003 if (i == (WB_RX_LIST_CNT - 1)) {
1004 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
1005 ld->wb_rx_list[i].wb_next =
1006 vtophys(&ld->wb_rx_list[0]);
1007 } else {
1008 cd->wb_rx_chain[i].wb_nextdesc =
1009 &cd->wb_rx_chain[i + 1];
1010 ld->wb_rx_list[i].wb_next =
1011 vtophys(&ld->wb_rx_list[i + 1]);
1012 }
1013 }
1014
1015 cd->wb_rx_head = &cd->wb_rx_chain[0];
1016
1017 return(0);
1018 }
1019
1020 static void
1021 wb_bfree(buf, args)
1022 void *buf;
1023 void *args;
1024 {
1025 return;
1026 }
1027
1028 /*
1029 * Initialize an RX descriptor and attach an MBUF cluster.
1030 */
1031 static int
1032 wb_newbuf(sc, c, m)
1033 struct wb_softc *sc;
1034 struct wb_chain_onefrag *c;
1035 struct mbuf *m;
1036 {
1037 struct mbuf *m_new = NULL;
1038
1039 if (m == NULL) {
1040 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1041 if (m_new == NULL)
1042 return(ENOBUFS);
1043 m_new->m_data = c->wb_buf;
1044 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES;
1045 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0,
1046 EXT_NET_DRV);
1047 } else {
1048 m_new = m;
1049 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
1050 m_new->m_data = m_new->m_ext.ext_buf;
1051 }
1052
1053 m_adj(m_new, sizeof(u_int64_t));
1054
1055 c->wb_mbuf = m_new;
1056 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
1057 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
1058 c->wb_ptr->wb_status = WB_RXSTAT;
1059
1060 return(0);
1061 }
1062
1063 /*
1064 * A frame has been uploaded: pass the resulting mbuf chain up to
1065 * the higher level protocols.
1066 */
1067 static void
1068 wb_rxeof(sc)
1069 struct wb_softc *sc;
1070 {
1071 struct mbuf *m = NULL;
1072 struct ifnet *ifp;
1073 struct wb_chain_onefrag *cur_rx;
1074 int total_len = 0;
1075 u_int32_t rxstat;
1076
1077 WB_LOCK_ASSERT(sc);
1078
1079 ifp = sc->wb_ifp;
1080
1081 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
1082 WB_RXSTAT_OWN)) {
1083 struct mbuf *m0 = NULL;
1084
1085 cur_rx = sc->wb_cdata.wb_rx_head;
1086 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
1087
1088 m = cur_rx->wb_mbuf;
1089
1090 if ((rxstat & WB_RXSTAT_MIIERR) ||
1091 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
1092 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
1093 !(rxstat & WB_RXSTAT_LASTFRAG) ||
1094 !(rxstat & WB_RXSTAT_RXCMP)) {
1095 ifp->if_ierrors++;
1096 wb_newbuf(sc, cur_rx, m);
1097 if_printf(ifp, "receiver babbling: possible chip "
1098 "bug, forcing reset\n");
1099 wb_fixmedia(sc);
1100 wb_reset(sc);
1101 wb_init(sc);
1102 return;
1103 }
1104
1105 if (rxstat & WB_RXSTAT_RXERR) {
1106 ifp->if_ierrors++;
1107 wb_newbuf(sc, cur_rx, m);
1108 break;
1109 }
1110
1111 /* No errors; receive the packet. */
1112 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
1113
1114 /*
1115 * XXX The Winbond chip includes the CRC with every
1116 * received frame, and there's no way to turn this
1117 * behavior off (at least, I can't find anything in
1118 * the manual that explains how to do it) so we have
1119 * to trim off the CRC manually.
1120 */
1121 total_len -= ETHER_CRC_LEN;
1122
1123 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp,
1124 NULL);
1125 wb_newbuf(sc, cur_rx, m);
1126 if (m0 == NULL) {
1127 ifp->if_ierrors++;
1128 break;
1129 }
1130 m = m0;
1131
1132 ifp->if_ipackets++;
1133 WB_UNLOCK(sc);
1134 (*ifp->if_input)(ifp, m);
1135 WB_LOCK(sc);
1136 }
1137 }
1138
1139 static void
1140 wb_rxeoc(sc)
1141 struct wb_softc *sc;
1142 {
1143 wb_rxeof(sc);
1144
1145 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1146 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1147 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1148 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
1149 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1150
1151 return;
1152 }
1153
1154 /*
1155 * A frame was downloaded to the chip. It's safe for us to clean up
1156 * the list buffers.
1157 */
1158 static void
1159 wb_txeof(sc)
1160 struct wb_softc *sc;
1161 {
1162 struct wb_chain *cur_tx;
1163 struct ifnet *ifp;
1164
1165 ifp = sc->wb_ifp;
1166
1167 /* Clear the timeout timer. */
1168 ifp->if_timer = 0;
1169
1170 if (sc->wb_cdata.wb_tx_head == NULL)
1171 return;
1172
1173 /*
1174 * Go through our tx list and free mbufs for those
1175 * frames that have been transmitted.
1176 */
1177 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
1178 u_int32_t txstat;
1179
1180 cur_tx = sc->wb_cdata.wb_tx_head;
1181 txstat = WB_TXSTATUS(cur_tx);
1182
1183 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
1184 break;
1185
1186 if (txstat & WB_TXSTAT_TXERR) {
1187 ifp->if_oerrors++;
1188 if (txstat & WB_TXSTAT_ABORT)
1189 ifp->if_collisions++;
1190 if (txstat & WB_TXSTAT_LATECOLL)
1191 ifp->if_collisions++;
1192 }
1193
1194 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1195
1196 ifp->if_opackets++;
1197 m_freem(cur_tx->wb_mbuf);
1198 cur_tx->wb_mbuf = NULL;
1199
1200 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1201 sc->wb_cdata.wb_tx_head = NULL;
1202 sc->wb_cdata.wb_tx_tail = NULL;
1203 break;
1204 }
1205
1206 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1207 }
1208
1209 return;
1210 }
1211
1212 /*
1213 * TX 'end of channel' interrupt handler.
1214 */
1215 static void
1216 wb_txeoc(sc)
1217 struct wb_softc *sc;
1218 {
1219 struct ifnet *ifp;
1220
1221 ifp = sc->wb_ifp;
1222
1223 ifp->if_timer = 0;
1224
1225 if (sc->wb_cdata.wb_tx_head == NULL) {
1226 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1227 sc->wb_cdata.wb_tx_tail = NULL;
1228 } else {
1229 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1230 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1231 ifp->if_timer = 5;
1232 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1233 }
1234 }
1235
1236 return;
1237 }
1238
1239 static void
1240 wb_intr(arg)
1241 void *arg;
1242 {
1243 struct wb_softc *sc;
1244 struct ifnet *ifp;
1245 u_int32_t status;
1246
1247 sc = arg;
1248 WB_LOCK(sc);
1249 ifp = sc->wb_ifp;
1250
1251 if (!(ifp->if_flags & IFF_UP)) {
1252 WB_UNLOCK(sc);
1253 return;
1254 }
1255
1256 /* Disable interrupts. */
1257 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1258
1259 for (;;) {
1260
1261 status = CSR_READ_4(sc, WB_ISR);
1262 if (status)
1263 CSR_WRITE_4(sc, WB_ISR, status);
1264
1265 if ((status & WB_INTRS) == 0)
1266 break;
1267
1268 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1269 ifp->if_ierrors++;
1270 wb_reset(sc);
1271 if (status & WB_ISR_RX_ERR)
1272 wb_fixmedia(sc);
1273 wb_init(sc);
1274 continue;
1275 }
1276
1277 if (status & WB_ISR_RX_OK)
1278 wb_rxeof(sc);
1279
1280 if (status & WB_ISR_RX_IDLE)
1281 wb_rxeoc(sc);
1282
1283 if (status & WB_ISR_TX_OK)
1284 wb_txeof(sc);
1285
1286 if (status & WB_ISR_TX_NOBUF)
1287 wb_txeoc(sc);
1288
1289 if (status & WB_ISR_TX_IDLE) {
1290 wb_txeof(sc);
1291 if (sc->wb_cdata.wb_tx_head != NULL) {
1292 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1293 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1294 }
1295 }
1296
1297 if (status & WB_ISR_TX_UNDERRUN) {
1298 ifp->if_oerrors++;
1299 wb_txeof(sc);
1300 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1301 /* Jack up TX threshold */
1302 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1303 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1304 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1305 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1306 }
1307
1308 if (status & WB_ISR_BUS_ERR) {
1309 wb_reset(sc);
1310 wb_init(sc);
1311 }
1312
1313 }
1314
1315 /* Re-enable interrupts. */
1316 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1317
1318 if (ifp->if_snd.ifq_head != NULL) {
1319 wb_start(ifp);
1320 }
1321
1322 WB_UNLOCK(sc);
1323
1324 return;
1325 }
1326
1327 static void
1328 wb_tick(xsc)
1329 void *xsc;
1330 {
1331 struct wb_softc *sc;
1332 struct mii_data *mii;
1333
1334 sc = xsc;
1335 WB_LOCK(sc);
1336 mii = device_get_softc(sc->wb_miibus);
1337
1338 mii_tick(mii);
1339
1340 sc->wb_stat_ch = timeout(wb_tick, sc, hz);
1341
1342 WB_UNLOCK(sc);
1343
1344 return;
1345 }
1346
1347 /*
1348 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1349 * pointers to the fragment pointers.
1350 */
1351 static int
1352 wb_encap(sc, c, m_head)
1353 struct wb_softc *sc;
1354 struct wb_chain *c;
1355 struct mbuf *m_head;
1356 {
1357 int frag = 0;
1358 struct wb_desc *f = NULL;
1359 int total_len;
1360 struct mbuf *m;
1361
1362 /*
1363 * Start packing the mbufs in this chain into
1364 * the fragment pointers. Stop when we run out
1365 * of fragments or hit the end of the mbuf chain.
1366 */
1367 m = m_head;
1368 total_len = 0;
1369
1370 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1371 if (m->m_len != 0) {
1372 if (frag == WB_MAXFRAGS)
1373 break;
1374 total_len += m->m_len;
1375 f = &c->wb_ptr->wb_frag[frag];
1376 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1377 if (frag == 0) {
1378 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1379 f->wb_status = 0;
1380 } else
1381 f->wb_status = WB_TXSTAT_OWN;
1382 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1383 f->wb_data = vtophys(mtod(m, vm_offset_t));
1384 frag++;
1385 }
1386 }
1387
1388 /*
1389 * Handle special case: we used up all 16 fragments,
1390 * but we have more mbufs left in the chain. Copy the
1391 * data into an mbuf cluster. Note that we don't
1392 * bother clearing the values in the other fragment
1393 * pointers/counters; it wouldn't gain us anything,
1394 * and would waste cycles.
1395 */
1396 if (m != NULL) {
1397 struct mbuf *m_new = NULL;
1398
1399 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1400 if (m_new == NULL)
1401 return(1);
1402 if (m_head->m_pkthdr.len > MHLEN) {
1403 MCLGET(m_new, M_DONTWAIT);
1404 if (!(m_new->m_flags & M_EXT)) {
1405 m_freem(m_new);
1406 return(1);
1407 }
1408 }
1409 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1410 mtod(m_new, caddr_t));
1411 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1412 m_freem(m_head);
1413 m_head = m_new;
1414 f = &c->wb_ptr->wb_frag[0];
1415 f->wb_status = 0;
1416 f->wb_data = vtophys(mtod(m_new, caddr_t));
1417 f->wb_ctl = total_len = m_new->m_len;
1418 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1419 frag = 1;
1420 }
1421
1422 if (total_len < WB_MIN_FRAMELEN) {
1423 f = &c->wb_ptr->wb_frag[frag];
1424 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1425 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1426 f->wb_ctl |= WB_TXCTL_TLINK;
1427 f->wb_status = WB_TXSTAT_OWN;
1428 frag++;
1429 }
1430
1431 c->wb_mbuf = m_head;
1432 c->wb_lastdesc = frag - 1;
1433 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1434 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1435
1436 return(0);
1437 }
1438
1439 /*
1440 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1441 * to the mbuf data regions directly in the transmit lists. We also save a
1442 * copy of the pointers since the transmit list fragment pointers are
1443 * physical addresses.
1444 */
1445
1446 static void
1447 wb_start(ifp)
1448 struct ifnet *ifp;
1449 {
1450 struct wb_softc *sc;
1451 struct mbuf *m_head = NULL;
1452 struct wb_chain *cur_tx = NULL, *start_tx;
1453
1454 sc = ifp->if_softc;
1455 WB_LOCK(sc);
1456
1457 /*
1458 * Check for an available queue slot. If there are none,
1459 * punt.
1460 */
1461 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1462 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1463 WB_UNLOCK(sc);
1464 return;
1465 }
1466
1467 start_tx = sc->wb_cdata.wb_tx_free;
1468
1469 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1470 IF_DEQUEUE(&ifp->if_snd, m_head);
1471 if (m_head == NULL)
1472 break;
1473
1474 /* Pick a descriptor off the free list. */
1475 cur_tx = sc->wb_cdata.wb_tx_free;
1476 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1477
1478 /* Pack the data into the descriptor. */
1479 wb_encap(sc, cur_tx, m_head);
1480
1481 if (cur_tx != start_tx)
1482 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1483
1484 /*
1485 * If there's a BPF listener, bounce a copy of this frame
1486 * to him.
1487 */
1488 BPF_MTAP(ifp, cur_tx->wb_mbuf);
1489 }
1490
1491 /*
1492 * If there are no packets queued, bail.
1493 */
1494 if (cur_tx == NULL) {
1495 WB_UNLOCK(sc);
1496 return;
1497 }
1498
1499 /*
1500 * Place the request for the upload interrupt
1501 * in the last descriptor in the chain. This way, if
1502 * we're chaining several packets at once, we'll only
1503 * get an interupt once for the whole chain rather than
1504 * once for each packet.
1505 */
1506 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1507 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1508 sc->wb_cdata.wb_tx_tail = cur_tx;
1509
1510 if (sc->wb_cdata.wb_tx_head == NULL) {
1511 sc->wb_cdata.wb_tx_head = start_tx;
1512 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1513 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1514 } else {
1515 /*
1516 * We need to distinguish between the case where
1517 * the own bit is clear because the chip cleared it
1518 * and where the own bit is clear because we haven't
1519 * set it yet. The magic value WB_UNSET is just some
1520 * ramdomly chosen number which doesn't have the own
1521 * bit set. When we actually transmit the frame, the
1522 * status word will have _only_ the own bit set, so
1523 * the txeoc handler will be able to tell if it needs
1524 * to initiate another transmission to flush out pending
1525 * frames.
1526 */
1527 WB_TXOWN(start_tx) = WB_UNSENT;
1528 }
1529
1530 /*
1531 * Set a timeout in case the chip goes out to lunch.
1532 */
1533 ifp->if_timer = 5;
1534 WB_UNLOCK(sc);
1535
1536 return;
1537 }
1538
1539 static void
1540 wb_init(xsc)
1541 void *xsc;
1542 {
1543 struct wb_softc *sc = xsc;
1544 struct ifnet *ifp = sc->wb_ifp;
1545 int i;
1546 struct mii_data *mii;
1547
1548 WB_LOCK(sc);
1549 mii = device_get_softc(sc->wb_miibus);
1550
1551 /*
1552 * Cancel pending I/O and free all RX/TX buffers.
1553 */
1554 wb_stop(sc);
1555 wb_reset(sc);
1556
1557 sc->wb_txthresh = WB_TXTHRESH_INIT;
1558
1559 /*
1560 * Set cache alignment and burst length.
1561 */
1562 #ifdef foo
1563 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1564 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1565 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1566 #endif
1567
1568 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION);
1569 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
1570 switch(sc->wb_cachesize) {
1571 case 32:
1572 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
1573 break;
1574 case 16:
1575 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
1576 break;
1577 case 8:
1578 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
1579 break;
1580 case 0:
1581 default:
1582 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
1583 break;
1584 }
1585
1586 /* This doesn't tend to work too well at 100Mbps. */
1587 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1588
1589 /* Init our MAC address */
1590 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1591 CSR_WRITE_1(sc, WB_NODE0 + i, IFP2ENADDR(sc->wb_ifp)[i]);
1592 }
1593
1594 /* Init circular RX list. */
1595 if (wb_list_rx_init(sc) == ENOBUFS) {
1596 if_printf(ifp,
1597 "initialization failed: no memory for rx buffers\n");
1598 wb_stop(sc);
1599 WB_UNLOCK(sc);
1600 return;
1601 }
1602
1603 /* Init TX descriptors. */
1604 wb_list_tx_init(sc);
1605
1606 /* If we want promiscuous mode, set the allframes bit. */
1607 if (ifp->if_flags & IFF_PROMISC) {
1608 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1609 } else {
1610 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1611 }
1612
1613 /*
1614 * Set capture broadcast bit to capture broadcast frames.
1615 */
1616 if (ifp->if_flags & IFF_BROADCAST) {
1617 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1618 } else {
1619 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1620 }
1621
1622 /*
1623 * Program the multicast filter, if necessary.
1624 */
1625 wb_setmulti(sc);
1626
1627 /*
1628 * Load the address of the RX list.
1629 */
1630 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1631 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1632
1633 /*
1634 * Enable interrupts.
1635 */
1636 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1637 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1638
1639 /* Enable receiver and transmitter. */
1640 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1641 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1642
1643 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1644 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1645 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1646
1647 mii_mediachg(mii);
1648
1649 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1650 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1651
1652 sc->wb_stat_ch = timeout(wb_tick, sc, hz);
1653 WB_UNLOCK(sc);
1654
1655 return;
1656 }
1657
1658 /*
1659 * Set media options.
1660 */
1661 static int
1662 wb_ifmedia_upd(ifp)
1663 struct ifnet *ifp;
1664 {
1665 struct wb_softc *sc;
1666
1667 sc = ifp->if_softc;
1668
1669 if (ifp->if_flags & IFF_UP)
1670 wb_init(sc);
1671
1672 return(0);
1673 }
1674
1675 /*
1676 * Report current media status.
1677 */
1678 static void
1679 wb_ifmedia_sts(ifp, ifmr)
1680 struct ifnet *ifp;
1681 struct ifmediareq *ifmr;
1682 {
1683 struct wb_softc *sc;
1684 struct mii_data *mii;
1685
1686 sc = ifp->if_softc;
1687
1688 mii = device_get_softc(sc->wb_miibus);
1689
1690 mii_pollstat(mii);
1691 ifmr->ifm_active = mii->mii_media_active;
1692 ifmr->ifm_status = mii->mii_media_status;
1693
1694 return;
1695 }
1696
1697 static int
1698 wb_ioctl(ifp, command, data)
1699 struct ifnet *ifp;
1700 u_long command;
1701 caddr_t data;
1702 {
1703 struct wb_softc *sc = ifp->if_softc;
1704 struct mii_data *mii;
1705 struct ifreq *ifr = (struct ifreq *) data;
1706 int error = 0;
1707
1708 WB_LOCK(sc);
1709
1710 switch(command) {
1711 case SIOCSIFFLAGS:
1712 if (ifp->if_flags & IFF_UP) {
1713 wb_init(sc);
1714 } else {
1715 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1716 wb_stop(sc);
1717 }
1718 error = 0;
1719 break;
1720 case SIOCADDMULTI:
1721 case SIOCDELMULTI:
1722 wb_setmulti(sc);
1723 error = 0;
1724 break;
1725 case SIOCGIFMEDIA:
1726 case SIOCSIFMEDIA:
1727 mii = device_get_softc(sc->wb_miibus);
1728 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1729 break;
1730 default:
1731 error = ether_ioctl(ifp, command, data);
1732 break;
1733 }
1734
1735 WB_UNLOCK(sc);
1736
1737 return(error);
1738 }
1739
1740 static void
1741 wb_watchdog(ifp)
1742 struct ifnet *ifp;
1743 {
1744 struct wb_softc *sc;
1745
1746 sc = ifp->if_softc;
1747
1748 WB_LOCK(sc);
1749 ifp->if_oerrors++;
1750 if_printf(ifp, "watchdog timeout\n");
1751 #ifdef foo
1752 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1753 if_printf(ifp, "no carrier - transceiver cable problem?\n");
1754 #endif
1755 wb_stop(sc);
1756 wb_reset(sc);
1757 wb_init(sc);
1758
1759 if (ifp->if_snd.ifq_head != NULL)
1760 wb_start(ifp);
1761 WB_UNLOCK(sc);
1762
1763 return;
1764 }
1765
1766 /*
1767 * Stop the adapter and free any mbufs allocated to the
1768 * RX and TX lists.
1769 */
1770 static void
1771 wb_stop(sc)
1772 struct wb_softc *sc;
1773 {
1774 register int i;
1775 struct ifnet *ifp;
1776
1777 WB_LOCK(sc);
1778 ifp = sc->wb_ifp;
1779 ifp->if_timer = 0;
1780
1781 untimeout(wb_tick, sc, sc->wb_stat_ch);
1782
1783 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
1784 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1785 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
1786 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
1787
1788 /*
1789 * Free data in the RX lists.
1790 */
1791 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1792 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
1793 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
1794 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
1795 }
1796 }
1797 bzero((char *)&sc->wb_ldata->wb_rx_list,
1798 sizeof(sc->wb_ldata->wb_rx_list));
1799
1800 /*
1801 * Free the TX list buffers.
1802 */
1803 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1804 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
1805 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
1806 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
1807 }
1808 }
1809
1810 bzero((char *)&sc->wb_ldata->wb_tx_list,
1811 sizeof(sc->wb_ldata->wb_tx_list));
1812
1813 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1814 WB_UNLOCK(sc);
1815
1816 return;
1817 }
1818
1819 /*
1820 * Stop all chip I/O so that the kernel's probe routines don't
1821 * get confused by errant DMAs when rebooting.
1822 */
1823 static void
1824 wb_shutdown(dev)
1825 device_t dev;
1826 {
1827 struct wb_softc *sc;
1828
1829 sc = device_get_softc(dev);
1830 wb_stop(sc);
1831
1832 return;
1833 }
Cache object: ba26eab43fb93a281142fe76117e616b
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