FreeBSD/Linux Kernel Cross Reference
sys/pci/if_wb.c
1 /*-
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 /*
37 * Winbond fast ethernet PCI NIC driver
38 *
39 * Supports various cheap network adapters based on the Winbond W89C840F
40 * fast ethernet controller chip. This includes adapters manufactured by
41 * Winbond itself and some made by Linksys.
42 *
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
46 */
47 /*
48 * The Winbond W89C840F chip is a bus master; in some ways it resembles
49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
50 * one major difference which is that while the registers do many of
51 * the same things as a tulip adapter, the offsets are different: where
52 * tulip registers are typically spaced 8 bytes apart, the Winbond
53 * registers are spaced 4 bytes apart. The receiver filter is also
54 * programmed differently.
55 *
56 * Like the tulip, the Winbond chip uses small descriptors containing
57 * a status word, a control word and 32-bit areas that can either be used
58 * to point to two external data blocks, or to point to a single block
59 * and another descriptor in a linked list. Descriptors can be grouped
60 * together in blocks to form fixed length rings or can be chained
61 * together in linked lists. A single packet may be spread out over
62 * several descriptors if necessary.
63 *
64 * For the receive ring, this driver uses a linked list of descriptors,
65 * each pointing to a single mbuf cluster buffer, which us large enough
66 * to hold an entire packet. The link list is looped back to created a
67 * closed ring.
68 *
69 * For transmission, the driver creates a linked list of 'super descriptors'
70 * which each contain several individual descriptors linked toghether.
71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
72 * abuse as fragment pointers. This allows us to use a buffer managment
73 * scheme very similar to that used in the ThunderLAN and Etherlink XL
74 * drivers.
75 *
76 * Autonegotiation is performed using the external PHY via the MII bus.
77 * The sample boards I have all use a Davicom PHY.
78 *
79 * Note: the author of the Linux driver for the Winbond chip alludes
80 * to some sort of flaw in the chip's design that seems to mandate some
81 * drastic workaround which signigicantly impairs transmit performance.
82 * I have no idea what he's on about: transmit performance with all
83 * three of my test boards seems fine.
84 */
85
86 #include "opt_bdg.h"
87
88 #include <sys/param.h>
89 #include <sys/systm.h>
90 #include <sys/sockio.h>
91 #include <sys/mbuf.h>
92 #include <sys/malloc.h>
93 #include <sys/module.h>
94 #include <sys/kernel.h>
95 #include <sys/socket.h>
96 #include <sys/queue.h>
97
98 #include <net/if.h>
99 #include <net/if_arp.h>
100 #include <net/ethernet.h>
101 #include <net/if_dl.h>
102 #include <net/if_media.h>
103 #include <net/if_types.h>
104
105 #include <net/bpf.h>
106
107 #include <vm/vm.h> /* for vtophys */
108 #include <vm/pmap.h> /* for vtophys */
109 #include <machine/bus.h>
110 #include <machine/resource.h>
111 #include <sys/bus.h>
112 #include <sys/rman.h>
113
114 #include <dev/pci/pcireg.h>
115 #include <dev/pci/pcivar.h>
116
117 #include <dev/mii/mii.h>
118 #include <dev/mii/miivar.h>
119
120 /* "controller miibus0" required. See GENERIC if you get errors here. */
121 #include "miibus_if.h"
122
123 #define WB_USEIOSPACE
124
125 #include <pci/if_wbreg.h>
126
127 MODULE_DEPEND(wb, pci, 1, 1, 1);
128 MODULE_DEPEND(wb, ether, 1, 1, 1);
129 MODULE_DEPEND(wb, miibus, 1, 1, 1);
130
131 /*
132 * Various supported device vendors/types and their names.
133 */
134 static struct wb_type wb_devs[] = {
135 { WB_VENDORID, WB_DEVICEID_840F,
136 "Winbond W89C840F 10/100BaseTX" },
137 { CP_VENDORID, CP_DEVICEID_RL100,
138 "Compex RL100-ATX 10/100baseTX" },
139 { 0, 0, NULL }
140 };
141
142 static int wb_probe(device_t);
143 static int wb_attach(device_t);
144 static int wb_detach(device_t);
145
146 static void wb_bfree(void *addr, void *args);
147 static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *,
148 struct mbuf *);
149 static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *);
150
151 static void wb_rxeof(struct wb_softc *);
152 static void wb_rxeoc(struct wb_softc *);
153 static void wb_txeof(struct wb_softc *);
154 static void wb_txeoc(struct wb_softc *);
155 static void wb_intr(void *);
156 static void wb_tick(void *);
157 static void wb_start(struct ifnet *);
158 static void wb_start_locked(struct ifnet *);
159 static int wb_ioctl(struct ifnet *, u_long, caddr_t);
160 static void wb_init(void *);
161 static void wb_init_locked(struct wb_softc *);
162 static void wb_stop(struct wb_softc *);
163 static void wb_watchdog(struct ifnet *);
164 static void wb_shutdown(device_t);
165 static int wb_ifmedia_upd(struct ifnet *);
166 static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *);
167
168 static void wb_eeprom_putbyte(struct wb_softc *, int);
169 static void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *);
170 static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int);
171 static void wb_mii_sync(struct wb_softc *);
172 static void wb_mii_send(struct wb_softc *, u_int32_t, int);
173 static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *);
174 static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *);
175
176 static void wb_setcfg(struct wb_softc *, u_int32_t);
177 static void wb_setmulti(struct wb_softc *);
178 static void wb_reset(struct wb_softc *);
179 static void wb_fixmedia(struct wb_softc *);
180 static int wb_list_rx_init(struct wb_softc *);
181 static int wb_list_tx_init(struct wb_softc *);
182
183 static int wb_miibus_readreg(device_t, int, int);
184 static int wb_miibus_writereg(device_t, int, int, int);
185 static void wb_miibus_statchg(device_t);
186
187 #ifdef WB_USEIOSPACE
188 #define WB_RES SYS_RES_IOPORT
189 #define WB_RID WB_PCI_LOIO
190 #else
191 #define WB_RES SYS_RES_MEMORY
192 #define WB_RID WB_PCI_LOMEM
193 #endif
194
195 static device_method_t wb_methods[] = {
196 /* Device interface */
197 DEVMETHOD(device_probe, wb_probe),
198 DEVMETHOD(device_attach, wb_attach),
199 DEVMETHOD(device_detach, wb_detach),
200 DEVMETHOD(device_shutdown, wb_shutdown),
201
202 /* bus interface, for miibus */
203 DEVMETHOD(bus_print_child, bus_generic_print_child),
204 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
205
206 /* MII interface */
207 DEVMETHOD(miibus_readreg, wb_miibus_readreg),
208 DEVMETHOD(miibus_writereg, wb_miibus_writereg),
209 DEVMETHOD(miibus_statchg, wb_miibus_statchg),
210 { 0, 0 }
211 };
212
213 static driver_t wb_driver = {
214 "wb",
215 wb_methods,
216 sizeof(struct wb_softc)
217 };
218
219 static devclass_t wb_devclass;
220
221 DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0);
222 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
223
224 #define WB_SETBIT(sc, reg, x) \
225 CSR_WRITE_4(sc, reg, \
226 CSR_READ_4(sc, reg) | (x))
227
228 #define WB_CLRBIT(sc, reg, x) \
229 CSR_WRITE_4(sc, reg, \
230 CSR_READ_4(sc, reg) & ~(x))
231
232 #define SIO_SET(x) \
233 CSR_WRITE_4(sc, WB_SIO, \
234 CSR_READ_4(sc, WB_SIO) | (x))
235
236 #define SIO_CLR(x) \
237 CSR_WRITE_4(sc, WB_SIO, \
238 CSR_READ_4(sc, WB_SIO) & ~(x))
239
240 /*
241 * Send a read command and address to the EEPROM, check for ACK.
242 */
243 static void
244 wb_eeprom_putbyte(sc, addr)
245 struct wb_softc *sc;
246 int addr;
247 {
248 register int d, i;
249
250 d = addr | WB_EECMD_READ;
251
252 /*
253 * Feed in each bit and stobe the clock.
254 */
255 for (i = 0x400; i; i >>= 1) {
256 if (d & i) {
257 SIO_SET(WB_SIO_EE_DATAIN);
258 } else {
259 SIO_CLR(WB_SIO_EE_DATAIN);
260 }
261 DELAY(100);
262 SIO_SET(WB_SIO_EE_CLK);
263 DELAY(150);
264 SIO_CLR(WB_SIO_EE_CLK);
265 DELAY(100);
266 }
267
268 return;
269 }
270
271 /*
272 * Read a word of data stored in the EEPROM at address 'addr.'
273 */
274 static void
275 wb_eeprom_getword(sc, addr, dest)
276 struct wb_softc *sc;
277 int addr;
278 u_int16_t *dest;
279 {
280 register int i;
281 u_int16_t word = 0;
282
283 /* Enter EEPROM access mode. */
284 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
285
286 /*
287 * Send address of word we want to read.
288 */
289 wb_eeprom_putbyte(sc, addr);
290
291 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
292
293 /*
294 * Start reading bits from EEPROM.
295 */
296 for (i = 0x8000; i; i >>= 1) {
297 SIO_SET(WB_SIO_EE_CLK);
298 DELAY(100);
299 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
300 word |= i;
301 SIO_CLR(WB_SIO_EE_CLK);
302 DELAY(100);
303 }
304
305 /* Turn off EEPROM access mode. */
306 CSR_WRITE_4(sc, WB_SIO, 0);
307
308 *dest = word;
309
310 return;
311 }
312
313 /*
314 * Read a sequence of words from the EEPROM.
315 */
316 static void
317 wb_read_eeprom(sc, dest, off, cnt, swap)
318 struct wb_softc *sc;
319 caddr_t dest;
320 int off;
321 int cnt;
322 int swap;
323 {
324 int i;
325 u_int16_t word = 0, *ptr;
326
327 for (i = 0; i < cnt; i++) {
328 wb_eeprom_getword(sc, off + i, &word);
329 ptr = (u_int16_t *)(dest + (i * 2));
330 if (swap)
331 *ptr = ntohs(word);
332 else
333 *ptr = word;
334 }
335
336 return;
337 }
338
339 /*
340 * Sync the PHYs by setting data bit and strobing the clock 32 times.
341 */
342 static void
343 wb_mii_sync(sc)
344 struct wb_softc *sc;
345 {
346 register int i;
347
348 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN);
349
350 for (i = 0; i < 32; i++) {
351 SIO_SET(WB_SIO_MII_CLK);
352 DELAY(1);
353 SIO_CLR(WB_SIO_MII_CLK);
354 DELAY(1);
355 }
356
357 return;
358 }
359
360 /*
361 * Clock a series of bits through the MII.
362 */
363 static void
364 wb_mii_send(sc, bits, cnt)
365 struct wb_softc *sc;
366 u_int32_t bits;
367 int cnt;
368 {
369 int i;
370
371 SIO_CLR(WB_SIO_MII_CLK);
372
373 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
374 if (bits & i) {
375 SIO_SET(WB_SIO_MII_DATAIN);
376 } else {
377 SIO_CLR(WB_SIO_MII_DATAIN);
378 }
379 DELAY(1);
380 SIO_CLR(WB_SIO_MII_CLK);
381 DELAY(1);
382 SIO_SET(WB_SIO_MII_CLK);
383 }
384 }
385
386 /*
387 * Read an PHY register through the MII.
388 */
389 static int
390 wb_mii_readreg(sc, frame)
391 struct wb_softc *sc;
392 struct wb_mii_frame *frame;
393
394 {
395 int i, ack;
396
397 /*
398 * Set up frame for RX.
399 */
400 frame->mii_stdelim = WB_MII_STARTDELIM;
401 frame->mii_opcode = WB_MII_READOP;
402 frame->mii_turnaround = 0;
403 frame->mii_data = 0;
404
405 CSR_WRITE_4(sc, WB_SIO, 0);
406
407 /*
408 * Turn on data xmit.
409 */
410 SIO_SET(WB_SIO_MII_DIR);
411
412 wb_mii_sync(sc);
413
414 /*
415 * Send command/address info.
416 */
417 wb_mii_send(sc, frame->mii_stdelim, 2);
418 wb_mii_send(sc, frame->mii_opcode, 2);
419 wb_mii_send(sc, frame->mii_phyaddr, 5);
420 wb_mii_send(sc, frame->mii_regaddr, 5);
421
422 /* Idle bit */
423 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN));
424 DELAY(1);
425 SIO_SET(WB_SIO_MII_CLK);
426 DELAY(1);
427
428 /* Turn off xmit. */
429 SIO_CLR(WB_SIO_MII_DIR);
430 /* Check for ack */
431 SIO_CLR(WB_SIO_MII_CLK);
432 DELAY(1);
433 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
434 SIO_SET(WB_SIO_MII_CLK);
435 DELAY(1);
436 SIO_CLR(WB_SIO_MII_CLK);
437 DELAY(1);
438 SIO_SET(WB_SIO_MII_CLK);
439 DELAY(1);
440
441 /*
442 * Now try reading data bits. If the ack failed, we still
443 * need to clock through 16 cycles to keep the PHY(s) in sync.
444 */
445 if (ack) {
446 for(i = 0; i < 16; i++) {
447 SIO_CLR(WB_SIO_MII_CLK);
448 DELAY(1);
449 SIO_SET(WB_SIO_MII_CLK);
450 DELAY(1);
451 }
452 goto fail;
453 }
454
455 for (i = 0x8000; i; i >>= 1) {
456 SIO_CLR(WB_SIO_MII_CLK);
457 DELAY(1);
458 if (!ack) {
459 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
460 frame->mii_data |= i;
461 DELAY(1);
462 }
463 SIO_SET(WB_SIO_MII_CLK);
464 DELAY(1);
465 }
466
467 fail:
468
469 SIO_CLR(WB_SIO_MII_CLK);
470 DELAY(1);
471 SIO_SET(WB_SIO_MII_CLK);
472 DELAY(1);
473
474 if (ack)
475 return(1);
476 return(0);
477 }
478
479 /*
480 * Write to a PHY register through the MII.
481 */
482 static int
483 wb_mii_writereg(sc, frame)
484 struct wb_softc *sc;
485 struct wb_mii_frame *frame;
486
487 {
488
489 /*
490 * Set up frame for TX.
491 */
492
493 frame->mii_stdelim = WB_MII_STARTDELIM;
494 frame->mii_opcode = WB_MII_WRITEOP;
495 frame->mii_turnaround = WB_MII_TURNAROUND;
496
497 /*
498 * Turn on data output.
499 */
500 SIO_SET(WB_SIO_MII_DIR);
501
502 wb_mii_sync(sc);
503
504 wb_mii_send(sc, frame->mii_stdelim, 2);
505 wb_mii_send(sc, frame->mii_opcode, 2);
506 wb_mii_send(sc, frame->mii_phyaddr, 5);
507 wb_mii_send(sc, frame->mii_regaddr, 5);
508 wb_mii_send(sc, frame->mii_turnaround, 2);
509 wb_mii_send(sc, frame->mii_data, 16);
510
511 /* Idle bit. */
512 SIO_SET(WB_SIO_MII_CLK);
513 DELAY(1);
514 SIO_CLR(WB_SIO_MII_CLK);
515 DELAY(1);
516
517 /*
518 * Turn off xmit.
519 */
520 SIO_CLR(WB_SIO_MII_DIR);
521
522 return(0);
523 }
524
525 static int
526 wb_miibus_readreg(dev, phy, reg)
527 device_t dev;
528 int phy, reg;
529 {
530 struct wb_softc *sc;
531 struct wb_mii_frame frame;
532
533 sc = device_get_softc(dev);
534
535 bzero((char *)&frame, sizeof(frame));
536
537 frame.mii_phyaddr = phy;
538 frame.mii_regaddr = reg;
539 wb_mii_readreg(sc, &frame);
540
541 return(frame.mii_data);
542 }
543
544 static int
545 wb_miibus_writereg(dev, phy, reg, data)
546 device_t dev;
547 int phy, reg, data;
548 {
549 struct wb_softc *sc;
550 struct wb_mii_frame frame;
551
552 sc = device_get_softc(dev);
553
554 bzero((char *)&frame, sizeof(frame));
555
556 frame.mii_phyaddr = phy;
557 frame.mii_regaddr = reg;
558 frame.mii_data = data;
559
560 wb_mii_writereg(sc, &frame);
561
562 return(0);
563 }
564
565 static void
566 wb_miibus_statchg(dev)
567 device_t dev;
568 {
569 struct wb_softc *sc;
570 struct mii_data *mii;
571
572 sc = device_get_softc(dev);
573 mii = device_get_softc(sc->wb_miibus);
574 wb_setcfg(sc, mii->mii_media_active);
575
576 return;
577 }
578
579 /*
580 * Program the 64-bit multicast hash filter.
581 */
582 static void
583 wb_setmulti(sc)
584 struct wb_softc *sc;
585 {
586 struct ifnet *ifp;
587 int h = 0;
588 u_int32_t hashes[2] = { 0, 0 };
589 struct ifmultiaddr *ifma;
590 u_int32_t rxfilt;
591 int mcnt = 0;
592
593 ifp = sc->wb_ifp;
594
595 rxfilt = CSR_READ_4(sc, WB_NETCFG);
596
597 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
598 rxfilt |= WB_NETCFG_RX_MULTI;
599 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
600 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
601 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
602 return;
603 }
604
605 /* first, zot all the existing hash bits */
606 CSR_WRITE_4(sc, WB_MAR0, 0);
607 CSR_WRITE_4(sc, WB_MAR1, 0);
608
609 /* now program new ones */
610 IF_ADDR_LOCK(ifp);
611 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
612 if (ifma->ifma_addr->sa_family != AF_LINK)
613 continue;
614 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
615 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
616 if (h < 32)
617 hashes[0] |= (1 << h);
618 else
619 hashes[1] |= (1 << (h - 32));
620 mcnt++;
621 }
622 IF_ADDR_UNLOCK(ifp);
623
624 if (mcnt)
625 rxfilt |= WB_NETCFG_RX_MULTI;
626 else
627 rxfilt &= ~WB_NETCFG_RX_MULTI;
628
629 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
630 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
631 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
632
633 return;
634 }
635
636 /*
637 * The Winbond manual states that in order to fiddle with the
638 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
639 * first have to put the transmit and/or receive logic in the idle state.
640 */
641 static void
642 wb_setcfg(sc, media)
643 struct wb_softc *sc;
644 u_int32_t media;
645 {
646 int i, restart = 0;
647
648 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
649 restart = 1;
650 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
651
652 for (i = 0; i < WB_TIMEOUT; i++) {
653 DELAY(10);
654 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
655 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
656 break;
657 }
658
659 if (i == WB_TIMEOUT)
660 if_printf(sc->wb_ifp,
661 "failed to force tx and rx to idle state\n");
662 }
663
664 if (IFM_SUBTYPE(media) == IFM_10_T)
665 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
666 else
667 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
668
669 if ((media & IFM_GMASK) == IFM_FDX)
670 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
671 else
672 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
673
674 if (restart)
675 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
676
677 return;
678 }
679
680 static void
681 wb_reset(sc)
682 struct wb_softc *sc;
683 {
684 register int i;
685 struct mii_data *mii;
686
687 CSR_WRITE_4(sc, WB_NETCFG, 0);
688 CSR_WRITE_4(sc, WB_BUSCTL, 0);
689 CSR_WRITE_4(sc, WB_TXADDR, 0);
690 CSR_WRITE_4(sc, WB_RXADDR, 0);
691
692 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
693 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
694
695 for (i = 0; i < WB_TIMEOUT; i++) {
696 DELAY(10);
697 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
698 break;
699 }
700 if (i == WB_TIMEOUT)
701 if_printf(sc->wb_ifp, "reset never completed!\n");
702
703 /* Wait a little while for the chip to get its brains in order. */
704 DELAY(1000);
705
706 if (sc->wb_miibus == NULL)
707 return;
708
709 mii = device_get_softc(sc->wb_miibus);
710 if (mii == NULL)
711 return;
712
713 if (mii->mii_instance) {
714 struct mii_softc *miisc;
715 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
716 mii_phy_reset(miisc);
717 }
718
719 return;
720 }
721
722 static void
723 wb_fixmedia(sc)
724 struct wb_softc *sc;
725 {
726 struct mii_data *mii = NULL;
727 struct ifnet *ifp;
728 u_int32_t media;
729
730 if (sc->wb_miibus == NULL)
731 return;
732
733 mii = device_get_softc(sc->wb_miibus);
734 ifp = sc->wb_ifp;
735
736 mii_pollstat(mii);
737 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
738 media = mii->mii_media_active & ~IFM_10_T;
739 media |= IFM_100_TX;
740 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
741 media = mii->mii_media_active & ~IFM_100_TX;
742 media |= IFM_10_T;
743 } else
744 return;
745
746 ifmedia_set(&mii->mii_media, media);
747
748 return;
749 }
750
751 /*
752 * Probe for a Winbond chip. Check the PCI vendor and device
753 * IDs against our list and return a device name if we find a match.
754 */
755 static int
756 wb_probe(dev)
757 device_t dev;
758 {
759 struct wb_type *t;
760
761 t = wb_devs;
762
763 while(t->wb_name != NULL) {
764 if ((pci_get_vendor(dev) == t->wb_vid) &&
765 (pci_get_device(dev) == t->wb_did)) {
766 device_set_desc(dev, t->wb_name);
767 return (BUS_PROBE_DEFAULT);
768 }
769 t++;
770 }
771
772 return(ENXIO);
773 }
774
775 /*
776 * Attach the interface. Allocate softc structures, do ifmedia
777 * setup and ethernet/BPF attach.
778 */
779 static int
780 wb_attach(dev)
781 device_t dev;
782 {
783 u_char eaddr[ETHER_ADDR_LEN];
784 struct wb_softc *sc;
785 struct ifnet *ifp;
786 int error = 0, rid;
787
788 sc = device_get_softc(dev);
789
790 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
791 MTX_DEF);
792 callout_init_mtx(&sc->wb_stat_callout, &sc->wb_mtx, 0);
793
794 /*
795 * Map control/status registers.
796 */
797 pci_enable_busmaster(dev);
798
799 rid = WB_RID;
800 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE);
801
802 if (sc->wb_res == NULL) {
803 device_printf(dev, "couldn't map ports/memory\n");
804 error = ENXIO;
805 goto fail;
806 }
807
808 sc->wb_btag = rman_get_bustag(sc->wb_res);
809 sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
810
811 /* Allocate interrupt */
812 rid = 0;
813 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
814 RF_SHAREABLE | RF_ACTIVE);
815
816 if (sc->wb_irq == NULL) {
817 device_printf(dev, "couldn't map interrupt\n");
818 error = ENXIO;
819 goto fail;
820 }
821
822 /* Save the cache line size. */
823 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
824
825 /* Reset the adapter. */
826 wb_reset(sc);
827
828 /*
829 * Get station address from the EEPROM.
830 */
831 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0);
832
833 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
834 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
835
836 if (sc->wb_ldata == NULL) {
837 device_printf(dev, "no memory for list buffers!\n");
838 error = ENXIO;
839 goto fail;
840 }
841
842 bzero(sc->wb_ldata, sizeof(struct wb_list_data));
843
844 ifp = sc->wb_ifp = if_alloc(IFT_ETHER);
845 if (ifp == NULL) {
846 device_printf(dev, "can not if_alloc()\n");
847 error = ENOSPC;
848 goto fail;
849 }
850 ifp->if_softc = sc;
851 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
852 ifp->if_mtu = ETHERMTU;
853 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
854 ifp->if_ioctl = wb_ioctl;
855 ifp->if_start = wb_start;
856 ifp->if_watchdog = wb_watchdog;
857 ifp->if_init = wb_init;
858 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1;
859
860 /*
861 * Do MII setup.
862 */
863 if (mii_phy_probe(dev, &sc->wb_miibus,
864 wb_ifmedia_upd, wb_ifmedia_sts)) {
865 error = ENXIO;
866 goto fail;
867 }
868
869 /*
870 * Call MI attach routine.
871 */
872 ether_ifattach(ifp, eaddr);
873
874 /* Hook interrupt last to avoid having to lock softc */
875 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET | INTR_MPSAFE,
876 wb_intr, sc, &sc->wb_intrhand);
877
878 if (error) {
879 device_printf(dev, "couldn't set up irq\n");
880 ether_ifdetach(ifp);
881 goto fail;
882 }
883
884 fail:
885 if (error)
886 wb_detach(dev);
887
888 return(error);
889 }
890
891 /*
892 * Shutdown hardware and free up resources. This can be called any
893 * time after the mutex has been initialized. It is called in both
894 * the error case in attach and the normal detach case so it needs
895 * to be careful about only freeing resources that have actually been
896 * allocated.
897 */
898 static int
899 wb_detach(dev)
900 device_t dev;
901 {
902 struct wb_softc *sc;
903 struct ifnet *ifp;
904
905 sc = device_get_softc(dev);
906 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized"));
907 ifp = sc->wb_ifp;
908
909 /*
910 * Delete any miibus and phy devices attached to this interface.
911 * This should only be done if attach succeeded.
912 */
913 if (device_is_attached(dev)) {
914 WB_LOCK(sc);
915 wb_stop(sc);
916 WB_UNLOCK(sc);
917 callout_drain(&sc->wb_stat_callout);
918 ether_ifdetach(ifp);
919 }
920 if (ifp)
921 if_free(ifp);
922 if (sc->wb_miibus)
923 device_delete_child(dev, sc->wb_miibus);
924 bus_generic_detach(dev);
925
926 if (sc->wb_intrhand)
927 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
928 if (sc->wb_irq)
929 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
930 if (sc->wb_res)
931 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
932
933 if (sc->wb_ldata) {
934 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8,
935 M_DEVBUF);
936 }
937
938 mtx_destroy(&sc->wb_mtx);
939
940 return(0);
941 }
942
943 /*
944 * Initialize the transmit descriptors.
945 */
946 static int
947 wb_list_tx_init(sc)
948 struct wb_softc *sc;
949 {
950 struct wb_chain_data *cd;
951 struct wb_list_data *ld;
952 int i;
953
954 cd = &sc->wb_cdata;
955 ld = sc->wb_ldata;
956
957 for (i = 0; i < WB_TX_LIST_CNT; i++) {
958 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
959 if (i == (WB_TX_LIST_CNT - 1)) {
960 cd->wb_tx_chain[i].wb_nextdesc =
961 &cd->wb_tx_chain[0];
962 } else {
963 cd->wb_tx_chain[i].wb_nextdesc =
964 &cd->wb_tx_chain[i + 1];
965 }
966 }
967
968 cd->wb_tx_free = &cd->wb_tx_chain[0];
969 cd->wb_tx_tail = cd->wb_tx_head = NULL;
970
971 return(0);
972 }
973
974
975 /*
976 * Initialize the RX descriptors and allocate mbufs for them. Note that
977 * we arrange the descriptors in a closed ring, so that the last descriptor
978 * points back to the first.
979 */
980 static int
981 wb_list_rx_init(sc)
982 struct wb_softc *sc;
983 {
984 struct wb_chain_data *cd;
985 struct wb_list_data *ld;
986 int i;
987
988 cd = &sc->wb_cdata;
989 ld = sc->wb_ldata;
990
991 for (i = 0; i < WB_RX_LIST_CNT; i++) {
992 cd->wb_rx_chain[i].wb_ptr =
993 (struct wb_desc *)&ld->wb_rx_list[i];
994 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i];
995 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
996 return(ENOBUFS);
997 if (i == (WB_RX_LIST_CNT - 1)) {
998 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
999 ld->wb_rx_list[i].wb_next =
1000 vtophys(&ld->wb_rx_list[0]);
1001 } else {
1002 cd->wb_rx_chain[i].wb_nextdesc =
1003 &cd->wb_rx_chain[i + 1];
1004 ld->wb_rx_list[i].wb_next =
1005 vtophys(&ld->wb_rx_list[i + 1]);
1006 }
1007 }
1008
1009 cd->wb_rx_head = &cd->wb_rx_chain[0];
1010
1011 return(0);
1012 }
1013
1014 static void
1015 wb_bfree(buf, args)
1016 void *buf;
1017 void *args;
1018 {
1019 return;
1020 }
1021
1022 /*
1023 * Initialize an RX descriptor and attach an MBUF cluster.
1024 */
1025 static int
1026 wb_newbuf(sc, c, m)
1027 struct wb_softc *sc;
1028 struct wb_chain_onefrag *c;
1029 struct mbuf *m;
1030 {
1031 struct mbuf *m_new = NULL;
1032
1033 if (m == NULL) {
1034 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1035 if (m_new == NULL)
1036 return(ENOBUFS);
1037 m_new->m_data = c->wb_buf;
1038 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES;
1039 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0,
1040 EXT_NET_DRV);
1041 } else {
1042 m_new = m;
1043 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
1044 m_new->m_data = m_new->m_ext.ext_buf;
1045 }
1046
1047 m_adj(m_new, sizeof(u_int64_t));
1048
1049 c->wb_mbuf = m_new;
1050 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
1051 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
1052 c->wb_ptr->wb_status = WB_RXSTAT;
1053
1054 return(0);
1055 }
1056
1057 /*
1058 * A frame has been uploaded: pass the resulting mbuf chain up to
1059 * the higher level protocols.
1060 */
1061 static void
1062 wb_rxeof(sc)
1063 struct wb_softc *sc;
1064 {
1065 struct mbuf *m = NULL;
1066 struct ifnet *ifp;
1067 struct wb_chain_onefrag *cur_rx;
1068 int total_len = 0;
1069 u_int32_t rxstat;
1070
1071 WB_LOCK_ASSERT(sc);
1072
1073 ifp = sc->wb_ifp;
1074
1075 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
1076 WB_RXSTAT_OWN)) {
1077 struct mbuf *m0 = NULL;
1078
1079 cur_rx = sc->wb_cdata.wb_rx_head;
1080 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
1081
1082 m = cur_rx->wb_mbuf;
1083
1084 if ((rxstat & WB_RXSTAT_MIIERR) ||
1085 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
1086 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
1087 !(rxstat & WB_RXSTAT_LASTFRAG) ||
1088 !(rxstat & WB_RXSTAT_RXCMP)) {
1089 ifp->if_ierrors++;
1090 wb_newbuf(sc, cur_rx, m);
1091 if_printf(ifp, "receiver babbling: possible chip "
1092 "bug, forcing reset\n");
1093 wb_fixmedia(sc);
1094 wb_reset(sc);
1095 wb_init_locked(sc);
1096 return;
1097 }
1098
1099 if (rxstat & WB_RXSTAT_RXERR) {
1100 ifp->if_ierrors++;
1101 wb_newbuf(sc, cur_rx, m);
1102 break;
1103 }
1104
1105 /* No errors; receive the packet. */
1106 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
1107
1108 /*
1109 * XXX The Winbond chip includes the CRC with every
1110 * received frame, and there's no way to turn this
1111 * behavior off (at least, I can't find anything in
1112 * the manual that explains how to do it) so we have
1113 * to trim off the CRC manually.
1114 */
1115 total_len -= ETHER_CRC_LEN;
1116
1117 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp,
1118 NULL);
1119 wb_newbuf(sc, cur_rx, m);
1120 if (m0 == NULL) {
1121 ifp->if_ierrors++;
1122 break;
1123 }
1124 m = m0;
1125
1126 ifp->if_ipackets++;
1127 WB_UNLOCK(sc);
1128 (*ifp->if_input)(ifp, m);
1129 WB_LOCK(sc);
1130 }
1131 }
1132
1133 static void
1134 wb_rxeoc(sc)
1135 struct wb_softc *sc;
1136 {
1137 wb_rxeof(sc);
1138
1139 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1140 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1141 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1142 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
1143 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1144
1145 return;
1146 }
1147
1148 /*
1149 * A frame was downloaded to the chip. It's safe for us to clean up
1150 * the list buffers.
1151 */
1152 static void
1153 wb_txeof(sc)
1154 struct wb_softc *sc;
1155 {
1156 struct wb_chain *cur_tx;
1157 struct ifnet *ifp;
1158
1159 ifp = sc->wb_ifp;
1160
1161 /* Clear the timeout timer. */
1162 ifp->if_timer = 0;
1163
1164 if (sc->wb_cdata.wb_tx_head == NULL)
1165 return;
1166
1167 /*
1168 * Go through our tx list and free mbufs for those
1169 * frames that have been transmitted.
1170 */
1171 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
1172 u_int32_t txstat;
1173
1174 cur_tx = sc->wb_cdata.wb_tx_head;
1175 txstat = WB_TXSTATUS(cur_tx);
1176
1177 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
1178 break;
1179
1180 if (txstat & WB_TXSTAT_TXERR) {
1181 ifp->if_oerrors++;
1182 if (txstat & WB_TXSTAT_ABORT)
1183 ifp->if_collisions++;
1184 if (txstat & WB_TXSTAT_LATECOLL)
1185 ifp->if_collisions++;
1186 }
1187
1188 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1189
1190 ifp->if_opackets++;
1191 m_freem(cur_tx->wb_mbuf);
1192 cur_tx->wb_mbuf = NULL;
1193
1194 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1195 sc->wb_cdata.wb_tx_head = NULL;
1196 sc->wb_cdata.wb_tx_tail = NULL;
1197 break;
1198 }
1199
1200 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1201 }
1202
1203 return;
1204 }
1205
1206 /*
1207 * TX 'end of channel' interrupt handler.
1208 */
1209 static void
1210 wb_txeoc(sc)
1211 struct wb_softc *sc;
1212 {
1213 struct ifnet *ifp;
1214
1215 ifp = sc->wb_ifp;
1216
1217 ifp->if_timer = 0;
1218
1219 if (sc->wb_cdata.wb_tx_head == NULL) {
1220 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1221 sc->wb_cdata.wb_tx_tail = NULL;
1222 } else {
1223 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1224 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1225 ifp->if_timer = 5;
1226 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1227 }
1228 }
1229
1230 return;
1231 }
1232
1233 static void
1234 wb_intr(arg)
1235 void *arg;
1236 {
1237 struct wb_softc *sc;
1238 struct ifnet *ifp;
1239 u_int32_t status;
1240
1241 sc = arg;
1242 WB_LOCK(sc);
1243 ifp = sc->wb_ifp;
1244
1245 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1246 WB_UNLOCK(sc);
1247 return;
1248 }
1249
1250 /* Disable interrupts. */
1251 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1252
1253 for (;;) {
1254
1255 status = CSR_READ_4(sc, WB_ISR);
1256 if (status)
1257 CSR_WRITE_4(sc, WB_ISR, status);
1258
1259 if ((status & WB_INTRS) == 0)
1260 break;
1261
1262 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1263 ifp->if_ierrors++;
1264 wb_reset(sc);
1265 if (status & WB_ISR_RX_ERR)
1266 wb_fixmedia(sc);
1267 wb_init_locked(sc);
1268 continue;
1269 }
1270
1271 if (status & WB_ISR_RX_OK)
1272 wb_rxeof(sc);
1273
1274 if (status & WB_ISR_RX_IDLE)
1275 wb_rxeoc(sc);
1276
1277 if (status & WB_ISR_TX_OK)
1278 wb_txeof(sc);
1279
1280 if (status & WB_ISR_TX_NOBUF)
1281 wb_txeoc(sc);
1282
1283 if (status & WB_ISR_TX_IDLE) {
1284 wb_txeof(sc);
1285 if (sc->wb_cdata.wb_tx_head != NULL) {
1286 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1287 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1288 }
1289 }
1290
1291 if (status & WB_ISR_TX_UNDERRUN) {
1292 ifp->if_oerrors++;
1293 wb_txeof(sc);
1294 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1295 /* Jack up TX threshold */
1296 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1297 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1298 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1299 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1300 }
1301
1302 if (status & WB_ISR_BUS_ERR) {
1303 wb_reset(sc);
1304 wb_init_locked(sc);
1305 }
1306
1307 }
1308
1309 /* Re-enable interrupts. */
1310 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1311
1312 if (ifp->if_snd.ifq_head != NULL) {
1313 wb_start_locked(ifp);
1314 }
1315
1316 WB_UNLOCK(sc);
1317
1318 return;
1319 }
1320
1321 static void
1322 wb_tick(xsc)
1323 void *xsc;
1324 {
1325 struct wb_softc *sc;
1326 struct mii_data *mii;
1327
1328 sc = xsc;
1329 WB_LOCK_ASSERT(sc);
1330 mii = device_get_softc(sc->wb_miibus);
1331
1332 mii_tick(mii);
1333
1334 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc);
1335
1336 return;
1337 }
1338
1339 /*
1340 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1341 * pointers to the fragment pointers.
1342 */
1343 static int
1344 wb_encap(sc, c, m_head)
1345 struct wb_softc *sc;
1346 struct wb_chain *c;
1347 struct mbuf *m_head;
1348 {
1349 int frag = 0;
1350 struct wb_desc *f = NULL;
1351 int total_len;
1352 struct mbuf *m;
1353
1354 /*
1355 * Start packing the mbufs in this chain into
1356 * the fragment pointers. Stop when we run out
1357 * of fragments or hit the end of the mbuf chain.
1358 */
1359 m = m_head;
1360 total_len = 0;
1361
1362 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1363 if (m->m_len != 0) {
1364 if (frag == WB_MAXFRAGS)
1365 break;
1366 total_len += m->m_len;
1367 f = &c->wb_ptr->wb_frag[frag];
1368 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1369 if (frag == 0) {
1370 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1371 f->wb_status = 0;
1372 } else
1373 f->wb_status = WB_TXSTAT_OWN;
1374 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1375 f->wb_data = vtophys(mtod(m, vm_offset_t));
1376 frag++;
1377 }
1378 }
1379
1380 /*
1381 * Handle special case: we used up all 16 fragments,
1382 * but we have more mbufs left in the chain. Copy the
1383 * data into an mbuf cluster. Note that we don't
1384 * bother clearing the values in the other fragment
1385 * pointers/counters; it wouldn't gain us anything,
1386 * and would waste cycles.
1387 */
1388 if (m != NULL) {
1389 struct mbuf *m_new = NULL;
1390
1391 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1392 if (m_new == NULL)
1393 return(1);
1394 if (m_head->m_pkthdr.len > MHLEN) {
1395 MCLGET(m_new, M_DONTWAIT);
1396 if (!(m_new->m_flags & M_EXT)) {
1397 m_freem(m_new);
1398 return(1);
1399 }
1400 }
1401 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1402 mtod(m_new, caddr_t));
1403 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1404 m_freem(m_head);
1405 m_head = m_new;
1406 f = &c->wb_ptr->wb_frag[0];
1407 f->wb_status = 0;
1408 f->wb_data = vtophys(mtod(m_new, caddr_t));
1409 f->wb_ctl = total_len = m_new->m_len;
1410 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1411 frag = 1;
1412 }
1413
1414 if (total_len < WB_MIN_FRAMELEN) {
1415 f = &c->wb_ptr->wb_frag[frag];
1416 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1417 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1418 f->wb_ctl |= WB_TXCTL_TLINK;
1419 f->wb_status = WB_TXSTAT_OWN;
1420 frag++;
1421 }
1422
1423 c->wb_mbuf = m_head;
1424 c->wb_lastdesc = frag - 1;
1425 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1426 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1427
1428 return(0);
1429 }
1430
1431 /*
1432 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1433 * to the mbuf data regions directly in the transmit lists. We also save a
1434 * copy of the pointers since the transmit list fragment pointers are
1435 * physical addresses.
1436 */
1437
1438 static void
1439 wb_start(ifp)
1440 struct ifnet *ifp;
1441 {
1442 struct wb_softc *sc;
1443
1444 sc = ifp->if_softc;
1445 WB_LOCK(sc);
1446 wb_start_locked(ifp);
1447 WB_UNLOCK(sc);
1448 }
1449
1450 static void
1451 wb_start_locked(ifp)
1452 struct ifnet *ifp;
1453 {
1454 struct wb_softc *sc;
1455 struct mbuf *m_head = NULL;
1456 struct wb_chain *cur_tx = NULL, *start_tx;
1457
1458 sc = ifp->if_softc;
1459 WB_LOCK_ASSERT(sc);
1460
1461 /*
1462 * Check for an available queue slot. If there are none,
1463 * punt.
1464 */
1465 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1466 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1467 return;
1468 }
1469
1470 start_tx = sc->wb_cdata.wb_tx_free;
1471
1472 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1473 IF_DEQUEUE(&ifp->if_snd, m_head);
1474 if (m_head == NULL)
1475 break;
1476
1477 /* Pick a descriptor off the free list. */
1478 cur_tx = sc->wb_cdata.wb_tx_free;
1479 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1480
1481 /* Pack the data into the descriptor. */
1482 wb_encap(sc, cur_tx, m_head);
1483
1484 if (cur_tx != start_tx)
1485 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1486
1487 /*
1488 * If there's a BPF listener, bounce a copy of this frame
1489 * to him.
1490 */
1491 BPF_MTAP(ifp, cur_tx->wb_mbuf);
1492 }
1493
1494 /*
1495 * If there are no packets queued, bail.
1496 */
1497 if (cur_tx == NULL)
1498 return;
1499
1500 /*
1501 * Place the request for the upload interrupt
1502 * in the last descriptor in the chain. This way, if
1503 * we're chaining several packets at once, we'll only
1504 * get an interupt once for the whole chain rather than
1505 * once for each packet.
1506 */
1507 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1508 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1509 sc->wb_cdata.wb_tx_tail = cur_tx;
1510
1511 if (sc->wb_cdata.wb_tx_head == NULL) {
1512 sc->wb_cdata.wb_tx_head = start_tx;
1513 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1514 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1515 } else {
1516 /*
1517 * We need to distinguish between the case where
1518 * the own bit is clear because the chip cleared it
1519 * and where the own bit is clear because we haven't
1520 * set it yet. The magic value WB_UNSET is just some
1521 * ramdomly chosen number which doesn't have the own
1522 * bit set. When we actually transmit the frame, the
1523 * status word will have _only_ the own bit set, so
1524 * the txeoc handler will be able to tell if it needs
1525 * to initiate another transmission to flush out pending
1526 * frames.
1527 */
1528 WB_TXOWN(start_tx) = WB_UNSENT;
1529 }
1530
1531 /*
1532 * Set a timeout in case the chip goes out to lunch.
1533 */
1534 ifp->if_timer = 5;
1535
1536 return;
1537 }
1538
1539 static void
1540 wb_init(xsc)
1541 void *xsc;
1542 {
1543 struct wb_softc *sc = xsc;
1544
1545 WB_LOCK(sc);
1546 wb_init_locked(sc);
1547 WB_UNLOCK(sc);
1548 }
1549
1550 static void
1551 wb_init_locked(sc)
1552 struct wb_softc *sc;
1553 {
1554 struct ifnet *ifp = sc->wb_ifp;
1555 int i;
1556 struct mii_data *mii;
1557
1558 WB_LOCK_ASSERT(sc);
1559 mii = device_get_softc(sc->wb_miibus);
1560
1561 /*
1562 * Cancel pending I/O and free all RX/TX buffers.
1563 */
1564 wb_stop(sc);
1565 wb_reset(sc);
1566
1567 sc->wb_txthresh = WB_TXTHRESH_INIT;
1568
1569 /*
1570 * Set cache alignment and burst length.
1571 */
1572 #ifdef foo
1573 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1574 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1575 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1576 #endif
1577
1578 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION);
1579 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
1580 switch(sc->wb_cachesize) {
1581 case 32:
1582 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
1583 break;
1584 case 16:
1585 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
1586 break;
1587 case 8:
1588 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
1589 break;
1590 case 0:
1591 default:
1592 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
1593 break;
1594 }
1595
1596 /* This doesn't tend to work too well at 100Mbps. */
1597 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1598
1599 /* Init our MAC address */
1600 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1601 CSR_WRITE_1(sc, WB_NODE0 + i, IFP2ENADDR(sc->wb_ifp)[i]);
1602 }
1603
1604 /* Init circular RX list. */
1605 if (wb_list_rx_init(sc) == ENOBUFS) {
1606 if_printf(ifp,
1607 "initialization failed: no memory for rx buffers\n");
1608 wb_stop(sc);
1609 return;
1610 }
1611
1612 /* Init TX descriptors. */
1613 wb_list_tx_init(sc);
1614
1615 /* If we want promiscuous mode, set the allframes bit. */
1616 if (ifp->if_flags & IFF_PROMISC) {
1617 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1618 } else {
1619 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1620 }
1621
1622 /*
1623 * Set capture broadcast bit to capture broadcast frames.
1624 */
1625 if (ifp->if_flags & IFF_BROADCAST) {
1626 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1627 } else {
1628 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1629 }
1630
1631 /*
1632 * Program the multicast filter, if necessary.
1633 */
1634 wb_setmulti(sc);
1635
1636 /*
1637 * Load the address of the RX list.
1638 */
1639 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1640 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1641
1642 /*
1643 * Enable interrupts.
1644 */
1645 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1646 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1647
1648 /* Enable receiver and transmitter. */
1649 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1650 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1651
1652 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1653 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1654 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1655
1656 mii_mediachg(mii);
1657
1658 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1659 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1660
1661 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc);
1662
1663 return;
1664 }
1665
1666 /*
1667 * Set media options.
1668 */
1669 static int
1670 wb_ifmedia_upd(ifp)
1671 struct ifnet *ifp;
1672 {
1673 struct wb_softc *sc;
1674
1675 sc = ifp->if_softc;
1676
1677 WB_LOCK(sc);
1678 if (ifp->if_flags & IFF_UP)
1679 wb_init_locked(sc);
1680 WB_UNLOCK(sc);
1681
1682 return(0);
1683 }
1684
1685 /*
1686 * Report current media status.
1687 */
1688 static void
1689 wb_ifmedia_sts(ifp, ifmr)
1690 struct ifnet *ifp;
1691 struct ifmediareq *ifmr;
1692 {
1693 struct wb_softc *sc;
1694 struct mii_data *mii;
1695
1696 sc = ifp->if_softc;
1697
1698 WB_LOCK(sc);
1699 mii = device_get_softc(sc->wb_miibus);
1700
1701 mii_pollstat(mii);
1702 ifmr->ifm_active = mii->mii_media_active;
1703 ifmr->ifm_status = mii->mii_media_status;
1704 WB_UNLOCK(sc);
1705
1706 return;
1707 }
1708
1709 static int
1710 wb_ioctl(ifp, command, data)
1711 struct ifnet *ifp;
1712 u_long command;
1713 caddr_t data;
1714 {
1715 struct wb_softc *sc = ifp->if_softc;
1716 struct mii_data *mii;
1717 struct ifreq *ifr = (struct ifreq *) data;
1718 int error = 0;
1719
1720 switch(command) {
1721 case SIOCSIFFLAGS:
1722 WB_LOCK(sc);
1723 if (ifp->if_flags & IFF_UP) {
1724 wb_init_locked(sc);
1725 } else {
1726 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1727 wb_stop(sc);
1728 }
1729 WB_UNLOCK(sc);
1730 error = 0;
1731 break;
1732 case SIOCADDMULTI:
1733 case SIOCDELMULTI:
1734 WB_LOCK(sc);
1735 wb_setmulti(sc);
1736 WB_UNLOCK(sc);
1737 error = 0;
1738 break;
1739 case SIOCGIFMEDIA:
1740 case SIOCSIFMEDIA:
1741 mii = device_get_softc(sc->wb_miibus);
1742 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1743 break;
1744 default:
1745 error = ether_ioctl(ifp, command, data);
1746 break;
1747 }
1748
1749 return(error);
1750 }
1751
1752 static void
1753 wb_watchdog(ifp)
1754 struct ifnet *ifp;
1755 {
1756 struct wb_softc *sc;
1757
1758 sc = ifp->if_softc;
1759
1760 WB_LOCK(sc);
1761 ifp->if_oerrors++;
1762 if_printf(ifp, "watchdog timeout\n");
1763 #ifdef foo
1764 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1765 if_printf(ifp, "no carrier - transceiver cable problem?\n");
1766 #endif
1767 wb_stop(sc);
1768 wb_reset(sc);
1769 wb_init_locked(sc);
1770
1771 if (ifp->if_snd.ifq_head != NULL)
1772 wb_start_locked(ifp);
1773 WB_UNLOCK(sc);
1774
1775 return;
1776 }
1777
1778 /*
1779 * Stop the adapter and free any mbufs allocated to the
1780 * RX and TX lists.
1781 */
1782 static void
1783 wb_stop(sc)
1784 struct wb_softc *sc;
1785 {
1786 register int i;
1787 struct ifnet *ifp;
1788
1789 WB_LOCK_ASSERT(sc);
1790 ifp = sc->wb_ifp;
1791 ifp->if_timer = 0;
1792
1793 callout_stop(&sc->wb_stat_callout);
1794
1795 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
1796 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1797 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
1798 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
1799
1800 /*
1801 * Free data in the RX lists.
1802 */
1803 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1804 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
1805 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
1806 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
1807 }
1808 }
1809 bzero((char *)&sc->wb_ldata->wb_rx_list,
1810 sizeof(sc->wb_ldata->wb_rx_list));
1811
1812 /*
1813 * Free the TX list buffers.
1814 */
1815 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1816 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
1817 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
1818 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
1819 }
1820 }
1821
1822 bzero((char *)&sc->wb_ldata->wb_tx_list,
1823 sizeof(sc->wb_ldata->wb_tx_list));
1824
1825 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1826
1827 return;
1828 }
1829
1830 /*
1831 * Stop all chip I/O so that the kernel's probe routines don't
1832 * get confused by errant DMAs when rebooting.
1833 */
1834 static void
1835 wb_shutdown(dev)
1836 device_t dev;
1837 {
1838 struct wb_softc *sc;
1839
1840 sc = device_get_softc(dev);
1841
1842 WB_LOCK(sc);
1843 wb_stop(sc);
1844 WB_UNLOCK(sc);
1845
1846 return;
1847 }
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