The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_wb.c

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    1 /*-
    2  * Copyright (c) 1997, 1998
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  */
   32 
   33 #include <sys/cdefs.h>
   34 __FBSDID("$FreeBSD$");
   35 
   36 /*
   37  * Winbond fast ethernet PCI NIC driver
   38  *
   39  * Supports various cheap network adapters based on the Winbond W89C840F
   40  * fast ethernet controller chip. This includes adapters manufactured by
   41  * Winbond itself and some made by Linksys.
   42  *
   43  * Written by Bill Paul <wpaul@ctr.columbia.edu>
   44  * Electrical Engineering Department
   45  * Columbia University, New York City
   46  */
   47 /*
   48  * The Winbond W89C840F chip is a bus master; in some ways it resembles
   49  * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
   50  * one major difference which is that while the registers do many of
   51  * the same things as a tulip adapter, the offsets are different: where
   52  * tulip registers are typically spaced 8 bytes apart, the Winbond
   53  * registers are spaced 4 bytes apart. The receiver filter is also
   54  * programmed differently.
   55  * 
   56  * Like the tulip, the Winbond chip uses small descriptors containing
   57  * a status word, a control word and 32-bit areas that can either be used
   58  * to point to two external data blocks, or to point to a single block
   59  * and another descriptor in a linked list. Descriptors can be grouped
   60  * together in blocks to form fixed length rings or can be chained
   61  * together in linked lists. A single packet may be spread out over
   62  * several descriptors if necessary.
   63  *
   64  * For the receive ring, this driver uses a linked list of descriptors,
   65  * each pointing to a single mbuf cluster buffer, which us large enough
   66  * to hold an entire packet. The link list is looped back to created a
   67  * closed ring.
   68  *
   69  * For transmission, the driver creates a linked list of 'super descriptors'
   70  * which each contain several individual descriptors linked toghether.
   71  * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
   72  * abuse as fragment pointers. This allows us to use a buffer managment
   73  * scheme very similar to that used in the ThunderLAN and Etherlink XL
   74  * drivers.
   75  *
   76  * Autonegotiation is performed using the external PHY via the MII bus.
   77  * The sample boards I have all use a Davicom PHY.
   78  *
   79  * Note: the author of the Linux driver for the Winbond chip alludes
   80  * to some sort of flaw in the chip's design that seems to mandate some
   81  * drastic workaround which signigicantly impairs transmit performance.
   82  * I have no idea what he's on about: transmit performance with all
   83  * three of my test boards seems fine.
   84  */
   85 
   86 #include <sys/param.h>
   87 #include <sys/systm.h>
   88 #include <sys/sockio.h>
   89 #include <sys/mbuf.h>
   90 #include <sys/malloc.h>
   91 #include <sys/module.h>
   92 #include <sys/kernel.h>
   93 #include <sys/socket.h>
   94 #include <sys/queue.h>
   95 
   96 #include <net/if.h>
   97 #include <net/if_arp.h>
   98 #include <net/ethernet.h>
   99 #include <net/if_dl.h>
  100 #include <net/if_media.h>
  101 #include <net/if_types.h>
  102 
  103 #include <net/bpf.h>
  104 
  105 #include <vm/vm.h>              /* for vtophys */
  106 #include <vm/pmap.h>            /* for vtophys */
  107 #include <machine/bus.h>
  108 #include <machine/resource.h>
  109 #include <sys/bus.h>
  110 #include <sys/rman.h>
  111 
  112 #include <dev/pci/pcireg.h>
  113 #include <dev/pci/pcivar.h>
  114 
  115 #include <dev/mii/mii.h>
  116 #include <dev/mii/miivar.h>
  117 
  118 /* "device miibus" required.  See GENERIC if you get errors here. */
  119 #include "miibus_if.h"
  120 
  121 #define WB_USEIOSPACE
  122 
  123 #include <pci/if_wbreg.h>
  124 
  125 MODULE_DEPEND(wb, pci, 1, 1, 1);
  126 MODULE_DEPEND(wb, ether, 1, 1, 1);
  127 MODULE_DEPEND(wb, miibus, 1, 1, 1);
  128 
  129 /*
  130  * Various supported device vendors/types and their names.
  131  */
  132 static struct wb_type wb_devs[] = {
  133         { WB_VENDORID, WB_DEVICEID_840F,
  134                 "Winbond W89C840F 10/100BaseTX" },
  135         { CP_VENDORID, CP_DEVICEID_RL100,
  136                 "Compex RL100-ATX 10/100baseTX" },
  137         { 0, 0, NULL }
  138 };
  139 
  140 static int wb_probe(device_t);
  141 static int wb_attach(device_t);
  142 static int wb_detach(device_t);
  143 
  144 static void wb_bfree(void *addr, void *args);
  145 static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *,
  146                 struct mbuf *);
  147 static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *);
  148 
  149 static void wb_rxeof(struct wb_softc *);
  150 static void wb_rxeoc(struct wb_softc *);
  151 static void wb_txeof(struct wb_softc *);
  152 static void wb_txeoc(struct wb_softc *);
  153 static void wb_intr(void *);
  154 static void wb_tick(void *);
  155 static void wb_start(struct ifnet *);
  156 static void wb_start_locked(struct ifnet *);
  157 static int wb_ioctl(struct ifnet *, u_long, caddr_t);
  158 static void wb_init(void *);
  159 static void wb_init_locked(struct wb_softc *);
  160 static void wb_stop(struct wb_softc *);
  161 static void wb_watchdog(struct ifnet *);
  162 static void wb_shutdown(device_t);
  163 static int wb_ifmedia_upd(struct ifnet *);
  164 static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  165 
  166 static void wb_eeprom_putbyte(struct wb_softc *, int);
  167 static void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *);
  168 static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int);
  169 static void wb_mii_sync(struct wb_softc *);
  170 static void wb_mii_send(struct wb_softc *, u_int32_t, int);
  171 static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *);
  172 static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *);
  173 
  174 static void wb_setcfg(struct wb_softc *, u_int32_t);
  175 static void wb_setmulti(struct wb_softc *);
  176 static void wb_reset(struct wb_softc *);
  177 static void wb_fixmedia(struct wb_softc *);
  178 static int wb_list_rx_init(struct wb_softc *);
  179 static int wb_list_tx_init(struct wb_softc *);
  180 
  181 static int wb_miibus_readreg(device_t, int, int);
  182 static int wb_miibus_writereg(device_t, int, int, int);
  183 static void wb_miibus_statchg(device_t);
  184 
  185 #ifdef WB_USEIOSPACE
  186 #define WB_RES                  SYS_RES_IOPORT
  187 #define WB_RID                  WB_PCI_LOIO
  188 #else
  189 #define WB_RES                  SYS_RES_MEMORY
  190 #define WB_RID                  WB_PCI_LOMEM
  191 #endif
  192 
  193 static device_method_t wb_methods[] = {
  194         /* Device interface */
  195         DEVMETHOD(device_probe,         wb_probe),
  196         DEVMETHOD(device_attach,        wb_attach),
  197         DEVMETHOD(device_detach,        wb_detach),
  198         DEVMETHOD(device_shutdown,      wb_shutdown),
  199 
  200         /* bus interface, for miibus */
  201         DEVMETHOD(bus_print_child,      bus_generic_print_child),
  202         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
  203 
  204         /* MII interface */
  205         DEVMETHOD(miibus_readreg,       wb_miibus_readreg),
  206         DEVMETHOD(miibus_writereg,      wb_miibus_writereg),
  207         DEVMETHOD(miibus_statchg,       wb_miibus_statchg),
  208         { 0, 0 }
  209 };
  210 
  211 static driver_t wb_driver = {
  212         "wb",
  213         wb_methods,
  214         sizeof(struct wb_softc)
  215 };
  216 
  217 static devclass_t wb_devclass;
  218 
  219 DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0);
  220 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
  221 
  222 #define WB_SETBIT(sc, reg, x)                           \
  223         CSR_WRITE_4(sc, reg,                            \
  224                 CSR_READ_4(sc, reg) | (x))
  225 
  226 #define WB_CLRBIT(sc, reg, x)                           \
  227         CSR_WRITE_4(sc, reg,                            \
  228                 CSR_READ_4(sc, reg) & ~(x))
  229 
  230 #define SIO_SET(x)                                      \
  231         CSR_WRITE_4(sc, WB_SIO,                         \
  232                 CSR_READ_4(sc, WB_SIO) | (x))
  233 
  234 #define SIO_CLR(x)                                      \
  235         CSR_WRITE_4(sc, WB_SIO,                         \
  236                 CSR_READ_4(sc, WB_SIO) & ~(x))
  237 
  238 /*
  239  * Send a read command and address to the EEPROM, check for ACK.
  240  */
  241 static void
  242 wb_eeprom_putbyte(sc, addr)
  243         struct wb_softc         *sc;
  244         int                     addr;
  245 {
  246         register int            d, i;
  247 
  248         d = addr | WB_EECMD_READ;
  249 
  250         /*
  251          * Feed in each bit and stobe the clock.
  252          */
  253         for (i = 0x400; i; i >>= 1) {
  254                 if (d & i) {
  255                         SIO_SET(WB_SIO_EE_DATAIN);
  256                 } else {
  257                         SIO_CLR(WB_SIO_EE_DATAIN);
  258                 }
  259                 DELAY(100);
  260                 SIO_SET(WB_SIO_EE_CLK);
  261                 DELAY(150);
  262                 SIO_CLR(WB_SIO_EE_CLK);
  263                 DELAY(100);
  264         }
  265 
  266         return;
  267 }
  268 
  269 /*
  270  * Read a word of data stored in the EEPROM at address 'addr.'
  271  */
  272 static void
  273 wb_eeprom_getword(sc, addr, dest)
  274         struct wb_softc         *sc;
  275         int                     addr;
  276         u_int16_t               *dest;
  277 {
  278         register int            i;
  279         u_int16_t               word = 0;
  280 
  281         /* Enter EEPROM access mode. */
  282         CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
  283 
  284         /*
  285          * Send address of word we want to read.
  286          */
  287         wb_eeprom_putbyte(sc, addr);
  288 
  289         CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
  290 
  291         /*
  292          * Start reading bits from EEPROM.
  293          */
  294         for (i = 0x8000; i; i >>= 1) {
  295                 SIO_SET(WB_SIO_EE_CLK);
  296                 DELAY(100);
  297                 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
  298                         word |= i;
  299                 SIO_CLR(WB_SIO_EE_CLK);
  300                 DELAY(100);
  301         }
  302 
  303         /* Turn off EEPROM access mode. */
  304         CSR_WRITE_4(sc, WB_SIO, 0);
  305 
  306         *dest = word;
  307 
  308         return;
  309 }
  310 
  311 /*
  312  * Read a sequence of words from the EEPROM.
  313  */
  314 static void
  315 wb_read_eeprom(sc, dest, off, cnt, swap)
  316         struct wb_softc         *sc;
  317         caddr_t                 dest;
  318         int                     off;
  319         int                     cnt;
  320         int                     swap;
  321 {
  322         int                     i;
  323         u_int16_t               word = 0, *ptr;
  324 
  325         for (i = 0; i < cnt; i++) {
  326                 wb_eeprom_getword(sc, off + i, &word);
  327                 ptr = (u_int16_t *)(dest + (i * 2));
  328                 if (swap)
  329                         *ptr = ntohs(word);
  330                 else
  331                         *ptr = word;
  332         }
  333 
  334         return;
  335 }
  336 
  337 /*
  338  * Sync the PHYs by setting data bit and strobing the clock 32 times.
  339  */
  340 static void
  341 wb_mii_sync(sc)
  342         struct wb_softc         *sc;
  343 {
  344         register int            i;
  345 
  346         SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN);
  347 
  348         for (i = 0; i < 32; i++) {
  349                 SIO_SET(WB_SIO_MII_CLK);
  350                 DELAY(1);
  351                 SIO_CLR(WB_SIO_MII_CLK);
  352                 DELAY(1);
  353         }
  354 
  355         return;
  356 }
  357 
  358 /*
  359  * Clock a series of bits through the MII.
  360  */
  361 static void
  362 wb_mii_send(sc, bits, cnt)
  363         struct wb_softc         *sc;
  364         u_int32_t               bits;
  365         int                     cnt;
  366 {
  367         int                     i;
  368 
  369         SIO_CLR(WB_SIO_MII_CLK);
  370 
  371         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
  372                 if (bits & i) {
  373                         SIO_SET(WB_SIO_MII_DATAIN);
  374                 } else {
  375                         SIO_CLR(WB_SIO_MII_DATAIN);
  376                 }
  377                 DELAY(1);
  378                 SIO_CLR(WB_SIO_MII_CLK);
  379                 DELAY(1);
  380                 SIO_SET(WB_SIO_MII_CLK);
  381         }
  382 }
  383 
  384 /*
  385  * Read an PHY register through the MII.
  386  */
  387 static int
  388 wb_mii_readreg(sc, frame)
  389         struct wb_softc         *sc;
  390         struct wb_mii_frame     *frame;
  391         
  392 {
  393         int                     i, ack;
  394 
  395         /*
  396          * Set up frame for RX.
  397          */
  398         frame->mii_stdelim = WB_MII_STARTDELIM;
  399         frame->mii_opcode = WB_MII_READOP;
  400         frame->mii_turnaround = 0;
  401         frame->mii_data = 0;
  402         
  403         CSR_WRITE_4(sc, WB_SIO, 0);
  404 
  405         /*
  406          * Turn on data xmit.
  407          */
  408         SIO_SET(WB_SIO_MII_DIR);
  409 
  410         wb_mii_sync(sc);
  411 
  412         /*
  413          * Send command/address info.
  414          */
  415         wb_mii_send(sc, frame->mii_stdelim, 2);
  416         wb_mii_send(sc, frame->mii_opcode, 2);
  417         wb_mii_send(sc, frame->mii_phyaddr, 5);
  418         wb_mii_send(sc, frame->mii_regaddr, 5);
  419 
  420         /* Idle bit */
  421         SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN));
  422         DELAY(1);
  423         SIO_SET(WB_SIO_MII_CLK);
  424         DELAY(1);
  425 
  426         /* Turn off xmit. */
  427         SIO_CLR(WB_SIO_MII_DIR);
  428         /* Check for ack */
  429         SIO_CLR(WB_SIO_MII_CLK);
  430         DELAY(1);
  431         ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
  432         SIO_SET(WB_SIO_MII_CLK);
  433         DELAY(1);
  434         SIO_CLR(WB_SIO_MII_CLK);
  435         DELAY(1);
  436         SIO_SET(WB_SIO_MII_CLK);
  437         DELAY(1);
  438 
  439         /*
  440          * Now try reading data bits. If the ack failed, we still
  441          * need to clock through 16 cycles to keep the PHY(s) in sync.
  442          */
  443         if (ack) {
  444                 for(i = 0; i < 16; i++) {
  445                         SIO_CLR(WB_SIO_MII_CLK);
  446                         DELAY(1);
  447                         SIO_SET(WB_SIO_MII_CLK);
  448                         DELAY(1);
  449                 }
  450                 goto fail;
  451         }
  452 
  453         for (i = 0x8000; i; i >>= 1) {
  454                 SIO_CLR(WB_SIO_MII_CLK);
  455                 DELAY(1);
  456                 if (!ack) {
  457                         if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
  458                                 frame->mii_data |= i;
  459                         DELAY(1);
  460                 }
  461                 SIO_SET(WB_SIO_MII_CLK);
  462                 DELAY(1);
  463         }
  464 
  465 fail:
  466 
  467         SIO_CLR(WB_SIO_MII_CLK);
  468         DELAY(1);
  469         SIO_SET(WB_SIO_MII_CLK);
  470         DELAY(1);
  471 
  472         if (ack)
  473                 return(1);
  474         return(0);
  475 }
  476 
  477 /*
  478  * Write to a PHY register through the MII.
  479  */
  480 static int
  481 wb_mii_writereg(sc, frame)
  482         struct wb_softc         *sc;
  483         struct wb_mii_frame     *frame;
  484         
  485 {
  486 
  487         /*
  488          * Set up frame for TX.
  489          */
  490 
  491         frame->mii_stdelim = WB_MII_STARTDELIM;
  492         frame->mii_opcode = WB_MII_WRITEOP;
  493         frame->mii_turnaround = WB_MII_TURNAROUND;
  494         
  495         /*
  496          * Turn on data output.
  497          */
  498         SIO_SET(WB_SIO_MII_DIR);
  499 
  500         wb_mii_sync(sc);
  501 
  502         wb_mii_send(sc, frame->mii_stdelim, 2);
  503         wb_mii_send(sc, frame->mii_opcode, 2);
  504         wb_mii_send(sc, frame->mii_phyaddr, 5);
  505         wb_mii_send(sc, frame->mii_regaddr, 5);
  506         wb_mii_send(sc, frame->mii_turnaround, 2);
  507         wb_mii_send(sc, frame->mii_data, 16);
  508 
  509         /* Idle bit. */
  510         SIO_SET(WB_SIO_MII_CLK);
  511         DELAY(1);
  512         SIO_CLR(WB_SIO_MII_CLK);
  513         DELAY(1);
  514 
  515         /*
  516          * Turn off xmit.
  517          */
  518         SIO_CLR(WB_SIO_MII_DIR);
  519 
  520         return(0);
  521 }
  522 
  523 static int
  524 wb_miibus_readreg(dev, phy, reg)
  525         device_t                dev;
  526         int                     phy, reg;
  527 {
  528         struct wb_softc         *sc;
  529         struct wb_mii_frame     frame;
  530 
  531         sc = device_get_softc(dev);
  532 
  533         bzero((char *)&frame, sizeof(frame));
  534 
  535         frame.mii_phyaddr = phy;
  536         frame.mii_regaddr = reg;
  537         wb_mii_readreg(sc, &frame);
  538 
  539         return(frame.mii_data);
  540 }
  541 
  542 static int
  543 wb_miibus_writereg(dev, phy, reg, data)
  544         device_t                dev;
  545         int                     phy, reg, data;
  546 {
  547         struct wb_softc         *sc;
  548         struct wb_mii_frame     frame;
  549 
  550         sc = device_get_softc(dev);
  551 
  552         bzero((char *)&frame, sizeof(frame));
  553 
  554         frame.mii_phyaddr = phy;
  555         frame.mii_regaddr = reg;
  556         frame.mii_data = data;
  557 
  558         wb_mii_writereg(sc, &frame);
  559 
  560         return(0);
  561 }
  562 
  563 static void
  564 wb_miibus_statchg(dev)
  565         device_t                dev;
  566 {
  567         struct wb_softc         *sc;
  568         struct mii_data         *mii;
  569 
  570         sc = device_get_softc(dev);
  571         mii = device_get_softc(sc->wb_miibus);
  572         wb_setcfg(sc, mii->mii_media_active);
  573 
  574         return;
  575 }
  576 
  577 /*
  578  * Program the 64-bit multicast hash filter.
  579  */
  580 static void
  581 wb_setmulti(sc)
  582         struct wb_softc         *sc;
  583 {
  584         struct ifnet            *ifp;
  585         int                     h = 0;
  586         u_int32_t               hashes[2] = { 0, 0 };
  587         struct ifmultiaddr      *ifma;
  588         u_int32_t               rxfilt;
  589         int                     mcnt = 0;
  590 
  591         ifp = sc->wb_ifp;
  592 
  593         rxfilt = CSR_READ_4(sc, WB_NETCFG);
  594 
  595         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
  596                 rxfilt |= WB_NETCFG_RX_MULTI;
  597                 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
  598                 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
  599                 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
  600                 return;
  601         }
  602 
  603         /* first, zot all the existing hash bits */
  604         CSR_WRITE_4(sc, WB_MAR0, 0);
  605         CSR_WRITE_4(sc, WB_MAR1, 0);
  606 
  607         /* now program new ones */
  608         IF_ADDR_LOCK(ifp);
  609         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
  610                 if (ifma->ifma_addr->sa_family != AF_LINK)
  611                         continue;
  612                 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
  613                     ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
  614                 if (h < 32)
  615                         hashes[0] |= (1 << h);
  616                 else
  617                         hashes[1] |= (1 << (h - 32));
  618                 mcnt++;
  619         }
  620         IF_ADDR_UNLOCK(ifp);
  621 
  622         if (mcnt)
  623                 rxfilt |= WB_NETCFG_RX_MULTI;
  624         else
  625                 rxfilt &= ~WB_NETCFG_RX_MULTI;
  626 
  627         CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
  628         CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
  629         CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
  630 
  631         return;
  632 }
  633 
  634 /*
  635  * The Winbond manual states that in order to fiddle with the
  636  * 'full-duplex' and '100Mbps' bits in the netconfig register, we
  637  * first have to put the transmit and/or receive logic in the idle state.
  638  */
  639 static void
  640 wb_setcfg(sc, media)
  641         struct wb_softc         *sc;
  642         u_int32_t               media;
  643 {
  644         int                     i, restart = 0;
  645 
  646         if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
  647                 restart = 1;
  648                 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
  649 
  650                 for (i = 0; i < WB_TIMEOUT; i++) {
  651                         DELAY(10);
  652                         if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
  653                                 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
  654                                 break;
  655                 }
  656 
  657                 if (i == WB_TIMEOUT)
  658                         device_printf(sc->wb_dev,
  659                             "failed to force tx and rx to idle state\n");
  660         }
  661 
  662         if (IFM_SUBTYPE(media) == IFM_10_T)
  663                 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
  664         else
  665                 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
  666 
  667         if ((media & IFM_GMASK) == IFM_FDX)
  668                 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
  669         else
  670                 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
  671 
  672         if (restart)
  673                 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
  674 
  675         return;
  676 }
  677 
  678 static void
  679 wb_reset(sc)
  680         struct wb_softc         *sc;
  681 {
  682         register int            i;
  683         struct mii_data         *mii;
  684 
  685         CSR_WRITE_4(sc, WB_NETCFG, 0);
  686         CSR_WRITE_4(sc, WB_BUSCTL, 0);
  687         CSR_WRITE_4(sc, WB_TXADDR, 0);
  688         CSR_WRITE_4(sc, WB_RXADDR, 0);
  689 
  690         WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
  691         WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
  692 
  693         for (i = 0; i < WB_TIMEOUT; i++) {
  694                 DELAY(10);
  695                 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
  696                         break;
  697         }
  698         if (i == WB_TIMEOUT)
  699                 device_printf(sc->wb_dev, "reset never completed!\n");
  700 
  701         /* Wait a little while for the chip to get its brains in order. */
  702         DELAY(1000);
  703 
  704         if (sc->wb_miibus == NULL)
  705                 return;
  706 
  707         mii = device_get_softc(sc->wb_miibus);
  708         if (mii == NULL)
  709                 return;
  710 
  711         if (mii->mii_instance) {
  712                 struct mii_softc        *miisc;
  713                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
  714                         mii_phy_reset(miisc);
  715         }
  716 
  717         return;
  718 }
  719 
  720 static void
  721 wb_fixmedia(sc)
  722         struct wb_softc         *sc;
  723 {
  724         struct mii_data         *mii = NULL;
  725         struct ifnet            *ifp;
  726         u_int32_t               media;
  727 
  728         if (sc->wb_miibus == NULL)
  729                 return;
  730 
  731         mii = device_get_softc(sc->wb_miibus);
  732         ifp = sc->wb_ifp;
  733 
  734         mii_pollstat(mii);
  735         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
  736                 media = mii->mii_media_active & ~IFM_10_T;
  737                 media |= IFM_100_TX;
  738         } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
  739                 media = mii->mii_media_active & ~IFM_100_TX;
  740                 media |= IFM_10_T;
  741         } else
  742                 return;
  743 
  744         ifmedia_set(&mii->mii_media, media);
  745 
  746         return;
  747 }
  748 
  749 /*
  750  * Probe for a Winbond chip. Check the PCI vendor and device
  751  * IDs against our list and return a device name if we find a match.
  752  */
  753 static int
  754 wb_probe(dev)
  755         device_t                dev;
  756 {
  757         struct wb_type          *t;
  758 
  759         t = wb_devs;
  760 
  761         while(t->wb_name != NULL) {
  762                 if ((pci_get_vendor(dev) == t->wb_vid) &&
  763                     (pci_get_device(dev) == t->wb_did)) {
  764                         device_set_desc(dev, t->wb_name);
  765                         return (BUS_PROBE_DEFAULT);
  766                 }
  767                 t++;
  768         }
  769 
  770         return(ENXIO);
  771 }
  772 
  773 /*
  774  * Attach the interface. Allocate softc structures, do ifmedia
  775  * setup and ethernet/BPF attach.
  776  */
  777 static int
  778 wb_attach(dev)
  779         device_t                dev;
  780 {
  781         u_char                  eaddr[ETHER_ADDR_LEN];
  782         struct wb_softc         *sc;
  783         struct ifnet            *ifp;
  784         int                     error = 0, rid;
  785 
  786         sc = device_get_softc(dev);
  787         sc->wb_dev = dev;
  788 
  789         mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
  790             MTX_DEF);
  791         callout_init_mtx(&sc->wb_stat_callout, &sc->wb_mtx, 0);
  792 
  793         /*
  794          * Map control/status registers.
  795          */
  796         pci_enable_busmaster(dev);
  797 
  798         rid = WB_RID;
  799         sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE);
  800 
  801         if (sc->wb_res == NULL) {
  802                 device_printf(dev, "couldn't map ports/memory\n");
  803                 error = ENXIO;
  804                 goto fail;
  805         }
  806 
  807         sc->wb_btag = rman_get_bustag(sc->wb_res);
  808         sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
  809 
  810         /* Allocate interrupt */
  811         rid = 0;
  812         sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
  813             RF_SHAREABLE | RF_ACTIVE);
  814 
  815         if (sc->wb_irq == NULL) {
  816                 device_printf(dev, "couldn't map interrupt\n");
  817                 error = ENXIO;
  818                 goto fail;
  819         }
  820 
  821         /* Save the cache line size. */
  822         sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
  823 
  824         /* Reset the adapter. */
  825         wb_reset(sc);
  826 
  827         /*
  828          * Get station address from the EEPROM.
  829          */
  830         wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0);
  831 
  832         sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
  833             M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
  834 
  835         if (sc->wb_ldata == NULL) {
  836                 device_printf(dev, "no memory for list buffers!\n");
  837                 error = ENXIO;
  838                 goto fail;
  839         }
  840 
  841         bzero(sc->wb_ldata, sizeof(struct wb_list_data));
  842 
  843         ifp = sc->wb_ifp = if_alloc(IFT_ETHER);
  844         if (ifp == NULL) {
  845                 device_printf(dev, "can not if_alloc()\n");
  846                 error = ENOSPC;
  847                 goto fail;
  848         }
  849         ifp->if_softc = sc;
  850         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
  851         ifp->if_mtu = ETHERMTU;
  852         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
  853         ifp->if_ioctl = wb_ioctl;
  854         ifp->if_start = wb_start;
  855         ifp->if_watchdog = wb_watchdog;
  856         ifp->if_init = wb_init;
  857         ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1;
  858 
  859         /*
  860          * Do MII setup.
  861          */
  862         if (mii_phy_probe(dev, &sc->wb_miibus,
  863             wb_ifmedia_upd, wb_ifmedia_sts)) {
  864                 error = ENXIO;
  865                 goto fail;
  866         }
  867 
  868         /*
  869          * Call MI attach routine.
  870          */
  871         ether_ifattach(ifp, eaddr);
  872 
  873         /* Hook interrupt last to avoid having to lock softc */
  874         error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET | INTR_MPSAFE,
  875             NULL, wb_intr, sc, &sc->wb_intrhand);
  876 
  877         if (error) {
  878                 device_printf(dev, "couldn't set up irq\n");
  879                 ether_ifdetach(ifp);
  880                 goto fail;
  881         }
  882 
  883 fail:
  884         if (error)
  885                 wb_detach(dev);
  886 
  887         return(error);
  888 }
  889 
  890 /*
  891  * Shutdown hardware and free up resources. This can be called any
  892  * time after the mutex has been initialized. It is called in both
  893  * the error case in attach and the normal detach case so it needs
  894  * to be careful about only freeing resources that have actually been
  895  * allocated.
  896  */
  897 static int
  898 wb_detach(dev)
  899         device_t                dev;
  900 {
  901         struct wb_softc         *sc;
  902         struct ifnet            *ifp;
  903 
  904         sc = device_get_softc(dev);
  905         KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized"));
  906         ifp = sc->wb_ifp;
  907 
  908         /* 
  909          * Delete any miibus and phy devices attached to this interface.
  910          * This should only be done if attach succeeded.
  911          */
  912         if (device_is_attached(dev)) {
  913                 WB_LOCK(sc);
  914                 wb_stop(sc);
  915                 WB_UNLOCK(sc);
  916                 callout_drain(&sc->wb_stat_callout);
  917                 ether_ifdetach(ifp);
  918         }
  919         if (sc->wb_miibus)
  920                 device_delete_child(dev, sc->wb_miibus);
  921         bus_generic_detach(dev);
  922 
  923         if (sc->wb_intrhand)
  924                 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
  925         if (sc->wb_irq)
  926                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
  927         if (sc->wb_res)
  928                 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
  929 
  930         if (ifp)
  931                 if_free(ifp);
  932 
  933         if (sc->wb_ldata) {
  934                 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8,
  935                     M_DEVBUF);
  936         }
  937 
  938         mtx_destroy(&sc->wb_mtx);
  939 
  940         return(0);
  941 }
  942 
  943 /*
  944  * Initialize the transmit descriptors.
  945  */
  946 static int
  947 wb_list_tx_init(sc)
  948         struct wb_softc         *sc;
  949 {
  950         struct wb_chain_data    *cd;
  951         struct wb_list_data     *ld;
  952         int                     i;
  953 
  954         cd = &sc->wb_cdata;
  955         ld = sc->wb_ldata;
  956 
  957         for (i = 0; i < WB_TX_LIST_CNT; i++) {
  958                 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
  959                 if (i == (WB_TX_LIST_CNT - 1)) {
  960                         cd->wb_tx_chain[i].wb_nextdesc =
  961                                 &cd->wb_tx_chain[0];
  962                 } else {
  963                         cd->wb_tx_chain[i].wb_nextdesc =
  964                                 &cd->wb_tx_chain[i + 1];
  965                 }
  966         }
  967 
  968         cd->wb_tx_free = &cd->wb_tx_chain[0];
  969         cd->wb_tx_tail = cd->wb_tx_head = NULL;
  970 
  971         return(0);
  972 }
  973 
  974 
  975 /*
  976  * Initialize the RX descriptors and allocate mbufs for them. Note that
  977  * we arrange the descriptors in a closed ring, so that the last descriptor
  978  * points back to the first.
  979  */
  980 static int
  981 wb_list_rx_init(sc)
  982         struct wb_softc         *sc;
  983 {
  984         struct wb_chain_data    *cd;
  985         struct wb_list_data     *ld;
  986         int                     i;
  987 
  988         cd = &sc->wb_cdata;
  989         ld = sc->wb_ldata;
  990 
  991         for (i = 0; i < WB_RX_LIST_CNT; i++) {
  992                 cd->wb_rx_chain[i].wb_ptr =
  993                         (struct wb_desc *)&ld->wb_rx_list[i];
  994                 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i];
  995                 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
  996                         return(ENOBUFS);
  997                 if (i == (WB_RX_LIST_CNT - 1)) {
  998                         cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
  999                         ld->wb_rx_list[i].wb_next = 
 1000                                         vtophys(&ld->wb_rx_list[0]);
 1001                 } else {
 1002                         cd->wb_rx_chain[i].wb_nextdesc =
 1003                                         &cd->wb_rx_chain[i + 1];
 1004                         ld->wb_rx_list[i].wb_next =
 1005                                         vtophys(&ld->wb_rx_list[i + 1]);
 1006                 }
 1007         }
 1008 
 1009         cd->wb_rx_head = &cd->wb_rx_chain[0];
 1010 
 1011         return(0);
 1012 }
 1013 
 1014 static void
 1015 wb_bfree(buf, args)
 1016         void                    *buf;
 1017         void                    *args;
 1018 {
 1019         return;
 1020 }
 1021 
 1022 /*
 1023  * Initialize an RX descriptor and attach an MBUF cluster.
 1024  */
 1025 static int
 1026 wb_newbuf(sc, c, m)
 1027         struct wb_softc         *sc;
 1028         struct wb_chain_onefrag *c;
 1029         struct mbuf             *m;
 1030 {
 1031         struct mbuf             *m_new = NULL;
 1032 
 1033         if (m == NULL) {
 1034                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1035                 if (m_new == NULL)
 1036                         return(ENOBUFS);
 1037                 m_new->m_data = c->wb_buf;
 1038                 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES;
 1039                 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0,
 1040                     EXT_NET_DRV);
 1041         } else {
 1042                 m_new = m;
 1043                 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
 1044                 m_new->m_data = m_new->m_ext.ext_buf;
 1045         }
 1046 
 1047         m_adj(m_new, sizeof(u_int64_t));
 1048 
 1049         c->wb_mbuf = m_new;
 1050         c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
 1051         c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
 1052         c->wb_ptr->wb_status = WB_RXSTAT;
 1053 
 1054         return(0);
 1055 }
 1056 
 1057 /*
 1058  * A frame has been uploaded: pass the resulting mbuf chain up to
 1059  * the higher level protocols.
 1060  */
 1061 static void
 1062 wb_rxeof(sc)
 1063         struct wb_softc         *sc;
 1064 {
 1065         struct mbuf             *m = NULL;
 1066         struct ifnet            *ifp;
 1067         struct wb_chain_onefrag *cur_rx;
 1068         int                     total_len = 0;
 1069         u_int32_t               rxstat;
 1070 
 1071         WB_LOCK_ASSERT(sc);
 1072 
 1073         ifp = sc->wb_ifp;
 1074 
 1075         while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
 1076                                                         WB_RXSTAT_OWN)) {
 1077                 struct mbuf             *m0 = NULL;
 1078 
 1079                 cur_rx = sc->wb_cdata.wb_rx_head;
 1080                 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
 1081 
 1082                 m = cur_rx->wb_mbuf;
 1083 
 1084                 if ((rxstat & WB_RXSTAT_MIIERR) ||
 1085                     (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
 1086                     (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
 1087                     !(rxstat & WB_RXSTAT_LASTFRAG) ||
 1088                     !(rxstat & WB_RXSTAT_RXCMP)) {
 1089                         ifp->if_ierrors++;
 1090                         wb_newbuf(sc, cur_rx, m);
 1091                         device_printf(sc->wb_dev,
 1092                             "receiver babbling: possible chip bug,"
 1093                             " forcing reset\n");
 1094                         wb_fixmedia(sc);
 1095                         wb_reset(sc);
 1096                         wb_init_locked(sc);
 1097                         return;
 1098                 }
 1099 
 1100                 if (rxstat & WB_RXSTAT_RXERR) {
 1101                         ifp->if_ierrors++;
 1102                         wb_newbuf(sc, cur_rx, m);
 1103                         break;
 1104                 }
 1105 
 1106                 /* No errors; receive the packet. */    
 1107                 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
 1108 
 1109                 /*
 1110                  * XXX The Winbond chip includes the CRC with every
 1111                  * received frame, and there's no way to turn this
 1112                  * behavior off (at least, I can't find anything in
 1113                  * the manual that explains how to do it) so we have
 1114                  * to trim off the CRC manually.
 1115                  */
 1116                 total_len -= ETHER_CRC_LEN;
 1117 
 1118                 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp,
 1119                     NULL);
 1120                 wb_newbuf(sc, cur_rx, m);
 1121                 if (m0 == NULL) {
 1122                         ifp->if_ierrors++;
 1123                         break;
 1124                 }
 1125                 m = m0;
 1126 
 1127                 ifp->if_ipackets++;
 1128                 WB_UNLOCK(sc);
 1129                 (*ifp->if_input)(ifp, m);
 1130                 WB_LOCK(sc);
 1131         }
 1132 }
 1133 
 1134 static void
 1135 wb_rxeoc(sc)
 1136         struct wb_softc         *sc;
 1137 {
 1138         wb_rxeof(sc);
 1139 
 1140         WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
 1141         CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
 1142         WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
 1143         if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
 1144                 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
 1145 
 1146         return;
 1147 }
 1148 
 1149 /*
 1150  * A frame was downloaded to the chip. It's safe for us to clean up
 1151  * the list buffers.
 1152  */
 1153 static void
 1154 wb_txeof(sc)
 1155         struct wb_softc         *sc;
 1156 {
 1157         struct wb_chain         *cur_tx;
 1158         struct ifnet            *ifp;
 1159 
 1160         ifp = sc->wb_ifp;
 1161 
 1162         /* Clear the timeout timer. */
 1163         ifp->if_timer = 0;
 1164 
 1165         if (sc->wb_cdata.wb_tx_head == NULL)
 1166                 return;
 1167 
 1168         /*
 1169          * Go through our tx list and free mbufs for those
 1170          * frames that have been transmitted.
 1171          */
 1172         while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
 1173                 u_int32_t               txstat;
 1174 
 1175                 cur_tx = sc->wb_cdata.wb_tx_head;
 1176                 txstat = WB_TXSTATUS(cur_tx);
 1177 
 1178                 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
 1179                         break;
 1180 
 1181                 if (txstat & WB_TXSTAT_TXERR) {
 1182                         ifp->if_oerrors++;
 1183                         if (txstat & WB_TXSTAT_ABORT)
 1184                                 ifp->if_collisions++;
 1185                         if (txstat & WB_TXSTAT_LATECOLL)
 1186                                 ifp->if_collisions++;
 1187                 }
 1188 
 1189                 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
 1190 
 1191                 ifp->if_opackets++;
 1192                 m_freem(cur_tx->wb_mbuf);
 1193                 cur_tx->wb_mbuf = NULL;
 1194 
 1195                 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
 1196                         sc->wb_cdata.wb_tx_head = NULL;
 1197                         sc->wb_cdata.wb_tx_tail = NULL;
 1198                         break;
 1199                 }
 1200 
 1201                 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
 1202         }
 1203 
 1204         return;
 1205 }
 1206 
 1207 /*
 1208  * TX 'end of channel' interrupt handler.
 1209  */
 1210 static void
 1211 wb_txeoc(sc)
 1212         struct wb_softc         *sc;
 1213 {
 1214         struct ifnet            *ifp;
 1215 
 1216         ifp = sc->wb_ifp;
 1217 
 1218         ifp->if_timer = 0;
 1219 
 1220         if (sc->wb_cdata.wb_tx_head == NULL) {
 1221                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 1222                 sc->wb_cdata.wb_tx_tail = NULL;
 1223         } else {
 1224                 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
 1225                         WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
 1226                         ifp->if_timer = 5;
 1227                         CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
 1228                 }
 1229         }
 1230 
 1231         return;
 1232 }
 1233 
 1234 static void
 1235 wb_intr(arg)
 1236         void                    *arg;
 1237 {
 1238         struct wb_softc         *sc;
 1239         struct ifnet            *ifp;
 1240         u_int32_t               status;
 1241 
 1242         sc = arg;
 1243         WB_LOCK(sc);
 1244         ifp = sc->wb_ifp;
 1245 
 1246         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
 1247                 WB_UNLOCK(sc);
 1248                 return;
 1249         }
 1250 
 1251         /* Disable interrupts. */
 1252         CSR_WRITE_4(sc, WB_IMR, 0x00000000);
 1253 
 1254         for (;;) {
 1255 
 1256                 status = CSR_READ_4(sc, WB_ISR);
 1257                 if (status)
 1258                         CSR_WRITE_4(sc, WB_ISR, status);
 1259 
 1260                 if ((status & WB_INTRS) == 0)
 1261                         break;
 1262 
 1263                 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
 1264                         ifp->if_ierrors++;
 1265                         wb_reset(sc);
 1266                         if (status & WB_ISR_RX_ERR)
 1267                                 wb_fixmedia(sc);
 1268                         wb_init_locked(sc);
 1269                         continue;
 1270                 }
 1271 
 1272                 if (status & WB_ISR_RX_OK)
 1273                         wb_rxeof(sc);
 1274         
 1275                 if (status & WB_ISR_RX_IDLE)
 1276                         wb_rxeoc(sc);
 1277 
 1278                 if (status & WB_ISR_TX_OK)
 1279                         wb_txeof(sc);
 1280 
 1281                 if (status & WB_ISR_TX_NOBUF)
 1282                         wb_txeoc(sc);
 1283 
 1284                 if (status & WB_ISR_TX_IDLE) {
 1285                         wb_txeof(sc);
 1286                         if (sc->wb_cdata.wb_tx_head != NULL) {
 1287                                 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
 1288                                 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
 1289                         }
 1290                 }
 1291 
 1292                 if (status & WB_ISR_TX_UNDERRUN) {
 1293                         ifp->if_oerrors++;
 1294                         wb_txeof(sc);
 1295                         WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
 1296                         /* Jack up TX threshold */
 1297                         sc->wb_txthresh += WB_TXTHRESH_CHUNK;
 1298                         WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
 1299                         WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
 1300                         WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
 1301                 }
 1302 
 1303                 if (status & WB_ISR_BUS_ERR) {
 1304                         wb_reset(sc);
 1305                         wb_init_locked(sc);
 1306                 }
 1307 
 1308         }
 1309 
 1310         /* Re-enable interrupts. */
 1311         CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
 1312 
 1313         if (ifp->if_snd.ifq_head != NULL) {
 1314                 wb_start_locked(ifp);
 1315         }
 1316 
 1317         WB_UNLOCK(sc);
 1318 
 1319         return;
 1320 }
 1321 
 1322 static void
 1323 wb_tick(xsc)
 1324         void                    *xsc;
 1325 {
 1326         struct wb_softc         *sc;
 1327         struct mii_data         *mii;
 1328 
 1329         sc = xsc;
 1330         WB_LOCK_ASSERT(sc);
 1331         mii = device_get_softc(sc->wb_miibus);
 1332 
 1333         mii_tick(mii);
 1334 
 1335         callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc);
 1336 
 1337         return;
 1338 }
 1339 
 1340 /*
 1341  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
 1342  * pointers to the fragment pointers.
 1343  */
 1344 static int
 1345 wb_encap(sc, c, m_head)
 1346         struct wb_softc         *sc;
 1347         struct wb_chain         *c;
 1348         struct mbuf             *m_head;
 1349 {
 1350         int                     frag = 0;
 1351         struct wb_desc          *f = NULL;
 1352         int                     total_len;
 1353         struct mbuf             *m;
 1354 
 1355         /*
 1356          * Start packing the mbufs in this chain into
 1357          * the fragment pointers. Stop when we run out
 1358          * of fragments or hit the end of the mbuf chain.
 1359          */
 1360         m = m_head;
 1361         total_len = 0;
 1362 
 1363         for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
 1364                 if (m->m_len != 0) {
 1365                         if (frag == WB_MAXFRAGS)
 1366                                 break;
 1367                         total_len += m->m_len;
 1368                         f = &c->wb_ptr->wb_frag[frag];
 1369                         f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
 1370                         if (frag == 0) {
 1371                                 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
 1372                                 f->wb_status = 0;
 1373                         } else
 1374                                 f->wb_status = WB_TXSTAT_OWN;
 1375                         f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
 1376                         f->wb_data = vtophys(mtod(m, vm_offset_t));
 1377                         frag++;
 1378                 }
 1379         }
 1380 
 1381         /*
 1382          * Handle special case: we used up all 16 fragments,
 1383          * but we have more mbufs left in the chain. Copy the
 1384          * data into an mbuf cluster. Note that we don't
 1385          * bother clearing the values in the other fragment
 1386          * pointers/counters; it wouldn't gain us anything,
 1387          * and would waste cycles.
 1388          */
 1389         if (m != NULL) {
 1390                 struct mbuf             *m_new = NULL;
 1391 
 1392                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1393                 if (m_new == NULL)
 1394                         return(1);
 1395                 if (m_head->m_pkthdr.len > MHLEN) {
 1396                         MCLGET(m_new, M_DONTWAIT);
 1397                         if (!(m_new->m_flags & M_EXT)) {
 1398                                 m_freem(m_new);
 1399                                 return(1);
 1400                         }
 1401                 }
 1402                 m_copydata(m_head, 0, m_head->m_pkthdr.len,     
 1403                                         mtod(m_new, caddr_t));
 1404                 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
 1405                 m_freem(m_head);
 1406                 m_head = m_new;
 1407                 f = &c->wb_ptr->wb_frag[0];
 1408                 f->wb_status = 0;
 1409                 f->wb_data = vtophys(mtod(m_new, caddr_t));
 1410                 f->wb_ctl = total_len = m_new->m_len;
 1411                 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
 1412                 frag = 1;
 1413         }
 1414 
 1415         if (total_len < WB_MIN_FRAMELEN) {
 1416                 f = &c->wb_ptr->wb_frag[frag];
 1417                 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
 1418                 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
 1419                 f->wb_ctl |= WB_TXCTL_TLINK;
 1420                 f->wb_status = WB_TXSTAT_OWN;
 1421                 frag++;
 1422         }
 1423 
 1424         c->wb_mbuf = m_head;
 1425         c->wb_lastdesc = frag - 1;
 1426         WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
 1427         WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
 1428 
 1429         return(0);
 1430 }
 1431 
 1432 /*
 1433  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
 1434  * to the mbuf data regions directly in the transmit lists. We also save a
 1435  * copy of the pointers since the transmit list fragment pointers are
 1436  * physical addresses.
 1437  */
 1438 
 1439 static void
 1440 wb_start(ifp)
 1441         struct ifnet            *ifp;
 1442 {
 1443         struct wb_softc         *sc;
 1444 
 1445         sc = ifp->if_softc;
 1446         WB_LOCK(sc);
 1447         wb_start_locked(ifp);
 1448         WB_UNLOCK(sc);
 1449 }
 1450 
 1451 static void
 1452 wb_start_locked(ifp)
 1453         struct ifnet            *ifp;
 1454 {
 1455         struct wb_softc         *sc;
 1456         struct mbuf             *m_head = NULL;
 1457         struct wb_chain         *cur_tx = NULL, *start_tx;
 1458 
 1459         sc = ifp->if_softc;
 1460         WB_LOCK_ASSERT(sc);
 1461 
 1462         /*
 1463          * Check for an available queue slot. If there are none,
 1464          * punt.
 1465          */
 1466         if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
 1467                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 1468                 return;
 1469         }
 1470 
 1471         start_tx = sc->wb_cdata.wb_tx_free;
 1472 
 1473         while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
 1474                 IF_DEQUEUE(&ifp->if_snd, m_head);
 1475                 if (m_head == NULL)
 1476                         break;
 1477 
 1478                 /* Pick a descriptor off the free list. */
 1479                 cur_tx = sc->wb_cdata.wb_tx_free;
 1480                 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
 1481 
 1482                 /* Pack the data into the descriptor. */
 1483                 wb_encap(sc, cur_tx, m_head);
 1484 
 1485                 if (cur_tx != start_tx)
 1486                         WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
 1487 
 1488                 /*
 1489                  * If there's a BPF listener, bounce a copy of this frame
 1490                  * to him.
 1491                  */
 1492                 BPF_MTAP(ifp, cur_tx->wb_mbuf);
 1493         }
 1494 
 1495         /*
 1496          * If there are no packets queued, bail.
 1497          */
 1498         if (cur_tx == NULL)
 1499                 return;
 1500 
 1501         /*
 1502          * Place the request for the upload interrupt
 1503          * in the last descriptor in the chain. This way, if
 1504          * we're chaining several packets at once, we'll only
 1505          * get an interrupt once for the whole chain rather than
 1506          * once for each packet.
 1507          */
 1508         WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
 1509         cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
 1510         sc->wb_cdata.wb_tx_tail = cur_tx;
 1511 
 1512         if (sc->wb_cdata.wb_tx_head == NULL) {
 1513                 sc->wb_cdata.wb_tx_head = start_tx;
 1514                 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
 1515                 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
 1516         } else {
 1517                 /*
 1518                  * We need to distinguish between the case where
 1519                  * the own bit is clear because the chip cleared it
 1520                  * and where the own bit is clear because we haven't
 1521                  * set it yet. The magic value WB_UNSET is just some
 1522                  * ramdomly chosen number which doesn't have the own
 1523                  * bit set. When we actually transmit the frame, the
 1524                  * status word will have _only_ the own bit set, so
 1525                  * the txeoc handler will be able to tell if it needs
 1526                  * to initiate another transmission to flush out pending
 1527                  * frames.
 1528                  */
 1529                 WB_TXOWN(start_tx) = WB_UNSENT;
 1530         }
 1531 
 1532         /*
 1533          * Set a timeout in case the chip goes out to lunch.
 1534          */
 1535         ifp->if_timer = 5;
 1536 
 1537         return;
 1538 }
 1539 
 1540 static void
 1541 wb_init(xsc)
 1542         void                    *xsc;
 1543 {
 1544         struct wb_softc         *sc = xsc;
 1545 
 1546         WB_LOCK(sc);
 1547         wb_init_locked(sc);
 1548         WB_UNLOCK(sc);
 1549 }
 1550 
 1551 static void
 1552 wb_init_locked(sc)
 1553         struct wb_softc         *sc;
 1554 {
 1555         struct ifnet            *ifp = sc->wb_ifp;
 1556         int                     i;
 1557         struct mii_data         *mii;
 1558 
 1559         WB_LOCK_ASSERT(sc);
 1560         mii = device_get_softc(sc->wb_miibus);
 1561 
 1562         /*
 1563          * Cancel pending I/O and free all RX/TX buffers.
 1564          */
 1565         wb_stop(sc);
 1566         wb_reset(sc);
 1567 
 1568         sc->wb_txthresh = WB_TXTHRESH_INIT;
 1569 
 1570         /*
 1571          * Set cache alignment and burst length.
 1572          */
 1573 #ifdef foo
 1574         CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
 1575         WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
 1576         WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
 1577 #endif
 1578 
 1579         CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION);
 1580         WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
 1581         switch(sc->wb_cachesize) {
 1582         case 32:
 1583                 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
 1584                 break;
 1585         case 16:
 1586                 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
 1587                 break;
 1588         case 8:
 1589                 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
 1590                 break;
 1591         case 0:
 1592         default:
 1593                 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
 1594                 break;
 1595         }
 1596 
 1597         /* This doesn't tend to work too well at 100Mbps. */
 1598         WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
 1599 
 1600         /* Init our MAC address */
 1601         for (i = 0; i < ETHER_ADDR_LEN; i++) {
 1602                 CSR_WRITE_1(sc, WB_NODE0 + i, IF_LLADDR(sc->wb_ifp)[i]);
 1603         }
 1604 
 1605         /* Init circular RX list. */
 1606         if (wb_list_rx_init(sc) == ENOBUFS) {
 1607                 device_printf(sc->wb_dev,
 1608                     "initialization failed: no memory for rx buffers\n");
 1609                 wb_stop(sc);
 1610                 return;
 1611         }
 1612 
 1613         /* Init TX descriptors. */
 1614         wb_list_tx_init(sc);
 1615 
 1616         /* If we want promiscuous mode, set the allframes bit. */
 1617         if (ifp->if_flags & IFF_PROMISC) {
 1618                 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
 1619         } else {
 1620                 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
 1621         }
 1622 
 1623         /*
 1624          * Set capture broadcast bit to capture broadcast frames.
 1625          */
 1626         if (ifp->if_flags & IFF_BROADCAST) {
 1627                 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
 1628         } else {
 1629                 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
 1630         }
 1631 
 1632         /*
 1633          * Program the multicast filter, if necessary.
 1634          */
 1635         wb_setmulti(sc);
 1636 
 1637         /*
 1638          * Load the address of the RX list.
 1639          */
 1640         WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
 1641         CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
 1642 
 1643         /*
 1644          * Enable interrupts.
 1645          */
 1646         CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
 1647         CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
 1648 
 1649         /* Enable receiver and transmitter. */
 1650         WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
 1651         CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
 1652 
 1653         WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
 1654         CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
 1655         WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
 1656 
 1657         mii_mediachg(mii);
 1658 
 1659         ifp->if_drv_flags |= IFF_DRV_RUNNING;
 1660         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 1661 
 1662         callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc);
 1663 
 1664         return;
 1665 }
 1666 
 1667 /*
 1668  * Set media options.
 1669  */
 1670 static int
 1671 wb_ifmedia_upd(ifp)
 1672         struct ifnet            *ifp;
 1673 {
 1674         struct wb_softc         *sc;
 1675 
 1676         sc = ifp->if_softc;
 1677 
 1678         WB_LOCK(sc);
 1679         if (ifp->if_flags & IFF_UP)
 1680                 wb_init_locked(sc);
 1681         WB_UNLOCK(sc);
 1682 
 1683         return(0);
 1684 }
 1685 
 1686 /*
 1687  * Report current media status.
 1688  */
 1689 static void
 1690 wb_ifmedia_sts(ifp, ifmr)
 1691         struct ifnet            *ifp;
 1692         struct ifmediareq       *ifmr;
 1693 {
 1694         struct wb_softc         *sc;
 1695         struct mii_data         *mii;
 1696 
 1697         sc = ifp->if_softc;
 1698 
 1699         WB_LOCK(sc);
 1700         mii = device_get_softc(sc->wb_miibus);
 1701 
 1702         mii_pollstat(mii);
 1703         ifmr->ifm_active = mii->mii_media_active;
 1704         ifmr->ifm_status = mii->mii_media_status;
 1705         WB_UNLOCK(sc);
 1706 
 1707         return;
 1708 }
 1709 
 1710 static int
 1711 wb_ioctl(ifp, command, data)
 1712         struct ifnet            *ifp;
 1713         u_long                  command;
 1714         caddr_t                 data;
 1715 {
 1716         struct wb_softc         *sc = ifp->if_softc;
 1717         struct mii_data         *mii;
 1718         struct ifreq            *ifr = (struct ifreq *) data;
 1719         int                     error = 0;
 1720 
 1721         switch(command) {
 1722         case SIOCSIFFLAGS:
 1723                 WB_LOCK(sc);
 1724                 if (ifp->if_flags & IFF_UP) {
 1725                         wb_init_locked(sc);
 1726                 } else {
 1727                         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
 1728                                 wb_stop(sc);
 1729                 }
 1730                 WB_UNLOCK(sc);
 1731                 error = 0;
 1732                 break;
 1733         case SIOCADDMULTI:
 1734         case SIOCDELMULTI:
 1735                 WB_LOCK(sc);
 1736                 wb_setmulti(sc);
 1737                 WB_UNLOCK(sc);
 1738                 error = 0;
 1739                 break;
 1740         case SIOCGIFMEDIA:
 1741         case SIOCSIFMEDIA:
 1742                 mii = device_get_softc(sc->wb_miibus);
 1743                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
 1744                 break;
 1745         default:
 1746                 error = ether_ioctl(ifp, command, data);
 1747                 break;
 1748         }
 1749 
 1750         return(error);
 1751 }
 1752 
 1753 static void
 1754 wb_watchdog(ifp)
 1755         struct ifnet            *ifp;
 1756 {
 1757         struct wb_softc         *sc;
 1758 
 1759         sc = ifp->if_softc;
 1760 
 1761         WB_LOCK(sc);
 1762         ifp->if_oerrors++;
 1763         if_printf(ifp, "watchdog timeout\n");
 1764 #ifdef foo
 1765         if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
 1766                 if_printf(ifp, "no carrier - transceiver cable problem?\n");
 1767 #endif
 1768         wb_stop(sc);
 1769         wb_reset(sc);
 1770         wb_init_locked(sc);
 1771 
 1772         if (ifp->if_snd.ifq_head != NULL)
 1773                 wb_start_locked(ifp);
 1774         WB_UNLOCK(sc);
 1775 
 1776         return;
 1777 }
 1778 
 1779 /*
 1780  * Stop the adapter and free any mbufs allocated to the
 1781  * RX and TX lists.
 1782  */
 1783 static void
 1784 wb_stop(sc)
 1785         struct wb_softc         *sc;
 1786 {
 1787         register int            i;
 1788         struct ifnet            *ifp;
 1789 
 1790         WB_LOCK_ASSERT(sc);
 1791         ifp = sc->wb_ifp;
 1792         ifp->if_timer = 0;
 1793 
 1794         callout_stop(&sc->wb_stat_callout);
 1795 
 1796         WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
 1797         CSR_WRITE_4(sc, WB_IMR, 0x00000000);
 1798         CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
 1799         CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
 1800 
 1801         /*
 1802          * Free data in the RX lists.
 1803          */
 1804         for (i = 0; i < WB_RX_LIST_CNT; i++) {
 1805                 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
 1806                         m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
 1807                         sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
 1808                 }
 1809         }
 1810         bzero((char *)&sc->wb_ldata->wb_rx_list,
 1811                 sizeof(sc->wb_ldata->wb_rx_list));
 1812 
 1813         /*
 1814          * Free the TX list buffers.
 1815          */
 1816         for (i = 0; i < WB_TX_LIST_CNT; i++) {
 1817                 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
 1818                         m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
 1819                         sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
 1820                 }
 1821         }
 1822 
 1823         bzero((char *)&sc->wb_ldata->wb_tx_list,
 1824                 sizeof(sc->wb_ldata->wb_tx_list));
 1825 
 1826         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
 1827 
 1828         return;
 1829 }
 1830 
 1831 /*
 1832  * Stop all chip I/O so that the kernel's probe routines don't
 1833  * get confused by errant DMAs when rebooting.
 1834  */
 1835 static void
 1836 wb_shutdown(dev)
 1837         device_t                dev;
 1838 {
 1839         struct wb_softc         *sc;
 1840 
 1841         sc = device_get_softc(dev);
 1842 
 1843         WB_LOCK(sc);
 1844         wb_stop(sc);
 1845         WB_UNLOCK(sc);
 1846 
 1847         return;
 1848 }

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