FreeBSD/Linux Kernel Cross Reference
sys/pci/if_wb.c
1 /*-
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 /*
37 * Winbond fast ethernet PCI NIC driver
38 *
39 * Supports various cheap network adapters based on the Winbond W89C840F
40 * fast ethernet controller chip. This includes adapters manufactured by
41 * Winbond itself and some made by Linksys.
42 *
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
46 */
47 /*
48 * The Winbond W89C840F chip is a bus master; in some ways it resembles
49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
50 * one major difference which is that while the registers do many of
51 * the same things as a tulip adapter, the offsets are different: where
52 * tulip registers are typically spaced 8 bytes apart, the Winbond
53 * registers are spaced 4 bytes apart. The receiver filter is also
54 * programmed differently.
55 *
56 * Like the tulip, the Winbond chip uses small descriptors containing
57 * a status word, a control word and 32-bit areas that can either be used
58 * to point to two external data blocks, or to point to a single block
59 * and another descriptor in a linked list. Descriptors can be grouped
60 * together in blocks to form fixed length rings or can be chained
61 * together in linked lists. A single packet may be spread out over
62 * several descriptors if necessary.
63 *
64 * For the receive ring, this driver uses a linked list of descriptors,
65 * each pointing to a single mbuf cluster buffer, which us large enough
66 * to hold an entire packet. The link list is looped back to created a
67 * closed ring.
68 *
69 * For transmission, the driver creates a linked list of 'super descriptors'
70 * which each contain several individual descriptors linked toghether.
71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
72 * abuse as fragment pointers. This allows us to use a buffer managment
73 * scheme very similar to that used in the ThunderLAN and Etherlink XL
74 * drivers.
75 *
76 * Autonegotiation is performed using the external PHY via the MII bus.
77 * The sample boards I have all use a Davicom PHY.
78 *
79 * Note: the author of the Linux driver for the Winbond chip alludes
80 * to some sort of flaw in the chip's design that seems to mandate some
81 * drastic workaround which signigicantly impairs transmit performance.
82 * I have no idea what he's on about: transmit performance with all
83 * three of my test boards seems fine.
84 */
85
86 #include <sys/param.h>
87 #include <sys/systm.h>
88 #include <sys/sockio.h>
89 #include <sys/mbuf.h>
90 #include <sys/malloc.h>
91 #include <sys/module.h>
92 #include <sys/kernel.h>
93 #include <sys/socket.h>
94 #include <sys/queue.h>
95
96 #include <net/if.h>
97 #include <net/if_arp.h>
98 #include <net/ethernet.h>
99 #include <net/if_dl.h>
100 #include <net/if_media.h>
101 #include <net/if_types.h>
102
103 #include <net/bpf.h>
104
105 #include <vm/vm.h> /* for vtophys */
106 #include <vm/pmap.h> /* for vtophys */
107 #include <machine/bus.h>
108 #include <machine/resource.h>
109 #include <sys/bus.h>
110 #include <sys/rman.h>
111
112 #include <dev/pci/pcireg.h>
113 #include <dev/pci/pcivar.h>
114
115 #include <dev/mii/mii.h>
116 #include <dev/mii/mii_bitbang.h>
117 #include <dev/mii/miivar.h>
118
119 /* "device miibus" required. See GENERIC if you get errors here. */
120 #include "miibus_if.h"
121
122 #define WB_USEIOSPACE
123
124 #include <pci/if_wbreg.h>
125
126 MODULE_DEPEND(wb, pci, 1, 1, 1);
127 MODULE_DEPEND(wb, ether, 1, 1, 1);
128 MODULE_DEPEND(wb, miibus, 1, 1, 1);
129
130 /*
131 * Various supported device vendors/types and their names.
132 */
133 static const struct wb_type const wb_devs[] = {
134 { WB_VENDORID, WB_DEVICEID_840F,
135 "Winbond W89C840F 10/100BaseTX" },
136 { CP_VENDORID, CP_DEVICEID_RL100,
137 "Compex RL100-ATX 10/100baseTX" },
138 { 0, 0, NULL }
139 };
140
141 static int wb_probe(device_t);
142 static int wb_attach(device_t);
143 static int wb_detach(device_t);
144
145 static void wb_bfree(void *addr, void *args);
146 static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *,
147 struct mbuf *);
148 static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *);
149
150 static void wb_rxeof(struct wb_softc *);
151 static void wb_rxeoc(struct wb_softc *);
152 static void wb_txeof(struct wb_softc *);
153 static void wb_txeoc(struct wb_softc *);
154 static void wb_intr(void *);
155 static void wb_tick(void *);
156 static void wb_start(struct ifnet *);
157 static void wb_start_locked(struct ifnet *);
158 static int wb_ioctl(struct ifnet *, u_long, caddr_t);
159 static void wb_init(void *);
160 static void wb_init_locked(struct wb_softc *);
161 static void wb_stop(struct wb_softc *);
162 static void wb_watchdog(struct wb_softc *);
163 static void wb_shutdown(device_t);
164 static int wb_ifmedia_upd(struct ifnet *);
165 static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *);
166
167 static void wb_eeprom_putbyte(struct wb_softc *, int);
168 static void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *);
169 static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int);
170
171 static void wb_setcfg(struct wb_softc *, u_int32_t);
172 static void wb_setmulti(struct wb_softc *);
173 static void wb_reset(struct wb_softc *);
174 static void wb_fixmedia(struct wb_softc *);
175 static int wb_list_rx_init(struct wb_softc *);
176 static int wb_list_tx_init(struct wb_softc *);
177
178 static int wb_miibus_readreg(device_t, int, int);
179 static int wb_miibus_writereg(device_t, int, int, int);
180 static void wb_miibus_statchg(device_t);
181
182 /*
183 * MII bit-bang glue
184 */
185 static uint32_t wb_mii_bitbang_read(device_t);
186 static void wb_mii_bitbang_write(device_t, uint32_t);
187
188 static const struct mii_bitbang_ops wb_mii_bitbang_ops = {
189 wb_mii_bitbang_read,
190 wb_mii_bitbang_write,
191 {
192 WB_SIO_MII_DATAOUT, /* MII_BIT_MDO */
193 WB_SIO_MII_DATAIN, /* MII_BIT_MDI */
194 WB_SIO_MII_CLK, /* MII_BIT_MDC */
195 WB_SIO_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
196 0, /* MII_BIT_DIR_PHY_HOST */
197 }
198 };
199
200 #ifdef WB_USEIOSPACE
201 #define WB_RES SYS_RES_IOPORT
202 #define WB_RID WB_PCI_LOIO
203 #else
204 #define WB_RES SYS_RES_MEMORY
205 #define WB_RID WB_PCI_LOMEM
206 #endif
207
208 static device_method_t wb_methods[] = {
209 /* Device interface */
210 DEVMETHOD(device_probe, wb_probe),
211 DEVMETHOD(device_attach, wb_attach),
212 DEVMETHOD(device_detach, wb_detach),
213 DEVMETHOD(device_shutdown, wb_shutdown),
214
215 /* bus interface, for miibus */
216 DEVMETHOD(bus_print_child, bus_generic_print_child),
217 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
218
219 /* MII interface */
220 DEVMETHOD(miibus_readreg, wb_miibus_readreg),
221 DEVMETHOD(miibus_writereg, wb_miibus_writereg),
222 DEVMETHOD(miibus_statchg, wb_miibus_statchg),
223 { 0, 0 }
224 };
225
226 static driver_t wb_driver = {
227 "wb",
228 wb_methods,
229 sizeof(struct wb_softc)
230 };
231
232 static devclass_t wb_devclass;
233
234 DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0);
235 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
236
237 #define WB_SETBIT(sc, reg, x) \
238 CSR_WRITE_4(sc, reg, \
239 CSR_READ_4(sc, reg) | (x))
240
241 #define WB_CLRBIT(sc, reg, x) \
242 CSR_WRITE_4(sc, reg, \
243 CSR_READ_4(sc, reg) & ~(x))
244
245 #define SIO_SET(x) \
246 CSR_WRITE_4(sc, WB_SIO, \
247 CSR_READ_4(sc, WB_SIO) | (x))
248
249 #define SIO_CLR(x) \
250 CSR_WRITE_4(sc, WB_SIO, \
251 CSR_READ_4(sc, WB_SIO) & ~(x))
252
253 /*
254 * Send a read command and address to the EEPROM, check for ACK.
255 */
256 static void
257 wb_eeprom_putbyte(sc, addr)
258 struct wb_softc *sc;
259 int addr;
260 {
261 register int d, i;
262
263 d = addr | WB_EECMD_READ;
264
265 /*
266 * Feed in each bit and stobe the clock.
267 */
268 for (i = 0x400; i; i >>= 1) {
269 if (d & i) {
270 SIO_SET(WB_SIO_EE_DATAIN);
271 } else {
272 SIO_CLR(WB_SIO_EE_DATAIN);
273 }
274 DELAY(100);
275 SIO_SET(WB_SIO_EE_CLK);
276 DELAY(150);
277 SIO_CLR(WB_SIO_EE_CLK);
278 DELAY(100);
279 }
280 }
281
282 /*
283 * Read a word of data stored in the EEPROM at address 'addr.'
284 */
285 static void
286 wb_eeprom_getword(sc, addr, dest)
287 struct wb_softc *sc;
288 int addr;
289 u_int16_t *dest;
290 {
291 register int i;
292 u_int16_t word = 0;
293
294 /* Enter EEPROM access mode. */
295 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
296
297 /*
298 * Send address of word we want to read.
299 */
300 wb_eeprom_putbyte(sc, addr);
301
302 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
303
304 /*
305 * Start reading bits from EEPROM.
306 */
307 for (i = 0x8000; i; i >>= 1) {
308 SIO_SET(WB_SIO_EE_CLK);
309 DELAY(100);
310 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
311 word |= i;
312 SIO_CLR(WB_SIO_EE_CLK);
313 DELAY(100);
314 }
315
316 /* Turn off EEPROM access mode. */
317 CSR_WRITE_4(sc, WB_SIO, 0);
318
319 *dest = word;
320 }
321
322 /*
323 * Read a sequence of words from the EEPROM.
324 */
325 static void
326 wb_read_eeprom(sc, dest, off, cnt, swap)
327 struct wb_softc *sc;
328 caddr_t dest;
329 int off;
330 int cnt;
331 int swap;
332 {
333 int i;
334 u_int16_t word = 0, *ptr;
335
336 for (i = 0; i < cnt; i++) {
337 wb_eeprom_getword(sc, off + i, &word);
338 ptr = (u_int16_t *)(dest + (i * 2));
339 if (swap)
340 *ptr = ntohs(word);
341 else
342 *ptr = word;
343 }
344 }
345
346 /*
347 * Read the MII serial port for the MII bit-bang module.
348 */
349 static uint32_t
350 wb_mii_bitbang_read(device_t dev)
351 {
352 struct wb_softc *sc;
353 uint32_t val;
354
355 sc = device_get_softc(dev);
356
357 val = CSR_READ_4(sc, WB_SIO);
358 CSR_BARRIER(sc, WB_SIO, 4,
359 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
360
361 return (val);
362 }
363
364 /*
365 * Write the MII serial port for the MII bit-bang module.
366 */
367 static void
368 wb_mii_bitbang_write(device_t dev, uint32_t val)
369 {
370 struct wb_softc *sc;
371
372 sc = device_get_softc(dev);
373
374 CSR_WRITE_4(sc, WB_SIO, val);
375 CSR_BARRIER(sc, WB_SIO, 4,
376 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
377 }
378
379 static int
380 wb_miibus_readreg(dev, phy, reg)
381 device_t dev;
382 int phy, reg;
383 {
384
385 return (mii_bitbang_readreg(dev, &wb_mii_bitbang_ops, phy, reg));
386 }
387
388 static int
389 wb_miibus_writereg(dev, phy, reg, data)
390 device_t dev;
391 int phy, reg, data;
392 {
393
394 mii_bitbang_writereg(dev, &wb_mii_bitbang_ops, phy, reg, data);
395
396 return(0);
397 }
398
399 static void
400 wb_miibus_statchg(dev)
401 device_t dev;
402 {
403 struct wb_softc *sc;
404 struct mii_data *mii;
405
406 sc = device_get_softc(dev);
407 mii = device_get_softc(sc->wb_miibus);
408 wb_setcfg(sc, mii->mii_media_active);
409 }
410
411 /*
412 * Program the 64-bit multicast hash filter.
413 */
414 static void
415 wb_setmulti(sc)
416 struct wb_softc *sc;
417 {
418 struct ifnet *ifp;
419 int h = 0;
420 u_int32_t hashes[2] = { 0, 0 };
421 struct ifmultiaddr *ifma;
422 u_int32_t rxfilt;
423 int mcnt = 0;
424
425 ifp = sc->wb_ifp;
426
427 rxfilt = CSR_READ_4(sc, WB_NETCFG);
428
429 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
430 rxfilt |= WB_NETCFG_RX_MULTI;
431 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
432 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
433 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
434 return;
435 }
436
437 /* first, zot all the existing hash bits */
438 CSR_WRITE_4(sc, WB_MAR0, 0);
439 CSR_WRITE_4(sc, WB_MAR1, 0);
440
441 /* now program new ones */
442 IF_ADDR_LOCK(ifp);
443 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
444 if (ifma->ifma_addr->sa_family != AF_LINK)
445 continue;
446 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
447 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
448 if (h < 32)
449 hashes[0] |= (1 << h);
450 else
451 hashes[1] |= (1 << (h - 32));
452 mcnt++;
453 }
454 IF_ADDR_UNLOCK(ifp);
455
456 if (mcnt)
457 rxfilt |= WB_NETCFG_RX_MULTI;
458 else
459 rxfilt &= ~WB_NETCFG_RX_MULTI;
460
461 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
462 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
463 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
464 }
465
466 /*
467 * The Winbond manual states that in order to fiddle with the
468 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
469 * first have to put the transmit and/or receive logic in the idle state.
470 */
471 static void
472 wb_setcfg(sc, media)
473 struct wb_softc *sc;
474 u_int32_t media;
475 {
476 int i, restart = 0;
477
478 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
479 restart = 1;
480 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
481
482 for (i = 0; i < WB_TIMEOUT; i++) {
483 DELAY(10);
484 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
485 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
486 break;
487 }
488
489 if (i == WB_TIMEOUT)
490 device_printf(sc->wb_dev,
491 "failed to force tx and rx to idle state\n");
492 }
493
494 if (IFM_SUBTYPE(media) == IFM_10_T)
495 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
496 else
497 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
498
499 if ((media & IFM_GMASK) == IFM_FDX)
500 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
501 else
502 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
503
504 if (restart)
505 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
506 }
507
508 static void
509 wb_reset(sc)
510 struct wb_softc *sc;
511 {
512 register int i;
513 struct mii_data *mii;
514 struct mii_softc *miisc;
515
516 CSR_WRITE_4(sc, WB_NETCFG, 0);
517 CSR_WRITE_4(sc, WB_BUSCTL, 0);
518 CSR_WRITE_4(sc, WB_TXADDR, 0);
519 CSR_WRITE_4(sc, WB_RXADDR, 0);
520
521 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
522 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
523
524 for (i = 0; i < WB_TIMEOUT; i++) {
525 DELAY(10);
526 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
527 break;
528 }
529 if (i == WB_TIMEOUT)
530 device_printf(sc->wb_dev, "reset never completed!\n");
531
532 /* Wait a little while for the chip to get its brains in order. */
533 DELAY(1000);
534
535 if (sc->wb_miibus == NULL)
536 return;
537
538 mii = device_get_softc(sc->wb_miibus);
539 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
540 mii_phy_reset(miisc);
541 }
542
543 static void
544 wb_fixmedia(sc)
545 struct wb_softc *sc;
546 {
547 struct mii_data *mii = NULL;
548 struct ifnet *ifp;
549 u_int32_t media;
550
551 mii = device_get_softc(sc->wb_miibus);
552 ifp = sc->wb_ifp;
553
554 mii_pollstat(mii);
555 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
556 media = mii->mii_media_active & ~IFM_10_T;
557 media |= IFM_100_TX;
558 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
559 media = mii->mii_media_active & ~IFM_100_TX;
560 media |= IFM_10_T;
561 } else
562 return;
563
564 ifmedia_set(&mii->mii_media, media);
565 }
566
567 /*
568 * Probe for a Winbond chip. Check the PCI vendor and device
569 * IDs against our list and return a device name if we find a match.
570 */
571 static int
572 wb_probe(dev)
573 device_t dev;
574 {
575 const struct wb_type *t;
576
577 t = wb_devs;
578
579 while(t->wb_name != NULL) {
580 if ((pci_get_vendor(dev) == t->wb_vid) &&
581 (pci_get_device(dev) == t->wb_did)) {
582 device_set_desc(dev, t->wb_name);
583 return (BUS_PROBE_DEFAULT);
584 }
585 t++;
586 }
587
588 return(ENXIO);
589 }
590
591 /*
592 * Attach the interface. Allocate softc structures, do ifmedia
593 * setup and ethernet/BPF attach.
594 */
595 static int
596 wb_attach(dev)
597 device_t dev;
598 {
599 u_char eaddr[ETHER_ADDR_LEN];
600 struct wb_softc *sc;
601 struct ifnet *ifp;
602 int error = 0, rid;
603
604 sc = device_get_softc(dev);
605 sc->wb_dev = dev;
606
607 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
608 MTX_DEF);
609 callout_init_mtx(&sc->wb_stat_callout, &sc->wb_mtx, 0);
610
611 /*
612 * Map control/status registers.
613 */
614 pci_enable_busmaster(dev);
615
616 rid = WB_RID;
617 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE);
618
619 if (sc->wb_res == NULL) {
620 device_printf(dev, "couldn't map ports/memory\n");
621 error = ENXIO;
622 goto fail;
623 }
624
625 sc->wb_btag = rman_get_bustag(sc->wb_res);
626 sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
627
628 /* Allocate interrupt */
629 rid = 0;
630 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
631 RF_SHAREABLE | RF_ACTIVE);
632
633 if (sc->wb_irq == NULL) {
634 device_printf(dev, "couldn't map interrupt\n");
635 error = ENXIO;
636 goto fail;
637 }
638
639 /* Save the cache line size. */
640 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
641
642 /* Reset the adapter. */
643 wb_reset(sc);
644
645 /*
646 * Get station address from the EEPROM.
647 */
648 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0);
649
650 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
651 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
652
653 if (sc->wb_ldata == NULL) {
654 device_printf(dev, "no memory for list buffers!\n");
655 error = ENXIO;
656 goto fail;
657 }
658
659 bzero(sc->wb_ldata, sizeof(struct wb_list_data));
660
661 ifp = sc->wb_ifp = if_alloc(IFT_ETHER);
662 if (ifp == NULL) {
663 device_printf(dev, "can not if_alloc()\n");
664 error = ENOSPC;
665 goto fail;
666 }
667 ifp->if_softc = sc;
668 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
669 ifp->if_mtu = ETHERMTU;
670 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
671 ifp->if_ioctl = wb_ioctl;
672 ifp->if_start = wb_start;
673 ifp->if_init = wb_init;
674 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1;
675
676 /*
677 * Do MII setup.
678 */
679 error = mii_attach(dev, &sc->wb_miibus, ifp, wb_ifmedia_upd,
680 wb_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
681 if (error != 0) {
682 device_printf(dev, "attaching PHYs failed\n");
683 goto fail;
684 }
685
686 /*
687 * Call MI attach routine.
688 */
689 ether_ifattach(ifp, eaddr);
690
691 /* Hook interrupt last to avoid having to lock softc */
692 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET | INTR_MPSAFE,
693 NULL, wb_intr, sc, &sc->wb_intrhand);
694
695 if (error) {
696 device_printf(dev, "couldn't set up irq\n");
697 ether_ifdetach(ifp);
698 goto fail;
699 }
700
701 fail:
702 if (error)
703 wb_detach(dev);
704
705 return(error);
706 }
707
708 /*
709 * Shutdown hardware and free up resources. This can be called any
710 * time after the mutex has been initialized. It is called in both
711 * the error case in attach and the normal detach case so it needs
712 * to be careful about only freeing resources that have actually been
713 * allocated.
714 */
715 static int
716 wb_detach(dev)
717 device_t dev;
718 {
719 struct wb_softc *sc;
720 struct ifnet *ifp;
721
722 sc = device_get_softc(dev);
723 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized"));
724 ifp = sc->wb_ifp;
725
726 /*
727 * Delete any miibus and phy devices attached to this interface.
728 * This should only be done if attach succeeded.
729 */
730 if (device_is_attached(dev)) {
731 ether_ifdetach(ifp);
732 WB_LOCK(sc);
733 wb_stop(sc);
734 WB_UNLOCK(sc);
735 callout_drain(&sc->wb_stat_callout);
736 }
737 if (sc->wb_miibus)
738 device_delete_child(dev, sc->wb_miibus);
739 bus_generic_detach(dev);
740
741 if (sc->wb_intrhand)
742 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
743 if (sc->wb_irq)
744 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
745 if (sc->wb_res)
746 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
747
748 if (ifp)
749 if_free(ifp);
750
751 if (sc->wb_ldata) {
752 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8,
753 M_DEVBUF);
754 }
755
756 mtx_destroy(&sc->wb_mtx);
757
758 return(0);
759 }
760
761 /*
762 * Initialize the transmit descriptors.
763 */
764 static int
765 wb_list_tx_init(sc)
766 struct wb_softc *sc;
767 {
768 struct wb_chain_data *cd;
769 struct wb_list_data *ld;
770 int i;
771
772 cd = &sc->wb_cdata;
773 ld = sc->wb_ldata;
774
775 for (i = 0; i < WB_TX_LIST_CNT; i++) {
776 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
777 if (i == (WB_TX_LIST_CNT - 1)) {
778 cd->wb_tx_chain[i].wb_nextdesc =
779 &cd->wb_tx_chain[0];
780 } else {
781 cd->wb_tx_chain[i].wb_nextdesc =
782 &cd->wb_tx_chain[i + 1];
783 }
784 }
785
786 cd->wb_tx_free = &cd->wb_tx_chain[0];
787 cd->wb_tx_tail = cd->wb_tx_head = NULL;
788
789 return(0);
790 }
791
792
793 /*
794 * Initialize the RX descriptors and allocate mbufs for them. Note that
795 * we arrange the descriptors in a closed ring, so that the last descriptor
796 * points back to the first.
797 */
798 static int
799 wb_list_rx_init(sc)
800 struct wb_softc *sc;
801 {
802 struct wb_chain_data *cd;
803 struct wb_list_data *ld;
804 int i;
805
806 cd = &sc->wb_cdata;
807 ld = sc->wb_ldata;
808
809 for (i = 0; i < WB_RX_LIST_CNT; i++) {
810 cd->wb_rx_chain[i].wb_ptr =
811 (struct wb_desc *)&ld->wb_rx_list[i];
812 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i];
813 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
814 return(ENOBUFS);
815 if (i == (WB_RX_LIST_CNT - 1)) {
816 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
817 ld->wb_rx_list[i].wb_next =
818 vtophys(&ld->wb_rx_list[0]);
819 } else {
820 cd->wb_rx_chain[i].wb_nextdesc =
821 &cd->wb_rx_chain[i + 1];
822 ld->wb_rx_list[i].wb_next =
823 vtophys(&ld->wb_rx_list[i + 1]);
824 }
825 }
826
827 cd->wb_rx_head = &cd->wb_rx_chain[0];
828
829 return(0);
830 }
831
832 static void
833 wb_bfree(buf, args)
834 void *buf;
835 void *args;
836 {
837
838 }
839
840 /*
841 * Initialize an RX descriptor and attach an MBUF cluster.
842 */
843 static int
844 wb_newbuf(sc, c, m)
845 struct wb_softc *sc;
846 struct wb_chain_onefrag *c;
847 struct mbuf *m;
848 {
849 struct mbuf *m_new = NULL;
850
851 if (m == NULL) {
852 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
853 if (m_new == NULL)
854 return(ENOBUFS);
855 m_new->m_data = c->wb_buf;
856 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES;
857 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0,
858 EXT_NET_DRV);
859 } else {
860 m_new = m;
861 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
862 m_new->m_data = m_new->m_ext.ext_buf;
863 }
864
865 m_adj(m_new, sizeof(u_int64_t));
866
867 c->wb_mbuf = m_new;
868 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
869 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
870 c->wb_ptr->wb_status = WB_RXSTAT;
871
872 return(0);
873 }
874
875 /*
876 * A frame has been uploaded: pass the resulting mbuf chain up to
877 * the higher level protocols.
878 */
879 static void
880 wb_rxeof(sc)
881 struct wb_softc *sc;
882 {
883 struct mbuf *m = NULL;
884 struct ifnet *ifp;
885 struct wb_chain_onefrag *cur_rx;
886 int total_len = 0;
887 u_int32_t rxstat;
888
889 WB_LOCK_ASSERT(sc);
890
891 ifp = sc->wb_ifp;
892
893 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
894 WB_RXSTAT_OWN)) {
895 struct mbuf *m0 = NULL;
896
897 cur_rx = sc->wb_cdata.wb_rx_head;
898 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
899
900 m = cur_rx->wb_mbuf;
901
902 if ((rxstat & WB_RXSTAT_MIIERR) ||
903 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
904 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
905 !(rxstat & WB_RXSTAT_LASTFRAG) ||
906 !(rxstat & WB_RXSTAT_RXCMP)) {
907 ifp->if_ierrors++;
908 wb_newbuf(sc, cur_rx, m);
909 device_printf(sc->wb_dev,
910 "receiver babbling: possible chip bug,"
911 " forcing reset\n");
912 wb_fixmedia(sc);
913 wb_reset(sc);
914 wb_init_locked(sc);
915 return;
916 }
917
918 if (rxstat & WB_RXSTAT_RXERR) {
919 ifp->if_ierrors++;
920 wb_newbuf(sc, cur_rx, m);
921 break;
922 }
923
924 /* No errors; receive the packet. */
925 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
926
927 /*
928 * XXX The Winbond chip includes the CRC with every
929 * received frame, and there's no way to turn this
930 * behavior off (at least, I can't find anything in
931 * the manual that explains how to do it) so we have
932 * to trim off the CRC manually.
933 */
934 total_len -= ETHER_CRC_LEN;
935
936 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp,
937 NULL);
938 wb_newbuf(sc, cur_rx, m);
939 if (m0 == NULL) {
940 ifp->if_ierrors++;
941 break;
942 }
943 m = m0;
944
945 ifp->if_ipackets++;
946 WB_UNLOCK(sc);
947 (*ifp->if_input)(ifp, m);
948 WB_LOCK(sc);
949 }
950 }
951
952 static void
953 wb_rxeoc(sc)
954 struct wb_softc *sc;
955 {
956 wb_rxeof(sc);
957
958 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
959 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
960 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
961 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
962 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
963 }
964
965 /*
966 * A frame was downloaded to the chip. It's safe for us to clean up
967 * the list buffers.
968 */
969 static void
970 wb_txeof(sc)
971 struct wb_softc *sc;
972 {
973 struct wb_chain *cur_tx;
974 struct ifnet *ifp;
975
976 ifp = sc->wb_ifp;
977
978 /* Clear the timeout timer. */
979 sc->wb_timer = 0;
980
981 if (sc->wb_cdata.wb_tx_head == NULL)
982 return;
983
984 /*
985 * Go through our tx list and free mbufs for those
986 * frames that have been transmitted.
987 */
988 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
989 u_int32_t txstat;
990
991 cur_tx = sc->wb_cdata.wb_tx_head;
992 txstat = WB_TXSTATUS(cur_tx);
993
994 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
995 break;
996
997 if (txstat & WB_TXSTAT_TXERR) {
998 ifp->if_oerrors++;
999 if (txstat & WB_TXSTAT_ABORT)
1000 ifp->if_collisions++;
1001 if (txstat & WB_TXSTAT_LATECOLL)
1002 ifp->if_collisions++;
1003 }
1004
1005 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1006
1007 ifp->if_opackets++;
1008 m_freem(cur_tx->wb_mbuf);
1009 cur_tx->wb_mbuf = NULL;
1010
1011 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1012 sc->wb_cdata.wb_tx_head = NULL;
1013 sc->wb_cdata.wb_tx_tail = NULL;
1014 break;
1015 }
1016
1017 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1018 }
1019 }
1020
1021 /*
1022 * TX 'end of channel' interrupt handler.
1023 */
1024 static void
1025 wb_txeoc(sc)
1026 struct wb_softc *sc;
1027 {
1028 struct ifnet *ifp;
1029
1030 ifp = sc->wb_ifp;
1031
1032 sc->wb_timer = 0;
1033
1034 if (sc->wb_cdata.wb_tx_head == NULL) {
1035 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1036 sc->wb_cdata.wb_tx_tail = NULL;
1037 } else {
1038 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1039 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1040 sc->wb_timer = 5;
1041 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1042 }
1043 }
1044 }
1045
1046 static void
1047 wb_intr(arg)
1048 void *arg;
1049 {
1050 struct wb_softc *sc;
1051 struct ifnet *ifp;
1052 u_int32_t status;
1053
1054 sc = arg;
1055 WB_LOCK(sc);
1056 ifp = sc->wb_ifp;
1057
1058 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1059 WB_UNLOCK(sc);
1060 return;
1061 }
1062
1063 /* Disable interrupts. */
1064 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1065
1066 for (;;) {
1067
1068 status = CSR_READ_4(sc, WB_ISR);
1069 if (status)
1070 CSR_WRITE_4(sc, WB_ISR, status);
1071
1072 if ((status & WB_INTRS) == 0)
1073 break;
1074
1075 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1076 ifp->if_ierrors++;
1077 wb_reset(sc);
1078 if (status & WB_ISR_RX_ERR)
1079 wb_fixmedia(sc);
1080 wb_init_locked(sc);
1081 continue;
1082 }
1083
1084 if (status & WB_ISR_RX_OK)
1085 wb_rxeof(sc);
1086
1087 if (status & WB_ISR_RX_IDLE)
1088 wb_rxeoc(sc);
1089
1090 if (status & WB_ISR_TX_OK)
1091 wb_txeof(sc);
1092
1093 if (status & WB_ISR_TX_NOBUF)
1094 wb_txeoc(sc);
1095
1096 if (status & WB_ISR_TX_IDLE) {
1097 wb_txeof(sc);
1098 if (sc->wb_cdata.wb_tx_head != NULL) {
1099 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1100 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1101 }
1102 }
1103
1104 if (status & WB_ISR_TX_UNDERRUN) {
1105 ifp->if_oerrors++;
1106 wb_txeof(sc);
1107 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1108 /* Jack up TX threshold */
1109 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1110 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1111 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1112 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1113 }
1114
1115 if (status & WB_ISR_BUS_ERR) {
1116 wb_reset(sc);
1117 wb_init_locked(sc);
1118 }
1119
1120 }
1121
1122 /* Re-enable interrupts. */
1123 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1124
1125 if (ifp->if_snd.ifq_head != NULL) {
1126 wb_start_locked(ifp);
1127 }
1128
1129 WB_UNLOCK(sc);
1130 }
1131
1132 static void
1133 wb_tick(xsc)
1134 void *xsc;
1135 {
1136 struct wb_softc *sc;
1137 struct mii_data *mii;
1138
1139 sc = xsc;
1140 WB_LOCK_ASSERT(sc);
1141 mii = device_get_softc(sc->wb_miibus);
1142
1143 mii_tick(mii);
1144
1145 if (sc->wb_timer > 0 && --sc->wb_timer == 0)
1146 wb_watchdog(sc);
1147 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc);
1148 }
1149
1150 /*
1151 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1152 * pointers to the fragment pointers.
1153 */
1154 static int
1155 wb_encap(sc, c, m_head)
1156 struct wb_softc *sc;
1157 struct wb_chain *c;
1158 struct mbuf *m_head;
1159 {
1160 int frag = 0;
1161 struct wb_desc *f = NULL;
1162 int total_len;
1163 struct mbuf *m;
1164
1165 /*
1166 * Start packing the mbufs in this chain into
1167 * the fragment pointers. Stop when we run out
1168 * of fragments or hit the end of the mbuf chain.
1169 */
1170 m = m_head;
1171 total_len = 0;
1172
1173 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1174 if (m->m_len != 0) {
1175 if (frag == WB_MAXFRAGS)
1176 break;
1177 total_len += m->m_len;
1178 f = &c->wb_ptr->wb_frag[frag];
1179 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1180 if (frag == 0) {
1181 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1182 f->wb_status = 0;
1183 } else
1184 f->wb_status = WB_TXSTAT_OWN;
1185 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1186 f->wb_data = vtophys(mtod(m, vm_offset_t));
1187 frag++;
1188 }
1189 }
1190
1191 /*
1192 * Handle special case: we used up all 16 fragments,
1193 * but we have more mbufs left in the chain. Copy the
1194 * data into an mbuf cluster. Note that we don't
1195 * bother clearing the values in the other fragment
1196 * pointers/counters; it wouldn't gain us anything,
1197 * and would waste cycles.
1198 */
1199 if (m != NULL) {
1200 struct mbuf *m_new = NULL;
1201
1202 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1203 if (m_new == NULL)
1204 return(1);
1205 if (m_head->m_pkthdr.len > MHLEN) {
1206 MCLGET(m_new, M_DONTWAIT);
1207 if (!(m_new->m_flags & M_EXT)) {
1208 m_freem(m_new);
1209 return(1);
1210 }
1211 }
1212 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1213 mtod(m_new, caddr_t));
1214 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1215 m_freem(m_head);
1216 m_head = m_new;
1217 f = &c->wb_ptr->wb_frag[0];
1218 f->wb_status = 0;
1219 f->wb_data = vtophys(mtod(m_new, caddr_t));
1220 f->wb_ctl = total_len = m_new->m_len;
1221 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1222 frag = 1;
1223 }
1224
1225 if (total_len < WB_MIN_FRAMELEN) {
1226 f = &c->wb_ptr->wb_frag[frag];
1227 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1228 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1229 f->wb_ctl |= WB_TXCTL_TLINK;
1230 f->wb_status = WB_TXSTAT_OWN;
1231 frag++;
1232 }
1233
1234 c->wb_mbuf = m_head;
1235 c->wb_lastdesc = frag - 1;
1236 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1237 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1238
1239 return(0);
1240 }
1241
1242 /*
1243 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1244 * to the mbuf data regions directly in the transmit lists. We also save a
1245 * copy of the pointers since the transmit list fragment pointers are
1246 * physical addresses.
1247 */
1248
1249 static void
1250 wb_start(ifp)
1251 struct ifnet *ifp;
1252 {
1253 struct wb_softc *sc;
1254
1255 sc = ifp->if_softc;
1256 WB_LOCK(sc);
1257 wb_start_locked(ifp);
1258 WB_UNLOCK(sc);
1259 }
1260
1261 static void
1262 wb_start_locked(ifp)
1263 struct ifnet *ifp;
1264 {
1265 struct wb_softc *sc;
1266 struct mbuf *m_head = NULL;
1267 struct wb_chain *cur_tx = NULL, *start_tx;
1268
1269 sc = ifp->if_softc;
1270 WB_LOCK_ASSERT(sc);
1271
1272 /*
1273 * Check for an available queue slot. If there are none,
1274 * punt.
1275 */
1276 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1277 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1278 return;
1279 }
1280
1281 start_tx = sc->wb_cdata.wb_tx_free;
1282
1283 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1284 IF_DEQUEUE(&ifp->if_snd, m_head);
1285 if (m_head == NULL)
1286 break;
1287
1288 /* Pick a descriptor off the free list. */
1289 cur_tx = sc->wb_cdata.wb_tx_free;
1290 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1291
1292 /* Pack the data into the descriptor. */
1293 wb_encap(sc, cur_tx, m_head);
1294
1295 if (cur_tx != start_tx)
1296 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1297
1298 /*
1299 * If there's a BPF listener, bounce a copy of this frame
1300 * to him.
1301 */
1302 BPF_MTAP(ifp, cur_tx->wb_mbuf);
1303 }
1304
1305 /*
1306 * If there are no packets queued, bail.
1307 */
1308 if (cur_tx == NULL)
1309 return;
1310
1311 /*
1312 * Place the request for the upload interrupt
1313 * in the last descriptor in the chain. This way, if
1314 * we're chaining several packets at once, we'll only
1315 * get an interrupt once for the whole chain rather than
1316 * once for each packet.
1317 */
1318 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1319 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1320 sc->wb_cdata.wb_tx_tail = cur_tx;
1321
1322 if (sc->wb_cdata.wb_tx_head == NULL) {
1323 sc->wb_cdata.wb_tx_head = start_tx;
1324 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1325 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1326 } else {
1327 /*
1328 * We need to distinguish between the case where
1329 * the own bit is clear because the chip cleared it
1330 * and where the own bit is clear because we haven't
1331 * set it yet. The magic value WB_UNSET is just some
1332 * ramdomly chosen number which doesn't have the own
1333 * bit set. When we actually transmit the frame, the
1334 * status word will have _only_ the own bit set, so
1335 * the txeoc handler will be able to tell if it needs
1336 * to initiate another transmission to flush out pending
1337 * frames.
1338 */
1339 WB_TXOWN(start_tx) = WB_UNSENT;
1340 }
1341
1342 /*
1343 * Set a timeout in case the chip goes out to lunch.
1344 */
1345 sc->wb_timer = 5;
1346 }
1347
1348 static void
1349 wb_init(xsc)
1350 void *xsc;
1351 {
1352 struct wb_softc *sc = xsc;
1353
1354 WB_LOCK(sc);
1355 wb_init_locked(sc);
1356 WB_UNLOCK(sc);
1357 }
1358
1359 static void
1360 wb_init_locked(sc)
1361 struct wb_softc *sc;
1362 {
1363 struct ifnet *ifp = sc->wb_ifp;
1364 int i;
1365 struct mii_data *mii;
1366
1367 WB_LOCK_ASSERT(sc);
1368 mii = device_get_softc(sc->wb_miibus);
1369
1370 /*
1371 * Cancel pending I/O and free all RX/TX buffers.
1372 */
1373 wb_stop(sc);
1374 wb_reset(sc);
1375
1376 sc->wb_txthresh = WB_TXTHRESH_INIT;
1377
1378 /*
1379 * Set cache alignment and burst length.
1380 */
1381 #ifdef foo
1382 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1383 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1384 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1385 #endif
1386
1387 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION);
1388 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
1389 switch(sc->wb_cachesize) {
1390 case 32:
1391 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
1392 break;
1393 case 16:
1394 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
1395 break;
1396 case 8:
1397 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
1398 break;
1399 case 0:
1400 default:
1401 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
1402 break;
1403 }
1404
1405 /* This doesn't tend to work too well at 100Mbps. */
1406 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1407
1408 /* Init our MAC address */
1409 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1410 CSR_WRITE_1(sc, WB_NODE0 + i, IF_LLADDR(sc->wb_ifp)[i]);
1411 }
1412
1413 /* Init circular RX list. */
1414 if (wb_list_rx_init(sc) == ENOBUFS) {
1415 device_printf(sc->wb_dev,
1416 "initialization failed: no memory for rx buffers\n");
1417 wb_stop(sc);
1418 return;
1419 }
1420
1421 /* Init TX descriptors. */
1422 wb_list_tx_init(sc);
1423
1424 /* If we want promiscuous mode, set the allframes bit. */
1425 if (ifp->if_flags & IFF_PROMISC) {
1426 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1427 } else {
1428 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1429 }
1430
1431 /*
1432 * Set capture broadcast bit to capture broadcast frames.
1433 */
1434 if (ifp->if_flags & IFF_BROADCAST) {
1435 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1436 } else {
1437 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1438 }
1439
1440 /*
1441 * Program the multicast filter, if necessary.
1442 */
1443 wb_setmulti(sc);
1444
1445 /*
1446 * Load the address of the RX list.
1447 */
1448 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1449 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1450
1451 /*
1452 * Enable interrupts.
1453 */
1454 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1455 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1456
1457 /* Enable receiver and transmitter. */
1458 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1459 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1460
1461 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1462 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1463 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1464
1465 mii_mediachg(mii);
1466
1467 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1468 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1469
1470 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc);
1471 }
1472
1473 /*
1474 * Set media options.
1475 */
1476 static int
1477 wb_ifmedia_upd(ifp)
1478 struct ifnet *ifp;
1479 {
1480 struct wb_softc *sc;
1481
1482 sc = ifp->if_softc;
1483
1484 WB_LOCK(sc);
1485 if (ifp->if_flags & IFF_UP)
1486 wb_init_locked(sc);
1487 WB_UNLOCK(sc);
1488
1489 return(0);
1490 }
1491
1492 /*
1493 * Report current media status.
1494 */
1495 static void
1496 wb_ifmedia_sts(ifp, ifmr)
1497 struct ifnet *ifp;
1498 struct ifmediareq *ifmr;
1499 {
1500 struct wb_softc *sc;
1501 struct mii_data *mii;
1502
1503 sc = ifp->if_softc;
1504
1505 WB_LOCK(sc);
1506 mii = device_get_softc(sc->wb_miibus);
1507
1508 mii_pollstat(mii);
1509 ifmr->ifm_active = mii->mii_media_active;
1510 ifmr->ifm_status = mii->mii_media_status;
1511 WB_UNLOCK(sc);
1512 }
1513
1514 static int
1515 wb_ioctl(ifp, command, data)
1516 struct ifnet *ifp;
1517 u_long command;
1518 caddr_t data;
1519 {
1520 struct wb_softc *sc = ifp->if_softc;
1521 struct mii_data *mii;
1522 struct ifreq *ifr = (struct ifreq *) data;
1523 int error = 0;
1524
1525 switch(command) {
1526 case SIOCSIFFLAGS:
1527 WB_LOCK(sc);
1528 if (ifp->if_flags & IFF_UP) {
1529 wb_init_locked(sc);
1530 } else {
1531 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1532 wb_stop(sc);
1533 }
1534 WB_UNLOCK(sc);
1535 error = 0;
1536 break;
1537 case SIOCADDMULTI:
1538 case SIOCDELMULTI:
1539 WB_LOCK(sc);
1540 wb_setmulti(sc);
1541 WB_UNLOCK(sc);
1542 error = 0;
1543 break;
1544 case SIOCGIFMEDIA:
1545 case SIOCSIFMEDIA:
1546 mii = device_get_softc(sc->wb_miibus);
1547 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1548 break;
1549 default:
1550 error = ether_ioctl(ifp, command, data);
1551 break;
1552 }
1553
1554 return(error);
1555 }
1556
1557 static void
1558 wb_watchdog(sc)
1559 struct wb_softc *sc;
1560 {
1561 struct ifnet *ifp;
1562
1563 WB_LOCK_ASSERT(sc);
1564 ifp = sc->wb_ifp;
1565 ifp->if_oerrors++;
1566 if_printf(ifp, "watchdog timeout\n");
1567 #ifdef foo
1568 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1569 if_printf(ifp, "no carrier - transceiver cable problem?\n");
1570 #endif
1571 wb_stop(sc);
1572 wb_reset(sc);
1573 wb_init_locked(sc);
1574
1575 if (ifp->if_snd.ifq_head != NULL)
1576 wb_start_locked(ifp);
1577 }
1578
1579 /*
1580 * Stop the adapter and free any mbufs allocated to the
1581 * RX and TX lists.
1582 */
1583 static void
1584 wb_stop(sc)
1585 struct wb_softc *sc;
1586 {
1587 register int i;
1588 struct ifnet *ifp;
1589
1590 WB_LOCK_ASSERT(sc);
1591 ifp = sc->wb_ifp;
1592 sc->wb_timer = 0;
1593
1594 callout_stop(&sc->wb_stat_callout);
1595
1596 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
1597 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1598 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
1599 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
1600
1601 /*
1602 * Free data in the RX lists.
1603 */
1604 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1605 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
1606 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
1607 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
1608 }
1609 }
1610 bzero((char *)&sc->wb_ldata->wb_rx_list,
1611 sizeof(sc->wb_ldata->wb_rx_list));
1612
1613 /*
1614 * Free the TX list buffers.
1615 */
1616 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1617 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
1618 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
1619 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
1620 }
1621 }
1622
1623 bzero((char *)&sc->wb_ldata->wb_tx_list,
1624 sizeof(sc->wb_ldata->wb_tx_list));
1625
1626 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1627 }
1628
1629 /*
1630 * Stop all chip I/O so that the kernel's probe routines don't
1631 * get confused by errant DMAs when rebooting.
1632 */
1633 static void
1634 wb_shutdown(dev)
1635 device_t dev;
1636 {
1637 struct wb_softc *sc;
1638
1639 sc = device_get_softc(dev);
1640
1641 WB_LOCK(sc);
1642 wb_stop(sc);
1643 WB_UNLOCK(sc);
1644
1645 return;
1646 }
Cache object: 87461cd35d67449f157448363766c9f3
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