FreeBSD/Linux Kernel Cross Reference
sys/pci/if_wbreg.h
1 /*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD$
33 */
34
35 /*
36 * Winbond register definitions.
37 */
38
39 #define WB_BUSCTL 0x00 /* bus control */
40 #define WB_TXSTART 0x04 /* tx start demand */
41 #define WB_RXSTART 0x08 /* rx start demand */
42 #define WB_RXADDR 0x0C /* rx descriptor list start addr */
43 #define WB_TXADDR 0x10 /* tx descriptor list start addr */
44 #define WB_ISR 0x14 /* interrupt status register */
45 #define WB_NETCFG 0x18 /* network config register */
46 #define WB_IMR 0x1C /* interrupt mask */
47 #define WB_FRAMESDISCARDED 0x20 /* # of discarded frames */
48 #define WB_SIO 0x24 /* MII and ROM/EEPROM access */
49 #define WB_BOOTROMADDR 0x28
50 #define WB_TIMER 0x2C /* general timer */
51 #define WB_CURRXCTL 0x30 /* current RX descriptor */
52 #define WB_CURRXBUF 0x34 /* current RX buffer */
53 #define WB_MAR0 0x38 /* multicast filter 0 */
54 #define WB_MAR1 0x3C /* multicast filter 1 */
55 #define WB_NODE0 0x40 /* station address 0 */
56 #define WB_NODE1 0x44 /* station address 1 */
57 #define WB_BOOTROMSIZE 0x48 /* boot ROM size */
58 #define WB_CURTXCTL 0x4C /* current TX descriptor */
59 #define WB_CURTXBUF 0x50 /* current TX buffer */
60
61 /*
62 * Bus control bits.
63 */
64 #define WB_BUSCTL_RESET 0x00000001
65 #define WB_BUSCTL_ARBITRATION 0x00000002
66 #define WB_BUSCTL_SKIPLEN 0x0000007C
67 #define WB_BUSCTL_BUF_BIGENDIAN 0x00000080
68 #define WB_BUSCTL_BURSTLEN 0x00003F00
69 #define WB_BUSCTL_CACHEALIGN 0x0000C000
70 #define WB_BUSCTL_DES_BIGENDIAN 0x00100000
71 #define WB_BUSCTL_WAIT 0x00200000
72
73 #define WB_SKIPLEN_1LONG 0x00000004
74 #define WB_SKIPLEN_2LONG 0x00000008
75 #define WB_SKIPLEN_3LONG 0x00000010
76 #define WB_SKIPLEN_4LONG 0x00000020
77 #define WB_SKIPLEN_5LONG 0x00000040
78
79 #define WB_CACHEALIGN_8LONG 0x00004000
80 #define WB_CACHEALIGN_16LONG 0x00008000
81 #define WB_CACHEALIGN_32LONG 0x0000C000
82
83 #define WB_BURSTLEN_USECA 0x00000000
84 #define WB_BURSTLEN_1LONG 0x00000100
85 #define WB_BURSTLEN_2LONG 0x00000200
86 #define WB_BURSTLEN_4LONG 0x00000400
87 #define WB_BURSTLEN_8LONG 0x00000800
88 #define WB_BURSTLEN_16LONG 0x00001000
89 #define WB_BURSTLEN_32LONG 0x00002000
90
91 #define WB_BUSCTL_CONFIG (WB_CACHEALIGN_8LONG|WB_SKIPLEN_3LONG| \
92 WB_BURSTLEN_8LONG)
93
94 /*
95 * Interrupt status bits.
96 */
97 #define WB_ISR_TX_OK 0x00000001
98 #define WB_ISR_TX_IDLE 0x00000002
99 #define WB_ISR_TX_NOBUF 0x00000004
100 #define WB_ISR_RX_EARLY 0x00000008
101 #define WB_ISR_RX_ERR 0x00000010
102 #define WB_ISR_TX_UNDERRUN 0x00000020
103 #define WB_ISR_RX_OK 0x00000040
104 #define WB_ISR_RX_NOBUF 0x00000080
105 #define WB_ISR_RX_IDLE 0x00000100
106 #define WB_ISR_TX_EARLY 0x00000400
107 #define WB_ISR_TIMER_EXPIRED 0x00000800
108 #define WB_ISR_BUS_ERR 0x00002000
109 #define WB_ISR_ABNORMAL 0x00008000
110 #define WB_ISR_NORMAL 0x00010000
111 #define WB_ISR_RX_STATE 0x000E0000
112 #define WB_ISR_TX_STATE 0x00700000
113 #define WB_ISR_BUSERRTYPE 0x03800000
114
115 /*
116 * The RX_STATE and TX_STATE fields are not described anywhere in the
117 * Winbond datasheet, however it appears that the Winbond chip is an
118 * attempt at a DEC 'tulip' clone, hence the ISR register is identical
119 * to that of the tulip chip and we can steal the bit definitions from
120 * the tulip documentation.
121 */
122 #define WB_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
123 #define WB_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
124 #define WB_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
125 #define WB_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
126 #define WB_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
127 #define WB_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
128 #define WB_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
129 #define WB_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
130
131 #define WB_TXSTATE_RESET 0x00000000 /* 000 - reset */
132 #define WB_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
133 #define WB_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
134 #define WB_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
135 #define WB_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
136 #define WB_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
137 #define WB_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
138 #define WB_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
139
140 /*
141 * Network config bits.
142 */
143 #define WB_NETCFG_RX_ON 0x00000002
144 #define WB_NETCFG_RX_ALLPHYS 0x00000008
145 #define WB_NETCFG_RX_MULTI 0x00000010
146 #define WB_NETCFG_RX_BROAD 0x00000020
147 #define WB_NETCFG_RX_RUNT 0x00000040
148 #define WB_NETCFG_RX_ERR 0x00000080
149 #define WB_NETCFG_FULLDUPLEX 0x00000200
150 #define WB_NETCFG_LOOPBACK 0x00000C00
151 #define WB_NETCFG_TX_ON 0x00002000
152 #define WB_NETCFG_TX_THRESH 0x001FC000
153 #define WB_NETCFG_RX_EARLYTHRSH 0x1FE00000
154 #define WB_NETCFG_100MBPS 0x20000000
155 #define WB_NETCFG_TX_EARLY_ON 0x40000000
156 #define WB_NETCFG_RX_EARLY_ON 0x80000000
157
158 /*
159 * The tx threshold can be adjusted in increments of 32 bytes.
160 */
161 #define WB_TXTHRESH(x) ((x >> 5) << 14)
162 #define WB_TXTHRESH_CHUNK 32
163 #define WB_TXTHRESH_INIT 0 /*72*/
164
165 /*
166 * Interrupt mask bits.
167 */
168 #define WB_IMR_TX_OK 0x00000001
169 #define WB_IMR_TX_IDLE 0x00000002
170 #define WB_IMR_TX_NOBUF 0x00000004
171 #define WB_IMR_RX_EARLY 0x00000008
172 #define WB_IMR_RX_ERR 0x00000010
173 #define WB_IMR_TX_UNDERRUN 0x00000020
174 #define WB_IMR_RX_OK 0x00000040
175 #define WB_IMR_RX_NOBUF 0x00000080
176 #define WB_IMR_RX_IDLE 0x00000100
177 #define WB_IMR_TX_EARLY 0x00000400
178 #define WB_IMR_TIMER_EXPIRED 0x00000800
179 #define WB_IMR_BUS_ERR 0x00002000
180 #define WB_IMR_ABNORMAL 0x00008000
181 #define WB_IMR_NORMAL 0x00010000
182
183 #define WB_INTRS \
184 (WB_IMR_RX_OK|WB_IMR_TX_OK|WB_IMR_RX_NOBUF|WB_IMR_RX_ERR| \
185 WB_IMR_TX_NOBUF|WB_IMR_TX_UNDERRUN|WB_IMR_BUS_ERR| \
186 WB_IMR_ABNORMAL|WB_IMR_NORMAL|WB_IMR_TX_EARLY)
187 /*
188 * Serial I/O (EEPROM/ROM) bits.
189 */
190 #define WB_SIO_EE_CS 0x00000001 /* EEPROM chip select */
191 #define WB_SIO_EE_CLK 0x00000002 /* EEPROM clock */
192 #define WB_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
193 #define WB_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
194 #define WB_SIO_ROMDATA4 0x00000010
195 #define WB_SIO_ROMDATA5 0x00000020
196 #define WB_SIO_ROMDATA6 0x00000040
197 #define WB_SIO_ROMDATA7 0x00000080
198 #define WB_SIO_ROMCTL_WRITE 0x00000200
199 #define WB_SIO_ROMCTL_READ 0x00000400
200 #define WB_SIO_EESEL 0x00000800
201 #define WB_SIO_MII_CLK 0x00010000 /* MDIO clock */
202 #define WB_SIO_MII_DATAIN 0x00020000 /* MDIO data out */
203 #define WB_SIO_MII_DIR 0x00040000 /* MDIO dir */
204 #define WB_SIO_MII_DATAOUT 0x00080000 /* MDIO data in */
205
206 #define WB_EECMD_WRITE 0x140
207 #define WB_EECMD_READ 0x180
208 #define WB_EECMD_ERASE 0x1c0
209
210 /*
211 * Winbond TX/RX descriptor structure.
212 */
213
214 struct wb_desc {
215 u_int32_t wb_status;
216 u_int32_t wb_ctl;
217 u_int32_t wb_ptr1;
218 u_int32_t wb_ptr2;
219 };
220
221 #define wb_data wb_ptr1
222 #define wb_next wb_ptr2
223
224 #define WB_RXSTAT_CRCERR 0x00000002
225 #define WB_RXSTAT_DRIBBLE 0x00000004
226 #define WB_RXSTAT_MIIERR 0x00000008
227 #define WB_RXSTAT_LATEEVENT 0x00000040
228 #define WB_RXSTAT_GIANT 0x00000080
229 #define WB_RXSTAT_LASTFRAG 0x00000100
230 #define WB_RXSTAT_FIRSTFRAG 0x00000200
231 #define WB_RXSTAT_MULTICAST 0x00000400
232 #define WB_RXSTAT_RUNT 0x00000800
233 #define WB_RXSTAT_RXTYPE 0x00003000
234 #define WB_RXSTAT_RXERR 0x00008000
235 #define WB_RXSTAT_RXLEN 0x3FFF0000
236 #define WB_RXSTAT_RXCMP 0x40000000
237 #define WB_RXSTAT_OWN 0x80000000
238
239 #define WB_RXBYTES(x) ((x & WB_RXSTAT_RXLEN) >> 16)
240 #define WB_RXSTAT (WB_RXSTAT_FIRSTFRAG|WB_RXSTAT_LASTFRAG|WB_RXSTAT_OWN)
241
242 #define WB_RXCTL_BUFLEN1 0x00000FFF
243 #define WB_RXCTL_BUFLEN2 0x00FFF000
244 #define WB_RXCTL_RLINK 0x01000000
245 #define WB_RXCTL_RLAST 0x02000000
246
247 #define WB_TXSTAT_DEFER 0x00000001
248 #define WB_TXSTAT_UNDERRUN 0x00000002
249 #define WB_TXSTAT_COLLCNT 0x00000078
250 #define WB_TXSTAT_SQE 0x00000080
251 #define WB_TXSTAT_ABORT 0x00000100
252 #define WB_TXSTAT_LATECOLL 0x00000200
253 #define WB_TXSTAT_NOCARRIER 0x00000400
254 #define WB_TXSTAT_CARRLOST 0x00000800
255 #define WB_TXSTAT_TXERR 0x00001000
256 #define WB_TXSTAT_OWN 0x80000000
257
258 #define WB_TXCTL_BUFLEN1 0x000007FF
259 #define WB_TXCTL_BUFLEN2 0x003FF800
260 #define WB_TXCTL_PAD 0x00800000
261 #define WB_TXCTL_TLINK 0x01000000
262 #define WB_TXCTL_TLAST 0x02000000
263 #define WB_TXCTL_NOCRC 0x08000000
264 #define WB_TXCTL_FIRSTFRAG 0x20000000
265 #define WB_TXCTL_LASTFRAG 0x40000000
266 #define WB_TXCTL_FINT 0x80000000
267
268 #define WB_MAXFRAGS 16
269 #define WB_RX_LIST_CNT 64
270 #define WB_TX_LIST_CNT 128
271 #define WB_MIN_FRAMELEN 60
272 #define ETHER_ALIGN 2
273
274 /*
275 * A transmit 'super descriptor' is actually WB_MAXFRAGS regular
276 * descriptors clumped together. The idea here is to emulate the
277 * multi-fragment descriptor layout found in devices such as the
278 * Texas Instruments ThunderLAN and 3Com boomerang and cylone chips.
279 * The advantage to using this scheme is that it avoids buffer copies.
280 * The disadvantage is that there's a certain amount of overhead due
281 * to the fact that each 'fragment' is 16 bytes long. In my tests,
282 * this limits top speed to about 10.5MB/sec. It should be more like
283 * 11.5MB/sec. However, the upshot is that you can achieve better
284 * results on slower machines: a Pentium 200 can pump out packets at
285 * same speed as a PII 400.
286 */
287 struct wb_txdesc {
288 struct wb_desc wb_frag[WB_MAXFRAGS];
289 };
290
291 #define WB_TXNEXT(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_next
292 #define WB_TXSTATUS(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_status
293 #define WB_TXCTL(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_ctl
294 #define WB_TXDATA(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_data
295
296 #define WB_TXOWN(x) x->wb_ptr->wb_frag[0].wb_status
297
298 #define WB_UNSENT 0x1234
299
300 struct wb_list_data {
301 struct wb_desc wb_rx_list[WB_RX_LIST_CNT];
302 struct wb_txdesc wb_tx_list[WB_TX_LIST_CNT];
303 };
304
305 struct wb_chain {
306 struct wb_txdesc *wb_ptr;
307 struct mbuf *wb_mbuf;
308 struct wb_chain *wb_nextdesc;
309 u_int8_t wb_lastdesc;
310 };
311
312 struct wb_chain_onefrag {
313 struct wb_desc *wb_ptr;
314 struct mbuf *wb_mbuf;
315 struct wb_chain_onefrag *wb_nextdesc;
316 u_int8_t wb_rlast;
317 };
318
319 struct wb_chain_data {
320 u_int8_t wb_pad[WB_MIN_FRAMELEN];
321 struct wb_chain_onefrag wb_rx_chain[WB_RX_LIST_CNT];
322 struct wb_chain wb_tx_chain[WB_TX_LIST_CNT];
323
324 struct wb_chain_onefrag *wb_rx_head;
325
326 struct wb_chain *wb_tx_head;
327 struct wb_chain *wb_tx_tail;
328 struct wb_chain *wb_tx_free;
329 };
330
331 struct wb_type {
332 u_int16_t wb_vid;
333 u_int16_t wb_did;
334 char *wb_name;
335 };
336
337 struct wb_mii_frame {
338 u_int8_t mii_stdelim;
339 u_int8_t mii_opcode;
340 u_int8_t mii_phyaddr;
341 u_int8_t mii_regaddr;
342 u_int8_t mii_turnaround;
343 u_int16_t mii_data;
344 };
345
346 /*
347 * MII constants
348 */
349 #define WB_MII_STARTDELIM 0x01
350 #define WB_MII_READOP 0x02
351 #define WB_MII_WRITEOP 0x01
352 #define WB_MII_TURNAROUND 0x02
353
354 #define WB_FLAG_FORCEDELAY 1
355 #define WB_FLAG_SCHEDDELAY 2
356 #define WB_FLAG_DELAYTIMEO 3
357
358 struct wb_softc {
359 struct arpcom arpcom; /* interface info */
360 struct ifmedia ifmedia; /* media info */
361 bus_space_handle_t wb_bhandle;
362 bus_space_tag_t wb_btag;
363 struct wb_type *wb_info; /* 3Com adapter info */
364 struct wb_type *wb_pinfo; /* phy info */
365 u_int8_t wb_unit; /* interface number */
366 u_int8_t wb_type;
367 u_int8_t wb_phy_addr; /* PHY address */
368 u_int8_t wb_tx_pend; /* TX pending */
369 u_int8_t wb_want_auto;
370 u_int8_t wb_autoneg;
371 u_int16_t wb_txthresh;
372 caddr_t wb_ldata_ptr;
373 struct wb_list_data *wb_ldata;
374 struct wb_chain_data wb_cdata;
375 };
376
377 /*
378 * register space access macros
379 */
380 #define CSR_WRITE_4(sc, reg, val) \
381 bus_space_write_4(sc->wb_btag, sc->wb_bhandle, reg, val)
382 #define CSR_WRITE_2(sc, reg, val) \
383 bus_space_write_2(sc->wb_btag, sc->wb_bhandle, reg, val)
384 #define CSR_WRITE_1(sc, reg, val) \
385 bus_space_write_1(sc->wb_btag, sc->wb_bhandle, reg, val)
386
387 #define CSR_READ_4(sc, reg) \
388 bus_space_read_4(sc->wb_btag, sc->wb_bhandle, reg)
389 #define CSR_READ_2(sc, reg) \
390 bus_space_read_2(sc->wb_btag, sc->wb_bhandle, reg)
391 #define CSR_READ_1(sc, reg) \
392 bus_space_read_1(sc->wb_btag, sc->wb_bhandle, reg)
393
394 #define WB_TIMEOUT 1000
395
396 /*
397 * General constants that are fun to know.
398 *
399 * Winbond PCI vendor ID
400 */
401 #define WB_VENDORID 0x1050
402
403 /*
404 * Winbond device IDs.
405 */
406 #define WB_DEVICEID_840F 0x0840
407
408 /*
409 * Compex vendor ID.
410 */
411 #define CP_VENDORID 0x11F6
412
413 /*
414 * Compex device IDs.
415 */
416 #define CP_DEVICEID_RL100 0x2011
417
418 /*
419 * Texas Instruments PHY identifiers
420 */
421 #define TI_PHY_VENDORID 0x4000
422 #define TI_PHY_10BT 0x501F
423 #define TI_PHY_100VGPMI 0x502F
424
425 /*
426 * These ID values are for the NS DP83840A 10/100 PHY
427 */
428 #define NS_PHY_VENDORID 0x2000
429 #define NS_PHY_83840A 0x5C0F
430
431 /*
432 * Level 1 10/100 PHY
433 */
434 #define LEVEL1_PHY_VENDORID 0x7810
435 #define LEVEL1_PHY_LXT970 0x000F
436
437 /*
438 * Intel 82555 10/100 PHY
439 */
440 #define INTEL_PHY_VENDORID 0x0A28
441 #define INTEL_PHY_82555 0x015F
442
443 /*
444 * SEEQ 80220 10/100 PHY
445 */
446 #define SEEQ_PHY_VENDORID 0x0016
447 #define SEEQ_PHY_80220 0xF83F
448
449
450 /*
451 * PCI low memory base and low I/O base register, and
452 * other PCI registers. Note: some are only available on
453 * the 3c905B, in particular those that related to power management.
454 */
455
456 #define WB_PCI_VENDOR_ID 0x00
457 #define WB_PCI_DEVICE_ID 0x02
458 #define WB_PCI_COMMAND 0x04
459 #define WB_PCI_STATUS 0x06
460 #define WB_PCI_CLASSCODE 0x09
461 #define WB_PCI_LATENCY_TIMER 0x0D
462 #define WB_PCI_HEADER_TYPE 0x0E
463 #define WB_PCI_LOIO 0x10
464 #define WB_PCI_LOMEM 0x14
465 #define WB_PCI_BIOSROM 0x30
466 #define WB_PCI_INTLINE 0x3C
467 #define WB_PCI_INTPIN 0x3D
468 #define WB_PCI_MINGNT 0x3E
469 #define WB_PCI_MINLAT 0x0F
470 #define WB_PCI_RESETOPT 0x48
471 #define WB_PCI_EEPROM_DATA 0x4C
472
473 /* power management registers */
474 #define WB_PCI_CAPID 0xDC /* 8 bits */
475 #define WB_PCI_NEXTPTR 0xDD /* 8 bits */
476 #define WB_PCI_PWRMGMTCAP 0xDE /* 16 bits */
477 #define WB_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */
478
479 #define WB_PSTATE_MASK 0x0003
480 #define WB_PSTATE_D0 0x0000
481 #define WB_PSTATE_D1 0x0002
482 #define WB_PSTATE_D2 0x0002
483 #define WB_PSTATE_D3 0x0003
484 #define WB_PME_EN 0x0010
485 #define WB_PME_STATUS 0x8000
486
487 #define PHY_UNKNOWN 6
488
489 #define WB_PHYADDR_MIN 0x00
490 #define WB_PHYADDR_MAX 0x1F
491
492 #define PHY_BMCR 0x00
493 #define PHY_BMSR 0x01
494 #define PHY_VENID 0x02
495 #define PHY_DEVID 0x03
496 #define PHY_ANAR 0x04
497 #define PHY_LPAR 0x05
498 #define PHY_ANEXP 0x06
499
500 #define PHY_ANAR_NEXTPAGE 0x8000
501 #define PHY_ANAR_RSVD0 0x4000
502 #define PHY_ANAR_TLRFLT 0x2000
503 #define PHY_ANAR_RSVD1 0x1000
504 #define PHY_ANAR_RSVD2 0x0800
505 #define PHY_ANAR_RSVD3 0x0400
506 #define PHY_ANAR_100BT4 0x0200
507 #define PHY_ANAR_100BTXFULL 0x0100
508 #define PHY_ANAR_100BTXHALF 0x0080
509 #define PHY_ANAR_10BTFULL 0x0040
510 #define PHY_ANAR_10BTHALF 0x0020
511 #define PHY_ANAR_PROTO4 0x0010
512 #define PHY_ANAR_PROTO3 0x0008
513 #define PHY_ANAR_PROTO2 0x0004
514 #define PHY_ANAR_PROTO1 0x0002
515 #define PHY_ANAR_PROTO0 0x0001
516
517 /*
518 * These are the register definitions for the PHY (physical layer
519 * interface chip).
520 */
521 /*
522 * PHY BMCR Basic Mode Control Register
523 */
524 #define PHY_BMCR_RESET 0x8000
525 #define PHY_BMCR_LOOPBK 0x4000
526 #define PHY_BMCR_SPEEDSEL 0x2000
527 #define PHY_BMCR_AUTONEGENBL 0x1000
528 #define PHY_BMCR_RSVD0 0x0800 /* write as zero */
529 #define PHY_BMCR_ISOLATE 0x0400
530 #define PHY_BMCR_AUTONEGRSTR 0x0200
531 #define PHY_BMCR_DUPLEX 0x0100
532 #define PHY_BMCR_COLLTEST 0x0080
533 #define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */
534 #define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */
535 #define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */
536 #define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */
537 #define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */
538 #define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */
539 #define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */
540 /*
541 * RESET: 1 == software reset, 0 == normal operation
542 * Resets status and control registers to default values.
543 * Relatches all hardware config values.
544 *
545 * LOOPBK: 1 == loopback operation enabled, 0 == normal operation
546 *
547 * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
548 * Link speed is selected byt his bit or if auto-negotiation if bit
549 * 12 (AUTONEGENBL) is set (in which case the value of this register
550 * is ignored).
551 *
552 * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
553 * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
554 * determine speed and mode. Should be cleared and then set if PHY configured
555 * for no autoneg on startup.
556 *
557 * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
558 *
559 * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
560 *
561 * DUPLEX: 1 == full duplex mode, 0 == half duplex mode
562 *
563 * COLLTEST: 1 == collision test enabled, 0 == normal operation
564 */
565
566 /*
567 * PHY, BMSR Basic Mode Status Register
568 */
569 #define PHY_BMSR_100BT4 0x8000
570 #define PHY_BMSR_100BTXFULL 0x4000
571 #define PHY_BMSR_100BTXHALF 0x2000
572 #define PHY_BMSR_10BTFULL 0x1000
573 #define PHY_BMSR_10BTHALF 0x0800
574 #define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */
575 #define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */
576 #define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */
577 #define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */
578 #define PHY_BMSR_MFPRESUP 0x0040
579 #define PHY_BMSR_AUTONEGCOMP 0x0020
580 #define PHY_BMSR_REMFAULT 0x0010
581 #define PHY_BMSR_CANAUTONEG 0x0008
582 #define PHY_BMSR_LINKSTAT 0x0004
583 #define PHY_BMSR_JABBER 0x0002
584 #define PHY_BMSR_EXTENDED 0x0001
585
586 #ifdef __alpha__
587 #undef vtophys
588 #define vtophys(va) (pmap_kextract(((vm_offset_t) (va))) \
589 + 1*1024*1024*1024)
590 #endif
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