FreeBSD/Linux Kernel Cross Reference
sys/pci/if_wxreg.h
1 /* $FreeBSD$ */
2 /*
3 * Principal Author: Matthew Jacob
4 * Copyright (c) 1999, 2001 by Traakan Software
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * Additional Copyright (c) 2001 by Parag Patel
30 * under same licence for MII PHY code.
31 */
32
33 #define WX_VENDOR_INTEL 0x8086
34 #define WX_PRODUCT_82452 0x1000
35 #define WX_PRODUCT_LIVENGOOD 0x1001
36 #define WX_PRODUCT_82452_SC 0x1003
37 #define WX_PRODUCT_82543 0x1004
38 #define WX_MMBA 0x10
39 #define MWI 0x10 /* Memory Write Invalidate */
40 #define WX_CACHELINE_SIZE 0x20
41
42 /* Join PCI ID and revision into one value */
43 #define WX_WISEMAN_0 0x10000000
44 #define WX_WISEMAN_2_0 0x10000002
45 #define WX_WISEMAN_2_1 0x10000003
46 #define WX_LIVENGOOD 0x10010000
47 #define WX_LIVENGOOD_CU 0x10040002
48
49 #define IS_WISEMAN(sc) ((sc)->wx_idnrev < WX_LIVENGOOD)
50 #define IS_LIVENGOOD(sc) ((sc)->wx_idnrev >= WX_LIVENGOOD)
51 #define IS_LIVENGOOD_CU(sc) ((sc)->wx_idnrev == WX_LIVENGOOD_CU)
52
53 /*
54 * Information about this chipset gathered from a released Intel Linux driver,
55 * which was clearly a port of an NT driver.
56 */
57
58 /*
59 * Various Descriptor Structures.
60 * These are all in little endian format (for now).
61 */
62
63 typedef struct {
64 u_int32_t lowpart;
65 u_int32_t highpart;
66 } wxpa_t, wxrp_t;
67
68 /*
69 * Receive Descriptor.
70 * The base address of a receive descriptor ring must be on a 4KB boundary,
71 * and they must be allocated in multiples of 8.
72 */
73 typedef struct {
74 wxpa_t address; /* physical address of buffer */
75 u_int16_t length;
76 u_int16_t csum;
77 u_int8_t status;
78 u_int8_t errors;
79 u_int16_t special;
80 } wxrd_t;
81
82 #define RDSTAT_DD 0x1 /* descriptor done */
83 #define RDSTAT_EOP 0x2 /* end of packet */
84 #define RDSTAT_RSVD 0x74 /* reserved bits */
85
86 #define RDERR_CRC 0x1 /* CRC Error */
87 #define RDERR_SE 0x2 /* Symbol Error */
88 #define RDERR_SEQ 0x4 /* Sequence Error */
89
90 /*
91 * Transmit Descriptor
92 * The base address of a transmit descriptor ring must be on a 4KB boundary,
93 * and they must be allocated in multiples of 8.
94 */
95 typedef struct {
96 wxpa_t address;
97 u_int16_t length;
98 u_int8_t cso; /* checksum offset */
99 u_int8_t cmd; /* cmd */
100 u_int8_t status; /* status */
101 u_int8_t css; /* checksum start */
102 u_int16_t special;
103 } wxtd_t;
104
105 #define TXCMD_EOP 0x1 /* last packet */
106 #define TXCMD_IFCS 0x2 /* insert FCS */
107 #define TXCMD_IC 0x4 /* insert checksum */
108 #define TXCMD_RS 0x8 /* report status */
109 #define TXCMD_RPS 0x10 /* report packet sent */
110 #define TXCMD_SM 0x20 /* symbol mode */
111 #define TXCMD_IDE 0x80 /* interrupt delay enable */
112
113 #define TXSTS_DD 0x1 /* descriptor done */
114 #define TXSTS_EC 0x2 /* excess collisions */
115 #define TXSTS_LC 0x4 /* late collision */
116
117 /*
118 * This device can only be accessed via memory space.
119 */
120
121 /*
122 * Register access via offsets.
123 *
124 * Our brilliant friends at Intel decided to move registers offsets
125 * around from chip version to chip version. It's amazing that some
126 * deity doesn't zap these suckers. Really.
127 */
128
129 #define WXREG_DCR 0x00000000
130 #define WXREG_DSR 0x00000008
131 #define WXREG_EECDR 0x00000010
132 #define WXREG_EXCT 0x00000018
133 #define WXREG_MDIC 0x00000020
134 #define WXREG_FCAL 0x00000028
135 #define WXREG_FCAH 0x0000002C
136 #define WXREG_FCT 0x00000030
137 #define WXREG_VET 0x00000038
138 #define WXREG_RAL_BASE 0x00000040
139 #define WXREG_RAL_LO(x) (WXREG_RAL_BASE + ((x) << 3))
140 #define WXREG_RAL_HI(x) (WXREG_RAL_LO(x) + 4)
141 #define WXREG_ICR 0x000000c0
142 #define WXREG_ICS 0x000000c8
143 #define WXREG_IMASK 0x000000d0
144 #define WXREG_IMCLR 0x000000d8
145 #define WXREG_RCTL 0x00000100
146 #define WXREG_RDTR0 0x00000108
147 #define WXREG_RDTR0_LIVENGOOD 0x00002820
148 #define WXREG_RDBA0_LO 0x00000110
149 #define WXREG_RDBA0_LO_LIVENGOOD 0x00002800
150 #define WXREG_RDBA0_HI 0x00000114
151 #define WXREG_RDBA0_HI_LIVENGOOD 0x00002804
152 #define WXREG_RDLEN0 0x00000118
153 #define WXREG_RDLEN0_LIVENGOOD 0x00002808
154 #define WXREG_RDH0 0x00000120
155 #define WXREG_RDH0_LIVENGOOD 0x00002810
156 #define WXREG_RDT0 0x00000128
157 #define WXREG_RDT0_LIVENGOOD 0x00002818
158 #define WXREG_RDTR1 0x00000130
159 #define WXREG_RDBA1_LO 0x00000138
160 #define WXREG_RDBA1_HI 0x0000013C
161 #define WXREG_RDLEN1 0x00000140
162 #define WXREG_RDH1 0x00000148
163 #define WXREG_RDT1 0x00000150
164 #define WXREG_FLOW_RCV_HI 0x00000160
165 #define WXREG_FLOW_RCV_HI_LIVENGOOD 0x00002168
166 #define WXREG_FLOW_RCV_LO 0x00000168
167 #define WXREG_FLOW_RCV_LO_LIVENGOOD 0x00002160
168 #define WXREG_FLOW_XTIMER 0x00000170
169 #define WXREG_XMIT_CFGW 0x00000178
170 #define WXREG_RECV_CFGW 0x00000180
171 #define WXREG_MTA 0x00000200
172 #define WXREG_TCTL 0x00000400
173 #define WXREG_TQSA_LO 0x00000408
174 #define WXREG_TQSA_HI 0x0000040C
175 #define WXREG_TIPG 0x00000410
176 #define WXREG_TQC 0x00000418
177 #define WXREG_TDBA_LO 0x00000420
178 #define WXREG_TDBA_LO_LIVENGOOD 0x00003800
179 #define WXREG_TDBA_HI 0x00000424
180 #define WXREG_TDBA_HI_LIVENGOOD 0x00003804
181 #define WXREG_TDLEN 0x00000428
182 #define WXREG_TDLEN_LIVENGOOD 0x00003808
183 #define WXREG_TDH 0x00000430
184 #define WXREG_TDH_LIVENGOOD 0x00003810
185 #define WXREG_TDT 0x00000438
186 #define WXREG_TDT_LIVENGOOD 0x00003818
187 #define WXREG_TIDV 0x00000440
188 #define WXREG_TIDV_LIVENGOOD 0x00003820
189 #define WXREG_VFTA 0x00000600
190
191 #define WX_RAL_TAB_SIZE 16
192 #define WX_RAL_AV 0x80000000
193
194 #define WX_MC_TAB_SIZE 128
195 #define WX_VLAN_TAB_SIZE 128
196
197 /*
198 * Device Control Register Defines
199 */
200 #define WXDCR_FD 0x1 /* full duplex */
201 #define WXDCR_BEM 0x2 /* big endian mode */
202 #define WXDCR_FAIR 0x4 /* 1->Fairness, 0->Receive Priority */
203 #define WXDCR_LRST 0x8 /* Link Reset */
204 #define WXDCR_ASDE 0x20 /* ??? */
205 #define WXDCR_SLE 0x20 /* ??? */
206 #define WXDCR_SLU 0x40 /* Set Link Up */
207 #define WXDCR_ILOS 0x80 /* Invert Loss-of-Signal */
208 #define WXDCR_10BT 0x000 /* set 10BaseT */
209 #define WXDCR_100BT 0x100 /* LIVENGOOD: Set 100BaseT */
210 #define WXDCR_1000BT 0x200 /* LIVENGOOD: Set 1000BaseT */
211 #define WXDCR_SPEED_MASK 0x300
212 #define WXDCR_BEM32 0x400 /* LIVENGOOD: Set Big Endian 32 (?) */
213 #define WXDCR_FRCSPD 0x800 /* LIVENGOOD: Force Speed (?) */
214 #define WXDCR_FRCDPX 0x1000 /* LIVENGOOD: Force Full Duplex */
215
216 /*
217 * General purpose I/O pins
218 *
219 * Pin 0 is for the LED.
220 *
221 * Pin 1 is to detect loss of signal (LOS)- if it is set, we've lost signal.
222 */
223 #define WXDCR_SWDPINS_SHIFT 18
224 #define WXDCR_SWDPINS_MASK 0xf
225 #define WXDCR_SWDPIN0 (1 << 18) /* 0x00040000 - PHY reset */
226 #define WXDCR_SWDPIN1 (1 << 19) /* 0x00080000 */
227 #define WXDCR_SWDPIN2 (1 << 20) /* 0x00100000 - PHY data */
228 #define WXDCR_SWDPIN3 (1 << 21) /* 0x00200000 - PHY clk */
229 #define WXDCR_SWDPIO_SHIFT 22
230 #define WXDCR_SWDPIO_MASK 0xf
231 #define WXDCR_SWDPIO0 (1 << 22) /* 0x00400000 - PHY rst dir */
232 #define WXDCR_SWDPIO1 (1 << 23) /* 0x00800000 */
233 #define WXDCR_SWDPIO2 (1 << 24) /* 0x01000000 - PHY data dir */
234 #define WXDCR_SWDPIO3 (1 << 25) /* 0x02000000 - PHY clk dir */
235
236
237 #define WXDCR_RST 0x04000000 /* Device Reset (self clearing) */
238 #define WXDCR_RFCE 0x08000000 /* Receive Flow Control Enable */
239 #define WXDCR_TFCE 0x10000000 /* Transmit Flow Control Enable */
240 #define WXDCR_RTE 0x20000000 /* Routing Tag Enable */
241 #define WXDCR_VME 0x40000000 /* VLAN Mode Enable */
242
243 /*
244 * Device Status Register Defines
245 */
246 #define WXDSR_FD 0x1 /* full duplex */
247 #define WXDSR_LU 0x2 /* link up */
248 #define WXDSR_TXCLK 0x4 /* transmit clock running */
249 #define WXDSR_RBCLK 0x8 /* receive clock running */
250 #define WXDSR_TXOFF 0x10 /* transmit paused */
251 #define WXDSR_TBIMODE 0x20 /* LIVENGOOD: Fibre Mode */
252 #define WXDSR_100BT 0x40 /* LIVENGOOD: 100BaseT */
253 #define WXDSR_1000BT 0x80 /* LIVENGOOD: 1000BaseT */
254 #define WXDSR_ASDV 0x300 /* LIVENGOOD: ?? */
255 #define WXDSR_MTXCKOK 0x400 /* LIVENGOOD: ?? */
256 #define WXDSR_PCI66 0x800 /* LIVENGOOD: 66 MHz bus */
257 #define WXDSR_BUS64 0x1000 /* LIVENGOOD: In 64 bit slot */
258
259 /*
260 * EEPROM Register Defines
261 */
262 #define WXEECD_SK 0x1 /* enable clock */
263 #define WXEECD_CS 0x2 /* chip select */
264 #define WXEECD_DI 0x4 /* data input */
265 #define WXEECD_DO 0x8 /* data output */
266
267 #define EEPROM_READ_OPCODE 0x6
268
269 /*
270 * Constant Flow Control Frame MAC Address and Type values.
271 */
272 #define FC_FRM_CONST_LO 0x00C28001
273 #define FC_FRM_CONST_HI 0x0100
274 #define FC_TYP_CONST 0x8808
275
276 /*
277 * Bits pertinent for the Receive Address register pairs. The low address
278 * is the low 32 bits of a 48 bit MAC address. The high address contains
279 * bits 32-47 of the 48 bit MAC address. The top bit in the high address
280 * is a 'valid' bit.
281 */
282 #define WXRAH_RDR1 0x40000000 /* second receive descriptor ring */
283 #define WXRAH_VALID 0x80000000
284
285 /*
286 * Interrupt Cause Bits
287 */
288 #define WXISR_TXDW 0x1 /* transmit descriptor written back */
289 #define WXISR_TXQE 0x2 /* transmit queue empty */
290 #define WXISR_LSC 0x4 /* link status change */
291 #define WXISR_RXSEQ 0x8 /* receive sequence error */
292 #define WXISR_RXDMT0 0x10 /* receiver ring 0 getting empty */
293 #define WXISR_RXDMT1 0x20 /* receiver ring 1 getting empty */
294 #define WXISR_RXO 0x40 /* receiver overrun */
295 #define WXISR_RXT0 0x80 /* ring 0 receiver timer interrupt */
296 #define WXISR_RXT1 0x100 /* ring 1 receiver timer interrupt */
297 #define WXISR_PCIE 0x200 /* ?? Probably PCI interface error... */
298 #define WXISR_MDIAC 0x200
299 #define WXISR_RXCFG 0x400
300 #define WXISR_GPI_EN0 0x800
301 #define WXISR_GPI_EN1 0x1000 /* appears to be PHY intr line */
302 #define WXISR_GPI_EN2 0x2000
303 #define WXISR_GPI_EN3 0x4000
304
305 #define WXIENABLE_DEFAULT \
306 (WXISR_RXO | WXISR_RXT0 | WXISR_RXDMT0 | WXISR_RXSEQ | WXISR_TXDW |\
307 WXISR_LSC | WXISR_PCIE | WXISR_GPI_EN1)
308
309 #define WXDISABLE 0xffffffff
310
311 /*
312 * Receive Control Register bits.
313 */
314
315 #define WXRCTL_RST 0x1 /* receiver reset */
316 #define WXRCTL_EN 0x2 /* receiver enable */
317 #define WXRCTL_SBP 0x4 /* store bad packets */
318 #define WXRCTL_UPE 0x8 /* unicast promiscuos mode */
319 #define WXRCTL_MPE 0x10 /* multicast promiscuous mode */
320 #define WXRCTL_LPE 0x20 /* large packet enable */
321 #define WXRCTL_BAM 0x8000 /* broadcast accept mode */
322 #define WXRCTL_BSEX 0x2000000 /* LIVENGOOD: Buffer Size Extension */
323
324 #define WXRCTL_2KRBUF (0 << 16) /* 2KB Receive Buffers */
325 #define WXRCTL_1KRBUF (1 << 16) /* 1KB Receive Buffers */
326 #define WXRCTL_512BRBUF (2 << 16) /* 512 Byte Receive Buffers */
327 #define WXRCTL_256BRBUF (3 << 16) /* 256 Byte Receive Buffers */
328
329 #define WXRCTL_4KRBUF (3 << 16) /* LIVENGOOD: 4KB Receive Buffers */
330 #define WXRCTL_8KRBUF (2 << 16) /* LIVENGOOD: 8KB Receive Buffers */
331 #define WXRCTL_16KRBUF (1 << 16) /* LIVENGOOD: 16KB Receive Buffers */
332
333
334 /*
335 * Receive Delay Timer Register bits.
336 */
337 #define WXRDTR_FPD 0x80000000 /* flush partial descriptor */
338
339 /*
340 * Transmit Configuration Word defines
341 */
342 #define WXTXCW_FD 0x00000020 /* Full Duplex */
343 #define WXTXCW_PMASK 0x00000180 /* pause mask */
344 #define WXTXCW_ANE 0x80000000 /* AutoNegotiate */
345 #define WXTXCW_DEFAULT 0x800001A0
346
347 /*
348 * Transmit Control Register defines.
349 */
350 #define WXTCTL_RST 0x1 /* transmitter reset */
351 #define WXTCTL_EN 0x2 /* transmitter enable */
352 #define WXTCTL_PSP 0x8 /* pad short packets */
353 #define WXTCTL_CT(x) (((x) & 0xff) << 4) /* 4:11 - Collision Threshold */
354 #define WXTCTL_COLD(x) (((x) & 0x3ff) << 12) /* 12:21 - Collision Distance */
355 #define WXTCTL_SWXOFF (1 << 22) /* Software XOFF */
356
357 #define WX_COLLISION_THRESHOLD 15
358 #define WX_FDX_COLLISION_DX 64
359 #define WX_HDX_COLLISION_DX 512
360
361 /*
362 * MDI control register bits - (best-guess)
363 */
364 #define WXMDIC_WRITE 0x04000000
365 #define WXMDIC_READ 0x08000000
366 #define WXMDIC_READY 0x10000000
367 #define WXMDIC_INTR 0x20000000
368 #define WXMDIC_ERR 0x40000000
369 #define WXMDIC_REGADDR_MASK 0x001F0000
370 #define WXMDIC_REGADDR_SHIFT 16
371 #define WXMDIC_PHYADDR_MASK 0x03E00000
372 #define WXMDIC_PHYADDR_SHIFT 21
373 #define WXMDIC_DATA_MASK 0x0000FFFF
374
375 /*
376 * EXCT control register bits
377 */
378 #define WXEXCT_GPI_EN0 0x00000001
379 #define WXEXCT_GPI_EN1 0x00000002
380 #define WXEXCT_GPI_EN2 0x00000004
381 #define WXEXCT_GPI_EN3 0x00000008
382 #define WXEXCT_SWDPIN4 0x00000010
383 #define WXEXCT_SWDPIN5 0x00000020
384 #define WXEXCT_SWDPIN6 0x00000040
385 #define WXEXCT_SWDPIN7 0x00000080
386 #define WXEXCT_SWDPIO4 0x00000100
387 #define WXEXCT_SWDPIO5 0x00000200
388 #define WXEXCT_SWDPIO6 0x00000400
389 #define WXEXCT_SWDPIO7 0x00000800
390 #define WXEXCT_ASDCHK 0x00001000
391 #define WXEXCT_EE_RST 0x00002000
392 #define WXEXCT_IPS 0x00004000
393 #define WXEXCT_SPD_BYPS 0x00008000
394
395 /*
396 * PHY access using GPIO pins
397 */
398 #define WXPHY_RESET_DIR WXDCR_SWDPIO0
399 #define WXPHY_RESET WXDCR_SWDPIN0
400 #define WXPHY_MDIO_DIR WXDCR_SWDPIO2
401 #define WXPHY_MDIO WXDCR_SWDPIN2
402 #define WXPHY_MDC_DIR WXDCR_SWDPIO3
403 #define WXPHY_MDC WXDCR_SWDPIN3
404 #define WXPHY_RESET_DIR4 WXEXCT_SWDPIO4
405 #define WXPHY_RESET4 WXEXCT_SWDPIN4
406
407 /*
408 * PHY commands
409 */
410 #define WXPHYC_PREAMBLE 0xFFFFFFFF
411 #define WXPHYC_PREAMBLE_LEN 32
412 #define WXPHYC_SOF 0x01
413 #define WXPHYC_READ 0x02
414 #define WXPHYC_WRITE 0x01
415 #define WXPHYC_TURNAROUND 0x02
416
417 /*
418 * Receive Configuration Word defines
419 */
420
421 #define WXRXCW_CWMASK 0x0000ffff
422 #define WXRXCW_NC 0x04000000
423 #define WXRXCW_IV 0x08000000
424 #define WXRXCW_CC 0x10000000
425 #define WXRXCW_C 0x20000000
426 #define WXRXCW_SYNCH 0x40000000
427 #define WXRXCW_ANC 0x80000000
428
429 /*
430 * Miscellaneous
431 */
432 #define WX_EEPROM_MAC_OFF 0
433
434 /*
435 * Offset for Initialization Control Word #1
436 */
437 #define WX_EEPROM_CTLR1_OFF 0xA
438 #define WX_EEPROM_CTLR1_FD (1 << 10)
439 #define WX_EEPROM_CTLR1_SWDPIO_SHIFT 5
440 #define WX_EEPROM_CTLR1_ILOS (1 << 4)
441
442 #define WX_EEPROM_CTLR2_OFF 0xF
443 #define WX_EEPROM_CTLR2_SWDPIO 0xF0
444 #define WX_EEPROM_EXT_SHIFT 4
445
446
447 #define WX_XTIMER_DFLT 0x100
448 #define WX_RCV_FLOW_HI_DFLT 0x8000
449 #define WX_RCV_FLOW_LO_DFLT 0x4000
450
451 #define WX_WISEMAN_TIPG_DFLT (10 | (2 << 10) | (10 << 20))
452 #define WX_LIVENGOOD_TIPG_DFLT (6 | (8 << 10) | (6 << 20))
453 #define WX_LIVENGOOD_CU_TIPG_DFLT (8 | (8 << 10) | (6 << 20))
454
455 #define WX_CRC_LENGTH 4
456
457
458 /*
459 * Hardware cannot transmit less than 16 bytes. It also cannot
460 * successfully receive less than 60 bytes.
461 */
462 #define WX_MIN_XPKT_SIZE 16
463 #define WX_MIN_RPKT_SIZE 60
464 #define WX_MAX_PKT_SIZE 1514
465 #define WX_MAX_PKT_SIZE_JUMBO 9014
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