Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_wxvar.h
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1 /* $FreeBSD$ */ 2 /* 3 * Principal Author: Matthew Jacob 4 * Copyright (c) 1999, 2001 by Traakan Software 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * Additional Copyright (c) 2001 by Parag Patel 30 * under same licence for MII PHY code. 31 */ 32 33 /* 34 * Softc definitions for the Intel Gigabit Ethernet driver. 35 * 36 * Guidance and inspiration from David Greenman's 37 * if_fxp driver gratefully acknowledged here. 38 */ 39 40 /* 41 * Platform specific defines and inline functions go here. 42 * Look further below for more generic structures. 43 */ 44 45 /* 46 * Enable for FreeBSD 5.0 SMP code 47 */ 48 /* #define SMPNG 1 */ 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/protosw.h> 54 #include <sys/socket.h> 55 #include <sys/malloc.h> 56 #include <sys/kernel.h> 57 #include <net/if.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #ifdef NS 61 #include <netns/ns.h> 62 #include <netns/ns_if.h> 63 #endif 64 #include <net/bpf.h> 65 #include <sys/sockio.h> 66 #include <sys/bus.h> 67 #include <machine/bus.h> 68 #include <sys/rman.h> 69 #include <machine/resource.h> 70 #include <net/ethernet.h> 71 #include <net/if_arp.h> 72 #include <vm/vm.h> 73 #include <vm/pmap.h> 74 #include <machine/clock.h> 75 #include <pci/pcivar.h> 76 #include <pci/pcireg.h> 77 #include <pci/if_wxreg.h> 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 #include <sys/sysctl.h> 81 82 #define NBPFILTER 1 83 84 MODULE_DEPEND(wx, miibus, 1, 1, 1); 85 #include "miibus_if.h" 86 87 #include "opt_bdg.h" 88 #ifdef BRIDGE 89 #include <net/if_types.h> 90 #include <net/bridge.h> 91 #endif 92 93 struct wxmdvar { 94 /* 95 * arpcom must be first 96 */ 97 struct arpcom arpcom; /* per-interface network data */ 98 struct device * dev; /* backpointer to device */ 99 struct resource * mem; /* resource descriptor for registers */ 100 struct resource * irq; /* resource descriptor for interrupt */ 101 void * ih; /* interrupt handler cookie */ 102 u_int16_t cmdw; 103 struct callout_handle sch; /* handle for timeouts */ 104 char name[8]; 105 bus_space_tag_t st; /* bus space tag */ 106 bus_space_handle_t sh; /* bus space handle */ 107 struct ifmedia ifm; 108 device_t miibus; 109 struct wx_softc * next; 110 #ifdef SMPNG 111 struct mtx wxmtx; 112 #else 113 int spl; 114 #endif 115 }; 116 #define wx_dev w.dev 117 #define wx_enaddr w.arpcom.ac_enaddr 118 #define wx_cmdw w.cmdw 119 #define wx_media w.ifm 120 #define wx_next w.next 121 122 #define wx_if w.arpcom.ac_if 123 #define wx_name w.name 124 #define wx_mtx w.wxmtx 125 126 #define IOCTL_CMD_TYPE u_long 127 #define WXMALLOC(len) malloc(len, M_DEVBUF, M_NOWAIT) 128 #define WXFREE(ptr) free(ptr, M_DEVBUF) 129 #define SOFTC_IFP(ifp) ifp->if_softc 130 #define WX_BPFTAP_ARG(ifp) ifp 131 #define VTIMEOUT(sc, func, arg, time) (void) timeout(func, arg, time) 132 #define TIMEOUT(sc, func, arg, time) (sc)->w.sch = timeout(func, arg, time) 133 #define UNTIMEOUT(f, arg, sc) untimeout(f, arg, (sc)->w.sch) 134 #define INLINE __inline 135 #ifdef SMPNG 136 #define WX_LOCK(_sc) mtx_lock(&(_sc)->wx_mtx) 137 #define WX_UNLOCK(_sc) mtx_unlock(&(_sc)->wx_mtx) 138 #define WX_ILOCK(_sc) mtx_lock(&(_sc)->wx_mtx) 139 #define WX_IUNLK(_sc) mtx_unlock(&(_sc)->wx_mtx) 140 #else 141 #define WX_LOCK(_sc) _sc->w.spl = splimp() 142 #define WX_UNLOCK(_sc) splx(_sc->w.spl) 143 #define WX_ILOCK(_sc) 144 #define WX_IUNLK(_sc) 145 #endif 146 #define WX_SOFTC_FROM_MII_ARG(x) device_get_softc(x) 147 #define WX_MII_FROM_SOFTC(x) device_get_softc((x)->w.miibus) 148 149 150 #define READ_CSR(sc, reg) \ 151 bus_space_read_4((sc)->w.st, (sc)->w.sh, (reg)) 152 #define WRITE_CSR(sc, reg, val) \ 153 bus_space_write_4((sc)->w.st, (sc)->w.sh, (reg), (val)) 154 155 /* 156 * Transmit soft descriptor, used to manage packets as they come in. 157 */ 158 typedef struct rxpkt { 159 struct mbuf *dptr; /* pointer to receive frame */ 160 u_int32_t dma_addr; /* dma address */ 161 } rxpkt_t; 162 163 164 /* 165 * Transmit soft descriptor, used to manage packets as they are transmitted. 166 */ 167 typedef struct txpkt { 168 struct txpkt *next; /* next in a chain */ 169 struct mbuf *dptr; /* pointer to mbuf being sent */ 170 u_int32_t sidx; /* start index */ 171 u_int32_t eidx; /* end index */ 172 } txpkt_t; 173 174 175 typedef struct wx_softc { 176 /* 177 * OS dependent storage... must be first... 178 */ 179 struct wxmdvar w; 180 181 /* 182 * misc goodies 183 */ 184 u_int32_t : 22, 185 wx_needreinit : 1, 186 wx_mii : 1, /* non-zero if we have a PHY */ 187 wx_no_flow : 1, 188 wx_ilos : 1, 189 wx_no_ilos : 1, 190 wx_verbose : 1, 191 wx_debug : 1, 192 ane_failed : 1, 193 linkup : 1, 194 all_mcasts : 1; 195 u_int32_t wx_idnrev; /* chip revision && PCI ID */ 196 u_int16_t wx_cfg1; 197 u_int16_t wx_unused; 198 u_int32_t wx_ienable; /* current ienable to use */ 199 u_int32_t wx_dcr; /* dcr used */ 200 u_int32_t wx_icr; /* last icr */ 201 202 /* 203 * Statistics, soft && hard 204 */ 205 u_int32_t wx_intr; 206 u_int32_t wx_linkintr; 207 u_int32_t wx_rxintr; 208 u_int32_t wx_txqe; 209 u_int32_t wx_xmitgc; 210 u_int32_t wx_xmitpullup; 211 u_int32_t wx_xmitcluster; 212 u_int32_t wx_xmitputback; 213 u_int32_t wx_xmitwanted; 214 u_int32_t wx_xmitblocked; 215 u_int32_t wx_xmitrunt; 216 u_int32_t wx_rxnobuf; 217 u_int32_t wx_oddpkt; 218 219 /* 220 * Soft copies of multicast addresses. We're only 221 * using (right now) the rest of the receive address 222 * registers- not the hashed multicast table. 223 */ 224 u_int8_t wx_mcaddr[WX_RAL_TAB_SIZE-1][6]; 225 u_int8_t wx_nmca; /* # active multicast addrs */ 226 227 228 /* 229 * Receive Management 230 * We have software and shared memory rings in a buddy store format. 231 */ 232 wxrd_t *rdescriptors; /* receive descriptor ring */ 233 rxpkt_t *rbase; /* base of soft rdesc list */ 234 u_int16_t rnxt; /* next descriptor to check */ 235 u_int16_t _pad; 236 struct mbuf *rpending; /* pending partial packet */ 237 238 /* 239 * Transmit Management 240 * We have software and shared memory rings in a buddy store format. 241 */ 242 txpkt_t *tbase; /* base of soft soft management */ 243 txpkt_t *tbsyf, *tbsyl; /* linked busy list */ 244 wxtd_t *tdescriptors; /* transmit descriptor ring */ 245 u_int16_t tnxtfree; /* next free index (circular) */ 246 u_int16_t tactive; /* # active */ 247 } wx_softc_t; 248 249 /* 250 * We offset the the receive frame header by two bytes so that the actual 251 * payload is 32 bit aligned. On platforms that require strict structure 252 * alignment, this means that the ethernet frame header may have to be shifted 253 * to align it at interrupt time, but because it's such a small amount 254 * (fourteen bytes) and processors have gotten pretty fast, that's okay. 255 * It may even turn out on some platforms that this doesn't have to happen. 256 */ 257 #define WX_RX_OFFSET_VALUE 2 258 259 /* 260 * Tunable Parameters. 261 * 262 * Descriptor lengths must be in multiples of 8. 263 */ 264 #define WX_MAX_TDESC 256 /* number of transmit descriptors */ 265 #define T_NXT_IDX(x) ((x + 1) & (WX_MAX_TDESC - 1)) 266 #define T_PREV_IDX(x) ((x - 1) & (WX_MAX_TDESC - 1)) 267 #define WX_MAX_RDESC 256 /* number of receive descriptors */ 268 #ifdef PADDED_CELL 269 #define RXINCR 2 270 #else 271 #define RXINCR 1 272 #endif 273 #define R_NXT_IDX(x) ((x + RXINCR) & (WX_MAX_RDESC - 1)) 274 #define R_PREV_IDX(x) ((x - RXINCR) & (WX_MAX_RDESC - 1)) 275 276 /* 277 * Link Up timeout, in milliseconds. 278 */ 279 280 #define WX_LINK_UP_TIMEOUT 500
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