FreeBSD/Linux Kernel Cross Reference
sys/pci/if_xl.c
1 /*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: releng/5.0/sys/pci/if_xl.c 106936 2002-11-14 23:49:09Z sam $
33 */
34
35 /*
36 * 3Com 3c90x Etherlink XL PCI NIC driver
37 *
38 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
39 * bus-master chips (3c90x cards and embedded controllers) including
40 * the following:
41 *
42 * 3Com 3c900-TPO 10Mbps/RJ-45
43 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
44 * 3Com 3c905-TX 10/100Mbps/RJ-45
45 * 3Com 3c905-T4 10/100Mbps/RJ-45
46 * 3Com 3c900B-TPO 10Mbps/RJ-45
47 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
48 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
49 * 3Com 3c900B-FL 10Mbps/Fiber-optic
50 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
51 * 3Com 3c905B-TX 10/100Mbps/RJ-45
52 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
53 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
54 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
55 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
56 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
57 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
58 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
59 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
60 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
61 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
62 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
66 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
67 * Dell on-board 3c920 10/100Mbps/RJ-45
68 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
69 * Dell Latitude laptop docking station embedded 3c905-TX
70 *
71 * Written by Bill Paul <wpaul@ctr.columbia.edu>
72 * Electrical Engineering Department
73 * Columbia University, New York City
74 */
75
76 /*
77 * The 3c90x series chips use a bus-master DMA interface for transfering
78 * packets to and from the controller chip. Some of the "vortex" cards
79 * (3c59x) also supported a bus master mode, however for those chips
80 * you could only DMA packets to/from a contiguous memory buffer. For
81 * transmission this would mean copying the contents of the queued mbuf
82 * chain into a an mbuf cluster and then DMAing the cluster. This extra
83 * copy would sort of defeat the purpose of the bus master support for
84 * any packet that doesn't fit into a single mbuf.
85 *
86 * By contrast, the 3c90x cards support a fragment-based bus master
87 * mode where mbuf chains can be encapsulated using TX descriptors.
88 * This is similar to other PCI chips such as the Texas Instruments
89 * ThunderLAN and the Intel 82557/82558.
90 *
91 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
92 * bus master chips because they maintain the old PIO interface for
93 * backwards compatibility, but starting with the 3c905B and the
94 * "cyclone" chips, the compatibility interface has been dropped.
95 * Since using bus master DMA is a big win, we use this driver to
96 * support the PCI "boomerang" chips even though they work with the
97 * "vortex" driver in order to obtain better performance.
98 *
99 * This driver is in the /sys/pci directory because it only supports
100 * PCI-based NICs.
101 */
102
103 #include <sys/param.h>
104 #include <sys/systm.h>
105 #include <sys/sockio.h>
106 #include <sys/mbuf.h>
107 #include <sys/malloc.h>
108 #include <sys/kernel.h>
109 #include <sys/socket.h>
110
111 #include <net/if.h>
112 #include <net/if_arp.h>
113 #include <net/ethernet.h>
114 #include <net/if_dl.h>
115 #include <net/if_media.h>
116
117 #include <net/bpf.h>
118
119 #include <vm/vm.h> /* for vtophys */
120 #include <vm/pmap.h> /* for vtophys */
121 #include <machine/bus_memio.h>
122 #include <machine/bus_pio.h>
123 #include <machine/bus.h>
124 #include <machine/resource.h>
125 #include <sys/bus.h>
126 #include <sys/rman.h>
127
128 #include <dev/mii/mii.h>
129 #include <dev/mii/miivar.h>
130
131 #include <pci/pcireg.h>
132 #include <pci/pcivar.h>
133
134 MODULE_DEPEND(xl, miibus, 1, 1, 1);
135
136 /* "controller miibus0" required. See GENERIC if you get errors here. */
137 #include "miibus_if.h"
138
139 /*
140 * The following #define causes the code to use PIO to access the
141 * chip's registers instead of memory mapped mode. The reason PIO mode
142 * is on by default is that the Etherlink XL manual seems to indicate
143 * that only the newer revision chips (3c905B) support both PIO and
144 * memory mapped access. Since we want to be compatible with the older
145 * bus master chips, we use PIO here. If you comment this out, the
146 * driver will use memory mapped I/O, which may be faster but which
147 * might not work on some devices.
148 */
149 #define XL_USEIOSPACE
150
151 #include <pci/if_xlreg.h>
152
153 #if !defined(lint)
154 static const char rcsid[] =
155 "$FreeBSD: releng/5.0/sys/pci/if_xl.c 106936 2002-11-14 23:49:09Z sam $";
156 #endif
157
158 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
159
160 /*
161 * Various supported device vendors/types and their names.
162 */
163 static struct xl_type xl_devs[] = {
164 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
165 "3Com 3c900-TPO Etherlink XL" },
166 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
167 "3Com 3c900-COMBO Etherlink XL" },
168 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
169 "3Com 3c905-TX Fast Etherlink XL" },
170 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
171 "3Com 3c905-T4 Fast Etherlink XL" },
172 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
173 "3Com 3c900B-TPO Etherlink XL" },
174 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
175 "3Com 3c900B-COMBO Etherlink XL" },
176 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
177 "3Com 3c900B-TPC Etherlink XL" },
178 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
179 "3Com 3c900B-FL Etherlink XL" },
180 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
181 "3Com 3c905B-TX Fast Etherlink XL" },
182 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
183 "3Com 3c905B-T4 Fast Etherlink XL" },
184 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
185 "3Com 3c905B-FX/SC Fast Etherlink XL" },
186 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
187 "3Com 3c905B-COMBO Fast Etherlink XL" },
188 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
189 "3Com 3c905C-TX Fast Etherlink XL" },
190 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
191 "3Com 3c980 Fast Etherlink XL" },
192 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
193 "3Com 3c980C Fast Etherlink XL" },
194 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
195 "3Com 3cSOHO100-TX OfficeConnect" },
196 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
197 "3Com 3c450-TX HomeConnect" },
198 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
199 "3Com 3c556 Fast Etherlink XL" },
200 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
201 "3Com 3c556B Fast Etherlink XL" },
202 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
203 "3Com 3c575TX Fast Etherlink XL" },
204 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
205 "3Com 3c575B Fast Etherlink XL" },
206 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
207 "3Com 3c575C Fast Etherlink XL" },
208 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
209 "3Com 3c656 Fast Etherlink XL" },
210 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
211 "3Com 3c656B Fast Etherlink XL" },
212 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
213 "3Com 3c656C Fast Etherlink XL" },
214 { 0, 0, NULL }
215 };
216
217 static int xl_probe (device_t);
218 static int xl_attach (device_t);
219 static int xl_detach (device_t);
220
221 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *);
222 static void xl_stats_update (void *);
223 static int xl_encap (struct xl_softc *, struct xl_chain *,
224 struct mbuf *);
225 static int xl_encap_90xB (struct xl_softc *, struct xl_chain *,
226 struct mbuf *);
227
228 static void xl_rxeof (struct xl_softc *);
229 static int xl_rx_resync (struct xl_softc *);
230 static void xl_txeof (struct xl_softc *);
231 static void xl_txeof_90xB (struct xl_softc *);
232 static void xl_txeoc (struct xl_softc *);
233 static void xl_intr (void *);
234 static void xl_start (struct ifnet *);
235 static void xl_start_90xB (struct ifnet *);
236 static int xl_ioctl (struct ifnet *, u_long, caddr_t);
237 static void xl_init (void *);
238 static void xl_stop (struct xl_softc *);
239 static void xl_watchdog (struct ifnet *);
240 static void xl_shutdown (device_t);
241 static int xl_suspend (device_t);
242 static int xl_resume (device_t);
243
244 static int xl_ifmedia_upd (struct ifnet *);
245 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
246
247 static int xl_eeprom_wait (struct xl_softc *);
248 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int);
249 static void xl_mii_sync (struct xl_softc *);
250 static void xl_mii_send (struct xl_softc *, u_int32_t, int);
251 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *);
252 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *);
253
254 static void xl_setcfg (struct xl_softc *);
255 static void xl_setmode (struct xl_softc *, int);
256 static u_int8_t xl_calchash (caddr_t);
257 static void xl_setmulti (struct xl_softc *);
258 static void xl_setmulti_hash (struct xl_softc *);
259 static void xl_reset (struct xl_softc *);
260 static int xl_list_rx_init (struct xl_softc *);
261 static int xl_list_tx_init (struct xl_softc *);
262 static int xl_list_tx_init_90xB (struct xl_softc *);
263 static void xl_wait (struct xl_softc *);
264 static void xl_mediacheck (struct xl_softc *);
265 static void xl_choose_xcvr (struct xl_softc *, int);
266 #ifdef notdef
267 static void xl_testpacket (struct xl_softc *);
268 #endif
269
270 static int xl_miibus_readreg (device_t, int, int);
271 static int xl_miibus_writereg (device_t, int, int, int);
272 static void xl_miibus_statchg (device_t);
273 static void xl_miibus_mediainit (device_t);
274
275 #ifdef XL_USEIOSPACE
276 #define XL_RES SYS_RES_IOPORT
277 #define XL_RID XL_PCI_LOIO
278 #else
279 #define XL_RES SYS_RES_MEMORY
280 #define XL_RID XL_PCI_LOMEM
281 #endif
282
283 static device_method_t xl_methods[] = {
284 /* Device interface */
285 DEVMETHOD(device_probe, xl_probe),
286 DEVMETHOD(device_attach, xl_attach),
287 DEVMETHOD(device_detach, xl_detach),
288 DEVMETHOD(device_shutdown, xl_shutdown),
289 DEVMETHOD(device_suspend, xl_suspend),
290 DEVMETHOD(device_resume, xl_resume),
291
292 /* bus interface */
293 DEVMETHOD(bus_print_child, bus_generic_print_child),
294 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
295
296 /* MII interface */
297 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
298 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
299 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
300 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
301
302 { 0, 0 }
303 };
304
305 static driver_t xl_driver = {
306 "xl",
307 xl_methods,
308 sizeof(struct xl_softc)
309 };
310
311 static devclass_t xl_devclass;
312
313 DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, 0, 0);
314 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0);
315 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
316
317 /*
318 * Murphy's law says that it's possible the chip can wedge and
319 * the 'command in progress' bit may never clear. Hence, we wait
320 * only a finite amount of time to avoid getting caught in an
321 * infinite loop. Normally this delay routine would be a macro,
322 * but it isn't called during normal operation so we can afford
323 * to make it a function.
324 */
325 static void
326 xl_wait(sc)
327 struct xl_softc *sc;
328 {
329 register int i;
330
331 for (i = 0; i < XL_TIMEOUT; i++) {
332 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
333 break;
334 }
335
336 if (i == XL_TIMEOUT)
337 printf("xl%d: command never completed!\n", sc->xl_unit);
338
339 return;
340 }
341
342 /*
343 * MII access routines are provided for adapters with external
344 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
345 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
346 * Note: if you don't perform the MDIO operations just right,
347 * it's possible to end up with code that works correctly with
348 * some chips/CPUs/processor speeds/bus speeds/etc but not
349 * with others.
350 */
351 #define MII_SET(x) \
352 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
353 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
354
355 #define MII_CLR(x) \
356 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
357 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
358
359 /*
360 * Sync the PHYs by setting data bit and strobing the clock 32 times.
361 */
362 static void
363 xl_mii_sync(sc)
364 struct xl_softc *sc;
365 {
366 register int i;
367
368 XL_SEL_WIN(4);
369 MII_SET(XL_MII_DIR|XL_MII_DATA);
370
371 for (i = 0; i < 32; i++) {
372 MII_SET(XL_MII_CLK);
373 MII_CLR(XL_MII_CLK);
374 }
375
376 return;
377 }
378
379 /*
380 * Clock a series of bits through the MII.
381 */
382 static void
383 xl_mii_send(sc, bits, cnt)
384 struct xl_softc *sc;
385 u_int32_t bits;
386 int cnt;
387 {
388 int i;
389
390 XL_SEL_WIN(4);
391 MII_CLR(XL_MII_CLK);
392
393 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
394 if (bits & i) {
395 MII_SET(XL_MII_DATA);
396 } else {
397 MII_CLR(XL_MII_DATA);
398 }
399 MII_CLR(XL_MII_CLK);
400 MII_SET(XL_MII_CLK);
401 }
402 }
403
404 /*
405 * Read an PHY register through the MII.
406 */
407 static int
408 xl_mii_readreg(sc, frame)
409 struct xl_softc *sc;
410 struct xl_mii_frame *frame;
411
412 {
413 int i, ack;
414
415 XL_LOCK(sc);
416
417 /*
418 * Set up frame for RX.
419 */
420 frame->mii_stdelim = XL_MII_STARTDELIM;
421 frame->mii_opcode = XL_MII_READOP;
422 frame->mii_turnaround = 0;
423 frame->mii_data = 0;
424
425 /*
426 * Select register window 4.
427 */
428
429 XL_SEL_WIN(4);
430
431 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
432 /*
433 * Turn on data xmit.
434 */
435 MII_SET(XL_MII_DIR);
436
437 xl_mii_sync(sc);
438
439 /*
440 * Send command/address info.
441 */
442 xl_mii_send(sc, frame->mii_stdelim, 2);
443 xl_mii_send(sc, frame->mii_opcode, 2);
444 xl_mii_send(sc, frame->mii_phyaddr, 5);
445 xl_mii_send(sc, frame->mii_regaddr, 5);
446
447 /* Idle bit */
448 MII_CLR((XL_MII_CLK|XL_MII_DATA));
449 MII_SET(XL_MII_CLK);
450
451 /* Turn off xmit. */
452 MII_CLR(XL_MII_DIR);
453
454 /* Check for ack */
455 MII_CLR(XL_MII_CLK);
456 MII_SET(XL_MII_CLK);
457 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
458
459 /*
460 * Now try reading data bits. If the ack failed, we still
461 * need to clock through 16 cycles to keep the PHY(s) in sync.
462 */
463 if (ack) {
464 for(i = 0; i < 16; i++) {
465 MII_CLR(XL_MII_CLK);
466 MII_SET(XL_MII_CLK);
467 }
468 goto fail;
469 }
470
471 for (i = 0x8000; i; i >>= 1) {
472 MII_CLR(XL_MII_CLK);
473 if (!ack) {
474 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
475 frame->mii_data |= i;
476 }
477 MII_SET(XL_MII_CLK);
478 }
479
480 fail:
481
482 MII_CLR(XL_MII_CLK);
483 MII_SET(XL_MII_CLK);
484
485 XL_UNLOCK(sc);
486
487 if (ack)
488 return(1);
489 return(0);
490 }
491
492 /*
493 * Write to a PHY register through the MII.
494 */
495 static int
496 xl_mii_writereg(sc, frame)
497 struct xl_softc *sc;
498 struct xl_mii_frame *frame;
499
500 {
501 XL_LOCK(sc);
502
503 /*
504 * Set up frame for TX.
505 */
506
507 frame->mii_stdelim = XL_MII_STARTDELIM;
508 frame->mii_opcode = XL_MII_WRITEOP;
509 frame->mii_turnaround = XL_MII_TURNAROUND;
510
511 /*
512 * Select the window 4.
513 */
514 XL_SEL_WIN(4);
515
516 /*
517 * Turn on data output.
518 */
519 MII_SET(XL_MII_DIR);
520
521 xl_mii_sync(sc);
522
523 xl_mii_send(sc, frame->mii_stdelim, 2);
524 xl_mii_send(sc, frame->mii_opcode, 2);
525 xl_mii_send(sc, frame->mii_phyaddr, 5);
526 xl_mii_send(sc, frame->mii_regaddr, 5);
527 xl_mii_send(sc, frame->mii_turnaround, 2);
528 xl_mii_send(sc, frame->mii_data, 16);
529
530 /* Idle bit. */
531 MII_SET(XL_MII_CLK);
532 MII_CLR(XL_MII_CLK);
533
534 /*
535 * Turn off xmit.
536 */
537 MII_CLR(XL_MII_DIR);
538
539 XL_UNLOCK(sc);
540
541 return(0);
542 }
543
544 static int
545 xl_miibus_readreg(dev, phy, reg)
546 device_t dev;
547 int phy, reg;
548 {
549 struct xl_softc *sc;
550 struct xl_mii_frame frame;
551
552 sc = device_get_softc(dev);
553
554 /*
555 * Pretend that PHYs are only available at MII address 24.
556 * This is to guard against problems with certain 3Com ASIC
557 * revisions that incorrectly map the internal transceiver
558 * control registers at all MII addresses. This can cause
559 * the miibus code to attach the same PHY several times over.
560 */
561 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
562 return(0);
563
564 bzero((char *)&frame, sizeof(frame));
565
566 frame.mii_phyaddr = phy;
567 frame.mii_regaddr = reg;
568 xl_mii_readreg(sc, &frame);
569
570 return(frame.mii_data);
571 }
572
573 static int
574 xl_miibus_writereg(dev, phy, reg, data)
575 device_t dev;
576 int phy, reg, data;
577 {
578 struct xl_softc *sc;
579 struct xl_mii_frame frame;
580
581 sc = device_get_softc(dev);
582
583 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
584 return(0);
585
586 bzero((char *)&frame, sizeof(frame));
587
588 frame.mii_phyaddr = phy;
589 frame.mii_regaddr = reg;
590 frame.mii_data = data;
591
592 xl_mii_writereg(sc, &frame);
593
594 return(0);
595 }
596
597 static void
598 xl_miibus_statchg(dev)
599 device_t dev;
600 {
601 struct xl_softc *sc;
602 struct mii_data *mii;
603
604
605 sc = device_get_softc(dev);
606 mii = device_get_softc(sc->xl_miibus);
607
608 XL_LOCK(sc);
609
610 xl_setcfg(sc);
611
612 /* Set ASIC's duplex mode to match the PHY. */
613 XL_SEL_WIN(3);
614 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
615 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
616 else
617 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
618 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
619
620 XL_UNLOCK(sc);
621
622 return;
623 }
624
625 /*
626 * Special support for the 3c905B-COMBO. This card has 10/100 support
627 * plus BNC and AUI ports. This means we will have both an miibus attached
628 * plus some non-MII media settings. In order to allow this, we have to
629 * add the extra media to the miibus's ifmedia struct, but we can't do
630 * that during xl_attach() because the miibus hasn't been attached yet.
631 * So instead, we wait until the miibus probe/attach is done, at which
632 * point we will get a callback telling is that it's safe to add our
633 * extra media.
634 */
635 static void
636 xl_miibus_mediainit(dev)
637 device_t dev;
638 {
639 struct xl_softc *sc;
640 struct mii_data *mii;
641 struct ifmedia *ifm;
642
643 sc = device_get_softc(dev);
644 mii = device_get_softc(sc->xl_miibus);
645 ifm = &mii->mii_media;
646
647 XL_LOCK(sc);
648
649 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
650 /*
651 * Check for a 10baseFL board in disguise.
652 */
653 if (sc->xl_type == XL_TYPE_905B &&
654 sc->xl_media == XL_MEDIAOPT_10FL) {
655 if (bootverbose)
656 printf("xl%d: found 10baseFL\n", sc->xl_unit);
657 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL);
658 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL);
659 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
660 ifmedia_add(ifm,
661 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
662 } else {
663 if (bootverbose)
664 printf("xl%d: found AUI\n", sc->xl_unit);
665 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL);
666 }
667 }
668
669 if (sc->xl_media & XL_MEDIAOPT_BNC) {
670 if (bootverbose)
671 printf("xl%d: found BNC\n", sc->xl_unit);
672 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL);
673 }
674
675 XL_UNLOCK(sc);
676
677 return;
678 }
679
680 /*
681 * The EEPROM is slow: give it time to come ready after issuing
682 * it a command.
683 */
684 static int
685 xl_eeprom_wait(sc)
686 struct xl_softc *sc;
687 {
688 int i;
689
690 for (i = 0; i < 100; i++) {
691 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
692 DELAY(162);
693 else
694 break;
695 }
696
697 if (i == 100) {
698 printf("xl%d: eeprom failed to come ready\n", sc->xl_unit);
699 return(1);
700 }
701
702 return(0);
703 }
704
705 /*
706 * Read a sequence of words from the EEPROM. Note that ethernet address
707 * data is stored in the EEPROM in network byte order.
708 */
709 static int
710 xl_read_eeprom(sc, dest, off, cnt, swap)
711 struct xl_softc *sc;
712 caddr_t dest;
713 int off;
714 int cnt;
715 int swap;
716 {
717 int err = 0, i;
718 u_int16_t word = 0, *ptr;
719 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
720 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
721 /* WARNING! DANGER!
722 * It's easy to accidentally overwrite the rom content!
723 * Note: the 3c575 uses 8bit EEPROM offsets.
724 */
725 XL_SEL_WIN(0);
726
727 if (xl_eeprom_wait(sc))
728 return(1);
729
730 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
731 off += 0x30;
732
733 for (i = 0; i < cnt; i++) {
734 if (sc->xl_flags & XL_FLAG_8BITROM)
735 CSR_WRITE_2(sc, XL_W0_EE_CMD,
736 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
737 else
738 CSR_WRITE_2(sc, XL_W0_EE_CMD,
739 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
740 err = xl_eeprom_wait(sc);
741 if (err)
742 break;
743 word = CSR_READ_2(sc, XL_W0_EE_DATA);
744 ptr = (u_int16_t *)(dest + (i * 2));
745 if (swap)
746 *ptr = ntohs(word);
747 else
748 *ptr = word;
749 }
750
751 return(err ? 1 : 0);
752 }
753
754 /*
755 * This routine is taken from the 3Com Etherlink XL manual,
756 * page 10-7. It calculates a CRC of the supplied multicast
757 * group address and returns the lower 8 bits, which are used
758 * as the multicast filter position.
759 * Note: the 3c905B currently only supports a 64-bit hash table,
760 * which means we really only need 6 bits, but the manual indicates
761 * that future chip revisions will have a 256-bit hash table,
762 * hence the routine is set up to calculate 8 bits of position
763 * info in case we need it some day.
764 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have a
765 * 256 bit hash table. This means we have to use all 8 bits regardless.
766 * On older cards, the upper 2 bits will be ignored. Grrrr....
767 */
768 static u_int8_t xl_calchash(addr)
769 caddr_t addr;
770 {
771 u_int32_t crc, carry;
772 int i, j;
773 u_int8_t c;
774
775 /* Compute CRC for the address value. */
776 crc = 0xFFFFFFFF; /* initial value */
777
778 for (i = 0; i < 6; i++) {
779 c = *(addr + i);
780 for (j = 0; j < 8; j++) {
781 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
782 crc <<= 1;
783 c >>= 1;
784 if (carry)
785 crc = (crc ^ 0x04c11db6) | carry;
786 }
787 }
788
789 /* return the filter bit position */
790 return(crc & 0x000000FF);
791 }
792
793 /*
794 * NICs older than the 3c905B have only one multicast option, which
795 * is to enable reception of all multicast frames.
796 */
797 static void
798 xl_setmulti(sc)
799 struct xl_softc *sc;
800 {
801 struct ifnet *ifp;
802 struct ifmultiaddr *ifma;
803 u_int8_t rxfilt;
804 int mcnt = 0;
805
806 ifp = &sc->arpcom.ac_if;
807
808 XL_SEL_WIN(5);
809 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
810
811 if (ifp->if_flags & IFF_ALLMULTI) {
812 rxfilt |= XL_RXFILTER_ALLMULTI;
813 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
814 return;
815 }
816
817 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
818 mcnt++;
819
820 if (mcnt)
821 rxfilt |= XL_RXFILTER_ALLMULTI;
822 else
823 rxfilt &= ~XL_RXFILTER_ALLMULTI;
824
825 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
826
827 return;
828 }
829
830 /*
831 * 3c905B adapters have a hash filter that we can program.
832 */
833 static void
834 xl_setmulti_hash(sc)
835 struct xl_softc *sc;
836 {
837 struct ifnet *ifp;
838 int h = 0, i;
839 struct ifmultiaddr *ifma;
840 u_int8_t rxfilt;
841 int mcnt = 0;
842
843 ifp = &sc->arpcom.ac_if;
844
845 XL_SEL_WIN(5);
846 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
847
848 if (ifp->if_flags & IFF_ALLMULTI) {
849 rxfilt |= XL_RXFILTER_ALLMULTI;
850 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
851 return;
852 } else
853 rxfilt &= ~XL_RXFILTER_ALLMULTI;
854
855
856 /* first, zot all the existing hash bits */
857 for (i = 0; i < XL_HASHFILT_SIZE; i++)
858 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
859
860 /* now program new ones */
861 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
862 if (ifma->ifma_addr->sa_family != AF_LINK)
863 continue;
864 h = xl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
865 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h);
866 mcnt++;
867 }
868
869 if (mcnt)
870 rxfilt |= XL_RXFILTER_MULTIHASH;
871 else
872 rxfilt &= ~XL_RXFILTER_MULTIHASH;
873
874 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
875
876 return;
877 }
878
879 #ifdef notdef
880 static void
881 xl_testpacket(sc)
882 struct xl_softc *sc;
883 {
884 struct mbuf *m;
885 struct ifnet *ifp;
886
887 ifp = &sc->arpcom.ac_if;
888
889 MGETHDR(m, M_DONTWAIT, MT_DATA);
890
891 if (m == NULL)
892 return;
893
894 bcopy(&sc->arpcom.ac_enaddr,
895 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
896 bcopy(&sc->arpcom.ac_enaddr,
897 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
898 mtod(m, struct ether_header *)->ether_type = htons(3);
899 mtod(m, unsigned char *)[14] = 0;
900 mtod(m, unsigned char *)[15] = 0;
901 mtod(m, unsigned char *)[16] = 0xE3;
902 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
903 IF_ENQUEUE(&ifp->if_snd, m);
904 xl_start(ifp);
905
906 return;
907 }
908 #endif
909
910 static void
911 xl_setcfg(sc)
912 struct xl_softc *sc;
913 {
914 u_int32_t icfg;
915
916 XL_SEL_WIN(3);
917 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
918 icfg &= ~XL_ICFG_CONNECTOR_MASK;
919 if (sc->xl_media & XL_MEDIAOPT_MII ||
920 sc->xl_media & XL_MEDIAOPT_BT4)
921 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
922 if (sc->xl_media & XL_MEDIAOPT_BTX)
923 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
924
925 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
926 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
927
928 return;
929 }
930
931 static void
932 xl_setmode(sc, media)
933 struct xl_softc *sc;
934 int media;
935 {
936 u_int32_t icfg;
937 u_int16_t mediastat;
938
939 printf("xl%d: selecting ", sc->xl_unit);
940
941 XL_SEL_WIN(4);
942 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
943 XL_SEL_WIN(3);
944 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
945
946 if (sc->xl_media & XL_MEDIAOPT_BT) {
947 if (IFM_SUBTYPE(media) == IFM_10_T) {
948 printf("10baseT transceiver, ");
949 sc->xl_xcvr = XL_XCVR_10BT;
950 icfg &= ~XL_ICFG_CONNECTOR_MASK;
951 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
952 mediastat |= XL_MEDIASTAT_LINKBEAT|
953 XL_MEDIASTAT_JABGUARD;
954 mediastat &= ~XL_MEDIASTAT_SQEENB;
955 }
956 }
957
958 if (sc->xl_media & XL_MEDIAOPT_BFX) {
959 if (IFM_SUBTYPE(media) == IFM_100_FX) {
960 printf("100baseFX port, ");
961 sc->xl_xcvr = XL_XCVR_100BFX;
962 icfg &= ~XL_ICFG_CONNECTOR_MASK;
963 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
964 mediastat |= XL_MEDIASTAT_LINKBEAT;
965 mediastat &= ~XL_MEDIASTAT_SQEENB;
966 }
967 }
968
969 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
970 if (IFM_SUBTYPE(media) == IFM_10_5) {
971 printf("AUI port, ");
972 sc->xl_xcvr = XL_XCVR_AUI;
973 icfg &= ~XL_ICFG_CONNECTOR_MASK;
974 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
975 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
976 XL_MEDIASTAT_JABGUARD);
977 mediastat |= ~XL_MEDIASTAT_SQEENB;
978 }
979 if (IFM_SUBTYPE(media) == IFM_10_FL) {
980 printf("10baseFL transceiver, ");
981 sc->xl_xcvr = XL_XCVR_AUI;
982 icfg &= ~XL_ICFG_CONNECTOR_MASK;
983 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
984 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
985 XL_MEDIASTAT_JABGUARD);
986 mediastat |= ~XL_MEDIASTAT_SQEENB;
987 }
988 }
989
990 if (sc->xl_media & XL_MEDIAOPT_BNC) {
991 if (IFM_SUBTYPE(media) == IFM_10_2) {
992 printf("BNC port, ");
993 sc->xl_xcvr = XL_XCVR_COAX;
994 icfg &= ~XL_ICFG_CONNECTOR_MASK;
995 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
996 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
997 XL_MEDIASTAT_JABGUARD|
998 XL_MEDIASTAT_SQEENB);
999 }
1000 }
1001
1002 if ((media & IFM_GMASK) == IFM_FDX ||
1003 IFM_SUBTYPE(media) == IFM_100_FX) {
1004 printf("full duplex\n");
1005 XL_SEL_WIN(3);
1006 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
1007 } else {
1008 printf("half duplex\n");
1009 XL_SEL_WIN(3);
1010 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
1011 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
1012 }
1013
1014 if (IFM_SUBTYPE(media) == IFM_10_2)
1015 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
1016 else
1017 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
1018 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
1019 XL_SEL_WIN(4);
1020 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
1021 DELAY(800);
1022 XL_SEL_WIN(7);
1023
1024 return;
1025 }
1026
1027 static void
1028 xl_reset(sc)
1029 struct xl_softc *sc;
1030 {
1031 register int i;
1032
1033 XL_SEL_WIN(0);
1034 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
1035 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
1036 XL_RESETOPT_DISADVFD:0));
1037
1038 for (i = 0; i < XL_TIMEOUT; i++) {
1039 DELAY(10);
1040 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
1041 break;
1042 }
1043
1044 if (i == XL_TIMEOUT)
1045 printf("xl%d: reset didn't complete\n", sc->xl_unit);
1046
1047 /* Reset TX and RX. */
1048 /* Note: the RX reset takes an absurd amount of time
1049 * on newer versions of the Tornado chips such as those
1050 * on the 3c905CX and newer 3c908C cards. We wait an
1051 * extra amount of time so that xl_wait() doesn't complain
1052 * and annoy the users.
1053 */
1054 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
1055 DELAY(100000);
1056 xl_wait(sc);
1057 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1058 xl_wait(sc);
1059
1060 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
1061 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
1062 XL_SEL_WIN(2);
1063 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc,
1064 XL_W2_RESET_OPTIONS)
1065 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0)
1066 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0)
1067 );
1068 }
1069
1070 /* Wait a little while for the chip to get its brains in order. */
1071 DELAY(100000);
1072 return;
1073 }
1074
1075 /*
1076 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1077 * IDs against our list and return a device name if we find a match.
1078 */
1079 static int
1080 xl_probe(dev)
1081 device_t dev;
1082 {
1083 struct xl_type *t;
1084
1085 t = xl_devs;
1086
1087 while(t->xl_name != NULL) {
1088 if ((pci_get_vendor(dev) == t->xl_vid) &&
1089 (pci_get_device(dev) == t->xl_did)) {
1090 device_set_desc(dev, t->xl_name);
1091 return(0);
1092 }
1093 t++;
1094 }
1095
1096 return(ENXIO);
1097 }
1098
1099 /*
1100 * This routine is a kludge to work around possible hardware faults
1101 * or manufacturing defects that can cause the media options register
1102 * (or reset options register, as it's called for the first generation
1103 * 3c90x adapters) to return an incorrect result. I have encountered
1104 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1105 * which doesn't have any of the 'mediaopt' bits set. This screws up
1106 * the attach routine pretty badly because it doesn't know what media
1107 * to look for. If we find ourselves in this predicament, this routine
1108 * will try to guess the media options values and warn the user of a
1109 * possible manufacturing defect with his adapter/system/whatever.
1110 */
1111 static void
1112 xl_mediacheck(sc)
1113 struct xl_softc *sc;
1114 {
1115
1116 /*
1117 * If some of the media options bits are set, assume they are
1118 * correct. If not, try to figure it out down below.
1119 * XXX I should check for 10baseFL, but I don't have an adapter
1120 * to test with.
1121 */
1122 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1123 /*
1124 * Check the XCVR value. If it's not in the normal range
1125 * of values, we need to fake it up here.
1126 */
1127 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1128 return;
1129 else {
1130 printf("xl%d: bogus xcvr value "
1131 "in EEPROM (%x)\n", sc->xl_unit, sc->xl_xcvr);
1132 printf("xl%d: choosing new default based "
1133 "on card type\n", sc->xl_unit);
1134 }
1135 } else {
1136 if (sc->xl_type == XL_TYPE_905B &&
1137 sc->xl_media & XL_MEDIAOPT_10FL)
1138 return;
1139 printf("xl%d: WARNING: no media options bits set in "
1140 "the media options register!!\n", sc->xl_unit);
1141 printf("xl%d: this could be a manufacturing defect in "
1142 "your adapter or system\n", sc->xl_unit);
1143 printf("xl%d: attempting to guess media type; you "
1144 "should probably consult your vendor\n", sc->xl_unit);
1145 }
1146
1147 xl_choose_xcvr(sc, 1);
1148
1149 return;
1150 }
1151
1152 static void
1153 xl_choose_xcvr(sc, verbose)
1154 struct xl_softc *sc;
1155 int verbose;
1156 {
1157 u_int16_t devid;
1158
1159 /*
1160 * Read the device ID from the EEPROM.
1161 * This is what's loaded into the PCI device ID register, so it has
1162 * to be correct otherwise we wouldn't have gotten this far.
1163 */
1164 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1165
1166 switch(devid) {
1167 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1168 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1169 sc->xl_media = XL_MEDIAOPT_BT;
1170 sc->xl_xcvr = XL_XCVR_10BT;
1171 if (verbose)
1172 printf("xl%d: guessing 10BaseT "
1173 "transceiver\n", sc->xl_unit);
1174 break;
1175 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1176 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1177 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1178 sc->xl_xcvr = XL_XCVR_10BT;
1179 if (verbose)
1180 printf("xl%d: guessing COMBO "
1181 "(AUI/BNC/TP)\n", sc->xl_unit);
1182 break;
1183 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1184 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1185 sc->xl_xcvr = XL_XCVR_10BT;
1186 if (verbose)
1187 printf("xl%d: guessing TPC (BNC/TP)\n", sc->xl_unit);
1188 break;
1189 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1190 sc->xl_media = XL_MEDIAOPT_10FL;
1191 sc->xl_xcvr = XL_XCVR_AUI;
1192 if (verbose)
1193 printf("xl%d: guessing 10baseFL\n", sc->xl_unit);
1194 break;
1195 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1196 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1197 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1198 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1199 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1200 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1201 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1202 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1203 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1204 sc->xl_media = XL_MEDIAOPT_MII;
1205 sc->xl_xcvr = XL_XCVR_MII;
1206 if (verbose)
1207 printf("xl%d: guessing MII\n", sc->xl_unit);
1208 break;
1209 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1210 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1211 sc->xl_media = XL_MEDIAOPT_BT4;
1212 sc->xl_xcvr = XL_XCVR_MII;
1213 if (verbose)
1214 printf("xl%d: guessing 100BaseT4/MII\n", sc->xl_unit);
1215 break;
1216 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1217 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1218 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1219 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1220 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1221 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1222 sc->xl_media = XL_MEDIAOPT_BTX;
1223 sc->xl_xcvr = XL_XCVR_AUTO;
1224 if (verbose)
1225 printf("xl%d: guessing 10/100 internal\n", sc->xl_unit);
1226 break;
1227 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1228 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1229 sc->xl_xcvr = XL_XCVR_AUTO;
1230 if (verbose)
1231 printf("xl%d: guessing 10/100 "
1232 "plus BNC/AUI\n", sc->xl_unit);
1233 break;
1234 default:
1235 printf("xl%d: unknown device ID: %x -- "
1236 "defaulting to 10baseT\n", sc->xl_unit, devid);
1237 sc->xl_media = XL_MEDIAOPT_BT;
1238 break;
1239 }
1240
1241 return;
1242 }
1243
1244 /*
1245 * Attach the interface. Allocate softc structures, do ifmedia
1246 * setup and ethernet/BPF attach.
1247 */
1248 static int
1249 xl_attach(dev)
1250 device_t dev;
1251 {
1252 u_char eaddr[ETHER_ADDR_LEN];
1253 u_int32_t command;
1254 struct xl_softc *sc;
1255 struct ifnet *ifp;
1256 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1257 int unit, error = 0, rid;
1258
1259 sc = device_get_softc(dev);
1260 unit = device_get_unit(dev);
1261
1262 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1263 MTX_DEF | MTX_RECURSE);
1264 XL_LOCK(sc);
1265
1266 sc->xl_flags = 0;
1267 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 ||
1268 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B)
1269 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1270 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1271 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1272 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556)
1273 sc->xl_flags |= XL_FLAG_8BITROM;
1274 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B)
1275 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1276
1277 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A ||
1278 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B ||
1279 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C ||
1280 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B ||
1281 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C)
1282 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1283 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM;
1284 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656)
1285 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1286 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B)
1287 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1288 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C)
1289 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1290 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_656C)
1291 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1292 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656 ||
1293 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B)
1294 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1295 XL_FLAG_INVERT_LED_PWR;
1296
1297 /*
1298 * If this is a 3c905B, we have to check one extra thing.
1299 * The 905B supports power management and may be placed in
1300 * a low-power mode (D3 mode), typically by certain operating
1301 * systems which shall not be named. The PCI BIOS is supposed
1302 * to reset the NIC and bring it out of low-power mode, but
1303 * some do not. Consequently, we have to see if this chip
1304 * supports power management, and if so, make sure it's not
1305 * in low-power mode. If power management is available, the
1306 * capid byte will be 0x01.
1307 *
1308 * I _think_ that what actually happens is that the chip
1309 * loses its PCI configuration during the transition from
1310 * D3 back to D0; this means that it should be possible for
1311 * us to save the PCI iobase, membase and IRQ, put the chip
1312 * back in the D0 state, then restore the PCI config ourselves.
1313 */
1314
1315 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1316 u_int32_t iobase, membase, irq;
1317
1318 /* Save important PCI config data. */
1319 iobase = pci_read_config(dev, XL_PCI_LOIO, 4);
1320 membase = pci_read_config(dev, XL_PCI_LOMEM, 4);
1321 irq = pci_read_config(dev, XL_PCI_INTLINE, 4);
1322
1323 /* Reset the power state. */
1324 printf("xl%d: chip is in D%d power mode "
1325 "-- setting to D0\n", unit,
1326 pci_get_powerstate(dev));
1327
1328 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1329
1330 /* Restore PCI config data. */
1331 pci_write_config(dev, XL_PCI_LOIO, iobase, 4);
1332 pci_write_config(dev, XL_PCI_LOMEM, membase, 4);
1333 pci_write_config(dev, XL_PCI_INTLINE, irq, 4);
1334 }
1335
1336 /*
1337 * Map control/status registers.
1338 */
1339 pci_enable_busmaster(dev);
1340 pci_enable_io(dev, SYS_RES_IOPORT);
1341 pci_enable_io(dev, SYS_RES_MEMORY);
1342 command = pci_read_config(dev, PCIR_COMMAND, 4);
1343
1344 #ifdef XL_USEIOSPACE
1345 if (!(command & PCIM_CMD_PORTEN)) {
1346 printf("xl%d: failed to enable I/O ports!\n", unit);
1347 error = ENXIO;
1348 goto fail;
1349 }
1350 #else
1351 if (!(command & PCIM_CMD_MEMEN)) {
1352 printf("xl%d: failed to enable memory mapping!\n", unit);
1353 error = ENXIO;
1354 goto fail;
1355 }
1356 #endif
1357
1358 rid = XL_RID;
1359 sc->xl_res = bus_alloc_resource(dev, XL_RES, &rid,
1360 0, ~0, 1, RF_ACTIVE);
1361
1362 if (sc->xl_res == NULL) {
1363 printf ("xl%d: couldn't map ports/memory\n", unit);
1364 error = ENXIO;
1365 goto fail;
1366 }
1367
1368 sc->xl_btag = rman_get_bustag(sc->xl_res);
1369 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1370
1371 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1372 rid = XL_PCI_FUNCMEM;
1373 sc->xl_fres = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1374 0, ~0, 1, RF_ACTIVE);
1375
1376 if (sc->xl_fres == NULL) {
1377 printf ("xl%d: couldn't map ports/memory\n", unit);
1378 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1379 error = ENXIO;
1380 goto fail;
1381 }
1382
1383 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1384 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1385 }
1386
1387 rid = 0;
1388 sc->xl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1389 RF_SHAREABLE | RF_ACTIVE);
1390
1391 if (sc->xl_irq == NULL) {
1392 printf("xl%d: couldn't map interrupt\n", unit);
1393 if (sc->xl_fres != NULL)
1394 bus_release_resource(dev, SYS_RES_MEMORY,
1395 XL_PCI_FUNCMEM, sc->xl_fres);
1396 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1397 error = ENXIO;
1398 goto fail;
1399 }
1400
1401 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET,
1402 xl_intr, sc, &sc->xl_intrhand);
1403
1404 if (error) {
1405 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1406 if (sc->xl_fres != NULL)
1407 bus_release_resource(dev, SYS_RES_MEMORY,
1408 XL_PCI_FUNCMEM, sc->xl_fres);
1409 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1410 printf("xl%d: couldn't set up irq\n", unit);
1411 goto fail;
1412 }
1413
1414 /* Reset the adapter. */
1415 xl_reset(sc);
1416
1417 /*
1418 * Get station address from the EEPROM.
1419 */
1420 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1421 printf("xl%d: failed to read station address\n", sc->xl_unit);
1422 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1423 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1424 if (sc->xl_fres != NULL)
1425 bus_release_resource(dev, SYS_RES_MEMORY,
1426 XL_PCI_FUNCMEM, sc->xl_fres);
1427 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1428 error = ENXIO;
1429 goto fail;
1430 }
1431
1432 /*
1433 * A 3Com chip was detected. Inform the world.
1434 */
1435 printf("xl%d: Ethernet address: %6D\n", unit, eaddr, ":");
1436
1437 sc->xl_unit = unit;
1438 callout_handle_init(&sc->xl_stat_ch);
1439 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1440
1441 sc->xl_ldata = contigmalloc(sizeof(struct xl_list_data), M_DEVBUF,
1442 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1443
1444 if (sc->xl_ldata == NULL) {
1445 printf("xl%d: no memory for list buffers!\n", unit);
1446 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1447 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1448 if (sc->xl_fres != NULL)
1449 bus_release_resource(dev, SYS_RES_MEMORY,
1450 XL_PCI_FUNCMEM, sc->xl_fres);
1451 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1452 error = ENXIO;
1453 goto fail;
1454 }
1455
1456 bzero(sc->xl_ldata, sizeof(struct xl_list_data));
1457
1458 /*
1459 * Figure out the card type. 3c905B adapters have the
1460 * 'supportsNoTxLength' bit set in the capabilities
1461 * word in the EEPROM.
1462 */
1463 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1464 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH)
1465 sc->xl_type = XL_TYPE_905B;
1466 else
1467 sc->xl_type = XL_TYPE_90X;
1468
1469 ifp = &sc->arpcom.ac_if;
1470 ifp->if_softc = sc;
1471 ifp->if_unit = unit;
1472 ifp->if_name = "xl";
1473 ifp->if_mtu = ETHERMTU;
1474 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1475 ifp->if_ioctl = xl_ioctl;
1476 ifp->if_output = ether_output;
1477 if (sc->xl_type == XL_TYPE_905B) {
1478 ifp->if_start = xl_start_90xB;
1479 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1480 ifp->if_capabilities = IFCAP_HWCSUM;
1481 } else
1482 ifp->if_start = xl_start;
1483 ifp->if_watchdog = xl_watchdog;
1484 ifp->if_init = xl_init;
1485 ifp->if_baudrate = 10000000;
1486 ifp->if_snd.ifq_maxlen = XL_TX_LIST_CNT - 1;
1487 ifp->if_capenable = ifp->if_capabilities;
1488
1489 /*
1490 * Now we have to see what sort of media we have.
1491 * This includes probing for an MII interace and a
1492 * possible PHY.
1493 */
1494 XL_SEL_WIN(3);
1495 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1496 if (bootverbose)
1497 printf("xl%d: media options word: %x\n", sc->xl_unit,
1498 sc->xl_media);
1499
1500 xl_read_eeprom(sc, (char *)&sc->xl_xcvr, XL_EE_ICFG_0, 2, 0);
1501 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1502 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1503
1504 xl_mediacheck(sc);
1505
1506 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
1507 || sc->xl_media & XL_MEDIAOPT_BT4) {
1508 if (bootverbose)
1509 printf("xl%d: found MII/AUTO\n", sc->xl_unit);
1510 xl_setcfg(sc);
1511 if (mii_phy_probe(dev, &sc->xl_miibus,
1512 xl_ifmedia_upd, xl_ifmedia_sts)) {
1513 printf("xl%d: no PHY found!\n", sc->xl_unit);
1514 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1515 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1516 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1517 contigfree(sc->xl_ldata,
1518 sizeof(struct xl_list_data), M_DEVBUF);
1519 error = ENXIO;
1520 goto fail;
1521 }
1522
1523 goto done;
1524 }
1525
1526 /*
1527 * Sanity check. If the user has selected "auto" and this isn't
1528 * a 10/100 card of some kind, we need to force the transceiver
1529 * type to something sane.
1530 */
1531 if (sc->xl_xcvr == XL_XCVR_AUTO)
1532 xl_choose_xcvr(sc, bootverbose);
1533
1534 /*
1535 * Do ifmedia setup.
1536 */
1537
1538 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1539
1540 if (sc->xl_media & XL_MEDIAOPT_BT) {
1541 if (bootverbose)
1542 printf("xl%d: found 10baseT\n", sc->xl_unit);
1543 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1544 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1545 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1546 ifmedia_add(&sc->ifmedia,
1547 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1548 }
1549
1550 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1551 /*
1552 * Check for a 10baseFL board in disguise.
1553 */
1554 if (sc->xl_type == XL_TYPE_905B &&
1555 sc->xl_media == XL_MEDIAOPT_10FL) {
1556 if (bootverbose)
1557 printf("xl%d: found 10baseFL\n", sc->xl_unit);
1558 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1559 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1560 0, NULL);
1561 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1562 ifmedia_add(&sc->ifmedia,
1563 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1564 } else {
1565 if (bootverbose)
1566 printf("xl%d: found AUI\n", sc->xl_unit);
1567 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1568 }
1569 }
1570
1571 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1572 if (bootverbose)
1573 printf("xl%d: found BNC\n", sc->xl_unit);
1574 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1575 }
1576
1577 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1578 if (bootverbose)
1579 printf("xl%d: found 100baseFX\n", sc->xl_unit);
1580 ifp->if_baudrate = 100000000;
1581 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1582 }
1583
1584 /* Choose a default media. */
1585 switch(sc->xl_xcvr) {
1586 case XL_XCVR_10BT:
1587 media = IFM_ETHER|IFM_10_T;
1588 xl_setmode(sc, media);
1589 break;
1590 case XL_XCVR_AUI:
1591 if (sc->xl_type == XL_TYPE_905B &&
1592 sc->xl_media == XL_MEDIAOPT_10FL) {
1593 media = IFM_ETHER|IFM_10_FL;
1594 xl_setmode(sc, media);
1595 } else {
1596 media = IFM_ETHER|IFM_10_5;
1597 xl_setmode(sc, media);
1598 }
1599 break;
1600 case XL_XCVR_COAX:
1601 media = IFM_ETHER|IFM_10_2;
1602 xl_setmode(sc, media);
1603 break;
1604 case XL_XCVR_AUTO:
1605 case XL_XCVR_100BTX:
1606 case XL_XCVR_MII:
1607 /* Chosen by miibus */
1608 break;
1609 case XL_XCVR_100BFX:
1610 media = IFM_ETHER|IFM_100_FX;
1611 break;
1612 default:
1613 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit,
1614 sc->xl_xcvr);
1615 /*
1616 * This will probably be wrong, but it prevents
1617 * the ifmedia code from panicking.
1618 */
1619 media = IFM_ETHER|IFM_10_T;
1620 break;
1621 }
1622
1623 if (sc->xl_miibus == NULL)
1624 ifmedia_set(&sc->ifmedia, media);
1625
1626 done:
1627
1628 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1629 XL_SEL_WIN(0);
1630 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1631 }
1632
1633 /*
1634 * Call MI attach routine.
1635 */
1636 ether_ifattach(ifp, eaddr);
1637 XL_UNLOCK(sc);
1638 return(0);
1639
1640 fail:
1641 XL_UNLOCK(sc);
1642 mtx_destroy(&sc->xl_mtx);
1643
1644 return(error);
1645 }
1646
1647 static int
1648 xl_detach(dev)
1649 device_t dev;
1650 {
1651 struct xl_softc *sc;
1652 struct ifnet *ifp;
1653
1654 sc = device_get_softc(dev);
1655 XL_LOCK(sc);
1656 ifp = &sc->arpcom.ac_if;
1657
1658 xl_reset(sc);
1659 xl_stop(sc);
1660 ether_ifdetach(ifp);
1661
1662 /* Delete any miibus and phy devices attached to this interface */
1663 if (sc->xl_miibus != NULL) {
1664 bus_generic_detach(dev);
1665 device_delete_child(dev, sc->xl_miibus);
1666 }
1667
1668 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1669 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1670 if (sc->xl_fres != NULL)
1671 bus_release_resource(dev, SYS_RES_MEMORY,
1672 XL_PCI_FUNCMEM, sc->xl_fres);
1673 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res);
1674
1675 ifmedia_removeall(&sc->ifmedia);
1676 contigfree(sc->xl_ldata, sizeof(struct xl_list_data), M_DEVBUF);
1677
1678 XL_UNLOCK(sc);
1679 mtx_destroy(&sc->xl_mtx);
1680
1681 return(0);
1682 }
1683
1684 /*
1685 * Initialize the transmit descriptors.
1686 */
1687 static int
1688 xl_list_tx_init(sc)
1689 struct xl_softc *sc;
1690 {
1691 struct xl_chain_data *cd;
1692 struct xl_list_data *ld;
1693 int i;
1694
1695 cd = &sc->xl_cdata;
1696 ld = sc->xl_ldata;
1697 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1698 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1699 if (i == (XL_TX_LIST_CNT - 1))
1700 cd->xl_tx_chain[i].xl_next = NULL;
1701 else
1702 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1703 }
1704
1705 cd->xl_tx_free = &cd->xl_tx_chain[0];
1706 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1707
1708 return(0);
1709 }
1710
1711 /*
1712 * Initialize the transmit descriptors.
1713 */
1714 static int xl_list_tx_init_90xB(sc)
1715 struct xl_softc *sc;
1716 {
1717 struct xl_chain_data *cd;
1718 struct xl_list_data *ld;
1719 int i;
1720
1721 cd = &sc->xl_cdata;
1722 ld = sc->xl_ldata;
1723 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1724 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1725 cd->xl_tx_chain[i].xl_phys = vtophys(&ld->xl_tx_list[i]);
1726 if (i == (XL_TX_LIST_CNT - 1))
1727 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1728 else
1729 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1730 if (i == 0)
1731 cd->xl_tx_chain[i].xl_prev =
1732 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1733 else
1734 cd->xl_tx_chain[i].xl_prev =
1735 &cd->xl_tx_chain[i - 1];
1736 }
1737
1738 bzero((char *)ld->xl_tx_list,
1739 sizeof(struct xl_list) * XL_TX_LIST_CNT);
1740 ld->xl_tx_list[0].xl_status = XL_TXSTAT_EMPTY;
1741
1742 cd->xl_tx_prod = 1;
1743 cd->xl_tx_cons = 1;
1744 cd->xl_tx_cnt = 0;
1745
1746 return(0);
1747 }
1748
1749 /*
1750 * Initialize the RX descriptors and allocate mbufs for them. Note that
1751 * we arrange the descriptors in a closed ring, so that the last descriptor
1752 * points back to the first.
1753 */
1754 static int
1755 xl_list_rx_init(sc)
1756 struct xl_softc *sc;
1757 {
1758 struct xl_chain_data *cd;
1759 struct xl_list_data *ld;
1760 int i;
1761
1762 cd = &sc->xl_cdata;
1763 ld = sc->xl_ldata;
1764
1765 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1766 cd->xl_rx_chain[i].xl_ptr =
1767 (struct xl_list_onefrag *)&ld->xl_rx_list[i];
1768 if (xl_newbuf(sc, &cd->xl_rx_chain[i]) == ENOBUFS)
1769 return(ENOBUFS);
1770 if (i == (XL_RX_LIST_CNT - 1)) {
1771 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[0];
1772 ld->xl_rx_list[i].xl_next =
1773 vtophys(&ld->xl_rx_list[0]);
1774 } else {
1775 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[i + 1];
1776 ld->xl_rx_list[i].xl_next =
1777 vtophys(&ld->xl_rx_list[i + 1]);
1778 }
1779 }
1780
1781 cd->xl_rx_head = &cd->xl_rx_chain[0];
1782
1783 return(0);
1784 }
1785
1786 /*
1787 * Initialize an RX descriptor and attach an MBUF cluster.
1788 */
1789 static int
1790 xl_newbuf(sc, c)
1791 struct xl_softc *sc;
1792 struct xl_chain_onefrag *c;
1793 {
1794 struct mbuf *m_new = NULL;
1795
1796 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1797 if (m_new == NULL)
1798 return(ENOBUFS);
1799
1800 MCLGET(m_new, M_DONTWAIT);
1801 if (!(m_new->m_flags & M_EXT)) {
1802 m_freem(m_new);
1803 return(ENOBUFS);
1804 }
1805
1806 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1807
1808 /* Force longword alignment for packet payload. */
1809 m_adj(m_new, ETHER_ALIGN);
1810
1811 c->xl_mbuf = m_new;
1812 c->xl_ptr->xl_frag.xl_addr = vtophys(mtod(m_new, caddr_t));
1813 c->xl_ptr->xl_frag.xl_len = MCLBYTES | XL_LAST_FRAG;
1814 c->xl_ptr->xl_status = 0;
1815
1816 return(0);
1817 }
1818
1819 static int
1820 xl_rx_resync(sc)
1821 struct xl_softc *sc;
1822 {
1823 struct xl_chain_onefrag *pos;
1824 int i;
1825
1826 pos = sc->xl_cdata.xl_rx_head;
1827
1828 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1829 if (pos->xl_ptr->xl_status)
1830 break;
1831 pos = pos->xl_next;
1832 }
1833
1834 if (i == XL_RX_LIST_CNT)
1835 return(0);
1836
1837 sc->xl_cdata.xl_rx_head = pos;
1838
1839 return(EAGAIN);
1840 }
1841
1842 /*
1843 * A frame has been uploaded: pass the resulting mbuf chain up to
1844 * the higher level protocols.
1845 */
1846 static void
1847 xl_rxeof(sc)
1848 struct xl_softc *sc;
1849 {
1850 struct mbuf *m;
1851 struct ifnet *ifp;
1852 struct xl_chain_onefrag *cur_rx;
1853 int total_len = 0;
1854 u_int32_t rxstat;
1855
1856 ifp = &sc->arpcom.ac_if;
1857
1858 again:
1859
1860 while((rxstat = sc->xl_cdata.xl_rx_head->xl_ptr->xl_status)) {
1861 cur_rx = sc->xl_cdata.xl_rx_head;
1862 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1863
1864 /*
1865 * If an error occurs, update stats, clear the
1866 * status word and leave the mbuf cluster in place:
1867 * it should simply get re-used next time this descriptor
1868 * comes up in the ring.
1869 */
1870 if (rxstat & XL_RXSTAT_UP_ERROR) {
1871 ifp->if_ierrors++;
1872 cur_rx->xl_ptr->xl_status = 0;
1873 continue;
1874 }
1875
1876 /*
1877 * If there error bit was not set, the upload complete
1878 * bit should be set which means we have a valid packet.
1879 * If not, something truly strange has happened.
1880 */
1881 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
1882 printf("xl%d: bad receive status -- "
1883 "packet dropped\n", sc->xl_unit);
1884 ifp->if_ierrors++;
1885 cur_rx->xl_ptr->xl_status = 0;
1886 continue;
1887 }
1888
1889 /* No errors; receive the packet. */
1890 m = cur_rx->xl_mbuf;
1891 total_len = cur_rx->xl_ptr->xl_status & XL_RXSTAT_LENMASK;
1892
1893 /*
1894 * Try to conjure up a new mbuf cluster. If that
1895 * fails, it means we have an out of memory condition and
1896 * should leave the buffer in place and continue. This will
1897 * result in a lost packet, but there's little else we
1898 * can do in this situation.
1899 */
1900 if (xl_newbuf(sc, cur_rx) == ENOBUFS) {
1901 ifp->if_ierrors++;
1902 cur_rx->xl_ptr->xl_status = 0;
1903 continue;
1904 }
1905
1906 ifp->if_ipackets++;
1907 m->m_pkthdr.rcvif = ifp;
1908 m->m_pkthdr.len = m->m_len = total_len;
1909
1910 if (sc->xl_type == XL_TYPE_905B) {
1911 /* Do IP checksum checking. */
1912 if (rxstat & XL_RXSTAT_IPCKOK)
1913 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1914 if (!(rxstat & XL_RXSTAT_IPCKERR))
1915 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1916 if ((rxstat & XL_RXSTAT_TCPCOK &&
1917 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
1918 (rxstat & XL_RXSTAT_UDPCKOK &&
1919 !(rxstat & XL_RXSTAT_UDPCKERR))) {
1920 m->m_pkthdr.csum_flags |=
1921 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1922 m->m_pkthdr.csum_data = 0xffff;
1923 }
1924 }
1925
1926 (*ifp->if_input)(ifp, m);
1927 }
1928
1929 /*
1930 * Handle the 'end of channel' condition. When the upload
1931 * engine hits the end of the RX ring, it will stall. This
1932 * is our cue to flush the RX ring, reload the uplist pointer
1933 * register and unstall the engine.
1934 * XXX This is actually a little goofy. With the ThunderLAN
1935 * chip, you get an interrupt when the receiver hits the end
1936 * of the receive ring, which tells you exactly when you
1937 * you need to reload the ring pointer. Here we have to
1938 * fake it. I'm mad at myself for not being clever enough
1939 * to avoid the use of a goto here.
1940 */
1941 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
1942 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
1943 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
1944 xl_wait(sc);
1945 CSR_WRITE_4(sc, XL_UPLIST_PTR,
1946 vtophys(&sc->xl_ldata->xl_rx_list[0]));
1947 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
1948 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
1949 goto again;
1950 }
1951
1952 return;
1953 }
1954
1955 /*
1956 * A frame was downloaded to the chip. It's safe for us to clean up
1957 * the list buffers.
1958 */
1959 static void
1960 xl_txeof(sc)
1961 struct xl_softc *sc;
1962 {
1963 struct xl_chain *cur_tx;
1964 struct ifnet *ifp;
1965
1966 ifp = &sc->arpcom.ac_if;
1967
1968 /* Clear the timeout timer. */
1969 ifp->if_timer = 0;
1970
1971 /*
1972 * Go through our tx list and free mbufs for those
1973 * frames that have been uploaded. Note: the 3c905B
1974 * sets a special bit in the status word to let us
1975 * know that a frame has been downloaded, but the
1976 * original 3c900/3c905 adapters don't do that.
1977 * Consequently, we have to use a different test if
1978 * xl_type != XL_TYPE_905B.
1979 */
1980 while(sc->xl_cdata.xl_tx_head != NULL) {
1981 cur_tx = sc->xl_cdata.xl_tx_head;
1982
1983 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
1984 break;
1985
1986 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
1987 m_freem(cur_tx->xl_mbuf);
1988 cur_tx->xl_mbuf = NULL;
1989 ifp->if_opackets++;
1990
1991 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
1992 sc->xl_cdata.xl_tx_free = cur_tx;
1993 }
1994
1995 if (sc->xl_cdata.xl_tx_head == NULL) {
1996 ifp->if_flags &= ~IFF_OACTIVE;
1997 sc->xl_cdata.xl_tx_tail = NULL;
1998 } else {
1999 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2000 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2001 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2002 vtophys(sc->xl_cdata.xl_tx_head->xl_ptr));
2003 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2004 }
2005 }
2006
2007 return;
2008 }
2009
2010 static void xl_txeof_90xB(sc)
2011 struct xl_softc *sc;
2012 {
2013 struct xl_chain *cur_tx = NULL;
2014 struct ifnet *ifp;
2015 int idx;
2016
2017 ifp = &sc->arpcom.ac_if;
2018
2019 idx = sc->xl_cdata.xl_tx_cons;
2020 while(idx != sc->xl_cdata.xl_tx_prod) {
2021
2022 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2023
2024 if (!(cur_tx->xl_ptr->xl_status & XL_TXSTAT_DL_COMPLETE))
2025 break;
2026
2027 if (cur_tx->xl_mbuf != NULL) {
2028 m_freem(cur_tx->xl_mbuf);
2029 cur_tx->xl_mbuf = NULL;
2030 }
2031
2032 ifp->if_opackets++;
2033
2034 sc->xl_cdata.xl_tx_cnt--;
2035 XL_INC(idx, XL_TX_LIST_CNT);
2036 ifp->if_timer = 0;
2037 }
2038
2039 sc->xl_cdata.xl_tx_cons = idx;
2040
2041 if (cur_tx != NULL)
2042 ifp->if_flags &= ~IFF_OACTIVE;
2043
2044 return;
2045 }
2046
2047 /*
2048 * TX 'end of channel' interrupt handler. Actually, we should
2049 * only get a 'TX complete' interrupt if there's a transmit error,
2050 * so this is really TX error handler.
2051 */
2052 static void
2053 xl_txeoc(sc)
2054 struct xl_softc *sc;
2055 {
2056 u_int8_t txstat;
2057
2058 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2059 if (txstat & XL_TXSTATUS_UNDERRUN ||
2060 txstat & XL_TXSTATUS_JABBER ||
2061 txstat & XL_TXSTATUS_RECLAIM) {
2062 printf("xl%d: transmission error: %x\n",
2063 sc->xl_unit, txstat);
2064 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2065 xl_wait(sc);
2066 if (sc->xl_type == XL_TYPE_905B) {
2067 if (sc->xl_cdata.xl_tx_cnt) {
2068 int i;
2069 struct xl_chain *c;
2070 i = sc->xl_cdata.xl_tx_cons;
2071 c = &sc->xl_cdata.xl_tx_chain[i];
2072 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2073 c->xl_phys);
2074 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2075 }
2076 } else {
2077 if (sc->xl_cdata.xl_tx_head != NULL)
2078 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2079 vtophys(sc->xl_cdata.xl_tx_head->xl_ptr));
2080 }
2081 /*
2082 * Remember to set this for the
2083 * first generation 3c90X chips.
2084 */
2085 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2086 if (txstat & XL_TXSTATUS_UNDERRUN &&
2087 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2088 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2089 printf("xl%d: tx underrun, increasing tx start"
2090 " threshold to %d bytes\n", sc->xl_unit,
2091 sc->xl_tx_thresh);
2092 }
2093 CSR_WRITE_2(sc, XL_COMMAND,
2094 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2095 if (sc->xl_type == XL_TYPE_905B) {
2096 CSR_WRITE_2(sc, XL_COMMAND,
2097 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2098 }
2099 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2100 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2101 } else {
2102 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2103 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2104 }
2105 /*
2106 * Write an arbitrary byte to the TX_STATUS register
2107 * to clear this interrupt/error and advance to the next.
2108 */
2109 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2110 }
2111
2112 return;
2113 }
2114
2115 static void
2116 xl_intr(arg)
2117 void *arg;
2118 {
2119 struct xl_softc *sc;
2120 struct ifnet *ifp;
2121 u_int16_t status;
2122
2123 sc = arg;
2124 XL_LOCK(sc);
2125 ifp = &sc->arpcom.ac_if;
2126
2127 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) {
2128
2129 CSR_WRITE_2(sc, XL_COMMAND,
2130 XL_CMD_INTR_ACK|(status & XL_INTRS));
2131
2132 if (status & XL_STAT_UP_COMPLETE) {
2133 int curpkts;
2134
2135 curpkts = ifp->if_ipackets;
2136 xl_rxeof(sc);
2137 if (curpkts == ifp->if_ipackets) {
2138 while (xl_rx_resync(sc))
2139 xl_rxeof(sc);
2140 }
2141 }
2142
2143 if (status & XL_STAT_DOWN_COMPLETE) {
2144 if (sc->xl_type == XL_TYPE_905B)
2145 xl_txeof_90xB(sc);
2146 else
2147 xl_txeof(sc);
2148 }
2149
2150 if (status & XL_STAT_TX_COMPLETE) {
2151 ifp->if_oerrors++;
2152 xl_txeoc(sc);
2153 }
2154
2155 if (status & XL_STAT_ADFAIL) {
2156 xl_reset(sc);
2157 xl_init(sc);
2158 }
2159
2160 if (status & XL_STAT_STATSOFLOW) {
2161 sc->xl_stats_no_timeout = 1;
2162 xl_stats_update(sc);
2163 sc->xl_stats_no_timeout = 0;
2164 }
2165 }
2166
2167 if (ifp->if_snd.ifq_head != NULL)
2168 (*ifp->if_start)(ifp);
2169
2170 XL_UNLOCK(sc);
2171
2172 return;
2173 }
2174
2175 static void
2176 xl_stats_update(xsc)
2177 void *xsc;
2178 {
2179 struct xl_softc *sc;
2180 struct ifnet *ifp;
2181 struct xl_stats xl_stats;
2182 u_int8_t *p;
2183 int i;
2184 struct mii_data *mii = NULL;
2185
2186 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2187
2188 sc = xsc;
2189 ifp = &sc->arpcom.ac_if;
2190 if (sc->xl_miibus != NULL)
2191 mii = device_get_softc(sc->xl_miibus);
2192
2193 p = (u_int8_t *)&xl_stats;
2194
2195 /* Read all the stats registers. */
2196 XL_SEL_WIN(6);
2197
2198 for (i = 0; i < 16; i++)
2199 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2200
2201 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2202
2203 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2204 xl_stats.xl_tx_single_collision +
2205 xl_stats.xl_tx_late_collision;
2206
2207 /*
2208 * Boomerang and cyclone chips have an extra stats counter
2209 * in window 4 (BadSSD). We have to read this too in order
2210 * to clear out all the stats registers and avoid a statsoflow
2211 * interrupt.
2212 */
2213 XL_SEL_WIN(4);
2214 CSR_READ_1(sc, XL_W4_BADSSD);
2215
2216 if ((mii != NULL) && (!sc->xl_stats_no_timeout))
2217 mii_tick(mii);
2218
2219 XL_SEL_WIN(7);
2220
2221 if (!sc->xl_stats_no_timeout)
2222 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz);
2223
2224 return;
2225 }
2226
2227 /*
2228 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2229 * pointers to the fragment pointers.
2230 */
2231 static int
2232 xl_encap(sc, c, m_head)
2233 struct xl_softc *sc;
2234 struct xl_chain *c;
2235 struct mbuf *m_head;
2236 {
2237 int frag = 0;
2238 struct xl_frag *f = NULL;
2239 int total_len;
2240 struct mbuf *m;
2241
2242 /*
2243 * Start packing the mbufs in this chain into
2244 * the fragment pointers. Stop when we run out
2245 * of fragments or hit the end of the mbuf chain.
2246 */
2247 m = m_head;
2248 total_len = 0;
2249
2250 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
2251 if (m->m_len != 0) {
2252 if (frag == XL_MAXFRAGS)
2253 break;
2254 total_len+= m->m_len;
2255 c->xl_ptr->xl_frag[frag].xl_addr =
2256 vtophys(mtod(m, vm_offset_t));
2257 c->xl_ptr->xl_frag[frag].xl_len = m->m_len;
2258 frag++;
2259 }
2260 }
2261
2262 /*
2263 * Handle special case: we used up all 63 fragments,
2264 * but we have more mbufs left in the chain. Copy the
2265 * data into an mbuf cluster. Note that we don't
2266 * bother clearing the values in the other fragment
2267 * pointers/counters; it wouldn't gain us anything,
2268 * and would waste cycles.
2269 */
2270 if (m != NULL) {
2271 struct mbuf *m_new = NULL;
2272
2273 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
2274 if (m_new == NULL) {
2275 printf("xl%d: no memory for tx list\n", sc->xl_unit);
2276 return(1);
2277 }
2278 if (m_head->m_pkthdr.len > MHLEN) {
2279 MCLGET(m_new, M_DONTWAIT);
2280 if (!(m_new->m_flags & M_EXT)) {
2281 m_freem(m_new);
2282 printf("xl%d: no memory for tx list\n",
2283 sc->xl_unit);
2284 return(1);
2285 }
2286 }
2287 m_copydata(m_head, 0, m_head->m_pkthdr.len,
2288 mtod(m_new, caddr_t));
2289 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
2290 m_freem(m_head);
2291 m_head = m_new;
2292 f = &c->xl_ptr->xl_frag[0];
2293 f->xl_addr = vtophys(mtod(m_new, caddr_t));
2294 f->xl_len = total_len = m_new->m_len;
2295 frag = 1;
2296 }
2297
2298 c->xl_mbuf = m_head;
2299 c->xl_ptr->xl_frag[frag - 1].xl_len |= XL_LAST_FRAG;
2300 c->xl_ptr->xl_status = total_len;
2301 c->xl_ptr->xl_next = 0;
2302
2303 return(0);
2304 }
2305
2306 /*
2307 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2308 * to the mbuf data regions directly in the transmit lists. We also save a
2309 * copy of the pointers since the transmit list fragment pointers are
2310 * physical addresses.
2311 */
2312 static void
2313 xl_start(ifp)
2314 struct ifnet *ifp;
2315 {
2316 struct xl_softc *sc;
2317 struct mbuf *m_head = NULL;
2318 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2319
2320 sc = ifp->if_softc;
2321 XL_LOCK(sc);
2322 /*
2323 * Check for an available queue slot. If there are none,
2324 * punt.
2325 */
2326 if (sc->xl_cdata.xl_tx_free == NULL) {
2327 xl_txeoc(sc);
2328 xl_txeof(sc);
2329 if (sc->xl_cdata.xl_tx_free == NULL) {
2330 ifp->if_flags |= IFF_OACTIVE;
2331 XL_UNLOCK(sc);
2332 return;
2333 }
2334 }
2335
2336 start_tx = sc->xl_cdata.xl_tx_free;
2337
2338 while(sc->xl_cdata.xl_tx_free != NULL) {
2339 IF_DEQUEUE(&ifp->if_snd, m_head);
2340 if (m_head == NULL)
2341 break;
2342
2343 /* Pick a descriptor off the free list. */
2344 cur_tx = sc->xl_cdata.xl_tx_free;
2345 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2346
2347 cur_tx->xl_next = NULL;
2348
2349 /* Pack the data into the descriptor. */
2350 xl_encap(sc, cur_tx, m_head);
2351
2352 /* Chain it together. */
2353 if (prev != NULL) {
2354 prev->xl_next = cur_tx;
2355 prev->xl_ptr->xl_next = vtophys(cur_tx->xl_ptr);
2356 }
2357 prev = cur_tx;
2358
2359 /*
2360 * If there's a BPF listener, bounce a copy of this frame
2361 * to him.
2362 */
2363 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2364 }
2365
2366 /*
2367 * If there are no packets queued, bail.
2368 */
2369 if (cur_tx == NULL) {
2370 XL_UNLOCK(sc);
2371 return;
2372 }
2373
2374 /*
2375 * Place the request for the upload interrupt
2376 * in the last descriptor in the chain. This way, if
2377 * we're chaining several packets at once, we'll only
2378 * get an interupt once for the whole chain rather than
2379 * once for each packet.
2380 */
2381 cur_tx->xl_ptr->xl_status |= XL_TXSTAT_DL_INTR;
2382
2383 /*
2384 * Queue the packets. If the TX channel is clear, update
2385 * the downlist pointer register.
2386 */
2387 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2388 xl_wait(sc);
2389
2390 if (sc->xl_cdata.xl_tx_head != NULL) {
2391 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2392 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2393 vtophys(start_tx->xl_ptr);
2394 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &=
2395 ~XL_TXSTAT_DL_INTR;
2396 sc->xl_cdata.xl_tx_tail = cur_tx;
2397 } else {
2398 sc->xl_cdata.xl_tx_head = start_tx;
2399 sc->xl_cdata.xl_tx_tail = cur_tx;
2400 }
2401 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2402 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, vtophys(start_tx->xl_ptr));
2403
2404 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2405
2406 XL_SEL_WIN(7);
2407
2408 /*
2409 * Set a timeout in case the chip goes out to lunch.
2410 */
2411 ifp->if_timer = 5;
2412
2413 /*
2414 * XXX Under certain conditions, usually on slower machines
2415 * where interrupts may be dropped, it's possible for the
2416 * adapter to chew up all the buffers in the receive ring
2417 * and stall, without us being able to do anything about it.
2418 * To guard against this, we need to make a pass over the
2419 * RX queue to make sure there aren't any packets pending.
2420 * Doing it here means we can flush the receive ring at the
2421 * same time the chip is DMAing the transmit descriptors we
2422 * just gave it.
2423 *
2424 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2425 * nature of their chips in all their marketing literature;
2426 * we may as well take advantage of it. :)
2427 */
2428 xl_rxeof(sc);
2429
2430 XL_UNLOCK(sc);
2431
2432 return;
2433 }
2434
2435 static int xl_encap_90xB(sc, c, m_head)
2436 struct xl_softc *sc;
2437 struct xl_chain *c;
2438 struct mbuf *m_head;
2439 {
2440 int frag = 0;
2441 struct xl_frag *f = NULL;
2442 struct mbuf *m;
2443 struct xl_list *d;
2444
2445 /*
2446 * Start packing the mbufs in this chain into
2447 * the fragment pointers. Stop when we run out
2448 * of fragments or hit the end of the mbuf chain.
2449 */
2450 d = c->xl_ptr;
2451 d->xl_status = 0;
2452 d->xl_next = 0;
2453
2454 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
2455 if (m->m_len != 0) {
2456 if (frag == XL_MAXFRAGS)
2457 break;
2458 f = &d->xl_frag[frag];
2459 f->xl_addr = vtophys(mtod(m, vm_offset_t));
2460 f->xl_len = m->m_len;
2461 frag++;
2462 }
2463 }
2464
2465 c->xl_mbuf = m_head;
2466 c->xl_ptr->xl_frag[frag - 1].xl_len |= XL_LAST_FRAG;
2467 c->xl_ptr->xl_status = XL_TXSTAT_RND_DEFEAT;
2468
2469 if (m_head->m_pkthdr.csum_flags) {
2470 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2471 c->xl_ptr->xl_status |= XL_TXSTAT_IPCKSUM;
2472 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
2473 c->xl_ptr->xl_status |= XL_TXSTAT_TCPCKSUM;
2474 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
2475 c->xl_ptr->xl_status |= XL_TXSTAT_UDPCKSUM;
2476 }
2477 return(0);
2478 }
2479
2480 static void xl_start_90xB(ifp)
2481 struct ifnet *ifp;
2482 {
2483 struct xl_softc *sc;
2484 struct mbuf *m_head = NULL;
2485 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2486 int idx;
2487
2488 sc = ifp->if_softc;
2489 XL_LOCK(sc);
2490
2491 if (ifp->if_flags & IFF_OACTIVE) {
2492 XL_UNLOCK(sc);
2493 return;
2494 }
2495
2496 idx = sc->xl_cdata.xl_tx_prod;
2497 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2498
2499 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
2500
2501 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2502 ifp->if_flags |= IFF_OACTIVE;
2503 break;
2504 }
2505
2506 IF_DEQUEUE(&ifp->if_snd, m_head);
2507 if (m_head == NULL)
2508 break;
2509
2510 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2511
2512 /* Pack the data into the descriptor. */
2513 xl_encap_90xB(sc, cur_tx, m_head);
2514
2515 /* Chain it together. */
2516 if (prev != NULL)
2517 prev->xl_ptr->xl_next = cur_tx->xl_phys;
2518 prev = cur_tx;
2519
2520 /*
2521 * If there's a BPF listener, bounce a copy of this frame
2522 * to him.
2523 */
2524 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2525
2526 XL_INC(idx, XL_TX_LIST_CNT);
2527 sc->xl_cdata.xl_tx_cnt++;
2528 }
2529
2530 /*
2531 * If there are no packets queued, bail.
2532 */
2533 if (cur_tx == NULL) {
2534 XL_UNLOCK(sc);
2535 return;
2536 }
2537
2538 /*
2539 * Place the request for the upload interrupt
2540 * in the last descriptor in the chain. This way, if
2541 * we're chaining several packets at once, we'll only
2542 * get an interupt once for the whole chain rather than
2543 * once for each packet.
2544 */
2545 cur_tx->xl_ptr->xl_status |= XL_TXSTAT_DL_INTR;
2546
2547 /* Start transmission */
2548 sc->xl_cdata.xl_tx_prod = idx;
2549 start_tx->xl_prev->xl_ptr->xl_next = start_tx->xl_phys;
2550
2551 /*
2552 * Set a timeout in case the chip goes out to lunch.
2553 */
2554 ifp->if_timer = 5;
2555
2556 XL_UNLOCK(sc);
2557
2558 return;
2559 }
2560
2561 static void
2562 xl_init(xsc)
2563 void *xsc;
2564 {
2565 struct xl_softc *sc = xsc;
2566 struct ifnet *ifp = &sc->arpcom.ac_if;
2567 int i;
2568 u_int16_t rxfilt = 0;
2569 struct mii_data *mii = NULL;
2570
2571 XL_LOCK(sc);
2572
2573 /*
2574 * Cancel pending I/O and free all RX/TX buffers.
2575 */
2576 xl_stop(sc);
2577
2578 if (sc->xl_miibus == NULL) {
2579 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2580 xl_wait(sc);
2581 }
2582 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2583 xl_wait(sc);
2584 DELAY(10000);
2585
2586 if (sc->xl_miibus != NULL)
2587 mii = device_get_softc(sc->xl_miibus);
2588
2589 /* Init our MAC address */
2590 XL_SEL_WIN(2);
2591 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2592 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2593 sc->arpcom.ac_enaddr[i]);
2594 }
2595
2596 /* Clear the station mask. */
2597 for (i = 0; i < 3; i++)
2598 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2599 #ifdef notdef
2600 /* Reset TX and RX. */
2601 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2602 xl_wait(sc);
2603 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2604 xl_wait(sc);
2605 #endif
2606 /* Init circular RX list. */
2607 if (xl_list_rx_init(sc) == ENOBUFS) {
2608 printf("xl%d: initialization failed: no "
2609 "memory for rx buffers\n", sc->xl_unit);
2610 xl_stop(sc);
2611 XL_UNLOCK(sc);
2612 return;
2613 }
2614
2615 /* Init TX descriptors. */
2616 if (sc->xl_type == XL_TYPE_905B)
2617 xl_list_tx_init_90xB(sc);
2618 else
2619 xl_list_tx_init(sc);
2620
2621 /*
2622 * Set the TX freethresh value.
2623 * Note that this has no effect on 3c905B "cyclone"
2624 * cards but is required for 3c900/3c905 "boomerang"
2625 * cards in order to enable the download engine.
2626 */
2627 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2628
2629 /* Set the TX start threshold for best performance. */
2630 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
2631 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2632
2633 /*
2634 * If this is a 3c905B, also set the tx reclaim threshold.
2635 * This helps cut down on the number of tx reclaim errors
2636 * that could happen on a busy network. The chip multiplies
2637 * the register value by 16 to obtain the actual threshold
2638 * in bytes, so we divide by 16 when setting the value here.
2639 * The existing threshold value can be examined by reading
2640 * the register at offset 9 in window 5.
2641 */
2642 if (sc->xl_type == XL_TYPE_905B) {
2643 CSR_WRITE_2(sc, XL_COMMAND,
2644 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2645 }
2646
2647 /* Set RX filter bits. */
2648 XL_SEL_WIN(5);
2649 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2650
2651 /* Set the individual bit to receive frames for this host only. */
2652 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2653
2654 /* If we want promiscuous mode, set the allframes bit. */
2655 if (ifp->if_flags & IFF_PROMISC) {
2656 rxfilt |= XL_RXFILTER_ALLFRAMES;
2657 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2658 } else {
2659 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2660 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2661 }
2662
2663 /*
2664 * Set capture broadcast bit to capture broadcast frames.
2665 */
2666 if (ifp->if_flags & IFF_BROADCAST) {
2667 rxfilt |= XL_RXFILTER_BROADCAST;
2668 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2669 } else {
2670 rxfilt &= ~XL_RXFILTER_BROADCAST;
2671 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2672 }
2673
2674 /*
2675 * Program the multicast filter, if necessary.
2676 */
2677 if (sc->xl_type == XL_TYPE_905B)
2678 xl_setmulti_hash(sc);
2679 else
2680 xl_setmulti(sc);
2681
2682 /*
2683 * Load the address of the RX list. We have to
2684 * stall the upload engine before we can manipulate
2685 * the uplist pointer register, then unstall it when
2686 * we're finished. We also have to wait for the
2687 * stall command to complete before proceeding.
2688 * Note that we have to do this after any RX resets
2689 * have completed since the uplist register is cleared
2690 * by a reset.
2691 */
2692 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2693 xl_wait(sc);
2694 CSR_WRITE_4(sc, XL_UPLIST_PTR, vtophys(&sc->xl_ldata->xl_rx_list[0]));
2695 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2696 xl_wait(sc);
2697
2698
2699 if (sc->xl_type == XL_TYPE_905B) {
2700 /* Set polling interval */
2701 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2702 /* Load the address of the TX list */
2703 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2704 xl_wait(sc);
2705 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2706 vtophys(&sc->xl_ldata->xl_tx_list[0]));
2707 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2708 xl_wait(sc);
2709 }
2710
2711 /*
2712 * If the coax transceiver is on, make sure to enable
2713 * the DC-DC converter.
2714 */
2715 XL_SEL_WIN(3);
2716 if (sc->xl_xcvr == XL_XCVR_COAX)
2717 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2718 else
2719 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2720
2721 /* increase packet size to allow reception of 802.1q or ISL packets */
2722 if (sc->xl_type == XL_TYPE_905B)
2723 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2724 /* Clear out the stats counters. */
2725 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2726 sc->xl_stats_no_timeout = 1;
2727 xl_stats_update(sc);
2728 sc->xl_stats_no_timeout = 0;
2729 XL_SEL_WIN(4);
2730 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2731 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2732
2733 /*
2734 * Enable interrupts.
2735 */
2736 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2737 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2738 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2739 if (sc->xl_flags & XL_FLAG_FUNCREG)
2740 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2741
2742 /* Set the RX early threshold */
2743 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2744 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2745
2746 /* Enable receiver and transmitter. */
2747 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2748 xl_wait(sc);
2749 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2750 xl_wait(sc);
2751
2752 if (mii != NULL)
2753 mii_mediachg(mii);
2754
2755 /* Select window 7 for normal operations. */
2756 XL_SEL_WIN(7);
2757
2758 ifp->if_flags |= IFF_RUNNING;
2759 ifp->if_flags &= ~IFF_OACTIVE;
2760
2761 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz);
2762
2763 XL_UNLOCK(sc);
2764
2765 return;
2766 }
2767
2768 /*
2769 * Set media options.
2770 */
2771 static int
2772 xl_ifmedia_upd(ifp)
2773 struct ifnet *ifp;
2774 {
2775 struct xl_softc *sc;
2776 struct ifmedia *ifm = NULL;
2777 struct mii_data *mii = NULL;
2778
2779 sc = ifp->if_softc;
2780 if (sc->xl_miibus != NULL)
2781 mii = device_get_softc(sc->xl_miibus);
2782 if (mii == NULL)
2783 ifm = &sc->ifmedia;
2784 else
2785 ifm = &mii->mii_media;
2786
2787 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2788 case IFM_100_FX:
2789 case IFM_10_FL:
2790 case IFM_10_2:
2791 case IFM_10_5:
2792 xl_setmode(sc, ifm->ifm_media);
2793 return(0);
2794 break;
2795 default:
2796 break;
2797 }
2798
2799 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
2800 || sc->xl_media & XL_MEDIAOPT_BT4) {
2801 xl_init(sc);
2802 } else {
2803 xl_setmode(sc, ifm->ifm_media);
2804 }
2805
2806 return(0);
2807 }
2808
2809 /*
2810 * Report current media status.
2811 */
2812 static void
2813 xl_ifmedia_sts(ifp, ifmr)
2814 struct ifnet *ifp;
2815 struct ifmediareq *ifmr;
2816 {
2817 struct xl_softc *sc;
2818 u_int32_t icfg;
2819 struct mii_data *mii = NULL;
2820
2821 sc = ifp->if_softc;
2822 if (sc->xl_miibus != NULL)
2823 mii = device_get_softc(sc->xl_miibus);
2824
2825 XL_SEL_WIN(3);
2826 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
2827 icfg >>= XL_ICFG_CONNECTOR_BITS;
2828
2829 ifmr->ifm_active = IFM_ETHER;
2830
2831 switch(icfg) {
2832 case XL_XCVR_10BT:
2833 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2834 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2835 ifmr->ifm_active |= IFM_FDX;
2836 else
2837 ifmr->ifm_active |= IFM_HDX;
2838 break;
2839 case XL_XCVR_AUI:
2840 if (sc->xl_type == XL_TYPE_905B &&
2841 sc->xl_media == XL_MEDIAOPT_10FL) {
2842 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
2843 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2844 ifmr->ifm_active |= IFM_FDX;
2845 else
2846 ifmr->ifm_active |= IFM_HDX;
2847 } else
2848 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2849 break;
2850 case XL_XCVR_COAX:
2851 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
2852 break;
2853 /*
2854 * XXX MII and BTX/AUTO should be separate cases.
2855 */
2856
2857 case XL_XCVR_100BTX:
2858 case XL_XCVR_AUTO:
2859 case XL_XCVR_MII:
2860 if (mii != NULL) {
2861 mii_pollstat(mii);
2862 ifmr->ifm_active = mii->mii_media_active;
2863 ifmr->ifm_status = mii->mii_media_status;
2864 }
2865 break;
2866 case XL_XCVR_100BFX:
2867 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
2868 break;
2869 default:
2870 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, icfg);
2871 break;
2872 }
2873
2874 return;
2875 }
2876
2877 static int
2878 xl_ioctl(ifp, command, data)
2879 struct ifnet *ifp;
2880 u_long command;
2881 caddr_t data;
2882 {
2883 struct xl_softc *sc = ifp->if_softc;
2884 struct ifreq *ifr = (struct ifreq *) data;
2885 int error = 0;
2886 struct mii_data *mii = NULL;
2887 u_int8_t rxfilt;
2888
2889 XL_LOCK(sc);
2890
2891 switch(command) {
2892 case SIOCSIFFLAGS:
2893 XL_SEL_WIN(5);
2894 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2895 if (ifp->if_flags & IFF_UP) {
2896 if (ifp->if_flags & IFF_RUNNING &&
2897 ifp->if_flags & IFF_PROMISC &&
2898 !(sc->xl_if_flags & IFF_PROMISC)) {
2899 rxfilt |= XL_RXFILTER_ALLFRAMES;
2900 CSR_WRITE_2(sc, XL_COMMAND,
2901 XL_CMD_RX_SET_FILT|rxfilt);
2902 XL_SEL_WIN(7);
2903 } else if (ifp->if_flags & IFF_RUNNING &&
2904 !(ifp->if_flags & IFF_PROMISC) &&
2905 sc->xl_if_flags & IFF_PROMISC) {
2906 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2907 CSR_WRITE_2(sc, XL_COMMAND,
2908 XL_CMD_RX_SET_FILT|rxfilt);
2909 XL_SEL_WIN(7);
2910 } else
2911 xl_init(sc);
2912 } else {
2913 if (ifp->if_flags & IFF_RUNNING)
2914 xl_stop(sc);
2915 }
2916 sc->xl_if_flags = ifp->if_flags;
2917 error = 0;
2918 break;
2919 case SIOCADDMULTI:
2920 case SIOCDELMULTI:
2921 if (sc->xl_type == XL_TYPE_905B)
2922 xl_setmulti_hash(sc);
2923 else
2924 xl_setmulti(sc);
2925 error = 0;
2926 break;
2927 case SIOCGIFMEDIA:
2928 case SIOCSIFMEDIA:
2929 if (sc->xl_miibus != NULL)
2930 mii = device_get_softc(sc->xl_miibus);
2931 if (mii == NULL)
2932 error = ifmedia_ioctl(ifp, ifr,
2933 &sc->ifmedia, command);
2934 else
2935 error = ifmedia_ioctl(ifp, ifr,
2936 &mii->mii_media, command);
2937 break;
2938 default:
2939 error = ether_ioctl(ifp, command, data);
2940 break;
2941 }
2942
2943 XL_UNLOCK(sc);
2944
2945 return(error);
2946 }
2947
2948 static void
2949 xl_watchdog(ifp)
2950 struct ifnet *ifp;
2951 {
2952 struct xl_softc *sc;
2953 u_int16_t status = 0;
2954
2955 sc = ifp->if_softc;
2956
2957 XL_LOCK(sc);
2958
2959 ifp->if_oerrors++;
2960 XL_SEL_WIN(4);
2961 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
2962 printf("xl%d: watchdog timeout\n", sc->xl_unit);
2963
2964 if (status & XL_MEDIASTAT_CARRIER)
2965 printf("xl%d: no carrier - transceiver cable problem?\n",
2966 sc->xl_unit);
2967 xl_txeoc(sc);
2968 xl_txeof(sc);
2969 xl_rxeof(sc);
2970 xl_reset(sc);
2971 xl_init(sc);
2972
2973 if (ifp->if_snd.ifq_head != NULL)
2974 (*ifp->if_start)(ifp);
2975
2976 XL_UNLOCK(sc);
2977
2978 return;
2979 }
2980
2981 /*
2982 * Stop the adapter and free any mbufs allocated to the
2983 * RX and TX lists.
2984 */
2985 static void
2986 xl_stop(sc)
2987 struct xl_softc *sc;
2988 {
2989 register int i;
2990 struct ifnet *ifp;
2991
2992 XL_LOCK(sc);
2993
2994 ifp = &sc->arpcom.ac_if;
2995 ifp->if_timer = 0;
2996
2997 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
2998 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2999 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3000 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3001 xl_wait(sc);
3002 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3003 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3004 DELAY(800);
3005
3006 #ifdef foo
3007 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3008 xl_wait(sc);
3009 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3010 xl_wait(sc);
3011 #endif
3012
3013 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3014 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3015 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3016 if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3017
3018 /* Stop the stats updater. */
3019 untimeout(xl_stats_update, sc, sc->xl_stat_ch);
3020
3021 /*
3022 * Free data in the RX lists.
3023 */
3024 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3025 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3026 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3027 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3028 }
3029 }
3030 bzero((char *)&sc->xl_ldata->xl_rx_list,
3031 sizeof(sc->xl_ldata->xl_rx_list));
3032 /*
3033 * Free the TX list buffers.
3034 */
3035 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3036 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3037 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3038 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3039 }
3040 }
3041 bzero((char *)&sc->xl_ldata->xl_tx_list,
3042 sizeof(sc->xl_ldata->xl_tx_list));
3043
3044 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3045
3046 XL_UNLOCK(sc);
3047
3048 return;
3049 }
3050
3051 /*
3052 * Stop all chip I/O so that the kernel's probe routines don't
3053 * get confused by errant DMAs when rebooting.
3054 */
3055 static void
3056 xl_shutdown(dev)
3057 device_t dev;
3058 {
3059 struct xl_softc *sc;
3060
3061 sc = device_get_softc(dev);
3062
3063 XL_LOCK(sc);
3064 xl_reset(sc);
3065 xl_stop(sc);
3066 XL_UNLOCK(sc);
3067
3068 return;
3069 }
3070
3071 static int
3072 xl_suspend(dev)
3073 device_t dev;
3074 {
3075 struct xl_softc *sc;
3076
3077 sc = device_get_softc(dev);
3078
3079 XL_LOCK(sc);
3080 xl_stop(sc);
3081 XL_UNLOCK(sc);
3082
3083 return(0);
3084 }
3085
3086 static int
3087 xl_resume(dev)
3088 device_t dev;
3089 {
3090 struct xl_softc *sc;
3091 struct ifnet *ifp;
3092
3093 sc = device_get_softc(dev);
3094 XL_LOCK(sc);
3095 ifp = &sc->arpcom.ac_if;
3096
3097 xl_reset(sc);
3098 if (ifp->if_flags & IFF_UP)
3099 xl_init(sc);
3100
3101 XL_UNLOCK(sc);
3102 return(0);
3103 }
Cache object: bd77a0aa46a0b22c78aa3de6394909ae
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