FreeBSD/Linux Kernel Cross Reference
sys/pci/if_xl.c
1 /*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
33
34 /*
35 * 3Com 3c90x Etherlink XL PCI NIC driver
36 *
37 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
38 * bus-master chips (3c90x cards and embedded controllers) including
39 * the following:
40 *
41 * 3Com 3c900-TPO 10Mbps/RJ-45
42 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
43 * 3Com 3c905-TX 10/100Mbps/RJ-45
44 * 3Com 3c905-T4 10/100Mbps/RJ-45
45 * 3Com 3c900B-TPO 10Mbps/RJ-45
46 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
47 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
48 * 3Com 3c900B-FL 10Mbps/Fiber-optic
49 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
50 * 3Com 3c905B-TX 10/100Mbps/RJ-45
51 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
52 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
53 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
54 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
55 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
56 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
57 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
58 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
59 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
60 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
61 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
62 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
66 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
67 * Dell on-board 3c920 10/100Mbps/RJ-45
68 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
69 * Dell Latitude laptop docking station embedded 3c905-TX
70 *
71 * Written by Bill Paul <wpaul@ctr.columbia.edu>
72 * Electrical Engineering Department
73 * Columbia University, New York City
74 */
75
76 /*
77 * The 3c90x series chips use a bus-master DMA interface for transfering
78 * packets to and from the controller chip. Some of the "vortex" cards
79 * (3c59x) also supported a bus master mode, however for those chips
80 * you could only DMA packets to/from a contiguous memory buffer. For
81 * transmission this would mean copying the contents of the queued mbuf
82 * chain into an mbuf cluster and then DMAing the cluster. This extra
83 * copy would sort of defeat the purpose of the bus master support for
84 * any packet that doesn't fit into a single mbuf.
85 *
86 * By contrast, the 3c90x cards support a fragment-based bus master
87 * mode where mbuf chains can be encapsulated using TX descriptors.
88 * This is similar to other PCI chips such as the Texas Instruments
89 * ThunderLAN and the Intel 82557/82558.
90 *
91 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
92 * bus master chips because they maintain the old PIO interface for
93 * backwards compatibility, but starting with the 3c905B and the
94 * "cyclone" chips, the compatibility interface has been dropped.
95 * Since using bus master DMA is a big win, we use this driver to
96 * support the PCI "boomerang" chips even though they work with the
97 * "vortex" driver in order to obtain better performance.
98 *
99 * This driver is in the /sys/pci directory because it only supports
100 * PCI-based NICs.
101 */
102
103 #include <sys/cdefs.h>
104 __FBSDID("$FreeBSD: releng/5.1/sys/pci/if_xl.c 113812 2003-04-21 18:34:04Z imp $");
105
106 #include <sys/param.h>
107 #include <sys/systm.h>
108 #include <sys/sockio.h>
109 #include <sys/endian.h>
110 #include <sys/mbuf.h>
111 #include <sys/kernel.h>
112 #include <sys/socket.h>
113
114 #include <net/if.h>
115 #include <net/if_arp.h>
116 #include <net/ethernet.h>
117 #include <net/if_dl.h>
118 #include <net/if_media.h>
119
120 #include <net/bpf.h>
121
122 #include <machine/bus_memio.h>
123 #include <machine/bus_pio.h>
124 #include <machine/bus.h>
125 #include <machine/resource.h>
126 #include <sys/bus.h>
127 #include <sys/rman.h>
128
129 #include <dev/mii/mii.h>
130 #include <dev/mii/miivar.h>
131
132 #include <pci/pcireg.h>
133 #include <pci/pcivar.h>
134
135 MODULE_DEPEND(xl, pci, 1, 1, 1);
136 MODULE_DEPEND(xl, ether, 1, 1, 1);
137 MODULE_DEPEND(xl, miibus, 1, 1, 1);
138
139 /* "controller miibus0" required. See GENERIC if you get errors here. */
140 #include "miibus_if.h"
141
142 #include <pci/if_xlreg.h>
143
144 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
145
146 /*
147 * Various supported device vendors/types and their names.
148 */
149 static struct xl_type xl_devs[] = {
150 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
151 "3Com 3c900-TPO Etherlink XL" },
152 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
153 "3Com 3c900-COMBO Etherlink XL" },
154 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
155 "3Com 3c905-TX Fast Etherlink XL" },
156 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
157 "3Com 3c905-T4 Fast Etherlink XL" },
158 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
159 "3Com 3c900B-TPO Etherlink XL" },
160 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
161 "3Com 3c900B-COMBO Etherlink XL" },
162 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
163 "3Com 3c900B-TPC Etherlink XL" },
164 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
165 "3Com 3c900B-FL Etherlink XL" },
166 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
167 "3Com 3c905B-TX Fast Etherlink XL" },
168 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
169 "3Com 3c905B-T4 Fast Etherlink XL" },
170 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
171 "3Com 3c905B-FX/SC Fast Etherlink XL" },
172 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
173 "3Com 3c905B-COMBO Fast Etherlink XL" },
174 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
175 "3Com 3c905C-TX Fast Etherlink XL" },
176 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
177 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
178 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
179 "3Com 3c980 Fast Etherlink XL" },
180 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
181 "3Com 3c980C Fast Etherlink XL" },
182 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
183 "3Com 3cSOHO100-TX OfficeConnect" },
184 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
185 "3Com 3c450-TX HomeConnect" },
186 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
187 "3Com 3c555 Fast Etherlink XL" },
188 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
189 "3Com 3c556 Fast Etherlink XL" },
190 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
191 "3Com 3c556B Fast Etherlink XL" },
192 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
193 "3Com 3c575TX Fast Etherlink XL" },
194 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
195 "3Com 3c575B Fast Etherlink XL" },
196 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
197 "3Com 3c575C Fast Etherlink XL" },
198 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
199 "3Com 3c656 Fast Etherlink XL" },
200 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
201 "3Com 3c656B Fast Etherlink XL" },
202 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
203 "3Com 3c656C Fast Etherlink XL" },
204 { 0, 0, NULL }
205 };
206
207 static int xl_probe (device_t);
208 static int xl_attach (device_t);
209 static int xl_detach (device_t);
210
211 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *);
212 static void xl_stats_update (void *);
213 static int xl_encap (struct xl_softc *, struct xl_chain *,
214 struct mbuf *);
215 static void xl_rxeof (struct xl_softc *);
216 static int xl_rx_resync (struct xl_softc *);
217 static void xl_txeof (struct xl_softc *);
218 static void xl_txeof_90xB (struct xl_softc *);
219 static void xl_txeoc (struct xl_softc *);
220 static void xl_intr (void *);
221 static void xl_start (struct ifnet *);
222 static void xl_start_90xB (struct ifnet *);
223 static int xl_ioctl (struct ifnet *, u_long, caddr_t);
224 static void xl_init (void *);
225 static void xl_stop (struct xl_softc *);
226 static void xl_watchdog (struct ifnet *);
227 static void xl_shutdown (device_t);
228 static int xl_suspend (device_t);
229 static int xl_resume (device_t);
230
231 static int xl_ifmedia_upd (struct ifnet *);
232 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
233
234 static int xl_eeprom_wait (struct xl_softc *);
235 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int);
236 static void xl_mii_sync (struct xl_softc *);
237 static void xl_mii_send (struct xl_softc *, u_int32_t, int);
238 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *);
239 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *);
240
241 static void xl_setcfg (struct xl_softc *);
242 static void xl_setmode (struct xl_softc *, int);
243 static u_int8_t xl_calchash (caddr_t);
244 static void xl_setmulti (struct xl_softc *);
245 static void xl_setmulti_hash (struct xl_softc *);
246 static void xl_reset (struct xl_softc *);
247 static int xl_list_rx_init (struct xl_softc *);
248 static int xl_list_tx_init (struct xl_softc *);
249 static int xl_list_tx_init_90xB (struct xl_softc *);
250 static void xl_wait (struct xl_softc *);
251 static void xl_mediacheck (struct xl_softc *);
252 static void xl_choose_xcvr (struct xl_softc *, int);
253 static void xl_dma_map_addr (void *, bus_dma_segment_t *, int, int);
254 static void xl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t,
255 int);
256 static void xl_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t,
257 int);
258 #ifdef notdef
259 static void xl_testpacket (struct xl_softc *);
260 #endif
261
262 static int xl_miibus_readreg (device_t, int, int);
263 static int xl_miibus_writereg (device_t, int, int, int);
264 static void xl_miibus_statchg (device_t);
265 static void xl_miibus_mediainit (device_t);
266
267 static device_method_t xl_methods[] = {
268 /* Device interface */
269 DEVMETHOD(device_probe, xl_probe),
270 DEVMETHOD(device_attach, xl_attach),
271 DEVMETHOD(device_detach, xl_detach),
272 DEVMETHOD(device_shutdown, xl_shutdown),
273 DEVMETHOD(device_suspend, xl_suspend),
274 DEVMETHOD(device_resume, xl_resume),
275
276 /* bus interface */
277 DEVMETHOD(bus_print_child, bus_generic_print_child),
278 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
279
280 /* MII interface */
281 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
282 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
283 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
284 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
285
286 { 0, 0 }
287 };
288
289 static driver_t xl_driver = {
290 "xl",
291 xl_methods,
292 sizeof(struct xl_softc)
293 };
294
295 static devclass_t xl_devclass;
296
297 DRIVER_MODULE(xl, cardbus, xl_driver, xl_devclass, 0, 0);
298 DRIVER_MODULE(xl, pci, xl_driver, xl_devclass, 0, 0);
299 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
300
301 static void
302 xl_dma_map_addr(arg, segs, nseg, error)
303 void *arg;
304 bus_dma_segment_t *segs;
305 int nseg, error;
306 {
307 u_int32_t *paddr;
308
309 paddr = arg;
310 *paddr = segs->ds_addr;
311 }
312
313 static void
314 xl_dma_map_rxbuf(arg, segs, nseg, mapsize, error)
315 void *arg;
316 bus_dma_segment_t *segs;
317 int nseg;
318 bus_size_t mapsize;
319 int error;
320 {
321 u_int32_t *paddr;
322
323 if (error)
324 return;
325 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments"));
326 paddr = arg;
327 *paddr = segs->ds_addr;
328 }
329
330 static void
331 xl_dma_map_txbuf(arg, segs, nseg, mapsize, error)
332 void *arg;
333 bus_dma_segment_t *segs;
334 int nseg;
335 bus_size_t mapsize;
336 int error;
337 {
338 struct xl_list *l;
339 int i, total_len;
340
341 if (error)
342 return;
343
344 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments"));
345
346 total_len = 0;
347 l = arg;
348 for (i = 0; i < nseg; i++) {
349 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
350 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr);
351 l->xl_frag[i].xl_len = htole32(segs[i].ds_len);
352 total_len += segs[i].ds_len;
353 }
354 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len |
355 XL_LAST_FRAG);
356 l->xl_status = htole32(total_len);
357 l->xl_next = 0;
358 }
359
360 /*
361 * Murphy's law says that it's possible the chip can wedge and
362 * the 'command in progress' bit may never clear. Hence, we wait
363 * only a finite amount of time to avoid getting caught in an
364 * infinite loop. Normally this delay routine would be a macro,
365 * but it isn't called during normal operation so we can afford
366 * to make it a function.
367 */
368 static void
369 xl_wait(sc)
370 struct xl_softc *sc;
371 {
372 register int i;
373
374 for (i = 0; i < XL_TIMEOUT; i++) {
375 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
376 break;
377 }
378
379 if (i == XL_TIMEOUT)
380 printf("xl%d: command never completed!\n", sc->xl_unit);
381
382 return;
383 }
384
385 /*
386 * MII access routines are provided for adapters with external
387 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
388 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
389 * Note: if you don't perform the MDIO operations just right,
390 * it's possible to end up with code that works correctly with
391 * some chips/CPUs/processor speeds/bus speeds/etc but not
392 * with others.
393 */
394 #define MII_SET(x) \
395 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
396 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
397
398 #define MII_CLR(x) \
399 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
400 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
401
402 /*
403 * Sync the PHYs by setting data bit and strobing the clock 32 times.
404 */
405 static void
406 xl_mii_sync(sc)
407 struct xl_softc *sc;
408 {
409 register int i;
410
411 XL_SEL_WIN(4);
412 MII_SET(XL_MII_DIR|XL_MII_DATA);
413
414 for (i = 0; i < 32; i++) {
415 MII_SET(XL_MII_CLK);
416 MII_SET(XL_MII_DATA);
417 MII_CLR(XL_MII_CLK);
418 MII_SET(XL_MII_DATA);
419 }
420
421 return;
422 }
423
424 /*
425 * Clock a series of bits through the MII.
426 */
427 static void
428 xl_mii_send(sc, bits, cnt)
429 struct xl_softc *sc;
430 u_int32_t bits;
431 int cnt;
432 {
433 int i;
434
435 XL_SEL_WIN(4);
436 MII_CLR(XL_MII_CLK);
437
438 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
439 if (bits & i) {
440 MII_SET(XL_MII_DATA);
441 } else {
442 MII_CLR(XL_MII_DATA);
443 }
444 MII_CLR(XL_MII_CLK);
445 MII_SET(XL_MII_CLK);
446 }
447 }
448
449 /*
450 * Read an PHY register through the MII.
451 */
452 static int
453 xl_mii_readreg(sc, frame)
454 struct xl_softc *sc;
455 struct xl_mii_frame *frame;
456
457 {
458 int i, ack;
459
460 XL_LOCK(sc);
461
462 /*
463 * Set up frame for RX.
464 */
465 frame->mii_stdelim = XL_MII_STARTDELIM;
466 frame->mii_opcode = XL_MII_READOP;
467 frame->mii_turnaround = 0;
468 frame->mii_data = 0;
469
470 /*
471 * Select register window 4.
472 */
473
474 XL_SEL_WIN(4);
475
476 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
477 /*
478 * Turn on data xmit.
479 */
480 MII_SET(XL_MII_DIR);
481
482 xl_mii_sync(sc);
483
484 /*
485 * Send command/address info.
486 */
487 xl_mii_send(sc, frame->mii_stdelim, 2);
488 xl_mii_send(sc, frame->mii_opcode, 2);
489 xl_mii_send(sc, frame->mii_phyaddr, 5);
490 xl_mii_send(sc, frame->mii_regaddr, 5);
491
492 /* Idle bit */
493 MII_CLR((XL_MII_CLK|XL_MII_DATA));
494 MII_SET(XL_MII_CLK);
495
496 /* Turn off xmit. */
497 MII_CLR(XL_MII_DIR);
498
499 /* Check for ack */
500 MII_CLR(XL_MII_CLK);
501 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
502 MII_SET(XL_MII_CLK);
503
504 /*
505 * Now try reading data bits. If the ack failed, we still
506 * need to clock through 16 cycles to keep the PHY(s) in sync.
507 */
508 if (ack) {
509 for(i = 0; i < 16; i++) {
510 MII_CLR(XL_MII_CLK);
511 MII_SET(XL_MII_CLK);
512 }
513 goto fail;
514 }
515
516 for (i = 0x8000; i; i >>= 1) {
517 MII_CLR(XL_MII_CLK);
518 if (!ack) {
519 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
520 frame->mii_data |= i;
521 }
522 MII_SET(XL_MII_CLK);
523 }
524
525 fail:
526
527 MII_CLR(XL_MII_CLK);
528 MII_SET(XL_MII_CLK);
529
530 XL_UNLOCK(sc);
531
532 if (ack)
533 return(1);
534 return(0);
535 }
536
537 /*
538 * Write to a PHY register through the MII.
539 */
540 static int
541 xl_mii_writereg(sc, frame)
542 struct xl_softc *sc;
543 struct xl_mii_frame *frame;
544
545 {
546 XL_LOCK(sc);
547
548 /*
549 * Set up frame for TX.
550 */
551
552 frame->mii_stdelim = XL_MII_STARTDELIM;
553 frame->mii_opcode = XL_MII_WRITEOP;
554 frame->mii_turnaround = XL_MII_TURNAROUND;
555
556 /*
557 * Select the window 4.
558 */
559 XL_SEL_WIN(4);
560
561 /*
562 * Turn on data output.
563 */
564 MII_SET(XL_MII_DIR);
565
566 xl_mii_sync(sc);
567
568 xl_mii_send(sc, frame->mii_stdelim, 2);
569 xl_mii_send(sc, frame->mii_opcode, 2);
570 xl_mii_send(sc, frame->mii_phyaddr, 5);
571 xl_mii_send(sc, frame->mii_regaddr, 5);
572 xl_mii_send(sc, frame->mii_turnaround, 2);
573 xl_mii_send(sc, frame->mii_data, 16);
574
575 /* Idle bit. */
576 MII_SET(XL_MII_CLK);
577 MII_CLR(XL_MII_CLK);
578
579 /*
580 * Turn off xmit.
581 */
582 MII_CLR(XL_MII_DIR);
583
584 XL_UNLOCK(sc);
585
586 return(0);
587 }
588
589 static int
590 xl_miibus_readreg(dev, phy, reg)
591 device_t dev;
592 int phy, reg;
593 {
594 struct xl_softc *sc;
595 struct xl_mii_frame frame;
596
597 sc = device_get_softc(dev);
598
599 /*
600 * Pretend that PHYs are only available at MII address 24.
601 * This is to guard against problems with certain 3Com ASIC
602 * revisions that incorrectly map the internal transceiver
603 * control registers at all MII addresses. This can cause
604 * the miibus code to attach the same PHY several times over.
605 */
606 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
607 return(0);
608
609 bzero((char *)&frame, sizeof(frame));
610
611 frame.mii_phyaddr = phy;
612 frame.mii_regaddr = reg;
613 xl_mii_readreg(sc, &frame);
614
615 return(frame.mii_data);
616 }
617
618 static int
619 xl_miibus_writereg(dev, phy, reg, data)
620 device_t dev;
621 int phy, reg, data;
622 {
623 struct xl_softc *sc;
624 struct xl_mii_frame frame;
625
626 sc = device_get_softc(dev);
627
628 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
629 return(0);
630
631 bzero((char *)&frame, sizeof(frame));
632
633 frame.mii_phyaddr = phy;
634 frame.mii_regaddr = reg;
635 frame.mii_data = data;
636
637 xl_mii_writereg(sc, &frame);
638
639 return(0);
640 }
641
642 static void
643 xl_miibus_statchg(dev)
644 device_t dev;
645 {
646 struct xl_softc *sc;
647 struct mii_data *mii;
648
649
650 sc = device_get_softc(dev);
651 mii = device_get_softc(sc->xl_miibus);
652
653 XL_LOCK(sc);
654
655 xl_setcfg(sc);
656
657 /* Set ASIC's duplex mode to match the PHY. */
658 XL_SEL_WIN(3);
659 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
660 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
661 else
662 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
663 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
664
665 XL_UNLOCK(sc);
666
667 return;
668 }
669
670 /*
671 * Special support for the 3c905B-COMBO. This card has 10/100 support
672 * plus BNC and AUI ports. This means we will have both an miibus attached
673 * plus some non-MII media settings. In order to allow this, we have to
674 * add the extra media to the miibus's ifmedia struct, but we can't do
675 * that during xl_attach() because the miibus hasn't been attached yet.
676 * So instead, we wait until the miibus probe/attach is done, at which
677 * point we will get a callback telling is that it's safe to add our
678 * extra media.
679 */
680 static void
681 xl_miibus_mediainit(dev)
682 device_t dev;
683 {
684 struct xl_softc *sc;
685 struct mii_data *mii;
686 struct ifmedia *ifm;
687
688 sc = device_get_softc(dev);
689 mii = device_get_softc(sc->xl_miibus);
690 ifm = &mii->mii_media;
691
692 XL_LOCK(sc);
693
694 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
695 /*
696 * Check for a 10baseFL board in disguise.
697 */
698 if (sc->xl_type == XL_TYPE_905B &&
699 sc->xl_media == XL_MEDIAOPT_10FL) {
700 if (bootverbose)
701 printf("xl%d: found 10baseFL\n", sc->xl_unit);
702 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL);
703 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL);
704 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
705 ifmedia_add(ifm,
706 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
707 } else {
708 if (bootverbose)
709 printf("xl%d: found AUI\n", sc->xl_unit);
710 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL);
711 }
712 }
713
714 if (sc->xl_media & XL_MEDIAOPT_BNC) {
715 if (bootverbose)
716 printf("xl%d: found BNC\n", sc->xl_unit);
717 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL);
718 }
719
720 XL_UNLOCK(sc);
721
722 return;
723 }
724
725 /*
726 * The EEPROM is slow: give it time to come ready after issuing
727 * it a command.
728 */
729 static int
730 xl_eeprom_wait(sc)
731 struct xl_softc *sc;
732 {
733 int i;
734
735 for (i = 0; i < 100; i++) {
736 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
737 DELAY(162);
738 else
739 break;
740 }
741
742 if (i == 100) {
743 printf("xl%d: eeprom failed to come ready\n", sc->xl_unit);
744 return(1);
745 }
746
747 return(0);
748 }
749
750 /*
751 * Read a sequence of words from the EEPROM. Note that ethernet address
752 * data is stored in the EEPROM in network byte order.
753 */
754 static int
755 xl_read_eeprom(sc, dest, off, cnt, swap)
756 struct xl_softc *sc;
757 caddr_t dest;
758 int off;
759 int cnt;
760 int swap;
761 {
762 int err = 0, i;
763 u_int16_t word = 0, *ptr;
764 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
765 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
766 /* WARNING! DANGER!
767 * It's easy to accidentally overwrite the rom content!
768 * Note: the 3c575 uses 8bit EEPROM offsets.
769 */
770 XL_SEL_WIN(0);
771
772 if (xl_eeprom_wait(sc))
773 return(1);
774
775 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
776 off += 0x30;
777
778 for (i = 0; i < cnt; i++) {
779 if (sc->xl_flags & XL_FLAG_8BITROM)
780 CSR_WRITE_2(sc, XL_W0_EE_CMD,
781 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
782 else
783 CSR_WRITE_2(sc, XL_W0_EE_CMD,
784 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
785 err = xl_eeprom_wait(sc);
786 if (err)
787 break;
788 word = CSR_READ_2(sc, XL_W0_EE_DATA);
789 ptr = (u_int16_t *)(dest + (i * 2));
790 if (swap)
791 *ptr = ntohs(word);
792 else
793 *ptr = word;
794 }
795
796 return(err ? 1 : 0);
797 }
798
799 /*
800 * This routine is taken from the 3Com Etherlink XL manual,
801 * page 10-7. It calculates a CRC of the supplied multicast
802 * group address and returns the lower 8 bits, which are used
803 * as the multicast filter position.
804 * Note: the 3c905B currently only supports a 64-bit hash table,
805 * which means we really only need 6 bits, but the manual indicates
806 * that future chip revisions will have a 256-bit hash table,
807 * hence the routine is set up to calculate 8 bits of position
808 * info in case we need it some day.
809 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have a
810 * 256 bit hash table. This means we have to use all 8 bits regardless.
811 * On older cards, the upper 2 bits will be ignored. Grrrr....
812 */
813 static u_int8_t xl_calchash(addr)
814 caddr_t addr;
815 {
816 u_int32_t crc, carry;
817 int i, j;
818 u_int8_t c;
819
820 /* Compute CRC for the address value. */
821 crc = 0xFFFFFFFF; /* initial value */
822
823 for (i = 0; i < 6; i++) {
824 c = *(addr + i);
825 for (j = 0; j < 8; j++) {
826 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
827 crc <<= 1;
828 c >>= 1;
829 if (carry)
830 crc = (crc ^ 0x04c11db6) | carry;
831 }
832 }
833
834 /* return the filter bit position */
835 return(crc & 0x000000FF);
836 }
837
838 /*
839 * NICs older than the 3c905B have only one multicast option, which
840 * is to enable reception of all multicast frames.
841 */
842 static void
843 xl_setmulti(sc)
844 struct xl_softc *sc;
845 {
846 struct ifnet *ifp;
847 struct ifmultiaddr *ifma;
848 u_int8_t rxfilt;
849 int mcnt = 0;
850
851 ifp = &sc->arpcom.ac_if;
852
853 XL_SEL_WIN(5);
854 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
855
856 if (ifp->if_flags & IFF_ALLMULTI) {
857 rxfilt |= XL_RXFILTER_ALLMULTI;
858 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
859 return;
860 }
861
862 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
863 mcnt++;
864
865 if (mcnt)
866 rxfilt |= XL_RXFILTER_ALLMULTI;
867 else
868 rxfilt &= ~XL_RXFILTER_ALLMULTI;
869
870 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
871
872 return;
873 }
874
875 /*
876 * 3c905B adapters have a hash filter that we can program.
877 */
878 static void
879 xl_setmulti_hash(sc)
880 struct xl_softc *sc;
881 {
882 struct ifnet *ifp;
883 int h = 0, i;
884 struct ifmultiaddr *ifma;
885 u_int8_t rxfilt;
886 int mcnt = 0;
887
888 ifp = &sc->arpcom.ac_if;
889
890 XL_SEL_WIN(5);
891 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
892
893 if (ifp->if_flags & IFF_ALLMULTI) {
894 rxfilt |= XL_RXFILTER_ALLMULTI;
895 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
896 return;
897 } else
898 rxfilt &= ~XL_RXFILTER_ALLMULTI;
899
900
901 /* first, zot all the existing hash bits */
902 for (i = 0; i < XL_HASHFILT_SIZE; i++)
903 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
904
905 /* now program new ones */
906 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
907 if (ifma->ifma_addr->sa_family != AF_LINK)
908 continue;
909 h = xl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
910 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h);
911 mcnt++;
912 }
913
914 if (mcnt)
915 rxfilt |= XL_RXFILTER_MULTIHASH;
916 else
917 rxfilt &= ~XL_RXFILTER_MULTIHASH;
918
919 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
920
921 return;
922 }
923
924 #ifdef notdef
925 static void
926 xl_testpacket(sc)
927 struct xl_softc *sc;
928 {
929 struct mbuf *m;
930 struct ifnet *ifp;
931
932 ifp = &sc->arpcom.ac_if;
933
934 MGETHDR(m, M_DONTWAIT, MT_DATA);
935
936 if (m == NULL)
937 return;
938
939 bcopy(&sc->arpcom.ac_enaddr,
940 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
941 bcopy(&sc->arpcom.ac_enaddr,
942 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
943 mtod(m, struct ether_header *)->ether_type = htons(3);
944 mtod(m, unsigned char *)[14] = 0;
945 mtod(m, unsigned char *)[15] = 0;
946 mtod(m, unsigned char *)[16] = 0xE3;
947 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
948 IF_ENQUEUE(&ifp->if_snd, m);
949 xl_start(ifp);
950
951 return;
952 }
953 #endif
954
955 static void
956 xl_setcfg(sc)
957 struct xl_softc *sc;
958 {
959 u_int32_t icfg;
960
961 XL_SEL_WIN(3);
962 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
963 icfg &= ~XL_ICFG_CONNECTOR_MASK;
964 if (sc->xl_media & XL_MEDIAOPT_MII ||
965 sc->xl_media & XL_MEDIAOPT_BT4)
966 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
967 if (sc->xl_media & XL_MEDIAOPT_BTX)
968 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
969
970 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
971 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
972
973 return;
974 }
975
976 static void
977 xl_setmode(sc, media)
978 struct xl_softc *sc;
979 int media;
980 {
981 u_int32_t icfg;
982 u_int16_t mediastat;
983
984 printf("xl%d: selecting ", sc->xl_unit);
985
986 XL_SEL_WIN(4);
987 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
988 XL_SEL_WIN(3);
989 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
990
991 if (sc->xl_media & XL_MEDIAOPT_BT) {
992 if (IFM_SUBTYPE(media) == IFM_10_T) {
993 printf("10baseT transceiver, ");
994 sc->xl_xcvr = XL_XCVR_10BT;
995 icfg &= ~XL_ICFG_CONNECTOR_MASK;
996 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
997 mediastat |= XL_MEDIASTAT_LINKBEAT|
998 XL_MEDIASTAT_JABGUARD;
999 mediastat &= ~XL_MEDIASTAT_SQEENB;
1000 }
1001 }
1002
1003 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1004 if (IFM_SUBTYPE(media) == IFM_100_FX) {
1005 printf("100baseFX port, ");
1006 sc->xl_xcvr = XL_XCVR_100BFX;
1007 icfg &= ~XL_ICFG_CONNECTOR_MASK;
1008 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
1009 mediastat |= XL_MEDIASTAT_LINKBEAT;
1010 mediastat &= ~XL_MEDIASTAT_SQEENB;
1011 }
1012 }
1013
1014 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1015 if (IFM_SUBTYPE(media) == IFM_10_5) {
1016 printf("AUI port, ");
1017 sc->xl_xcvr = XL_XCVR_AUI;
1018 icfg &= ~XL_ICFG_CONNECTOR_MASK;
1019 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
1020 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
1021 XL_MEDIASTAT_JABGUARD);
1022 mediastat |= ~XL_MEDIASTAT_SQEENB;
1023 }
1024 if (IFM_SUBTYPE(media) == IFM_10_FL) {
1025 printf("10baseFL transceiver, ");
1026 sc->xl_xcvr = XL_XCVR_AUI;
1027 icfg &= ~XL_ICFG_CONNECTOR_MASK;
1028 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
1029 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
1030 XL_MEDIASTAT_JABGUARD);
1031 mediastat |= ~XL_MEDIASTAT_SQEENB;
1032 }
1033 }
1034
1035 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1036 if (IFM_SUBTYPE(media) == IFM_10_2) {
1037 printf("BNC port, ");
1038 sc->xl_xcvr = XL_XCVR_COAX;
1039 icfg &= ~XL_ICFG_CONNECTOR_MASK;
1040 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
1041 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
1042 XL_MEDIASTAT_JABGUARD|
1043 XL_MEDIASTAT_SQEENB);
1044 }
1045 }
1046
1047 if ((media & IFM_GMASK) == IFM_FDX ||
1048 IFM_SUBTYPE(media) == IFM_100_FX) {
1049 printf("full duplex\n");
1050 XL_SEL_WIN(3);
1051 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
1052 } else {
1053 printf("half duplex\n");
1054 XL_SEL_WIN(3);
1055 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
1056 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
1057 }
1058
1059 if (IFM_SUBTYPE(media) == IFM_10_2)
1060 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
1061 else
1062 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
1063 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
1064 XL_SEL_WIN(4);
1065 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
1066 DELAY(800);
1067 XL_SEL_WIN(7);
1068
1069 return;
1070 }
1071
1072 static void
1073 xl_reset(sc)
1074 struct xl_softc *sc;
1075 {
1076 register int i;
1077
1078 XL_SEL_WIN(0);
1079 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
1080 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
1081 XL_RESETOPT_DISADVFD:0));
1082
1083 for (i = 0; i < XL_TIMEOUT; i++) {
1084 DELAY(10);
1085 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
1086 break;
1087 }
1088
1089 if (i == XL_TIMEOUT)
1090 printf("xl%d: reset didn't complete\n", sc->xl_unit);
1091
1092 /* Reset TX and RX. */
1093 /* Note: the RX reset takes an absurd amount of time
1094 * on newer versions of the Tornado chips such as those
1095 * on the 3c905CX and newer 3c908C cards. We wait an
1096 * extra amount of time so that xl_wait() doesn't complain
1097 * and annoy the users.
1098 */
1099 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
1100 DELAY(100000);
1101 xl_wait(sc);
1102 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1103 xl_wait(sc);
1104
1105 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
1106 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
1107 XL_SEL_WIN(2);
1108 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc,
1109 XL_W2_RESET_OPTIONS)
1110 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0)
1111 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0)
1112 );
1113 }
1114
1115 /* Wait a little while for the chip to get its brains in order. */
1116 DELAY(100000);
1117 return;
1118 }
1119
1120 /*
1121 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1122 * IDs against our list and return a device name if we find a match.
1123 */
1124 static int
1125 xl_probe(dev)
1126 device_t dev;
1127 {
1128 struct xl_type *t;
1129
1130 t = xl_devs;
1131
1132 while(t->xl_name != NULL) {
1133 if ((pci_get_vendor(dev) == t->xl_vid) &&
1134 (pci_get_device(dev) == t->xl_did)) {
1135 device_set_desc(dev, t->xl_name);
1136 return(0);
1137 }
1138 t++;
1139 }
1140
1141 return(ENXIO);
1142 }
1143
1144 /*
1145 * This routine is a kludge to work around possible hardware faults
1146 * or manufacturing defects that can cause the media options register
1147 * (or reset options register, as it's called for the first generation
1148 * 3c90x adapters) to return an incorrect result. I have encountered
1149 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1150 * which doesn't have any of the 'mediaopt' bits set. This screws up
1151 * the attach routine pretty badly because it doesn't know what media
1152 * to look for. If we find ourselves in this predicament, this routine
1153 * will try to guess the media options values and warn the user of a
1154 * possible manufacturing defect with his adapter/system/whatever.
1155 */
1156 static void
1157 xl_mediacheck(sc)
1158 struct xl_softc *sc;
1159 {
1160
1161 /*
1162 * If some of the media options bits are set, assume they are
1163 * correct. If not, try to figure it out down below.
1164 * XXX I should check for 10baseFL, but I don't have an adapter
1165 * to test with.
1166 */
1167 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1168 /*
1169 * Check the XCVR value. If it's not in the normal range
1170 * of values, we need to fake it up here.
1171 */
1172 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1173 return;
1174 else {
1175 printf("xl%d: bogus xcvr value "
1176 "in EEPROM (%x)\n", sc->xl_unit, sc->xl_xcvr);
1177 printf("xl%d: choosing new default based "
1178 "on card type\n", sc->xl_unit);
1179 }
1180 } else {
1181 if (sc->xl_type == XL_TYPE_905B &&
1182 sc->xl_media & XL_MEDIAOPT_10FL)
1183 return;
1184 printf("xl%d: WARNING: no media options bits set in "
1185 "the media options register!!\n", sc->xl_unit);
1186 printf("xl%d: this could be a manufacturing defect in "
1187 "your adapter or system\n", sc->xl_unit);
1188 printf("xl%d: attempting to guess media type; you "
1189 "should probably consult your vendor\n", sc->xl_unit);
1190 }
1191
1192 xl_choose_xcvr(sc, 1);
1193
1194 return;
1195 }
1196
1197 static void
1198 xl_choose_xcvr(sc, verbose)
1199 struct xl_softc *sc;
1200 int verbose;
1201 {
1202 u_int16_t devid;
1203
1204 /*
1205 * Read the device ID from the EEPROM.
1206 * This is what's loaded into the PCI device ID register, so it has
1207 * to be correct otherwise we wouldn't have gotten this far.
1208 */
1209 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1210
1211 switch(devid) {
1212 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1213 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1214 sc->xl_media = XL_MEDIAOPT_BT;
1215 sc->xl_xcvr = XL_XCVR_10BT;
1216 if (verbose)
1217 printf("xl%d: guessing 10BaseT "
1218 "transceiver\n", sc->xl_unit);
1219 break;
1220 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1221 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1222 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1223 sc->xl_xcvr = XL_XCVR_10BT;
1224 if (verbose)
1225 printf("xl%d: guessing COMBO "
1226 "(AUI/BNC/TP)\n", sc->xl_unit);
1227 break;
1228 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1229 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1230 sc->xl_xcvr = XL_XCVR_10BT;
1231 if (verbose)
1232 printf("xl%d: guessing TPC (BNC/TP)\n", sc->xl_unit);
1233 break;
1234 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1235 sc->xl_media = XL_MEDIAOPT_10FL;
1236 sc->xl_xcvr = XL_XCVR_AUI;
1237 if (verbose)
1238 printf("xl%d: guessing 10baseFL\n", sc->xl_unit);
1239 break;
1240 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1241 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1242 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1243 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1244 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1245 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1246 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1247 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1248 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1249 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1250 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1251 sc->xl_media = XL_MEDIAOPT_MII;
1252 sc->xl_xcvr = XL_XCVR_MII;
1253 if (verbose)
1254 printf("xl%d: guessing MII\n", sc->xl_unit);
1255 break;
1256 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1257 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1258 sc->xl_media = XL_MEDIAOPT_BT4;
1259 sc->xl_xcvr = XL_XCVR_MII;
1260 if (verbose)
1261 printf("xl%d: guessing 100BaseT4/MII\n", sc->xl_unit);
1262 break;
1263 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1264 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1265 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1266 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1267 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1268 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1269 sc->xl_media = XL_MEDIAOPT_BTX;
1270 sc->xl_xcvr = XL_XCVR_AUTO;
1271 if (verbose)
1272 printf("xl%d: guessing 10/100 internal\n", sc->xl_unit);
1273 break;
1274 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1275 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1276 sc->xl_xcvr = XL_XCVR_AUTO;
1277 if (verbose)
1278 printf("xl%d: guessing 10/100 "
1279 "plus BNC/AUI\n", sc->xl_unit);
1280 break;
1281 default:
1282 printf("xl%d: unknown device ID: %x -- "
1283 "defaulting to 10baseT\n", sc->xl_unit, devid);
1284 sc->xl_media = XL_MEDIAOPT_BT;
1285 break;
1286 }
1287
1288 return;
1289 }
1290
1291 /*
1292 * Attach the interface. Allocate softc structures, do ifmedia
1293 * setup and ethernet/BPF attach.
1294 */
1295 static int
1296 xl_attach(dev)
1297 device_t dev;
1298 {
1299 u_char eaddr[ETHER_ADDR_LEN];
1300 u_int16_t xcvr[2];
1301 struct xl_softc *sc;
1302 struct ifnet *ifp;
1303 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1304 int unit, error = 0, rid, res;
1305
1306 sc = device_get_softc(dev);
1307 unit = device_get_unit(dev);
1308
1309 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1310 MTX_DEF | MTX_RECURSE);
1311 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1312
1313 sc->xl_flags = 0;
1314 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555)
1315 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1316 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 ||
1317 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B)
1318 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1319 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1320 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1321 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555 ||
1322 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556)
1323 sc->xl_flags |= XL_FLAG_8BITROM;
1324 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B)
1325 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1326
1327 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A ||
1328 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B ||
1329 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C ||
1330 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B ||
1331 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C)
1332 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1333 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM;
1334 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656)
1335 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1336 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B)
1337 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1338 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C)
1339 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1340 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_656C)
1341 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1342 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656 ||
1343 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B)
1344 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1345 XL_FLAG_INVERT_LED_PWR;
1346 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_10_100BT_920B)
1347 sc->xl_flags |= XL_FLAG_PHYOK;
1348
1349 /*
1350 * If this is a 3c905B, we have to check one extra thing.
1351 * The 905B supports power management and may be placed in
1352 * a low-power mode (D3 mode), typically by certain operating
1353 * systems which shall not be named. The PCI BIOS is supposed
1354 * to reset the NIC and bring it out of low-power mode, but
1355 * some do not. Consequently, we have to see if this chip
1356 * supports power management, and if so, make sure it's not
1357 * in low-power mode. If power management is available, the
1358 * capid byte will be 0x01.
1359 *
1360 * I _think_ that what actually happens is that the chip
1361 * loses its PCI configuration during the transition from
1362 * D3 back to D0; this means that it should be possible for
1363 * us to save the PCI iobase, membase and IRQ, put the chip
1364 * back in the D0 state, then restore the PCI config ourselves.
1365 */
1366
1367 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1368 u_int32_t iobase, membase, irq;
1369
1370 /* Save important PCI config data. */
1371 iobase = pci_read_config(dev, XL_PCI_LOIO, 4);
1372 membase = pci_read_config(dev, XL_PCI_LOMEM, 4);
1373 irq = pci_read_config(dev, XL_PCI_INTLINE, 4);
1374
1375 /* Reset the power state. */
1376 printf("xl%d: chip is in D%d power mode "
1377 "-- setting to D0\n", unit,
1378 pci_get_powerstate(dev));
1379
1380 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1381
1382 /* Restore PCI config data. */
1383 pci_write_config(dev, XL_PCI_LOIO, iobase, 4);
1384 pci_write_config(dev, XL_PCI_LOMEM, membase, 4);
1385 pci_write_config(dev, XL_PCI_INTLINE, irq, 4);
1386 }
1387
1388 /*
1389 * Map control/status registers.
1390 */
1391 pci_enable_busmaster(dev);
1392
1393 rid = XL_PCI_LOMEM;
1394 res = SYS_RES_MEMORY;
1395
1396 sc->xl_res = bus_alloc_resource(dev, res, &rid,
1397 0, ~0, 1, RF_ACTIVE);
1398
1399 if (sc->xl_res != NULL) {
1400 sc->xl_flags |= XL_FLAG_USE_MMIO;
1401 if (bootverbose)
1402 printf("xl%d: using memory mapped I/O\n", unit);
1403 } else {
1404 rid = XL_PCI_LOIO;
1405 res = SYS_RES_IOPORT;
1406 sc->xl_res = bus_alloc_resource(dev, res, &rid,
1407 0, ~0, 1, RF_ACTIVE);
1408 if (sc->xl_res == NULL) {
1409 printf ("xl%d: couldn't map ports/memory\n", unit);
1410 error = ENXIO;
1411 goto fail;
1412 }
1413 if (bootverbose)
1414 printf("xl%d: using port I/O\n", unit);
1415 }
1416
1417 sc->xl_btag = rman_get_bustag(sc->xl_res);
1418 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1419
1420 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1421 rid = XL_PCI_FUNCMEM;
1422 sc->xl_fres = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1423 0, ~0, 1, RF_ACTIVE);
1424
1425 if (sc->xl_fres == NULL) {
1426 printf ("xl%d: couldn't map ports/memory\n", unit);
1427 error = ENXIO;
1428 goto fail;
1429 }
1430
1431 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1432 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1433 }
1434
1435 /* Allocate interrupt */
1436 rid = 0;
1437 sc->xl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1438 RF_SHAREABLE | RF_ACTIVE);
1439 if (sc->xl_irq == NULL) {
1440 printf("xl%d: couldn't map interrupt\n", unit);
1441 error = ENXIO;
1442 goto fail;
1443 }
1444
1445 /* Reset the adapter. */
1446 xl_reset(sc);
1447
1448 /*
1449 * Get station address from the EEPROM.
1450 */
1451 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1452 printf("xl%d: failed to read station address\n", sc->xl_unit);
1453 error = ENXIO;
1454 goto fail;
1455 }
1456
1457 /*
1458 * A 3Com chip was detected. Inform the world.
1459 */
1460 printf("xl%d: Ethernet address: %6D\n", unit, eaddr, ":");
1461
1462 sc->xl_unit = unit;
1463 callout_handle_init(&sc->xl_stat_ch);
1464 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1465
1466 /*
1467 * Now allocate a tag for the DMA descriptor lists and a chunk
1468 * of DMA-able memory based on the tag. Also obtain the DMA
1469 * addresses of the RX and TX ring, which we'll need later.
1470 * All of our lists are allocated as a contiguous block
1471 * of memory.
1472 */
1473 error = bus_dma_tag_create(NULL, 8, 0,
1474 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1475 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, &sc->xl_ldata.xl_rx_tag);
1476 if (error) {
1477 printf("xl%d: failed to allocate rx dma tag\n", unit);
1478 goto fail;
1479 }
1480
1481 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1482 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT,
1483 &sc->xl_ldata.xl_rx_dmamap);
1484 if (error) {
1485 printf("xl%d: no memory for rx list buffers!\n", unit);
1486 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1487 sc->xl_ldata.xl_rx_tag = NULL;
1488 goto fail;
1489 }
1490
1491 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1492 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1493 XL_RX_LIST_SZ, xl_dma_map_addr,
1494 &sc->xl_ldata.xl_rx_dmaaddr, 0);
1495 if (error) {
1496 printf("xl%d: cannot get dma address of the rx ring!\n", unit);
1497 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1498 sc->xl_ldata.xl_rx_dmamap);
1499 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1500 sc->xl_ldata.xl_rx_tag = NULL;
1501 goto fail;
1502 }
1503
1504 error = bus_dma_tag_create(NULL, 8, 0,
1505 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1506 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, &sc->xl_ldata.xl_tx_tag);
1507 if (error) {
1508 printf("xl%d: failed to allocate tx dma tag\n", unit);
1509 goto fail;
1510 }
1511
1512 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1513 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT,
1514 &sc->xl_ldata.xl_tx_dmamap);
1515 if (error) {
1516 printf("xl%d: no memory for list buffers!\n", unit);
1517 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1518 sc->xl_ldata.xl_tx_tag = NULL;
1519 goto fail;
1520 }
1521
1522 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1523 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1524 XL_TX_LIST_SZ, xl_dma_map_addr,
1525 &sc->xl_ldata.xl_tx_dmaaddr, 0);
1526 if (error) {
1527 printf("xl%d: cannot get dma address of the tx ring!\n", unit);
1528 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1529 sc->xl_ldata.xl_tx_dmamap);
1530 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1531 sc->xl_ldata.xl_tx_tag = NULL;
1532 goto fail;
1533 }
1534
1535 /*
1536 * Allocate a DMA tag for the mapping of mbufs.
1537 */
1538 error = bus_dma_tag_create(NULL, 1, 0,
1539 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1540 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, &sc->xl_mtag);
1541 if (error) {
1542 printf("xl%d: failed to allocate mbuf dma tag\n", unit);
1543 goto fail;
1544 }
1545
1546 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
1547 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
1548
1549 /* We need a spare DMA map for the RX ring. */
1550 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1551 if (error)
1552 goto fail;
1553
1554 /*
1555 * Figure out the card type. 3c905B adapters have the
1556 * 'supportsNoTxLength' bit set in the capabilities
1557 * word in the EEPROM.
1558 */
1559 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1560 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH)
1561 sc->xl_type = XL_TYPE_905B;
1562 else
1563 sc->xl_type = XL_TYPE_90X;
1564
1565 ifp = &sc->arpcom.ac_if;
1566 ifp->if_softc = sc;
1567 ifp->if_unit = unit;
1568 ifp->if_name = "xl";
1569 ifp->if_mtu = ETHERMTU;
1570 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1571 ifp->if_ioctl = xl_ioctl;
1572 ifp->if_output = ether_output;
1573 if (sc->xl_type == XL_TYPE_905B) {
1574 ifp->if_start = xl_start_90xB;
1575 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1576 ifp->if_capabilities = IFCAP_HWCSUM;
1577 } else
1578 ifp->if_start = xl_start;
1579 ifp->if_watchdog = xl_watchdog;
1580 ifp->if_init = xl_init;
1581 ifp->if_baudrate = 10000000;
1582 ifp->if_snd.ifq_maxlen = XL_TX_LIST_CNT - 1;
1583 ifp->if_capenable = ifp->if_capabilities;
1584
1585 /*
1586 * Now we have to see what sort of media we have.
1587 * This includes probing for an MII interace and a
1588 * possible PHY.
1589 */
1590 XL_SEL_WIN(3);
1591 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1592 if (bootverbose)
1593 printf("xl%d: media options word: %x\n", sc->xl_unit,
1594 sc->xl_media);
1595
1596 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1597 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1598 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1599 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1600
1601 xl_mediacheck(sc);
1602
1603 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
1604 || sc->xl_media & XL_MEDIAOPT_BT4) {
1605 if (bootverbose)
1606 printf("xl%d: found MII/AUTO\n", sc->xl_unit);
1607 xl_setcfg(sc);
1608 if (mii_phy_probe(dev, &sc->xl_miibus,
1609 xl_ifmedia_upd, xl_ifmedia_sts)) {
1610 printf("xl%d: no PHY found!\n", sc->xl_unit);
1611 error = ENXIO;
1612 goto fail;
1613 }
1614
1615 goto done;
1616 }
1617
1618 /*
1619 * Sanity check. If the user has selected "auto" and this isn't
1620 * a 10/100 card of some kind, we need to force the transceiver
1621 * type to something sane.
1622 */
1623 if (sc->xl_xcvr == XL_XCVR_AUTO)
1624 xl_choose_xcvr(sc, bootverbose);
1625
1626 /*
1627 * Do ifmedia setup.
1628 */
1629 if (sc->xl_media & XL_MEDIAOPT_BT) {
1630 if (bootverbose)
1631 printf("xl%d: found 10baseT\n", sc->xl_unit);
1632 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1633 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1634 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1635 ifmedia_add(&sc->ifmedia,
1636 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1637 }
1638
1639 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1640 /*
1641 * Check for a 10baseFL board in disguise.
1642 */
1643 if (sc->xl_type == XL_TYPE_905B &&
1644 sc->xl_media == XL_MEDIAOPT_10FL) {
1645 if (bootverbose)
1646 printf("xl%d: found 10baseFL\n", sc->xl_unit);
1647 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1648 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1649 0, NULL);
1650 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1651 ifmedia_add(&sc->ifmedia,
1652 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1653 } else {
1654 if (bootverbose)
1655 printf("xl%d: found AUI\n", sc->xl_unit);
1656 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1657 }
1658 }
1659
1660 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1661 if (bootverbose)
1662 printf("xl%d: found BNC\n", sc->xl_unit);
1663 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1664 }
1665
1666 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1667 if (bootverbose)
1668 printf("xl%d: found 100baseFX\n", sc->xl_unit);
1669 ifp->if_baudrate = 100000000;
1670 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1671 }
1672
1673 /* Choose a default media. */
1674 switch(sc->xl_xcvr) {
1675 case XL_XCVR_10BT:
1676 media = IFM_ETHER|IFM_10_T;
1677 xl_setmode(sc, media);
1678 break;
1679 case XL_XCVR_AUI:
1680 if (sc->xl_type == XL_TYPE_905B &&
1681 sc->xl_media == XL_MEDIAOPT_10FL) {
1682 media = IFM_ETHER|IFM_10_FL;
1683 xl_setmode(sc, media);
1684 } else {
1685 media = IFM_ETHER|IFM_10_5;
1686 xl_setmode(sc, media);
1687 }
1688 break;
1689 case XL_XCVR_COAX:
1690 media = IFM_ETHER|IFM_10_2;
1691 xl_setmode(sc, media);
1692 break;
1693 case XL_XCVR_AUTO:
1694 case XL_XCVR_100BTX:
1695 case XL_XCVR_MII:
1696 /* Chosen by miibus */
1697 break;
1698 case XL_XCVR_100BFX:
1699 media = IFM_ETHER|IFM_100_FX;
1700 break;
1701 default:
1702 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit,
1703 sc->xl_xcvr);
1704 /*
1705 * This will probably be wrong, but it prevents
1706 * the ifmedia code from panicking.
1707 */
1708 media = IFM_ETHER|IFM_10_T;
1709 break;
1710 }
1711
1712 if (sc->xl_miibus == NULL)
1713 ifmedia_set(&sc->ifmedia, media);
1714
1715 done:
1716
1717 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1718 XL_SEL_WIN(0);
1719 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1720 }
1721
1722 /*
1723 * Call MI attach routine.
1724 */
1725 ether_ifattach(ifp, eaddr);
1726
1727 /* Hook interrupt last to avoid having to lock softc */
1728 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET,
1729 xl_intr, sc, &sc->xl_intrhand);
1730 if (error) {
1731 printf("xl%d: couldn't set up irq\n", unit);
1732 ether_ifdetach(ifp);
1733 goto fail;
1734 }
1735
1736 fail:
1737 if (error)
1738 xl_detach(dev);
1739
1740 return(error);
1741 }
1742
1743 /*
1744 * Shutdown hardware and free up resources. This can be called any
1745 * time after the mutex has been initialized. It is called in both
1746 * the error case in attach and the normal detach case so it needs
1747 * to be careful about only freeing resources that have actually been
1748 * allocated.
1749 */
1750 static int
1751 xl_detach(dev)
1752 device_t dev;
1753 {
1754 struct xl_softc *sc;
1755 struct ifnet *ifp;
1756 int rid, res;
1757
1758 sc = device_get_softc(dev);
1759 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized"));
1760 XL_LOCK(sc);
1761 ifp = &sc->arpcom.ac_if;
1762
1763 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1764 rid = XL_PCI_LOMEM;
1765 res = SYS_RES_MEMORY;
1766 } else {
1767 rid = XL_PCI_LOIO;
1768 res = SYS_RES_IOPORT;
1769 }
1770
1771 /* These should only be active if attach succeeded */
1772 if (device_is_attached(dev)) {
1773 xl_reset(sc);
1774 xl_stop(sc);
1775 ether_ifdetach(ifp);
1776 }
1777 if (sc->xl_miibus)
1778 device_delete_child(dev, sc->xl_miibus);
1779 bus_generic_detach(dev);
1780 ifmedia_removeall(&sc->ifmedia);
1781
1782 if (sc->xl_intrhand)
1783 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1784 if (sc->xl_irq)
1785 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1786 if (sc->xl_fres != NULL)
1787 bus_release_resource(dev, SYS_RES_MEMORY,
1788 XL_PCI_FUNCMEM, sc->xl_fres);
1789 if (sc->xl_res)
1790 bus_release_resource(dev, res, rid, sc->xl_res);
1791
1792 if (sc->xl_mtag) {
1793 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1794 bus_dma_tag_destroy(sc->xl_mtag);
1795 }
1796 if (sc->xl_ldata.xl_rx_tag) {
1797 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1798 sc->xl_ldata.xl_rx_dmamap);
1799 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1800 sc->xl_ldata.xl_rx_dmamap);
1801 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1802 }
1803 if (sc->xl_ldata.xl_tx_tag) {
1804 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1805 sc->xl_ldata.xl_tx_dmamap);
1806 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1807 sc->xl_ldata.xl_tx_dmamap);
1808 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1809 }
1810
1811 XL_UNLOCK(sc);
1812 mtx_destroy(&sc->xl_mtx);
1813
1814 return(0);
1815 }
1816
1817 /*
1818 * Initialize the transmit descriptors.
1819 */
1820 static int
1821 xl_list_tx_init(sc)
1822 struct xl_softc *sc;
1823 {
1824 struct xl_chain_data *cd;
1825 struct xl_list_data *ld;
1826 int error, i;
1827
1828 cd = &sc->xl_cdata;
1829 ld = &sc->xl_ldata;
1830 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1831 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1832 error = bus_dmamap_create(sc->xl_mtag, 0,
1833 &cd->xl_tx_chain[i].xl_map);
1834 if (error)
1835 return(error);
1836 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1837 i * sizeof(struct xl_list);
1838 if (i == (XL_TX_LIST_CNT - 1))
1839 cd->xl_tx_chain[i].xl_next = NULL;
1840 else
1841 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1842 }
1843
1844 cd->xl_tx_free = &cd->xl_tx_chain[0];
1845 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1846
1847 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1848 return(0);
1849 }
1850
1851 /*
1852 * Initialize the transmit descriptors.
1853 */
1854 static int
1855 xl_list_tx_init_90xB(sc)
1856 struct xl_softc *sc;
1857 {
1858 struct xl_chain_data *cd;
1859 struct xl_list_data *ld;
1860 int error, i;
1861
1862 cd = &sc->xl_cdata;
1863 ld = &sc->xl_ldata;
1864 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1865 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1866 error = bus_dmamap_create(sc->xl_mtag, 0,
1867 &cd->xl_tx_chain[i].xl_map);
1868 if (error)
1869 return(error);
1870 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1871 i * sizeof(struct xl_list);
1872 if (i == (XL_TX_LIST_CNT - 1))
1873 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1874 else
1875 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1876 if (i == 0)
1877 cd->xl_tx_chain[i].xl_prev =
1878 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1879 else
1880 cd->xl_tx_chain[i].xl_prev =
1881 &cd->xl_tx_chain[i - 1];
1882 }
1883
1884 bzero(ld->xl_tx_list, XL_TX_LIST_SZ);
1885 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1886
1887 cd->xl_tx_prod = 1;
1888 cd->xl_tx_cons = 1;
1889 cd->xl_tx_cnt = 0;
1890
1891 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1892 return(0);
1893 }
1894
1895 /*
1896 * Initialize the RX descriptors and allocate mbufs for them. Note that
1897 * we arrange the descriptors in a closed ring, so that the last descriptor
1898 * points back to the first.
1899 */
1900 static int
1901 xl_list_rx_init(sc)
1902 struct xl_softc *sc;
1903 {
1904 struct xl_chain_data *cd;
1905 struct xl_list_data *ld;
1906 int error, i, next;
1907 u_int32_t nextptr;
1908
1909 cd = &sc->xl_cdata;
1910 ld = &sc->xl_ldata;
1911
1912 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1913 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1914 error = bus_dmamap_create(sc->xl_mtag, 0,
1915 &cd->xl_rx_chain[i].xl_map);
1916 if (error)
1917 return(error);
1918 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1919 if (error)
1920 return(error);
1921 if (i == (XL_RX_LIST_CNT - 1))
1922 next = 0;
1923 else
1924 next = i + 1;
1925 nextptr = ld->xl_rx_dmaaddr +
1926 next * sizeof(struct xl_list_onefrag);
1927 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1928 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1929 }
1930
1931 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1932 cd->xl_rx_head = &cd->xl_rx_chain[0];
1933
1934 return(0);
1935 }
1936
1937 /*
1938 * Initialize an RX descriptor and attach an MBUF cluster.
1939 * If we fail to do so, we need to leave the old mbuf and
1940 * the old DMA map untouched so that it can be reused.
1941 */
1942 static int
1943 xl_newbuf(sc, c)
1944 struct xl_softc *sc;
1945 struct xl_chain_onefrag *c;
1946 {
1947 struct mbuf *m_new = NULL;
1948 bus_dmamap_t map;
1949 int error;
1950 u_int32_t baddr;
1951
1952 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1953 if (m_new == NULL)
1954 return(ENOBUFS);
1955
1956 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1957
1958 /* Force longword alignment for packet payload. */
1959 m_adj(m_new, ETHER_ALIGN);
1960
1961 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new,
1962 xl_dma_map_rxbuf, &baddr, 0);
1963 if (error) {
1964 m_freem(m_new);
1965 printf("xl%d: can't map mbuf (error %d)\n", sc->xl_unit, error);
1966 return(error);
1967 }
1968
1969 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1970 map = c->xl_map;
1971 c->xl_map = sc->xl_tmpmap;
1972 sc->xl_tmpmap = map;
1973 c->xl_mbuf = m_new;
1974 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
1975 c->xl_ptr->xl_status = 0;
1976 c->xl_ptr->xl_frag.xl_addr = htole32(baddr);
1977 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
1978 return(0);
1979 }
1980
1981 static int
1982 xl_rx_resync(sc)
1983 struct xl_softc *sc;
1984 {
1985 struct xl_chain_onefrag *pos;
1986 int i;
1987
1988 pos = sc->xl_cdata.xl_rx_head;
1989
1990 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1991 if (pos->xl_ptr->xl_status)
1992 break;
1993 pos = pos->xl_next;
1994 }
1995
1996 if (i == XL_RX_LIST_CNT)
1997 return(0);
1998
1999 sc->xl_cdata.xl_rx_head = pos;
2000
2001 return(EAGAIN);
2002 }
2003
2004 /*
2005 * A frame has been uploaded: pass the resulting mbuf chain up to
2006 * the higher level protocols.
2007 */
2008 static void
2009 xl_rxeof(sc)
2010 struct xl_softc *sc;
2011 {
2012 struct mbuf *m;
2013 struct ifnet *ifp;
2014 struct xl_chain_onefrag *cur_rx;
2015 int total_len = 0;
2016 u_int32_t rxstat;
2017
2018 ifp = &sc->arpcom.ac_if;
2019
2020 again:
2021
2022 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
2023 BUS_DMASYNC_POSTREAD);
2024 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
2025 cur_rx = sc->xl_cdata.xl_rx_head;
2026 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
2027
2028 /*
2029 * If an error occurs, update stats, clear the
2030 * status word and leave the mbuf cluster in place:
2031 * it should simply get re-used next time this descriptor
2032 * comes up in the ring.
2033 */
2034 if (rxstat & XL_RXSTAT_UP_ERROR) {
2035 ifp->if_ierrors++;
2036 cur_rx->xl_ptr->xl_status = 0;
2037 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2038 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2039 continue;
2040 }
2041
2042 /*
2043 * If there error bit was not set, the upload complete
2044 * bit should be set which means we have a valid packet.
2045 * If not, something truly strange has happened.
2046 */
2047 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
2048 printf("xl%d: bad receive status -- "
2049 "packet dropped\n", sc->xl_unit);
2050 ifp->if_ierrors++;
2051 cur_rx->xl_ptr->xl_status = 0;
2052 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2053 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2054 continue;
2055 }
2056
2057 /* No errors; receive the packet. */
2058 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
2059 BUS_DMASYNC_POSTREAD);
2060 m = cur_rx->xl_mbuf;
2061 total_len = le32toh(cur_rx->xl_ptr->xl_status) &
2062 XL_RXSTAT_LENMASK;
2063
2064 /*
2065 * Try to conjure up a new mbuf cluster. If that
2066 * fails, it means we have an out of memory condition and
2067 * should leave the buffer in place and continue. This will
2068 * result in a lost packet, but there's little else we
2069 * can do in this situation.
2070 */
2071 if (xl_newbuf(sc, cur_rx)) {
2072 ifp->if_ierrors++;
2073 cur_rx->xl_ptr->xl_status = 0;
2074 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2075 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2076 continue;
2077 }
2078 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2079 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2080
2081 ifp->if_ipackets++;
2082 m->m_pkthdr.rcvif = ifp;
2083 m->m_pkthdr.len = m->m_len = total_len;
2084
2085 if (sc->xl_type == XL_TYPE_905B) {
2086 /* Do IP checksum checking. */
2087 if (rxstat & XL_RXSTAT_IPCKOK)
2088 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2089 if (!(rxstat & XL_RXSTAT_IPCKERR))
2090 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2091 if ((rxstat & XL_RXSTAT_TCPCOK &&
2092 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
2093 (rxstat & XL_RXSTAT_UDPCKOK &&
2094 !(rxstat & XL_RXSTAT_UDPCKERR))) {
2095 m->m_pkthdr.csum_flags |=
2096 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2097 m->m_pkthdr.csum_data = 0xffff;
2098 }
2099 }
2100
2101 (*ifp->if_input)(ifp, m);
2102 }
2103
2104 /*
2105 * Handle the 'end of channel' condition. When the upload
2106 * engine hits the end of the RX ring, it will stall. This
2107 * is our cue to flush the RX ring, reload the uplist pointer
2108 * register and unstall the engine.
2109 * XXX This is actually a little goofy. With the ThunderLAN
2110 * chip, you get an interrupt when the receiver hits the end
2111 * of the receive ring, which tells you exactly when you
2112 * you need to reload the ring pointer. Here we have to
2113 * fake it. I'm mad at myself for not being clever enough
2114 * to avoid the use of a goto here.
2115 */
2116 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
2117 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
2118 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2119 xl_wait(sc);
2120 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2121 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
2122 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2123 goto again;
2124 }
2125
2126 return;
2127 }
2128
2129 /*
2130 * A frame was downloaded to the chip. It's safe for us to clean up
2131 * the list buffers.
2132 */
2133 static void
2134 xl_txeof(sc)
2135 struct xl_softc *sc;
2136 {
2137 struct xl_chain *cur_tx;
2138 struct ifnet *ifp;
2139
2140 ifp = &sc->arpcom.ac_if;
2141
2142 /* Clear the timeout timer. */
2143 ifp->if_timer = 0;
2144
2145 /*
2146 * Go through our tx list and free mbufs for those
2147 * frames that have been uploaded. Note: the 3c905B
2148 * sets a special bit in the status word to let us
2149 * know that a frame has been downloaded, but the
2150 * original 3c900/3c905 adapters don't do that.
2151 * Consequently, we have to use a different test if
2152 * xl_type != XL_TYPE_905B.
2153 */
2154 while(sc->xl_cdata.xl_tx_head != NULL) {
2155 cur_tx = sc->xl_cdata.xl_tx_head;
2156
2157 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2158 break;
2159
2160 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2161 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2162 BUS_DMASYNC_POSTWRITE);
2163 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2164 m_freem(cur_tx->xl_mbuf);
2165 cur_tx->xl_mbuf = NULL;
2166 ifp->if_opackets++;
2167
2168 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2169 sc->xl_cdata.xl_tx_free = cur_tx;
2170 }
2171
2172 if (sc->xl_cdata.xl_tx_head == NULL) {
2173 ifp->if_flags &= ~IFF_OACTIVE;
2174 sc->xl_cdata.xl_tx_tail = NULL;
2175 } else {
2176 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2177 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2178 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2179 sc->xl_cdata.xl_tx_head->xl_phys);
2180 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2181 }
2182 }
2183
2184 return;
2185 }
2186
2187 static void
2188 xl_txeof_90xB(sc)
2189 struct xl_softc *sc;
2190 {
2191 struct xl_chain *cur_tx = NULL;
2192 struct ifnet *ifp;
2193 int idx;
2194
2195 ifp = &sc->arpcom.ac_if;
2196
2197 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2198 BUS_DMASYNC_POSTREAD);
2199 idx = sc->xl_cdata.xl_tx_cons;
2200 while(idx != sc->xl_cdata.xl_tx_prod) {
2201
2202 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2203
2204 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2205 XL_TXSTAT_DL_COMPLETE))
2206 break;
2207
2208 if (cur_tx->xl_mbuf != NULL) {
2209 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2210 BUS_DMASYNC_POSTWRITE);
2211 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2212 m_freem(cur_tx->xl_mbuf);
2213 cur_tx->xl_mbuf = NULL;
2214 }
2215
2216 ifp->if_opackets++;
2217
2218 sc->xl_cdata.xl_tx_cnt--;
2219 XL_INC(idx, XL_TX_LIST_CNT);
2220 ifp->if_timer = 0;
2221 }
2222
2223 sc->xl_cdata.xl_tx_cons = idx;
2224
2225 if (cur_tx != NULL)
2226 ifp->if_flags &= ~IFF_OACTIVE;
2227
2228 return;
2229 }
2230
2231 /*
2232 * TX 'end of channel' interrupt handler. Actually, we should
2233 * only get a 'TX complete' interrupt if there's a transmit error,
2234 * so this is really TX error handler.
2235 */
2236 static void
2237 xl_txeoc(sc)
2238 struct xl_softc *sc;
2239 {
2240 u_int8_t txstat;
2241
2242 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2243 if (txstat & XL_TXSTATUS_UNDERRUN ||
2244 txstat & XL_TXSTATUS_JABBER ||
2245 txstat & XL_TXSTATUS_RECLAIM) {
2246 printf("xl%d: transmission error: %x\n",
2247 sc->xl_unit, txstat);
2248 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2249 xl_wait(sc);
2250 if (sc->xl_type == XL_TYPE_905B) {
2251 if (sc->xl_cdata.xl_tx_cnt) {
2252 int i;
2253 struct xl_chain *c;
2254 i = sc->xl_cdata.xl_tx_cons;
2255 c = &sc->xl_cdata.xl_tx_chain[i];
2256 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2257 c->xl_phys);
2258 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2259 }
2260 } else {
2261 if (sc->xl_cdata.xl_tx_head != NULL)
2262 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2263 sc->xl_cdata.xl_tx_head->xl_phys);
2264 }
2265 /*
2266 * Remember to set this for the
2267 * first generation 3c90X chips.
2268 */
2269 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2270 if (txstat & XL_TXSTATUS_UNDERRUN &&
2271 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2272 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2273 printf("xl%d: tx underrun, increasing tx start"
2274 " threshold to %d bytes\n", sc->xl_unit,
2275 sc->xl_tx_thresh);
2276 }
2277 CSR_WRITE_2(sc, XL_COMMAND,
2278 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2279 if (sc->xl_type == XL_TYPE_905B) {
2280 CSR_WRITE_2(sc, XL_COMMAND,
2281 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2282 }
2283 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2284 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2285 } else {
2286 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2287 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2288 }
2289 /*
2290 * Write an arbitrary byte to the TX_STATUS register
2291 * to clear this interrupt/error and advance to the next.
2292 */
2293 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2294 }
2295
2296 return;
2297 }
2298
2299 static void
2300 xl_intr(arg)
2301 void *arg;
2302 {
2303 struct xl_softc *sc;
2304 struct ifnet *ifp;
2305 u_int16_t status;
2306
2307 sc = arg;
2308 XL_LOCK(sc);
2309 ifp = &sc->arpcom.ac_if;
2310
2311 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) {
2312
2313 CSR_WRITE_2(sc, XL_COMMAND,
2314 XL_CMD_INTR_ACK|(status & XL_INTRS));
2315
2316 if (status & XL_STAT_UP_COMPLETE) {
2317 int curpkts;
2318
2319 curpkts = ifp->if_ipackets;
2320 xl_rxeof(sc);
2321 if (curpkts == ifp->if_ipackets) {
2322 while (xl_rx_resync(sc))
2323 xl_rxeof(sc);
2324 }
2325 }
2326
2327 if (status & XL_STAT_DOWN_COMPLETE) {
2328 if (sc->xl_type == XL_TYPE_905B)
2329 xl_txeof_90xB(sc);
2330 else
2331 xl_txeof(sc);
2332 }
2333
2334 if (status & XL_STAT_TX_COMPLETE) {
2335 ifp->if_oerrors++;
2336 xl_txeoc(sc);
2337 }
2338
2339 if (status & XL_STAT_ADFAIL) {
2340 xl_reset(sc);
2341 xl_init(sc);
2342 }
2343
2344 if (status & XL_STAT_STATSOFLOW) {
2345 sc->xl_stats_no_timeout = 1;
2346 xl_stats_update(sc);
2347 sc->xl_stats_no_timeout = 0;
2348 }
2349 }
2350
2351 if (ifp->if_snd.ifq_head != NULL)
2352 (*ifp->if_start)(ifp);
2353
2354 XL_UNLOCK(sc);
2355
2356 return;
2357 }
2358
2359 static void
2360 xl_stats_update(xsc)
2361 void *xsc;
2362 {
2363 struct xl_softc *sc;
2364 struct ifnet *ifp;
2365 struct xl_stats xl_stats;
2366 u_int8_t *p;
2367 int i;
2368 struct mii_data *mii = NULL;
2369
2370 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2371
2372 sc = xsc;
2373 ifp = &sc->arpcom.ac_if;
2374 if (sc->xl_miibus != NULL)
2375 mii = device_get_softc(sc->xl_miibus);
2376
2377 p = (u_int8_t *)&xl_stats;
2378
2379 /* Read all the stats registers. */
2380 XL_SEL_WIN(6);
2381
2382 for (i = 0; i < 16; i++)
2383 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2384
2385 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2386
2387 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2388 xl_stats.xl_tx_single_collision +
2389 xl_stats.xl_tx_late_collision;
2390
2391 /*
2392 * Boomerang and cyclone chips have an extra stats counter
2393 * in window 4 (BadSSD). We have to read this too in order
2394 * to clear out all the stats registers and avoid a statsoflow
2395 * interrupt.
2396 */
2397 XL_SEL_WIN(4);
2398 CSR_READ_1(sc, XL_W4_BADSSD);
2399
2400 if ((mii != NULL) && (!sc->xl_stats_no_timeout))
2401 mii_tick(mii);
2402
2403 XL_SEL_WIN(7);
2404
2405 if (!sc->xl_stats_no_timeout)
2406 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz);
2407
2408 return;
2409 }
2410
2411 /*
2412 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2413 * pointers to the fragment pointers.
2414 */
2415 static int
2416 xl_encap(sc, c, m_head)
2417 struct xl_softc *sc;
2418 struct xl_chain *c;
2419 struct mbuf *m_head;
2420 {
2421 int error;
2422 u_int32_t status;
2423
2424 /*
2425 * Start packing the mbufs in this chain into
2426 * the fragment pointers. Stop when we run out
2427 * of fragments or hit the end of the mbuf chain.
2428 */
2429 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head,
2430 xl_dma_map_txbuf, c->xl_ptr, 0);
2431
2432 if (error && error != EFBIG) {
2433 m_freem(m_head);
2434 printf("xl%d: can't map mbuf (error %d)\n", sc->xl_unit, error);
2435 return(1);
2436 }
2437
2438 /*
2439 * Handle special case: we used up all 63 fragments,
2440 * but we have more mbufs left in the chain. Copy the
2441 * data into an mbuf cluster. Note that we don't
2442 * bother clearing the values in the other fragment
2443 * pointers/counters; it wouldn't gain us anything,
2444 * and would waste cycles.
2445 */
2446 if (error) {
2447 struct mbuf *m_new;
2448
2449 m_new = m_defrag(m_head, M_DONTWAIT);
2450 if (m_new == NULL) {
2451 m_freem(m_head);
2452 return(1);
2453 } else {
2454 m_head = m_new;
2455 }
2456
2457 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map,
2458 m_head, xl_dma_map_txbuf, c->xl_ptr, 0);
2459 if (error) {
2460 m_freem(m_head);
2461 printf("xl%d: can't map mbuf (error %d)\n",
2462 sc->xl_unit, error);
2463 return(1);
2464 }
2465 }
2466
2467 if (sc->xl_type == XL_TYPE_905B) {
2468 status = XL_TXSTAT_RND_DEFEAT;
2469
2470 if (m_head->m_pkthdr.csum_flags) {
2471 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2472 status |= XL_TXSTAT_IPCKSUM;
2473 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
2474 status |= XL_TXSTAT_TCPCKSUM;
2475 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
2476 status |= XL_TXSTAT_UDPCKSUM;
2477 }
2478 c->xl_ptr->xl_status = htole32(status);
2479 }
2480
2481 c->xl_mbuf = m_head;
2482 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2483 return(0);
2484 }
2485
2486 /*
2487 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2488 * to the mbuf data regions directly in the transmit lists. We also save a
2489 * copy of the pointers since the transmit list fragment pointers are
2490 * physical addresses.
2491 */
2492 static void
2493 xl_start(ifp)
2494 struct ifnet *ifp;
2495 {
2496 struct xl_softc *sc;
2497 struct mbuf *m_head = NULL;
2498 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2499 struct xl_chain *prev_tx;
2500 u_int32_t status;
2501 int error;
2502
2503 sc = ifp->if_softc;
2504 XL_LOCK(sc);
2505 /*
2506 * Check for an available queue slot. If there are none,
2507 * punt.
2508 */
2509 if (sc->xl_cdata.xl_tx_free == NULL) {
2510 xl_txeoc(sc);
2511 xl_txeof(sc);
2512 if (sc->xl_cdata.xl_tx_free == NULL) {
2513 ifp->if_flags |= IFF_OACTIVE;
2514 XL_UNLOCK(sc);
2515 return;
2516 }
2517 }
2518
2519 start_tx = sc->xl_cdata.xl_tx_free;
2520
2521 while(sc->xl_cdata.xl_tx_free != NULL) {
2522 IF_DEQUEUE(&ifp->if_snd, m_head);
2523 if (m_head == NULL)
2524 break;
2525
2526 /* Pick a descriptor off the free list. */
2527 prev_tx = cur_tx;
2528 cur_tx = sc->xl_cdata.xl_tx_free;
2529
2530 /* Pack the data into the descriptor. */
2531 error = xl_encap(sc, cur_tx, m_head);
2532 if (error) {
2533 cur_tx = prev_tx;
2534 continue;
2535 }
2536
2537 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2538 cur_tx->xl_next = NULL;
2539
2540 /* Chain it together. */
2541 if (prev != NULL) {
2542 prev->xl_next = cur_tx;
2543 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2544 }
2545 prev = cur_tx;
2546
2547 /*
2548 * If there's a BPF listener, bounce a copy of this frame
2549 * to him.
2550 */
2551 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2552 }
2553
2554 /*
2555 * If there are no packets queued, bail.
2556 */
2557 if (cur_tx == NULL) {
2558 XL_UNLOCK(sc);
2559 return;
2560 }
2561
2562 /*
2563 * Place the request for the upload interrupt
2564 * in the last descriptor in the chain. This way, if
2565 * we're chaining several packets at once, we'll only
2566 * get an interupt once for the whole chain rather than
2567 * once for each packet.
2568 */
2569 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2570 XL_TXSTAT_DL_INTR);
2571 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2572 BUS_DMASYNC_PREWRITE);
2573
2574 /*
2575 * Queue the packets. If the TX channel is clear, update
2576 * the downlist pointer register.
2577 */
2578 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2579 xl_wait(sc);
2580
2581 if (sc->xl_cdata.xl_tx_head != NULL) {
2582 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2583 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2584 htole32(start_tx->xl_phys);
2585 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status;
2586 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status =
2587 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR);
2588 sc->xl_cdata.xl_tx_tail = cur_tx;
2589 } else {
2590 sc->xl_cdata.xl_tx_head = start_tx;
2591 sc->xl_cdata.xl_tx_tail = cur_tx;
2592 }
2593 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2594 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2595
2596 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2597
2598 XL_SEL_WIN(7);
2599
2600 /*
2601 * Set a timeout in case the chip goes out to lunch.
2602 */
2603 ifp->if_timer = 5;
2604
2605 /*
2606 * XXX Under certain conditions, usually on slower machines
2607 * where interrupts may be dropped, it's possible for the
2608 * adapter to chew up all the buffers in the receive ring
2609 * and stall, without us being able to do anything about it.
2610 * To guard against this, we need to make a pass over the
2611 * RX queue to make sure there aren't any packets pending.
2612 * Doing it here means we can flush the receive ring at the
2613 * same time the chip is DMAing the transmit descriptors we
2614 * just gave it.
2615 *
2616 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2617 * nature of their chips in all their marketing literature;
2618 * we may as well take advantage of it. :)
2619 */
2620 xl_rxeof(sc);
2621
2622 XL_UNLOCK(sc);
2623
2624 return;
2625 }
2626
2627 static void
2628 xl_start_90xB(ifp)
2629 struct ifnet *ifp;
2630 {
2631 struct xl_softc *sc;
2632 struct mbuf *m_head = NULL;
2633 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2634 struct xl_chain *prev_tx;
2635 int error, idx;
2636
2637 sc = ifp->if_softc;
2638 XL_LOCK(sc);
2639
2640 if (ifp->if_flags & IFF_OACTIVE) {
2641 XL_UNLOCK(sc);
2642 return;
2643 }
2644
2645 idx = sc->xl_cdata.xl_tx_prod;
2646 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2647
2648 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
2649
2650 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2651 ifp->if_flags |= IFF_OACTIVE;
2652 break;
2653 }
2654
2655 IF_DEQUEUE(&ifp->if_snd, m_head);
2656 if (m_head == NULL)
2657 break;
2658
2659 prev_tx = cur_tx;
2660 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2661
2662 /* Pack the data into the descriptor. */
2663 error = xl_encap(sc, cur_tx, m_head);
2664 if (error) {
2665 cur_tx = prev_tx;
2666 continue;
2667 }
2668
2669 /* Chain it together. */
2670 if (prev != NULL)
2671 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2672 prev = cur_tx;
2673
2674 /*
2675 * If there's a BPF listener, bounce a copy of this frame
2676 * to him.
2677 */
2678 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2679
2680 XL_INC(idx, XL_TX_LIST_CNT);
2681 sc->xl_cdata.xl_tx_cnt++;
2682 }
2683
2684 /*
2685 * If there are no packets queued, bail.
2686 */
2687 if (cur_tx == NULL) {
2688 XL_UNLOCK(sc);
2689 return;
2690 }
2691
2692 /*
2693 * Place the request for the upload interrupt
2694 * in the last descriptor in the chain. This way, if
2695 * we're chaining several packets at once, we'll only
2696 * get an interupt once for the whole chain rather than
2697 * once for each packet.
2698 */
2699 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2700 XL_TXSTAT_DL_INTR);
2701 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2702 BUS_DMASYNC_PREWRITE);
2703
2704 /* Start transmission */
2705 sc->xl_cdata.xl_tx_prod = idx;
2706 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2707
2708 /*
2709 * Set a timeout in case the chip goes out to lunch.
2710 */
2711 ifp->if_timer = 5;
2712
2713 XL_UNLOCK(sc);
2714
2715 return;
2716 }
2717
2718 static void
2719 xl_init(xsc)
2720 void *xsc;
2721 {
2722 struct xl_softc *sc = xsc;
2723 struct ifnet *ifp = &sc->arpcom.ac_if;
2724 int error, i;
2725 u_int16_t rxfilt = 0;
2726 struct mii_data *mii = NULL;
2727
2728 XL_LOCK(sc);
2729
2730 /*
2731 * Cancel pending I/O and free all RX/TX buffers.
2732 */
2733 xl_stop(sc);
2734
2735 if (sc->xl_miibus == NULL) {
2736 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2737 xl_wait(sc);
2738 }
2739 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2740 xl_wait(sc);
2741 DELAY(10000);
2742
2743 if (sc->xl_miibus != NULL)
2744 mii = device_get_softc(sc->xl_miibus);
2745
2746 /* Init our MAC address */
2747 XL_SEL_WIN(2);
2748 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2749 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2750 sc->arpcom.ac_enaddr[i]);
2751 }
2752
2753 /* Clear the station mask. */
2754 for (i = 0; i < 3; i++)
2755 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2756 #ifdef notdef
2757 /* Reset TX and RX. */
2758 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2759 xl_wait(sc);
2760 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2761 xl_wait(sc);
2762 #endif
2763 /* Init circular RX list. */
2764 error = xl_list_rx_init(sc);
2765 if (error) {
2766 printf("xl%d: initialization of the rx ring failed (%d)\n",
2767 sc->xl_unit, error);
2768 xl_stop(sc);
2769 XL_UNLOCK(sc);
2770 return;
2771 }
2772
2773 /* Init TX descriptors. */
2774 if (sc->xl_type == XL_TYPE_905B)
2775 error = xl_list_tx_init_90xB(sc);
2776 else
2777 error = xl_list_tx_init(sc);
2778 if (error) {
2779 printf("xl%d: initialization of the tx ring failed (%d)\n",
2780 sc->xl_unit, error);
2781 xl_stop(sc);
2782 XL_UNLOCK(sc);
2783 }
2784
2785 /*
2786 * Set the TX freethresh value.
2787 * Note that this has no effect on 3c905B "cyclone"
2788 * cards but is required for 3c900/3c905 "boomerang"
2789 * cards in order to enable the download engine.
2790 */
2791 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2792
2793 /* Set the TX start threshold for best performance. */
2794 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
2795 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2796
2797 /*
2798 * If this is a 3c905B, also set the tx reclaim threshold.
2799 * This helps cut down on the number of tx reclaim errors
2800 * that could happen on a busy network. The chip multiplies
2801 * the register value by 16 to obtain the actual threshold
2802 * in bytes, so we divide by 16 when setting the value here.
2803 * The existing threshold value can be examined by reading
2804 * the register at offset 9 in window 5.
2805 */
2806 if (sc->xl_type == XL_TYPE_905B) {
2807 CSR_WRITE_2(sc, XL_COMMAND,
2808 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2809 }
2810
2811 /* Set RX filter bits. */
2812 XL_SEL_WIN(5);
2813 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2814
2815 /* Set the individual bit to receive frames for this host only. */
2816 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2817
2818 /* If we want promiscuous mode, set the allframes bit. */
2819 if (ifp->if_flags & IFF_PROMISC) {
2820 rxfilt |= XL_RXFILTER_ALLFRAMES;
2821 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2822 } else {
2823 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2824 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2825 }
2826
2827 /*
2828 * Set capture broadcast bit to capture broadcast frames.
2829 */
2830 if (ifp->if_flags & IFF_BROADCAST) {
2831 rxfilt |= XL_RXFILTER_BROADCAST;
2832 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2833 } else {
2834 rxfilt &= ~XL_RXFILTER_BROADCAST;
2835 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2836 }
2837
2838 /*
2839 * Program the multicast filter, if necessary.
2840 */
2841 if (sc->xl_type == XL_TYPE_905B)
2842 xl_setmulti_hash(sc);
2843 else
2844 xl_setmulti(sc);
2845
2846 /*
2847 * Load the address of the RX list. We have to
2848 * stall the upload engine before we can manipulate
2849 * the uplist pointer register, then unstall it when
2850 * we're finished. We also have to wait for the
2851 * stall command to complete before proceeding.
2852 * Note that we have to do this after any RX resets
2853 * have completed since the uplist register is cleared
2854 * by a reset.
2855 */
2856 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2857 xl_wait(sc);
2858 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2859 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2860 xl_wait(sc);
2861
2862
2863 if (sc->xl_type == XL_TYPE_905B) {
2864 /* Set polling interval */
2865 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2866 /* Load the address of the TX list */
2867 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2868 xl_wait(sc);
2869 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2870 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2871 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2872 xl_wait(sc);
2873 }
2874
2875 /*
2876 * If the coax transceiver is on, make sure to enable
2877 * the DC-DC converter.
2878 */
2879 XL_SEL_WIN(3);
2880 if (sc->xl_xcvr == XL_XCVR_COAX)
2881 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2882 else
2883 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2884
2885 /* increase packet size to allow reception of 802.1q or ISL packets */
2886 if (sc->xl_type == XL_TYPE_905B)
2887 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2888 /* Clear out the stats counters. */
2889 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2890 sc->xl_stats_no_timeout = 1;
2891 xl_stats_update(sc);
2892 sc->xl_stats_no_timeout = 0;
2893 XL_SEL_WIN(4);
2894 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2895 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2896
2897 /*
2898 * Enable interrupts.
2899 */
2900 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2901 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2902 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2903 if (sc->xl_flags & XL_FLAG_FUNCREG)
2904 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2905
2906 /* Set the RX early threshold */
2907 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2908 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2909
2910 /* Enable receiver and transmitter. */
2911 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2912 xl_wait(sc);
2913 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2914 xl_wait(sc);
2915
2916 if (mii != NULL)
2917 mii_mediachg(mii);
2918
2919 /* Select window 7 for normal operations. */
2920 XL_SEL_WIN(7);
2921
2922 ifp->if_flags |= IFF_RUNNING;
2923 ifp->if_flags &= ~IFF_OACTIVE;
2924
2925 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz);
2926
2927 XL_UNLOCK(sc);
2928
2929 return;
2930 }
2931
2932 /*
2933 * Set media options.
2934 */
2935 static int
2936 xl_ifmedia_upd(ifp)
2937 struct ifnet *ifp;
2938 {
2939 struct xl_softc *sc;
2940 struct ifmedia *ifm = NULL;
2941 struct mii_data *mii = NULL;
2942
2943 sc = ifp->if_softc;
2944 if (sc->xl_miibus != NULL)
2945 mii = device_get_softc(sc->xl_miibus);
2946 if (mii == NULL)
2947 ifm = &sc->ifmedia;
2948 else
2949 ifm = &mii->mii_media;
2950
2951 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2952 case IFM_100_FX:
2953 case IFM_10_FL:
2954 case IFM_10_2:
2955 case IFM_10_5:
2956 xl_setmode(sc, ifm->ifm_media);
2957 return(0);
2958 break;
2959 default:
2960 break;
2961 }
2962
2963 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
2964 || sc->xl_media & XL_MEDIAOPT_BT4) {
2965 xl_init(sc);
2966 } else {
2967 xl_setmode(sc, ifm->ifm_media);
2968 }
2969
2970 return(0);
2971 }
2972
2973 /*
2974 * Report current media status.
2975 */
2976 static void
2977 xl_ifmedia_sts(ifp, ifmr)
2978 struct ifnet *ifp;
2979 struct ifmediareq *ifmr;
2980 {
2981 struct xl_softc *sc;
2982 u_int32_t icfg;
2983 struct mii_data *mii = NULL;
2984
2985 sc = ifp->if_softc;
2986 if (sc->xl_miibus != NULL)
2987 mii = device_get_softc(sc->xl_miibus);
2988
2989 XL_SEL_WIN(3);
2990 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
2991 icfg >>= XL_ICFG_CONNECTOR_BITS;
2992
2993 ifmr->ifm_active = IFM_ETHER;
2994
2995 switch(icfg) {
2996 case XL_XCVR_10BT:
2997 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2998 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2999 ifmr->ifm_active |= IFM_FDX;
3000 else
3001 ifmr->ifm_active |= IFM_HDX;
3002 break;
3003 case XL_XCVR_AUI:
3004 if (sc->xl_type == XL_TYPE_905B &&
3005 sc->xl_media == XL_MEDIAOPT_10FL) {
3006 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
3007 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3008 ifmr->ifm_active |= IFM_FDX;
3009 else
3010 ifmr->ifm_active |= IFM_HDX;
3011 } else
3012 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
3013 break;
3014 case XL_XCVR_COAX:
3015 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
3016 break;
3017 /*
3018 * XXX MII and BTX/AUTO should be separate cases.
3019 */
3020
3021 case XL_XCVR_100BTX:
3022 case XL_XCVR_AUTO:
3023 case XL_XCVR_MII:
3024 if (mii != NULL) {
3025 mii_pollstat(mii);
3026 ifmr->ifm_active = mii->mii_media_active;
3027 ifmr->ifm_status = mii->mii_media_status;
3028 }
3029 break;
3030 case XL_XCVR_100BFX:
3031 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
3032 break;
3033 default:
3034 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, icfg);
3035 break;
3036 }
3037
3038 return;
3039 }
3040
3041 static int
3042 xl_ioctl(ifp, command, data)
3043 struct ifnet *ifp;
3044 u_long command;
3045 caddr_t data;
3046 {
3047 struct xl_softc *sc = ifp->if_softc;
3048 struct ifreq *ifr = (struct ifreq *) data;
3049 int error = 0;
3050 struct mii_data *mii = NULL;
3051 u_int8_t rxfilt;
3052
3053 XL_LOCK(sc);
3054
3055 switch(command) {
3056 case SIOCSIFFLAGS:
3057 XL_SEL_WIN(5);
3058 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
3059 if (ifp->if_flags & IFF_UP) {
3060 if (ifp->if_flags & IFF_RUNNING &&
3061 ifp->if_flags & IFF_PROMISC &&
3062 !(sc->xl_if_flags & IFF_PROMISC)) {
3063 rxfilt |= XL_RXFILTER_ALLFRAMES;
3064 CSR_WRITE_2(sc, XL_COMMAND,
3065 XL_CMD_RX_SET_FILT|rxfilt);
3066 XL_SEL_WIN(7);
3067 } else if (ifp->if_flags & IFF_RUNNING &&
3068 !(ifp->if_flags & IFF_PROMISC) &&
3069 sc->xl_if_flags & IFF_PROMISC) {
3070 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
3071 CSR_WRITE_2(sc, XL_COMMAND,
3072 XL_CMD_RX_SET_FILT|rxfilt);
3073 XL_SEL_WIN(7);
3074 } else
3075 xl_init(sc);
3076 } else {
3077 if (ifp->if_flags & IFF_RUNNING)
3078 xl_stop(sc);
3079 }
3080 sc->xl_if_flags = ifp->if_flags;
3081 error = 0;
3082 break;
3083 case SIOCADDMULTI:
3084 case SIOCDELMULTI:
3085 if (sc->xl_type == XL_TYPE_905B)
3086 xl_setmulti_hash(sc);
3087 else
3088 xl_setmulti(sc);
3089 error = 0;
3090 break;
3091 case SIOCGIFMEDIA:
3092 case SIOCSIFMEDIA:
3093 if (sc->xl_miibus != NULL)
3094 mii = device_get_softc(sc->xl_miibus);
3095 if (mii == NULL)
3096 error = ifmedia_ioctl(ifp, ifr,
3097 &sc->ifmedia, command);
3098 else
3099 error = ifmedia_ioctl(ifp, ifr,
3100 &mii->mii_media, command);
3101 break;
3102 default:
3103 error = ether_ioctl(ifp, command, data);
3104 break;
3105 }
3106
3107 XL_UNLOCK(sc);
3108
3109 return(error);
3110 }
3111
3112 static void
3113 xl_watchdog(ifp)
3114 struct ifnet *ifp;
3115 {
3116 struct xl_softc *sc;
3117 u_int16_t status = 0;
3118
3119 sc = ifp->if_softc;
3120
3121 XL_LOCK(sc);
3122
3123 ifp->if_oerrors++;
3124 XL_SEL_WIN(4);
3125 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3126 printf("xl%d: watchdog timeout\n", sc->xl_unit);
3127
3128 if (status & XL_MEDIASTAT_CARRIER)
3129 printf("xl%d: no carrier - transceiver cable problem?\n",
3130 sc->xl_unit);
3131 xl_txeoc(sc);
3132 xl_txeof(sc);
3133 xl_rxeof(sc);
3134 xl_reset(sc);
3135 xl_init(sc);
3136
3137 if (ifp->if_snd.ifq_head != NULL)
3138 (*ifp->if_start)(ifp);
3139
3140 XL_UNLOCK(sc);
3141
3142 return;
3143 }
3144
3145 /*
3146 * Stop the adapter and free any mbufs allocated to the
3147 * RX and TX lists.
3148 */
3149 static void
3150 xl_stop(sc)
3151 struct xl_softc *sc;
3152 {
3153 register int i;
3154 struct ifnet *ifp;
3155
3156 XL_LOCK(sc);
3157
3158 ifp = &sc->arpcom.ac_if;
3159 ifp->if_timer = 0;
3160
3161 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3162 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3163 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3164 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3165 xl_wait(sc);
3166 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3167 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3168 DELAY(800);
3169
3170 #ifdef foo
3171 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3172 xl_wait(sc);
3173 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3174 xl_wait(sc);
3175 #endif
3176
3177 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3178 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3179 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3180 if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3181
3182 /* Stop the stats updater. */
3183 untimeout(xl_stats_update, sc, sc->xl_stat_ch);
3184
3185 /*
3186 * Free data in the RX lists.
3187 */
3188 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3189 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3190 bus_dmamap_unload(sc->xl_mtag,
3191 sc->xl_cdata.xl_rx_chain[i].xl_map);
3192 bus_dmamap_destroy(sc->xl_mtag,
3193 sc->xl_cdata.xl_rx_chain[i].xl_map);
3194 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3195 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3196 }
3197 }
3198 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3199 /*
3200 * Free the TX list buffers.
3201 */
3202 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3203 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3204 bus_dmamap_unload(sc->xl_mtag,
3205 sc->xl_cdata.xl_tx_chain[i].xl_map);
3206 bus_dmamap_destroy(sc->xl_mtag,
3207 sc->xl_cdata.xl_tx_chain[i].xl_map);
3208 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3209 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3210 }
3211 }
3212 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3213
3214 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3215
3216 XL_UNLOCK(sc);
3217
3218 return;
3219 }
3220
3221 /*
3222 * Stop all chip I/O so that the kernel's probe routines don't
3223 * get confused by errant DMAs when rebooting.
3224 */
3225 static void
3226 xl_shutdown(dev)
3227 device_t dev;
3228 {
3229 struct xl_softc *sc;
3230
3231 sc = device_get_softc(dev);
3232
3233 XL_LOCK(sc);
3234 xl_reset(sc);
3235 xl_stop(sc);
3236 XL_UNLOCK(sc);
3237
3238 return;
3239 }
3240
3241 static int
3242 xl_suspend(dev)
3243 device_t dev;
3244 {
3245 struct xl_softc *sc;
3246
3247 sc = device_get_softc(dev);
3248
3249 XL_LOCK(sc);
3250 xl_stop(sc);
3251 XL_UNLOCK(sc);
3252
3253 return(0);
3254 }
3255
3256 static int
3257 xl_resume(dev)
3258 device_t dev;
3259 {
3260 struct xl_softc *sc;
3261 struct ifnet *ifp;
3262
3263 sc = device_get_softc(dev);
3264 XL_LOCK(sc);
3265 ifp = &sc->arpcom.ac_if;
3266
3267 xl_reset(sc);
3268 if (ifp->if_flags & IFF_UP)
3269 xl_init(sc);
3270
3271 XL_UNLOCK(sc);
3272 return(0);
3273 }
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