Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/pci/if_xl.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/5.3/sys/pci/if_xl.c 135397 2004-09-17 19:46:40Z glebius $"); 35 36 /* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77 /* 78 * The 3c90x series chips use a bus-master DMA interface for transfering 79 * packets to and from the controller chip. Some of the "vortex" cards 80 * (3c59x) also supported a bus master mode, however for those chips 81 * you could only DMA packets to/from a contiguous memory buffer. For 82 * transmission this would mean copying the contents of the queued mbuf 83 * chain into an mbuf cluster and then DMAing the cluster. This extra 84 * copy would sort of defeat the purpose of the bus master support for 85 * any packet that doesn't fit into a single mbuf. 86 * 87 * By contrast, the 3c90x cards support a fragment-based bus master 88 * mode where mbuf chains can be encapsulated using TX descriptors. 89 * This is similar to other PCI chips such as the Texas Instruments 90 * ThunderLAN and the Intel 82557/82558. 91 * 92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 93 * bus master chips because they maintain the old PIO interface for 94 * backwards compatibility, but starting with the 3c905B and the 95 * "cyclone" chips, the compatibility interface has been dropped. 96 * Since using bus master DMA is a big win, we use this driver to 97 * support the PCI "boomerang" chips even though they work with the 98 * "vortex" driver in order to obtain better performance. 99 * 100 * This driver is in the /sys/pci directory because it only supports 101 * PCI-based NICs. 102 */ 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/sockio.h> 107 #include <sys/endian.h> 108 #include <sys/mbuf.h> 109 #include <sys/kernel.h> 110 #include <sys/module.h> 111 #include <sys/socket.h> 112 113 #include <net/if.h> 114 #include <net/if_arp.h> 115 #include <net/ethernet.h> 116 #include <net/if_dl.h> 117 #include <net/if_media.h> 118 119 #include <net/bpf.h> 120 121 #include <machine/bus_memio.h> 122 #include <machine/bus_pio.h> 123 #include <machine/bus.h> 124 #include <machine/resource.h> 125 #include <sys/bus.h> 126 #include <sys/rman.h> 127 128 #include <dev/mii/mii.h> 129 #include <dev/mii/miivar.h> 130 131 #include <dev/pci/pcireg.h> 132 #include <dev/pci/pcivar.h> 133 134 MODULE_DEPEND(xl, pci, 1, 1, 1); 135 MODULE_DEPEND(xl, ether, 1, 1, 1); 136 MODULE_DEPEND(xl, miibus, 1, 1, 1); 137 138 /* "device miibus" required. See GENERIC if you get errors here. */ 139 #include "miibus_if.h" 140 141 #include <pci/if_xlreg.h> 142 143 /* 144 * TX Checksumming is disabled by default for two reasons: 145 * - TX Checksumming will occasionally produce corrupt packets 146 * - TX Checksumming seems to reduce performance 147 * 148 * Only 905B/C cards were reported to have this problem, it is possible 149 * that later chips _may_ be immune. 150 */ 151 #define XL905B_TXCSUM_BROKEN 1 152 153 #ifdef XL905B_TXCSUM_BROKEN 154 #define XL905B_CSUM_FEATURES 0 155 #else 156 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 157 #endif 158 159 /* 160 * Various supported device vendors/types and their names. 161 */ 162 static struct xl_type xl_devs[] = { 163 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 164 "3Com 3c900-TPO Etherlink XL" }, 165 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 166 "3Com 3c900-COMBO Etherlink XL" }, 167 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 168 "3Com 3c905-TX Fast Etherlink XL" }, 169 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 170 "3Com 3c905-T4 Fast Etherlink XL" }, 171 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 172 "3Com 3c900B-TPO Etherlink XL" }, 173 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 174 "3Com 3c900B-COMBO Etherlink XL" }, 175 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 176 "3Com 3c900B-TPC Etherlink XL" }, 177 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 178 "3Com 3c900B-FL Etherlink XL" }, 179 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 180 "3Com 3c905B-TX Fast Etherlink XL" }, 181 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 182 "3Com 3c905B-T4 Fast Etherlink XL" }, 183 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 184 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 185 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 186 "3Com 3c905B-COMBO Fast Etherlink XL" }, 187 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 188 "3Com 3c905C-TX Fast Etherlink XL" }, 189 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 190 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 191 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 192 "3Com 3c980 Fast Etherlink XL" }, 193 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 194 "3Com 3c980C Fast Etherlink XL" }, 195 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 196 "3Com 3cSOHO100-TX OfficeConnect" }, 197 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 198 "3Com 3c450-TX HomeConnect" }, 199 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 200 "3Com 3c555 Fast Etherlink XL" }, 201 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 202 "3Com 3c556 Fast Etherlink XL" }, 203 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 204 "3Com 3c556B Fast Etherlink XL" }, 205 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 206 "3Com 3c575TX Fast Etherlink XL" }, 207 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 208 "3Com 3c575B Fast Etherlink XL" }, 209 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 210 "3Com 3c575C Fast Etherlink XL" }, 211 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 212 "3Com 3c656 Fast Etherlink XL" }, 213 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 214 "3Com 3c656B Fast Etherlink XL" }, 215 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 216 "3Com 3c656C Fast Etherlink XL" }, 217 { 0, 0, NULL } 218 }; 219 220 static int xl_probe (device_t); 221 static int xl_attach (device_t); 222 static int xl_detach (device_t); 223 224 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *); 225 static void xl_stats_update (void *); 226 static void xl_stats_update_locked 227 (struct xl_softc *); 228 static int xl_encap (struct xl_softc *, struct xl_chain *, 229 struct mbuf *); 230 static void xl_rxeof (struct xl_softc *); 231 static int xl_rx_resync (struct xl_softc *); 232 static void xl_txeof (struct xl_softc *); 233 static void xl_txeof_90xB (struct xl_softc *); 234 static void xl_txeoc (struct xl_softc *); 235 static void xl_intr (void *); 236 static void xl_start (struct ifnet *); 237 static void xl_start_locked (struct ifnet *); 238 static void xl_start_90xB_locked 239 (struct ifnet *); 240 static int xl_ioctl (struct ifnet *, u_long, caddr_t); 241 static void xl_init (void *); 242 static void xl_init_locked (struct xl_softc *); 243 static void xl_stop (struct xl_softc *); 244 static void xl_watchdog (struct ifnet *); 245 static void xl_shutdown (device_t); 246 static int xl_suspend (device_t); 247 static int xl_resume (device_t); 248 249 static int xl_ifmedia_upd (struct ifnet *); 250 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 251 252 static int xl_eeprom_wait (struct xl_softc *); 253 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int); 254 static void xl_mii_sync (struct xl_softc *); 255 static void xl_mii_send (struct xl_softc *, u_int32_t, int); 256 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *); 257 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *); 258 259 static void xl_setcfg (struct xl_softc *); 260 static void xl_setmode (struct xl_softc *, int); 261 static void xl_setmulti (struct xl_softc *); 262 static void xl_setmulti_hash (struct xl_softc *); 263 static void xl_reset (struct xl_softc *); 264 static int xl_list_rx_init (struct xl_softc *); 265 static int xl_list_tx_init (struct xl_softc *); 266 static int xl_list_tx_init_90xB (struct xl_softc *); 267 static void xl_wait (struct xl_softc *); 268 static void xl_mediacheck (struct xl_softc *); 269 static void xl_choose_media (struct xl_softc *sc, int *media); 270 static void xl_choose_xcvr (struct xl_softc *, int); 271 static void xl_dma_map_addr (void *, bus_dma_segment_t *, int, int); 272 static void xl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t, 273 int); 274 static void xl_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t, 275 int); 276 #ifdef notdef 277 static void xl_testpacket (struct xl_softc *); 278 #endif 279 280 static int xl_miibus_readreg (device_t, int, int); 281 static int xl_miibus_writereg (device_t, int, int, int); 282 static void xl_miibus_statchg (device_t); 283 static void xl_miibus_mediainit (device_t); 284 285 static device_method_t xl_methods[] = { 286 /* Device interface */ 287 DEVMETHOD(device_probe, xl_probe), 288 DEVMETHOD(device_attach, xl_attach), 289 DEVMETHOD(device_detach, xl_detach), 290 DEVMETHOD(device_shutdown, xl_shutdown), 291 DEVMETHOD(device_suspend, xl_suspend), 292 DEVMETHOD(device_resume, xl_resume), 293 294 /* bus interface */ 295 DEVMETHOD(bus_print_child, bus_generic_print_child), 296 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 297 298 /* MII interface */ 299 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 300 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 301 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 302 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 303 304 { 0, 0 } 305 }; 306 307 static driver_t xl_driver = { 308 "xl", 309 xl_methods, 310 sizeof(struct xl_softc) 311 }; 312 313 static devclass_t xl_devclass; 314 315 DRIVER_MODULE(xl, cardbus, xl_driver, xl_devclass, 0, 0); 316 DRIVER_MODULE(xl, pci, xl_driver, xl_devclass, 0, 0); 317 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 318 319 static void 320 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 321 { 322 u_int32_t *paddr; 323 324 paddr = arg; 325 *paddr = segs->ds_addr; 326 } 327 328 static void 329 xl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, 330 bus_size_t mapsize, int error) 331 { 332 u_int32_t *paddr; 333 334 if (error) 335 return; 336 337 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments")); 338 paddr = arg; 339 *paddr = segs->ds_addr; 340 } 341 342 static void 343 xl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 344 bus_size_t mapsize, int error) 345 { 346 struct xl_list *l; 347 int i, total_len; 348 349 if (error) 350 return; 351 352 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments")); 353 354 total_len = 0; 355 l = arg; 356 for (i = 0; i < nseg; i++) { 357 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 358 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr); 359 l->xl_frag[i].xl_len = htole32(segs[i].ds_len); 360 total_len += segs[i].ds_len; 361 } 362 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len | 363 XL_LAST_FRAG); 364 l->xl_status = htole32(total_len); 365 l->xl_next = 0; 366 } 367 368 /* 369 * Murphy's law says that it's possible the chip can wedge and 370 * the 'command in progress' bit may never clear. Hence, we wait 371 * only a finite amount of time to avoid getting caught in an 372 * infinite loop. Normally this delay routine would be a macro, 373 * but it isn't called during normal operation so we can afford 374 * to make it a function. 375 */ 376 static void 377 xl_wait(struct xl_softc *sc) 378 { 379 register int i; 380 381 for (i = 0; i < XL_TIMEOUT; i++) { 382 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0) 383 break; 384 } 385 386 if (i == XL_TIMEOUT) 387 if_printf(&sc->arpcom.ac_if, "command never completed!\n"); 388 } 389 390 /* 391 * MII access routines are provided for adapters with external 392 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 393 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 394 * Note: if you don't perform the MDIO operations just right, 395 * it's possible to end up with code that works correctly with 396 * some chips/CPUs/processor speeds/bus speeds/etc but not 397 * with others. 398 */ 399 #define MII_SET(x) \ 400 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 401 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 402 403 #define MII_CLR(x) \ 404 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 405 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 406 407 /* 408 * Sync the PHYs by setting data bit and strobing the clock 32 times. 409 */ 410 static void 411 xl_mii_sync(struct xl_softc *sc) 412 { 413 register int i; 414 415 XL_SEL_WIN(4); 416 MII_SET(XL_MII_DIR|XL_MII_DATA); 417 418 for (i = 0; i < 32; i++) { 419 MII_SET(XL_MII_CLK); 420 MII_SET(XL_MII_DATA); 421 MII_SET(XL_MII_DATA); 422 MII_CLR(XL_MII_CLK); 423 MII_SET(XL_MII_DATA); 424 MII_SET(XL_MII_DATA); 425 } 426 } 427 428 /* 429 * Clock a series of bits through the MII. 430 */ 431 static void 432 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt) 433 { 434 int i; 435 436 XL_SEL_WIN(4); 437 MII_CLR(XL_MII_CLK); 438 439 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 440 if (bits & i) { 441 MII_SET(XL_MII_DATA); 442 } else { 443 MII_CLR(XL_MII_DATA); 444 } 445 MII_CLR(XL_MII_CLK); 446 MII_SET(XL_MII_CLK); 447 } 448 } 449 450 /* 451 * Read an PHY register through the MII. 452 */ 453 static int 454 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame) 455 { 456 int i, ack; 457 458 /*XL_LOCK_ASSERT(sc);*/ 459 460 /* Set up frame for RX. */ 461 frame->mii_stdelim = XL_MII_STARTDELIM; 462 frame->mii_opcode = XL_MII_READOP; 463 frame->mii_turnaround = 0; 464 frame->mii_data = 0; 465 466 /* Select register window 4. */ 467 XL_SEL_WIN(4); 468 469 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 470 /* Turn on data xmit. */ 471 MII_SET(XL_MII_DIR); 472 473 xl_mii_sync(sc); 474 475 /* Send command/address info. */ 476 xl_mii_send(sc, frame->mii_stdelim, 2); 477 xl_mii_send(sc, frame->mii_opcode, 2); 478 xl_mii_send(sc, frame->mii_phyaddr, 5); 479 xl_mii_send(sc, frame->mii_regaddr, 5); 480 481 /* Idle bit */ 482 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 483 MII_SET(XL_MII_CLK); 484 485 /* Turn off xmit. */ 486 MII_CLR(XL_MII_DIR); 487 488 /* Check for ack */ 489 MII_CLR(XL_MII_CLK); 490 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 491 MII_SET(XL_MII_CLK); 492 493 /* 494 * Now try reading data bits. If the ack failed, we still 495 * need to clock through 16 cycles to keep the PHY(s) in sync. 496 */ 497 if (ack) { 498 for (i = 0; i < 16; i++) { 499 MII_CLR(XL_MII_CLK); 500 MII_SET(XL_MII_CLK); 501 } 502 goto fail; 503 } 504 505 for (i = 0x8000; i; i >>= 1) { 506 MII_CLR(XL_MII_CLK); 507 if (!ack) { 508 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 509 frame->mii_data |= i; 510 } 511 MII_SET(XL_MII_CLK); 512 } 513 514 fail: 515 MII_CLR(XL_MII_CLK); 516 MII_SET(XL_MII_CLK); 517 518 return (ack ? 1 : 0); 519 } 520 521 /* 522 * Write to a PHY register through the MII. 523 */ 524 static int 525 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame) 526 { 527 528 /*XL_LOCK_ASSERT(sc);*/ 529 530 /* Set up frame for TX. */ 531 frame->mii_stdelim = XL_MII_STARTDELIM; 532 frame->mii_opcode = XL_MII_WRITEOP; 533 frame->mii_turnaround = XL_MII_TURNAROUND; 534 535 /* Select the window 4. */ 536 XL_SEL_WIN(4); 537 538 /* Turn on data output. */ 539 MII_SET(XL_MII_DIR); 540 541 xl_mii_sync(sc); 542 543 xl_mii_send(sc, frame->mii_stdelim, 2); 544 xl_mii_send(sc, frame->mii_opcode, 2); 545 xl_mii_send(sc, frame->mii_phyaddr, 5); 546 xl_mii_send(sc, frame->mii_regaddr, 5); 547 xl_mii_send(sc, frame->mii_turnaround, 2); 548 xl_mii_send(sc, frame->mii_data, 16); 549 550 /* Idle bit. */ 551 MII_SET(XL_MII_CLK); 552 MII_CLR(XL_MII_CLK); 553 554 /* Turn off xmit. */ 555 MII_CLR(XL_MII_DIR); 556 557 return (0); 558 } 559 560 static int 561 xl_miibus_readreg(device_t dev, int phy, int reg) 562 { 563 struct xl_softc *sc; 564 struct xl_mii_frame frame; 565 566 sc = device_get_softc(dev); 567 568 /* 569 * Pretend that PHYs are only available at MII address 24. 570 * This is to guard against problems with certain 3Com ASIC 571 * revisions that incorrectly map the internal transceiver 572 * control registers at all MII addresses. This can cause 573 * the miibus code to attach the same PHY several times over. 574 */ 575 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24) 576 return (0); 577 578 bzero((char *)&frame, sizeof(frame)); 579 frame.mii_phyaddr = phy; 580 frame.mii_regaddr = reg; 581 582 xl_mii_readreg(sc, &frame); 583 584 return (frame.mii_data); 585 } 586 587 static int 588 xl_miibus_writereg(device_t dev, int phy, int reg, int data) 589 { 590 struct xl_softc *sc; 591 struct xl_mii_frame frame; 592 593 sc = device_get_softc(dev); 594 595 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24) 596 return (0); 597 598 bzero((char *)&frame, sizeof(frame)); 599 frame.mii_phyaddr = phy; 600 frame.mii_regaddr = reg; 601 frame.mii_data = data; 602 603 xl_mii_writereg(sc, &frame); 604 605 return (0); 606 } 607 608 static void 609 xl_miibus_statchg(device_t dev) 610 { 611 struct xl_softc *sc; 612 struct mii_data *mii; 613 614 sc = device_get_softc(dev); 615 mii = device_get_softc(sc->xl_miibus); 616 617 /*XL_LOCK_ASSERT(sc);*/ 618 619 xl_setcfg(sc); 620 621 /* Set ASIC's duplex mode to match the PHY. */ 622 XL_SEL_WIN(3); 623 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 624 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 625 else 626 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 627 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 628 } 629 630 /* 631 * Special support for the 3c905B-COMBO. This card has 10/100 support 632 * plus BNC and AUI ports. This means we will have both an miibus attached 633 * plus some non-MII media settings. In order to allow this, we have to 634 * add the extra media to the miibus's ifmedia struct, but we can't do 635 * that during xl_attach() because the miibus hasn't been attached yet. 636 * So instead, we wait until the miibus probe/attach is done, at which 637 * point we will get a callback telling is that it's safe to add our 638 * extra media. 639 */ 640 static void 641 xl_miibus_mediainit(device_t dev) 642 { 643 struct xl_softc *sc; 644 struct mii_data *mii; 645 struct ifmedia *ifm; 646 647 sc = device_get_softc(dev); 648 mii = device_get_softc(sc->xl_miibus); 649 ifm = &mii->mii_media; 650 651 /*XL_LOCK_ASSERT(sc);*/ 652 653 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) { 654 /* 655 * Check for a 10baseFL board in disguise. 656 */ 657 if (sc->xl_type == XL_TYPE_905B && 658 sc->xl_media == XL_MEDIAOPT_10FL) { 659 if (bootverbose) 660 if_printf(&sc->arpcom.ac_if, 661 "found 10baseFL\n"); 662 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL); 663 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0, 664 NULL); 665 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 666 ifmedia_add(ifm, 667 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL); 668 } else { 669 if (bootverbose) 670 if_printf(&sc->arpcom.ac_if, "found AUI\n"); 671 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL); 672 } 673 } 674 675 if (sc->xl_media & XL_MEDIAOPT_BNC) { 676 if (bootverbose) 677 if_printf(&sc->arpcom.ac_if, "found BNC\n"); 678 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL); 679 } 680 } 681 682 /* 683 * The EEPROM is slow: give it time to come ready after issuing 684 * it a command. 685 */ 686 static int 687 xl_eeprom_wait(struct xl_softc *sc) 688 { 689 int i; 690 691 for (i = 0; i < 100; i++) { 692 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 693 DELAY(162); 694 else 695 break; 696 } 697 698 if (i == 100) { 699 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n"); 700 return (1); 701 } 702 703 return (0); 704 } 705 706 /* 707 * Read a sequence of words from the EEPROM. Note that ethernet address 708 * data is stored in the EEPROM in network byte order. 709 */ 710 static int 711 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 712 { 713 int err = 0, i; 714 u_int16_t word = 0, *ptr; 715 716 XL_LOCK_ASSERT(sc); 717 718 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 719 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 720 /* 721 * XXX: WARNING! DANGER! 722 * It's easy to accidentally overwrite the rom content! 723 * Note: the 3c575 uses 8bit EEPROM offsets. 724 */ 725 XL_SEL_WIN(0); 726 727 if (xl_eeprom_wait(sc)) 728 return (1); 729 730 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 731 off += 0x30; 732 733 for (i = 0; i < cnt; i++) { 734 if (sc->xl_flags & XL_FLAG_8BITROM) 735 CSR_WRITE_2(sc, XL_W0_EE_CMD, 736 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 737 else 738 CSR_WRITE_2(sc, XL_W0_EE_CMD, 739 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 740 err = xl_eeprom_wait(sc); 741 if (err) 742 break; 743 word = CSR_READ_2(sc, XL_W0_EE_DATA); 744 ptr = (u_int16_t *)(dest + (i * 2)); 745 if (swap) 746 *ptr = ntohs(word); 747 else 748 *ptr = word; 749 } 750 751 return (err ? 1 : 0); 752 } 753 754 /* 755 * NICs older than the 3c905B have only one multicast option, which 756 * is to enable reception of all multicast frames. 757 */ 758 static void 759 xl_setmulti(struct xl_softc *sc) 760 { 761 struct ifnet *ifp = &sc->arpcom.ac_if; 762 struct ifmultiaddr *ifma; 763 u_int8_t rxfilt; 764 int mcnt = 0; 765 766 XL_LOCK_ASSERT(sc); 767 768 XL_SEL_WIN(5); 769 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 770 771 if (ifp->if_flags & IFF_ALLMULTI) { 772 rxfilt |= XL_RXFILTER_ALLMULTI; 773 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 774 return; 775 } 776 777 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 778 mcnt++; 779 780 if (mcnt) 781 rxfilt |= XL_RXFILTER_ALLMULTI; 782 else 783 rxfilt &= ~XL_RXFILTER_ALLMULTI; 784 785 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 786 } 787 788 /* 789 * 3c905B adapters have a hash filter that we can program. 790 */ 791 static void 792 xl_setmulti_hash(struct xl_softc *sc) 793 { 794 struct ifnet *ifp = &sc->arpcom.ac_if; 795 int h = 0, i; 796 struct ifmultiaddr *ifma; 797 u_int8_t rxfilt; 798 int mcnt = 0; 799 800 XL_LOCK_ASSERT(sc); 801 802 XL_SEL_WIN(5); 803 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 804 805 if (ifp->if_flags & IFF_ALLMULTI) { 806 rxfilt |= XL_RXFILTER_ALLMULTI; 807 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 808 return; 809 } else 810 rxfilt &= ~XL_RXFILTER_ALLMULTI; 811 812 /* first, zot all the existing hash bits */ 813 for (i = 0; i < XL_HASHFILT_SIZE; i++) 814 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 815 816 /* now program new ones */ 817 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 818 if (ifma->ifma_addr->sa_family != AF_LINK) 819 continue; 820 /* 821 * Note: the 3c905B currently only supports a 64-bit hash 822 * table, which means we really only need 6 bits, but the 823 * manual indicates that future chip revisions will have a 824 * 256-bit hash table, hence the routine is set up to 825 * calculate 8 bits of position info in case we need it some 826 * day. 827 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have 828 * a 256 bit hash table. This means we have to use all 8 bits 829 * regardless. On older cards, the upper 2 bits will be 830 * ignored. Grrrr.... 831 */ 832 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 833 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 834 CSR_WRITE_2(sc, XL_COMMAND, 835 h | XL_CMD_RX_SET_HASH | XL_HASH_SET); 836 mcnt++; 837 } 838 839 if (mcnt) 840 rxfilt |= XL_RXFILTER_MULTIHASH; 841 else 842 rxfilt &= ~XL_RXFILTER_MULTIHASH; 843 844 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 845 } 846 847 #ifdef notdef 848 static void 849 xl_testpacket(struct xl_softc *sc) 850 { 851 struct mbuf *m; 852 struct ifnet *ifp = &sc->arpcom.ac_if; 853 854 MGETHDR(m, M_DONTWAIT, MT_DATA); 855 856 if (m == NULL) 857 return; 858 859 bcopy(&sc->arpcom.ac_enaddr, 860 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 861 bcopy(&sc->arpcom.ac_enaddr, 862 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 863 mtod(m, struct ether_header *)->ether_type = htons(3); 864 mtod(m, unsigned char *)[14] = 0; 865 mtod(m, unsigned char *)[15] = 0; 866 mtod(m, unsigned char *)[16] = 0xE3; 867 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 868 IFQ_ENQUEUE(&ifp->if_snd, m); 869 xl_start(ifp); 870 } 871 #endif 872 873 static void 874 xl_setcfg(struct xl_softc *sc) 875 { 876 u_int32_t icfg; 877 878 /*XL_LOCK_ASSERT(sc);*/ 879 880 XL_SEL_WIN(3); 881 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 882 icfg &= ~XL_ICFG_CONNECTOR_MASK; 883 if (sc->xl_media & XL_MEDIAOPT_MII || 884 sc->xl_media & XL_MEDIAOPT_BT4) 885 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 886 if (sc->xl_media & XL_MEDIAOPT_BTX) 887 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 888 889 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 890 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 891 } 892 893 static void 894 xl_setmode(struct xl_softc *sc, int media) 895 { 896 u_int32_t icfg; 897 u_int16_t mediastat; 898 char *pmsg = "", *dmsg = ""; 899 900 /*XL_LOCK_ASSERT(sc);*/ 901 902 XL_SEL_WIN(4); 903 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 904 XL_SEL_WIN(3); 905 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 906 907 if (sc->xl_media & XL_MEDIAOPT_BT) { 908 if (IFM_SUBTYPE(media) == IFM_10_T) { 909 pmsg = "10baseT transceiver"; 910 sc->xl_xcvr = XL_XCVR_10BT; 911 icfg &= ~XL_ICFG_CONNECTOR_MASK; 912 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 913 mediastat |= XL_MEDIASTAT_LINKBEAT | 914 XL_MEDIASTAT_JABGUARD; 915 mediastat &= ~XL_MEDIASTAT_SQEENB; 916 } 917 } 918 919 if (sc->xl_media & XL_MEDIAOPT_BFX) { 920 if (IFM_SUBTYPE(media) == IFM_100_FX) { 921 pmsg = "100baseFX port"; 922 sc->xl_xcvr = XL_XCVR_100BFX; 923 icfg &= ~XL_ICFG_CONNECTOR_MASK; 924 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 925 mediastat |= XL_MEDIASTAT_LINKBEAT; 926 mediastat &= ~XL_MEDIASTAT_SQEENB; 927 } 928 } 929 930 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 931 if (IFM_SUBTYPE(media) == IFM_10_5) { 932 pmsg = "AUI port"; 933 sc->xl_xcvr = XL_XCVR_AUI; 934 icfg &= ~XL_ICFG_CONNECTOR_MASK; 935 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 936 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 937 XL_MEDIASTAT_JABGUARD); 938 mediastat |= ~XL_MEDIASTAT_SQEENB; 939 } 940 if (IFM_SUBTYPE(media) == IFM_10_FL) { 941 pmsg = "10baseFL transceiver"; 942 sc->xl_xcvr = XL_XCVR_AUI; 943 icfg &= ~XL_ICFG_CONNECTOR_MASK; 944 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 945 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 946 XL_MEDIASTAT_JABGUARD); 947 mediastat |= ~XL_MEDIASTAT_SQEENB; 948 } 949 } 950 951 if (sc->xl_media & XL_MEDIAOPT_BNC) { 952 if (IFM_SUBTYPE(media) == IFM_10_2) { 953 pmsg = "AUI port"; 954 sc->xl_xcvr = XL_XCVR_COAX; 955 icfg &= ~XL_ICFG_CONNECTOR_MASK; 956 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 957 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 958 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB); 959 } 960 } 961 962 if ((media & IFM_GMASK) == IFM_FDX || 963 IFM_SUBTYPE(media) == IFM_100_FX) { 964 dmsg = "full"; 965 XL_SEL_WIN(3); 966 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 967 } else { 968 dmsg = "half"; 969 XL_SEL_WIN(3); 970 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 971 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 972 } 973 974 if (IFM_SUBTYPE(media) == IFM_10_2) 975 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 976 else 977 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 978 979 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 980 XL_SEL_WIN(4); 981 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 982 983 DELAY(800); 984 XL_SEL_WIN(7); 985 986 if_printf(&sc->arpcom.ac_if, "selecting %s, %s duplex\n", pmsg, dmsg); 987 } 988 989 static void 990 xl_reset(struct xl_softc *sc) 991 { 992 register int i; 993 994 XL_LOCK_ASSERT(sc); 995 996 XL_SEL_WIN(0); 997 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 998 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 999 XL_RESETOPT_DISADVFD:0)); 1000 1001 /* 1002 * If we're using memory mapped register mode, pause briefly 1003 * after issuing the reset command before trying to access any 1004 * other registers. With my 3c575C cardbus card, failing to do 1005 * this results in the system locking up while trying to poll 1006 * the command busy bit in the status register. 1007 */ 1008 if (sc->xl_flags & XL_FLAG_USE_MMIO) 1009 DELAY(100000); 1010 1011 for (i = 0; i < XL_TIMEOUT; i++) { 1012 DELAY(10); 1013 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 1014 break; 1015 } 1016 1017 if (i == XL_TIMEOUT) 1018 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n"); 1019 1020 /* Reset TX and RX. */ 1021 /* Note: the RX reset takes an absurd amount of time 1022 * on newer versions of the Tornado chips such as those 1023 * on the 3c905CX and newer 3c908C cards. We wait an 1024 * extra amount of time so that xl_wait() doesn't complain 1025 * and annoy the users. 1026 */ 1027 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 1028 DELAY(100000); 1029 xl_wait(sc); 1030 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 1031 xl_wait(sc); 1032 1033 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 1034 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 1035 XL_SEL_WIN(2); 1036 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, 1037 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) | 1038 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ? 1039 XL_RESETOPT_INVERT_LED : 0) | 1040 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ? 1041 XL_RESETOPT_INVERT_MII : 0)); 1042 } 1043 1044 /* Wait a little while for the chip to get its brains in order. */ 1045 DELAY(100000); 1046 } 1047 1048 /* 1049 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1050 * IDs against our list and return a device name if we find a match. 1051 */ 1052 static int 1053 xl_probe(device_t dev) 1054 { 1055 struct xl_type *t; 1056 1057 t = xl_devs; 1058 1059 while (t->xl_name != NULL) { 1060 if ((pci_get_vendor(dev) == t->xl_vid) && 1061 (pci_get_device(dev) == t->xl_did)) { 1062 device_set_desc(dev, t->xl_name); 1063 return (0); 1064 } 1065 t++; 1066 } 1067 1068 return (ENXIO); 1069 } 1070 1071 /* 1072 * This routine is a kludge to work around possible hardware faults 1073 * or manufacturing defects that can cause the media options register 1074 * (or reset options register, as it's called for the first generation 1075 * 3c90x adapters) to return an incorrect result. I have encountered 1076 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1077 * which doesn't have any of the 'mediaopt' bits set. This screws up 1078 * the attach routine pretty badly because it doesn't know what media 1079 * to look for. If we find ourselves in this predicament, this routine 1080 * will try to guess the media options values and warn the user of a 1081 * possible manufacturing defect with his adapter/system/whatever. 1082 */ 1083 static void 1084 xl_mediacheck(struct xl_softc *sc) 1085 { 1086 1087 XL_LOCK_ASSERT(sc); 1088 1089 /* 1090 * If some of the media options bits are set, assume they are 1091 * correct. If not, try to figure it out down below. 1092 * XXX I should check for 10baseFL, but I don't have an adapter 1093 * to test with. 1094 */ 1095 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1096 /* 1097 * Check the XCVR value. If it's not in the normal range 1098 * of values, we need to fake it up here. 1099 */ 1100 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1101 return; 1102 else { 1103 if_printf(&sc->arpcom.ac_if, 1104 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr); 1105 if_printf(&sc->arpcom.ac_if, 1106 "choosing new default based on card type\n"); 1107 } 1108 } else { 1109 if (sc->xl_type == XL_TYPE_905B && 1110 sc->xl_media & XL_MEDIAOPT_10FL) 1111 return; 1112 if_printf(&sc->arpcom.ac_if, 1113 "WARNING: no media options bits set in the media options register!!\n"); 1114 if_printf(&sc->arpcom.ac_if, 1115 "this could be a manufacturing defect in your adapter or system\n"); 1116 if_printf(&sc->arpcom.ac_if, 1117 "attempting to guess media type; you should probably consult your vendor\n"); 1118 } 1119 1120 xl_choose_xcvr(sc, 1); 1121 } 1122 1123 static void 1124 xl_choose_xcvr(struct xl_softc *sc, int verbose) 1125 { 1126 u_int16_t devid; 1127 1128 /* 1129 * Read the device ID from the EEPROM. 1130 * This is what's loaded into the PCI device ID register, so it has 1131 * to be correct otherwise we wouldn't have gotten this far. 1132 */ 1133 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1134 1135 switch (devid) { 1136 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1137 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1138 sc->xl_media = XL_MEDIAOPT_BT; 1139 sc->xl_xcvr = XL_XCVR_10BT; 1140 if (verbose) 1141 if_printf(&sc->arpcom.ac_if, 1142 "guessing 10BaseT transceiver\n"); 1143 break; 1144 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1145 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1146 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1147 sc->xl_xcvr = XL_XCVR_10BT; 1148 if (verbose) 1149 if_printf(&sc->arpcom.ac_if, 1150 "guessing COMBO (AUI/BNC/TP)\n"); 1151 break; 1152 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1153 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1154 sc->xl_xcvr = XL_XCVR_10BT; 1155 if (verbose) 1156 if_printf(&sc->arpcom.ac_if, "guessing TPC (BNC/TP)\n"); 1157 break; 1158 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1159 sc->xl_media = XL_MEDIAOPT_10FL; 1160 sc->xl_xcvr = XL_XCVR_AUI; 1161 if (verbose) 1162 if_printf(&sc->arpcom.ac_if, "guessing 10baseFL\n"); 1163 break; 1164 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1165 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1166 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1167 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1168 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1169 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1170 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1171 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1172 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1173 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1174 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1175 sc->xl_media = XL_MEDIAOPT_MII; 1176 sc->xl_xcvr = XL_XCVR_MII; 1177 if (verbose) 1178 if_printf(&sc->arpcom.ac_if, "guessing MII\n"); 1179 break; 1180 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1181 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1182 sc->xl_media = XL_MEDIAOPT_BT4; 1183 sc->xl_xcvr = XL_XCVR_MII; 1184 if (verbose) 1185 if_printf(&sc->arpcom.ac_if, 1186 "guessing 100baseT4/MII\n"); 1187 break; 1188 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1189 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1190 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1191 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1192 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1193 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1194 sc->xl_media = XL_MEDIAOPT_BTX; 1195 sc->xl_xcvr = XL_XCVR_AUTO; 1196 if (verbose) 1197 if_printf(&sc->arpcom.ac_if, 1198 "guessing 10/100 internal\n"); 1199 break; 1200 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1201 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1202 sc->xl_xcvr = XL_XCVR_AUTO; 1203 if (verbose) 1204 if_printf(&sc->arpcom.ac_if, 1205 "guessing 10/100 plus BNC/AUI\n"); 1206 break; 1207 default: 1208 if_printf(&sc->arpcom.ac_if, 1209 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1210 sc->xl_media = XL_MEDIAOPT_BT; 1211 break; 1212 } 1213 } 1214 1215 /* 1216 * Attach the interface. Allocate softc structures, do ifmedia 1217 * setup and ethernet/BPF attach. 1218 */ 1219 static int 1220 xl_attach(device_t dev) 1221 { 1222 u_char eaddr[ETHER_ADDR_LEN]; 1223 u_int16_t xcvr[2]; 1224 struct xl_softc *sc; 1225 struct ifnet *ifp; 1226 int media; 1227 int unit, error = 0, rid, res; 1228 uint16_t did; 1229 1230 sc = device_get_softc(dev); 1231 unit = device_get_unit(dev); 1232 1233 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1234 MTX_DEF); 1235 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1236 1237 did = pci_get_device(dev); 1238 1239 sc->xl_flags = 0; 1240 if (did == TC_DEVICEID_HURRICANE_555) 1241 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1242 if (did == TC_DEVICEID_HURRICANE_556 || 1243 did == TC_DEVICEID_HURRICANE_556B) 1244 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1245 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1246 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1247 if (did == TC_DEVICEID_HURRICANE_555 || 1248 did == TC_DEVICEID_HURRICANE_556) 1249 sc->xl_flags |= XL_FLAG_8BITROM; 1250 if (did == TC_DEVICEID_HURRICANE_556B) 1251 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1252 1253 if (did == TC_DEVICEID_HURRICANE_575A || 1254 did == TC_DEVICEID_HURRICANE_575B || 1255 did == TC_DEVICEID_HURRICANE_575C || 1256 did == TC_DEVICEID_HURRICANE_656B || 1257 did == TC_DEVICEID_TORNADO_656C) 1258 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1259 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM; 1260 if (did == TC_DEVICEID_HURRICANE_656) 1261 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1262 if (did == TC_DEVICEID_HURRICANE_575B) 1263 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1264 if (did == TC_DEVICEID_HURRICANE_575C) 1265 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1266 if (did == TC_DEVICEID_TORNADO_656C) 1267 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1268 if (did == TC_DEVICEID_HURRICANE_656 || 1269 did == TC_DEVICEID_HURRICANE_656B) 1270 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1271 XL_FLAG_INVERT_LED_PWR; 1272 if (did == TC_DEVICEID_TORNADO_10_100BT_920B) 1273 sc->xl_flags |= XL_FLAG_PHYOK; 1274 1275 switch (did) { 1276 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1277 case TC_DEVICEID_HURRICANE_575A: 1278 case TC_DEVICEID_HURRICANE_575B: 1279 case TC_DEVICEID_HURRICANE_575C: 1280 sc->xl_flags |= XL_FLAG_NO_MMIO; 1281 break; 1282 default: 1283 break; 1284 } 1285 1286 /* 1287 * Map control/status registers. 1288 */ 1289 pci_enable_busmaster(dev); 1290 1291 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) { 1292 rid = XL_PCI_LOMEM; 1293 res = SYS_RES_MEMORY; 1294 1295 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1296 } 1297 1298 if (sc->xl_res != NULL) { 1299 sc->xl_flags |= XL_FLAG_USE_MMIO; 1300 if (bootverbose) 1301 device_printf(dev, "using memory mapped I/O\n"); 1302 } else { 1303 rid = XL_PCI_LOIO; 1304 res = SYS_RES_IOPORT; 1305 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1306 if (sc->xl_res == NULL) { 1307 device_printf(dev, "couldn't map ports/memory\n"); 1308 error = ENXIO; 1309 goto fail; 1310 } 1311 if (bootverbose) 1312 device_printf(dev, "using port I/O\n"); 1313 } 1314 1315 sc->xl_btag = rman_get_bustag(sc->xl_res); 1316 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1317 1318 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1319 rid = XL_PCI_FUNCMEM; 1320 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1321 RF_ACTIVE); 1322 1323 if (sc->xl_fres == NULL) { 1324 device_printf(dev, "couldn't map ports/memory\n"); 1325 error = ENXIO; 1326 goto fail; 1327 } 1328 1329 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1330 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1331 } 1332 1333 /* Allocate interrupt */ 1334 rid = 0; 1335 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1336 RF_SHAREABLE | RF_ACTIVE); 1337 if (sc->xl_irq == NULL) { 1338 device_printf(dev, "couldn't map interrupt\n"); 1339 error = ENXIO; 1340 goto fail; 1341 } 1342 1343 /* Initialize interface name. */ 1344 ifp = &sc->arpcom.ac_if; 1345 ifp->if_softc = sc; 1346 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1347 1348 XL_LOCK(sc); 1349 1350 /* Reset the adapter. */ 1351 xl_reset(sc); 1352 1353 /* 1354 * Get station address from the EEPROM. 1355 */ 1356 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1357 device_printf(dev, "failed to read station address\n"); 1358 error = ENXIO; 1359 XL_UNLOCK(sc); 1360 goto fail; 1361 } 1362 1363 XL_UNLOCK(sc); 1364 1365 sc->xl_unit = unit; 1366 callout_handle_init(&sc->xl_stat_ch); 1367 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1368 1369 /* 1370 * Now allocate a tag for the DMA descriptor lists and a chunk 1371 * of DMA-able memory based on the tag. Also obtain the DMA 1372 * addresses of the RX and TX ring, which we'll need later. 1373 * All of our lists are allocated as a contiguous block 1374 * of memory. 1375 */ 1376 error = bus_dma_tag_create(NULL, 8, 0, 1377 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1378 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL, 1379 &sc->xl_ldata.xl_rx_tag); 1380 if (error) { 1381 device_printf(dev, "failed to allocate rx dma tag\n"); 1382 goto fail; 1383 } 1384 1385 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1386 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1387 &sc->xl_ldata.xl_rx_dmamap); 1388 if (error) { 1389 device_printf(dev, "no memory for rx list buffers!\n"); 1390 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1391 sc->xl_ldata.xl_rx_tag = NULL; 1392 goto fail; 1393 } 1394 1395 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1396 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1397 XL_RX_LIST_SZ, xl_dma_map_addr, 1398 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1399 if (error) { 1400 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1401 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1402 sc->xl_ldata.xl_rx_dmamap); 1403 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1404 sc->xl_ldata.xl_rx_tag = NULL; 1405 goto fail; 1406 } 1407 1408 error = bus_dma_tag_create(NULL, 8, 0, 1409 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1410 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL, 1411 &sc->xl_ldata.xl_tx_tag); 1412 if (error) { 1413 device_printf(dev, "failed to allocate tx dma tag\n"); 1414 goto fail; 1415 } 1416 1417 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1418 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1419 &sc->xl_ldata.xl_tx_dmamap); 1420 if (error) { 1421 device_printf(dev, "no memory for list buffers!\n"); 1422 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1423 sc->xl_ldata.xl_tx_tag = NULL; 1424 goto fail; 1425 } 1426 1427 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1428 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1429 XL_TX_LIST_SZ, xl_dma_map_addr, 1430 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1431 if (error) { 1432 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1433 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1434 sc->xl_ldata.xl_tx_dmamap); 1435 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1436 sc->xl_ldata.xl_tx_tag = NULL; 1437 goto fail; 1438 } 1439 1440 /* 1441 * Allocate a DMA tag for the mapping of mbufs. 1442 */ 1443 error = bus_dma_tag_create(NULL, 1, 0, 1444 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1445 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL, 1446 NULL, &sc->xl_mtag); 1447 if (error) { 1448 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1449 goto fail; 1450 } 1451 1452 /* We need a spare DMA map for the RX ring. */ 1453 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1454 if (error) 1455 goto fail; 1456 1457 XL_LOCK(sc); 1458 1459 /* 1460 * Figure out the card type. 3c905B adapters have the 1461 * 'supportsNoTxLength' bit set in the capabilities 1462 * word in the EEPROM. 1463 * Note: my 3c575C cardbus card lies. It returns a value 1464 * of 0x1578 for its capabilities word, which is somewhat 1465 * nonsensical. Another way to distinguish a 3c90x chip 1466 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1467 * bit. This will only be set for 3c90x boomerage chips. 1468 */ 1469 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1470 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1471 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1472 sc->xl_type = XL_TYPE_905B; 1473 else 1474 sc->xl_type = XL_TYPE_90X; 1475 1476 ifp->if_mtu = ETHERMTU; 1477 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1478 ifp->if_ioctl = xl_ioctl; 1479 ifp->if_capabilities = IFCAP_VLAN_MTU; 1480 if (sc->xl_type == XL_TYPE_905B) { 1481 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1482 #ifdef XL905B_TXCSUM_BROKEN 1483 ifp->if_capabilities |= IFCAP_RXCSUM; 1484 #else 1485 ifp->if_capabilities |= IFCAP_HWCSUM; 1486 #endif 1487 } 1488 ifp->if_start = xl_start; 1489 ifp->if_watchdog = xl_watchdog; 1490 ifp->if_init = xl_init; 1491 ifp->if_baudrate = 10000000; 1492 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1493 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1; 1494 IFQ_SET_READY(&ifp->if_snd); 1495 ifp->if_capenable = ifp->if_capabilities; 1496 1497 /* 1498 * Now we have to see what sort of media we have. 1499 * This includes probing for an MII interace and a 1500 * possible PHY. 1501 */ 1502 XL_SEL_WIN(3); 1503 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1504 if (bootverbose) 1505 device_printf(dev, "media options word: %x\n", sc->xl_media); 1506 1507 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1508 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1509 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1510 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1511 1512 xl_mediacheck(sc); 1513 1514 /* XXX Downcalls to ifmedia, miibus about to happen. */ 1515 XL_UNLOCK(sc); 1516 1517 if (sc->xl_media & XL_MEDIAOPT_MII || 1518 sc->xl_media & XL_MEDIAOPT_BTX || 1519 sc->xl_media & XL_MEDIAOPT_BT4) { 1520 if (bootverbose) 1521 device_printf(dev, "found MII/AUTO\n"); 1522 xl_setcfg(sc); 1523 if (mii_phy_probe(dev, &sc->xl_miibus, 1524 xl_ifmedia_upd, xl_ifmedia_sts)) { 1525 device_printf(dev, "no PHY found!\n"); 1526 error = ENXIO; 1527 goto fail; 1528 } 1529 goto done; 1530 } 1531 1532 /* 1533 * Sanity check. If the user has selected "auto" and this isn't 1534 * a 10/100 card of some kind, we need to force the transceiver 1535 * type to something sane. 1536 */ 1537 if (sc->xl_xcvr == XL_XCVR_AUTO) { 1538 /* XXX Direct hardware access needs lock coverage. */ 1539 XL_LOCK(sc); 1540 xl_choose_xcvr(sc, bootverbose); 1541 XL_UNLOCK(sc); 1542 } 1543 1544 /* 1545 * Do ifmedia setup. 1546 */ 1547 if (sc->xl_media & XL_MEDIAOPT_BT) { 1548 if (bootverbose) 1549 device_printf(dev, "found 10baseT\n"); 1550 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1551 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1552 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1553 ifmedia_add(&sc->ifmedia, 1554 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1555 } 1556 1557 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1558 /* 1559 * Check for a 10baseFL board in disguise. 1560 */ 1561 if (sc->xl_type == XL_TYPE_905B && 1562 sc->xl_media == XL_MEDIAOPT_10FL) { 1563 if (bootverbose) 1564 device_printf(dev, "found 10baseFL\n"); 1565 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1566 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1567 0, NULL); 1568 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1569 ifmedia_add(&sc->ifmedia, 1570 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1571 } else { 1572 if (bootverbose) 1573 device_printf(dev, "found AUI\n"); 1574 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1575 } 1576 } 1577 1578 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1579 if (bootverbose) 1580 device_printf(dev, "found BNC\n"); 1581 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1582 } 1583 1584 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1585 if (bootverbose) 1586 device_printf(dev, "found 100baseFX\n"); 1587 ifp->if_baudrate = 100000000; 1588 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1589 } 1590 1591 /* XXX: Unlocked, leaf will take lock. */ 1592 media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1593 xl_choose_media(sc, &media); 1594 1595 if (sc->xl_miibus == NULL) 1596 ifmedia_set(&sc->ifmedia, media); 1597 1598 done: 1599 /* XXX: Unlocked hardware access, narrow race. */ 1600 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1601 XL_SEL_WIN(0); 1602 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1603 } 1604 1605 /* 1606 * Call MI attach routine. 1607 */ 1608 ether_ifattach(ifp, eaddr); 1609 1610 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1611 xl_intr, sc, &sc->xl_intrhand); 1612 if (error) { 1613 device_printf(dev, "couldn't set up irq\n"); 1614 ether_ifdetach(ifp); 1615 goto fail; 1616 } 1617 1618 fail: 1619 if (error) 1620 xl_detach(dev); 1621 1622 return (error); 1623 } 1624 1625 /* 1626 * Choose a default media. 1627 * XXX This is a leaf function only called by xl_attach() and 1628 * acquires/releases the non-recursible driver mutex. 1629 */ 1630 static void 1631 xl_choose_media(struct xl_softc *sc, int *media) 1632 { 1633 1634 XL_LOCK(sc); 1635 1636 switch (sc->xl_xcvr) { 1637 case XL_XCVR_10BT: 1638 *media = IFM_ETHER|IFM_10_T; 1639 xl_setmode(sc, *media); 1640 break; 1641 case XL_XCVR_AUI: 1642 if (sc->xl_type == XL_TYPE_905B && 1643 sc->xl_media == XL_MEDIAOPT_10FL) { 1644 *media = IFM_ETHER|IFM_10_FL; 1645 xl_setmode(sc, *media); 1646 } else { 1647 *media = IFM_ETHER|IFM_10_5; 1648 xl_setmode(sc, *media); 1649 } 1650 break; 1651 case XL_XCVR_COAX: 1652 *media = IFM_ETHER|IFM_10_2; 1653 xl_setmode(sc, *media); 1654 break; 1655 case XL_XCVR_AUTO: 1656 case XL_XCVR_100BTX: 1657 case XL_XCVR_MII: 1658 /* Chosen by miibus */ 1659 break; 1660 case XL_XCVR_100BFX: 1661 *media = IFM_ETHER|IFM_100_FX; 1662 break; 1663 default: 1664 if_printf(&sc->arpcom.ac_if, "unknown XCVR type: %d\n", 1665 sc->xl_xcvr); 1666 /* 1667 * This will probably be wrong, but it prevents 1668 * the ifmedia code from panicking. 1669 */ 1670 *media = IFM_ETHER|IFM_10_T; 1671 break; 1672 } 1673 1674 XL_UNLOCK(sc); 1675 } 1676 1677 /* 1678 * Shutdown hardware and free up resources. This can be called any 1679 * time after the mutex has been initialized. It is called in both 1680 * the error case in attach and the normal detach case so it needs 1681 * to be careful about only freeing resources that have actually been 1682 * allocated. 1683 */ 1684 static int 1685 xl_detach(device_t dev) 1686 { 1687 struct xl_softc *sc; 1688 struct ifnet *ifp; 1689 int rid, res; 1690 1691 sc = device_get_softc(dev); 1692 ifp = &sc->arpcom.ac_if; 1693 1694 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized")); 1695 XL_LOCK(sc); 1696 1697 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1698 rid = XL_PCI_LOMEM; 1699 res = SYS_RES_MEMORY; 1700 } else { 1701 rid = XL_PCI_LOIO; 1702 res = SYS_RES_IOPORT; 1703 } 1704 1705 /* These should only be active if attach succeeded */ 1706 if (device_is_attached(dev)) { 1707 xl_reset(sc); 1708 xl_stop(sc); 1709 ether_ifdetach(ifp); 1710 } 1711 if (sc->xl_miibus) 1712 device_delete_child(dev, sc->xl_miibus); 1713 bus_generic_detach(dev); 1714 ifmedia_removeall(&sc->ifmedia); 1715 1716 if (sc->xl_intrhand) 1717 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1718 if (sc->xl_irq) 1719 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1720 if (sc->xl_fres != NULL) 1721 bus_release_resource(dev, SYS_RES_MEMORY, 1722 XL_PCI_FUNCMEM, sc->xl_fres); 1723 if (sc->xl_res) 1724 bus_release_resource(dev, res, rid, sc->xl_res); 1725 1726 if (sc->xl_mtag) { 1727 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1728 bus_dma_tag_destroy(sc->xl_mtag); 1729 } 1730 if (sc->xl_ldata.xl_rx_tag) { 1731 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1732 sc->xl_ldata.xl_rx_dmamap); 1733 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1734 sc->xl_ldata.xl_rx_dmamap); 1735 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1736 } 1737 if (sc->xl_ldata.xl_tx_tag) { 1738 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1739 sc->xl_ldata.xl_tx_dmamap); 1740 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1741 sc->xl_ldata.xl_tx_dmamap); 1742 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1743 } 1744 1745 XL_UNLOCK(sc); 1746 mtx_destroy(&sc->xl_mtx); 1747 1748 return (0); 1749 } 1750 1751 /* 1752 * Initialize the transmit descriptors. 1753 */ 1754 static int 1755 xl_list_tx_init(struct xl_softc *sc) 1756 { 1757 struct xl_chain_data *cd; 1758 struct xl_list_data *ld; 1759 int error, i; 1760 1761 XL_LOCK_ASSERT(sc); 1762 1763 cd = &sc->xl_cdata; 1764 ld = &sc->xl_ldata; 1765 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1766 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1767 error = bus_dmamap_create(sc->xl_mtag, 0, 1768 &cd->xl_tx_chain[i].xl_map); 1769 if (error) 1770 return (error); 1771 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1772 i * sizeof(struct xl_list); 1773 if (i == (XL_TX_LIST_CNT - 1)) 1774 cd->xl_tx_chain[i].xl_next = NULL; 1775 else 1776 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1777 } 1778 1779 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1780 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1781 1782 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1783 return (0); 1784 } 1785 1786 /* 1787 * Initialize the transmit descriptors. 1788 */ 1789 static int 1790 xl_list_tx_init_90xB(struct xl_softc *sc) 1791 { 1792 struct xl_chain_data *cd; 1793 struct xl_list_data *ld; 1794 int error, i; 1795 1796 XL_LOCK_ASSERT(sc); 1797 1798 cd = &sc->xl_cdata; 1799 ld = &sc->xl_ldata; 1800 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1801 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1802 error = bus_dmamap_create(sc->xl_mtag, 0, 1803 &cd->xl_tx_chain[i].xl_map); 1804 if (error) 1805 return (error); 1806 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1807 i * sizeof(struct xl_list); 1808 if (i == (XL_TX_LIST_CNT - 1)) 1809 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1810 else 1811 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1812 if (i == 0) 1813 cd->xl_tx_chain[i].xl_prev = 1814 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1815 else 1816 cd->xl_tx_chain[i].xl_prev = 1817 &cd->xl_tx_chain[i - 1]; 1818 } 1819 1820 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1821 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1822 1823 cd->xl_tx_prod = 1; 1824 cd->xl_tx_cons = 1; 1825 cd->xl_tx_cnt = 0; 1826 1827 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1828 return (0); 1829 } 1830 1831 /* 1832 * Initialize the RX descriptors and allocate mbufs for them. Note that 1833 * we arrange the descriptors in a closed ring, so that the last descriptor 1834 * points back to the first. 1835 */ 1836 static int 1837 xl_list_rx_init(struct xl_softc *sc) 1838 { 1839 struct xl_chain_data *cd; 1840 struct xl_list_data *ld; 1841 int error, i, next; 1842 u_int32_t nextptr; 1843 1844 XL_LOCK_ASSERT(sc); 1845 1846 cd = &sc->xl_cdata; 1847 ld = &sc->xl_ldata; 1848 1849 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1850 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1851 error = bus_dmamap_create(sc->xl_mtag, 0, 1852 &cd->xl_rx_chain[i].xl_map); 1853 if (error) 1854 return (error); 1855 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1856 if (error) 1857 return (error); 1858 if (i == (XL_RX_LIST_CNT - 1)) 1859 next = 0; 1860 else 1861 next = i + 1; 1862 nextptr = ld->xl_rx_dmaaddr + 1863 next * sizeof(struct xl_list_onefrag); 1864 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1865 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1866 } 1867 1868 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1869 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1870 1871 return (0); 1872 } 1873 1874 /* 1875 * Initialize an RX descriptor and attach an MBUF cluster. 1876 * If we fail to do so, we need to leave the old mbuf and 1877 * the old DMA map untouched so that it can be reused. 1878 */ 1879 static int 1880 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) 1881 { 1882 struct mbuf *m_new = NULL; 1883 bus_dmamap_t map; 1884 int error; 1885 u_int32_t baddr; 1886 1887 XL_LOCK_ASSERT(sc); 1888 1889 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1890 if (m_new == NULL) 1891 return (ENOBUFS); 1892 1893 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1894 1895 /* Force longword alignment for packet payload. */ 1896 m_adj(m_new, ETHER_ALIGN); 1897 1898 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new, 1899 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT); 1900 if (error) { 1901 m_freem(m_new); 1902 if_printf(&sc->arpcom.ac_if, "can't map mbuf (error %d)\n", 1903 error); 1904 return (error); 1905 } 1906 1907 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1908 map = c->xl_map; 1909 c->xl_map = sc->xl_tmpmap; 1910 sc->xl_tmpmap = map; 1911 c->xl_mbuf = m_new; 1912 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 1913 c->xl_ptr->xl_status = 0; 1914 c->xl_ptr->xl_frag.xl_addr = htole32(baddr); 1915 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 1916 return (0); 1917 } 1918 1919 static int 1920 xl_rx_resync(struct xl_softc *sc) 1921 { 1922 struct xl_chain_onefrag *pos; 1923 int i; 1924 1925 XL_LOCK_ASSERT(sc); 1926 1927 pos = sc->xl_cdata.xl_rx_head; 1928 1929 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1930 if (pos->xl_ptr->xl_status) 1931 break; 1932 pos = pos->xl_next; 1933 } 1934 1935 if (i == XL_RX_LIST_CNT) 1936 return (0); 1937 1938 sc->xl_cdata.xl_rx_head = pos; 1939 1940 return (EAGAIN); 1941 } 1942 1943 /* 1944 * A frame has been uploaded: pass the resulting mbuf chain up to 1945 * the higher level protocols. 1946 */ 1947 static void 1948 xl_rxeof(struct xl_softc *sc) 1949 { 1950 struct mbuf *m; 1951 struct ifnet *ifp = &sc->arpcom.ac_if; 1952 struct xl_chain_onefrag *cur_rx; 1953 int total_len = 0; 1954 u_int32_t rxstat; 1955 1956 XL_LOCK_ASSERT(sc); 1957 again: 1958 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 1959 BUS_DMASYNC_POSTREAD); 1960 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 1961 cur_rx = sc->xl_cdata.xl_rx_head; 1962 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1963 total_len = rxstat & XL_RXSTAT_LENMASK; 1964 1965 /* 1966 * Since we have told the chip to allow large frames, 1967 * we need to trap giant frame errors in software. We allow 1968 * a little more than the normal frame size to account for 1969 * frames with VLAN tags. 1970 */ 1971 if (total_len > XL_MAX_FRAMELEN) 1972 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 1973 1974 /* 1975 * If an error occurs, update stats, clear the 1976 * status word and leave the mbuf cluster in place: 1977 * it should simply get re-used next time this descriptor 1978 * comes up in the ring. 1979 */ 1980 if (rxstat & XL_RXSTAT_UP_ERROR) { 1981 ifp->if_ierrors++; 1982 cur_rx->xl_ptr->xl_status = 0; 1983 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1984 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1985 continue; 1986 } 1987 1988 /* 1989 * If the error bit was not set, the upload complete 1990 * bit should be set which means we have a valid packet. 1991 * If not, something truly strange has happened. 1992 */ 1993 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 1994 if_printf(ifp, 1995 "bad receive status -- packet dropped\n"); 1996 ifp->if_ierrors++; 1997 cur_rx->xl_ptr->xl_status = 0; 1998 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1999 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2000 continue; 2001 } 2002 2003 /* No errors; receive the packet. */ 2004 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 2005 BUS_DMASYNC_POSTREAD); 2006 m = cur_rx->xl_mbuf; 2007 2008 /* 2009 * Try to conjure up a new mbuf cluster. If that 2010 * fails, it means we have an out of memory condition and 2011 * should leave the buffer in place and continue. This will 2012 * result in a lost packet, but there's little else we 2013 * can do in this situation. 2014 */ 2015 if (xl_newbuf(sc, cur_rx)) { 2016 ifp->if_ierrors++; 2017 cur_rx->xl_ptr->xl_status = 0; 2018 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2019 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2020 continue; 2021 } 2022 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2023 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2024 2025 ifp->if_ipackets++; 2026 m->m_pkthdr.rcvif = ifp; 2027 m->m_pkthdr.len = m->m_len = total_len; 2028 2029 if (ifp->if_capenable & IFCAP_RXCSUM) { 2030 /* Do IP checksum checking. */ 2031 if (rxstat & XL_RXSTAT_IPCKOK) 2032 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2033 if (!(rxstat & XL_RXSTAT_IPCKERR)) 2034 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2035 if ((rxstat & XL_RXSTAT_TCPCOK && 2036 !(rxstat & XL_RXSTAT_TCPCKERR)) || 2037 (rxstat & XL_RXSTAT_UDPCKOK && 2038 !(rxstat & XL_RXSTAT_UDPCKERR))) { 2039 m->m_pkthdr.csum_flags |= 2040 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2041 m->m_pkthdr.csum_data = 0xffff; 2042 } 2043 } 2044 2045 XL_UNLOCK(sc); 2046 (*ifp->if_input)(ifp, m); 2047 XL_LOCK(sc); 2048 } 2049 2050 /* 2051 * Handle the 'end of channel' condition. When the upload 2052 * engine hits the end of the RX ring, it will stall. This 2053 * is our cue to flush the RX ring, reload the uplist pointer 2054 * register and unstall the engine. 2055 * XXX This is actually a little goofy. With the ThunderLAN 2056 * chip, you get an interrupt when the receiver hits the end 2057 * of the receive ring, which tells you exactly when you 2058 * you need to reload the ring pointer. Here we have to 2059 * fake it. I'm mad at myself for not being clever enough 2060 * to avoid the use of a goto here. 2061 */ 2062 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2063 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2064 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2065 xl_wait(sc); 2066 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2067 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2068 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2069 goto again; 2070 } 2071 } 2072 2073 /* 2074 * A frame was downloaded to the chip. It's safe for us to clean up 2075 * the list buffers. 2076 */ 2077 static void 2078 xl_txeof(struct xl_softc *sc) 2079 { 2080 struct xl_chain *cur_tx; 2081 struct ifnet *ifp = &sc->arpcom.ac_if; 2082 2083 XL_LOCK_ASSERT(sc); 2084 2085 /* Clear the timeout timer. */ 2086 ifp->if_timer = 0; 2087 2088 /* 2089 * Go through our tx list and free mbufs for those 2090 * frames that have been uploaded. Note: the 3c905B 2091 * sets a special bit in the status word to let us 2092 * know that a frame has been downloaded, but the 2093 * original 3c900/3c905 adapters don't do that. 2094 * Consequently, we have to use a different test if 2095 * xl_type != XL_TYPE_905B. 2096 */ 2097 while (sc->xl_cdata.xl_tx_head != NULL) { 2098 cur_tx = sc->xl_cdata.xl_tx_head; 2099 2100 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2101 break; 2102 2103 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2104 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2105 BUS_DMASYNC_POSTWRITE); 2106 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2107 m_freem(cur_tx->xl_mbuf); 2108 cur_tx->xl_mbuf = NULL; 2109 ifp->if_opackets++; 2110 2111 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2112 sc->xl_cdata.xl_tx_free = cur_tx; 2113 } 2114 2115 if (sc->xl_cdata.xl_tx_head == NULL) { 2116 ifp->if_flags &= ~IFF_OACTIVE; 2117 sc->xl_cdata.xl_tx_tail = NULL; 2118 } else { 2119 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2120 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2121 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2122 sc->xl_cdata.xl_tx_head->xl_phys); 2123 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2124 } 2125 } 2126 } 2127 2128 static void 2129 xl_txeof_90xB(struct xl_softc *sc) 2130 { 2131 struct xl_chain *cur_tx = NULL; 2132 struct ifnet *ifp = &sc->arpcom.ac_if; 2133 int idx; 2134 2135 XL_LOCK_ASSERT(sc); 2136 2137 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2138 BUS_DMASYNC_POSTREAD); 2139 idx = sc->xl_cdata.xl_tx_cons; 2140 while (idx != sc->xl_cdata.xl_tx_prod) { 2141 2142 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2143 2144 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2145 XL_TXSTAT_DL_COMPLETE)) 2146 break; 2147 2148 if (cur_tx->xl_mbuf != NULL) { 2149 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2150 BUS_DMASYNC_POSTWRITE); 2151 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2152 m_freem(cur_tx->xl_mbuf); 2153 cur_tx->xl_mbuf = NULL; 2154 } 2155 2156 ifp->if_opackets++; 2157 2158 sc->xl_cdata.xl_tx_cnt--; 2159 XL_INC(idx, XL_TX_LIST_CNT); 2160 ifp->if_timer = 0; 2161 } 2162 2163 sc->xl_cdata.xl_tx_cons = idx; 2164 2165 if (cur_tx != NULL) 2166 ifp->if_flags &= ~IFF_OACTIVE; 2167 } 2168 2169 /* 2170 * TX 'end of channel' interrupt handler. Actually, we should 2171 * only get a 'TX complete' interrupt if there's a transmit error, 2172 * so this is really TX error handler. 2173 */ 2174 static void 2175 xl_txeoc(struct xl_softc *sc) 2176 { 2177 u_int8_t txstat; 2178 2179 XL_LOCK_ASSERT(sc); 2180 2181 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2182 if (txstat & XL_TXSTATUS_UNDERRUN || 2183 txstat & XL_TXSTATUS_JABBER || 2184 txstat & XL_TXSTATUS_RECLAIM) { 2185 if_printf(&sc->arpcom.ac_if, 2186 "transmission error: %x\n", txstat); 2187 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2188 xl_wait(sc); 2189 if (sc->xl_type == XL_TYPE_905B) { 2190 if (sc->xl_cdata.xl_tx_cnt) { 2191 int i; 2192 struct xl_chain *c; 2193 2194 i = sc->xl_cdata.xl_tx_cons; 2195 c = &sc->xl_cdata.xl_tx_chain[i]; 2196 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2197 c->xl_phys); 2198 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2199 } 2200 } else { 2201 if (sc->xl_cdata.xl_tx_head != NULL) 2202 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2203 sc->xl_cdata.xl_tx_head->xl_phys); 2204 } 2205 /* 2206 * Remember to set this for the 2207 * first generation 3c90X chips. 2208 */ 2209 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2210 if (txstat & XL_TXSTATUS_UNDERRUN && 2211 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2212 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2213 if_printf(&sc->arpcom.ac_if, 2214 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh); 2215 } 2216 CSR_WRITE_2(sc, XL_COMMAND, 2217 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2218 if (sc->xl_type == XL_TYPE_905B) { 2219 CSR_WRITE_2(sc, XL_COMMAND, 2220 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2221 } 2222 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2223 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2224 } else { 2225 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2226 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2227 } 2228 /* 2229 * Write an arbitrary byte to the TX_STATUS register 2230 * to clear this interrupt/error and advance to the next. 2231 */ 2232 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2233 } 2234 } 2235 2236 static void 2237 xl_intr(void *arg) 2238 { 2239 struct xl_softc *sc = arg; 2240 struct ifnet *ifp = &sc->arpcom.ac_if; 2241 u_int16_t status; 2242 2243 XL_LOCK(sc); 2244 2245 while ((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && 2246 status != 0xFFFF) { 2247 CSR_WRITE_2(sc, XL_COMMAND, 2248 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2249 2250 if (status & XL_STAT_UP_COMPLETE) { 2251 int curpkts; 2252 2253 curpkts = ifp->if_ipackets; 2254 xl_rxeof(sc); 2255 if (curpkts == ifp->if_ipackets) { 2256 while (xl_rx_resync(sc)) 2257 xl_rxeof(sc); 2258 } 2259 } 2260 2261 if (status & XL_STAT_DOWN_COMPLETE) { 2262 if (sc->xl_type == XL_TYPE_905B) 2263 xl_txeof_90xB(sc); 2264 else 2265 xl_txeof(sc); 2266 } 2267 2268 if (status & XL_STAT_TX_COMPLETE) { 2269 ifp->if_oerrors++; 2270 xl_txeoc(sc); 2271 } 2272 2273 if (status & XL_STAT_ADFAIL) { 2274 xl_reset(sc); 2275 xl_init_locked(sc); 2276 } 2277 2278 if (status & XL_STAT_STATSOFLOW) { 2279 sc->xl_stats_no_timeout = 1; 2280 xl_stats_update_locked(sc); 2281 sc->xl_stats_no_timeout = 0; 2282 } 2283 } 2284 2285 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2286 if (sc->xl_type == XL_TYPE_905B) 2287 xl_start_90xB_locked(ifp); 2288 else 2289 xl_start_locked(ifp); 2290 } 2291 2292 XL_UNLOCK(sc); 2293 } 2294 2295 /* 2296 * XXX: This is an entry point for callout which needs to take the lock. 2297 */ 2298 static void 2299 xl_stats_update(void *xsc) 2300 { 2301 struct xl_softc *sc = xsc; 2302 2303 XL_LOCK(sc); 2304 xl_stats_update_locked(sc); 2305 XL_UNLOCK(sc); 2306 } 2307 2308 static void 2309 xl_stats_update_locked(struct xl_softc *sc) 2310 { 2311 struct ifnet *ifp = &sc->arpcom.ac_if; 2312 struct xl_stats xl_stats; 2313 u_int8_t *p; 2314 int i; 2315 struct mii_data *mii = NULL; 2316 2317 XL_LOCK_ASSERT(sc); 2318 2319 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2320 2321 if (sc->xl_miibus != NULL) 2322 mii = device_get_softc(sc->xl_miibus); 2323 2324 p = (u_int8_t *)&xl_stats; 2325 2326 /* Read all the stats registers. */ 2327 XL_SEL_WIN(6); 2328 2329 for (i = 0; i < 16; i++) 2330 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2331 2332 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2333 2334 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2335 xl_stats.xl_tx_single_collision + xl_stats.xl_tx_late_collision; 2336 2337 /* 2338 * Boomerang and cyclone chips have an extra stats counter 2339 * in window 4 (BadSSD). We have to read this too in order 2340 * to clear out all the stats registers and avoid a statsoflow 2341 * interrupt. 2342 */ 2343 XL_SEL_WIN(4); 2344 CSR_READ_1(sc, XL_W4_BADSSD); 2345 2346 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2347 mii_tick(mii); 2348 2349 XL_SEL_WIN(7); 2350 2351 if (!sc->xl_stats_no_timeout) 2352 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz); 2353 } 2354 2355 /* 2356 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2357 * pointers to the fragment pointers. 2358 */ 2359 static int 2360 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head) 2361 { 2362 int error; 2363 u_int32_t status; 2364 struct ifnet *ifp = &sc->arpcom.ac_if; 2365 2366 XL_LOCK_ASSERT(sc); 2367 2368 /* 2369 * Start packing the mbufs in this chain into 2370 * the fragment pointers. Stop when we run out 2371 * of fragments or hit the end of the mbuf chain. 2372 */ 2373 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head, 2374 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2375 2376 if (error && error != EFBIG) { 2377 m_freem(m_head); 2378 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2379 return (1); 2380 } 2381 2382 /* 2383 * Handle special case: we used up all 63 fragments, 2384 * but we have more mbufs left in the chain. Copy the 2385 * data into an mbuf cluster. Note that we don't 2386 * bother clearing the values in the other fragment 2387 * pointers/counters; it wouldn't gain us anything, 2388 * and would waste cycles. 2389 */ 2390 if (error) { 2391 struct mbuf *m_new; 2392 2393 m_new = m_defrag(m_head, M_DONTWAIT); 2394 if (m_new == NULL) { 2395 m_freem(m_head); 2396 return (1); 2397 } else { 2398 m_head = m_new; 2399 } 2400 2401 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, 2402 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2403 if (error) { 2404 m_freem(m_head); 2405 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2406 return (1); 2407 } 2408 } 2409 2410 if (sc->xl_type == XL_TYPE_905B) { 2411 status = XL_TXSTAT_RND_DEFEAT; 2412 2413 #ifndef XL905B_TXCSUM_BROKEN 2414 if (m_head->m_pkthdr.csum_flags) { 2415 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2416 status |= XL_TXSTAT_IPCKSUM; 2417 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2418 status |= XL_TXSTAT_TCPCKSUM; 2419 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2420 status |= XL_TXSTAT_UDPCKSUM; 2421 } 2422 #endif 2423 c->xl_ptr->xl_status = htole32(status); 2424 } 2425 2426 c->xl_mbuf = m_head; 2427 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2428 return (0); 2429 } 2430 2431 /* 2432 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2433 * to the mbuf data regions directly in the transmit lists. We also save a 2434 * copy of the pointers since the transmit list fragment pointers are 2435 * physical addresses. 2436 */ 2437 2438 static void 2439 xl_start(struct ifnet *ifp) 2440 { 2441 struct xl_softc *sc = ifp->if_softc; 2442 2443 XL_LOCK(sc); 2444 2445 if (sc->xl_type == XL_TYPE_905B) 2446 xl_start_90xB_locked(ifp); 2447 else 2448 xl_start_locked(ifp); 2449 2450 XL_UNLOCK(sc); 2451 } 2452 2453 static void 2454 xl_start_locked(struct ifnet *ifp) 2455 { 2456 struct xl_softc *sc = ifp->if_softc; 2457 struct mbuf *m_head = NULL; 2458 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2459 struct xl_chain *prev_tx; 2460 u_int32_t status; 2461 int error; 2462 2463 XL_LOCK_ASSERT(sc); 2464 2465 /* 2466 * Check for an available queue slot. If there are none, 2467 * punt. 2468 */ 2469 if (sc->xl_cdata.xl_tx_free == NULL) { 2470 xl_txeoc(sc); 2471 xl_txeof(sc); 2472 if (sc->xl_cdata.xl_tx_free == NULL) { 2473 ifp->if_flags |= IFF_OACTIVE; 2474 return; 2475 } 2476 } 2477 2478 start_tx = sc->xl_cdata.xl_tx_free; 2479 2480 while (sc->xl_cdata.xl_tx_free != NULL) { 2481 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2482 if (m_head == NULL) 2483 break; 2484 2485 /* Pick a descriptor off the free list. */ 2486 prev_tx = cur_tx; 2487 cur_tx = sc->xl_cdata.xl_tx_free; 2488 2489 /* Pack the data into the descriptor. */ 2490 error = xl_encap(sc, cur_tx, m_head); 2491 if (error) { 2492 cur_tx = prev_tx; 2493 continue; 2494 } 2495 2496 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2497 cur_tx->xl_next = NULL; 2498 2499 /* Chain it together. */ 2500 if (prev != NULL) { 2501 prev->xl_next = cur_tx; 2502 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2503 } 2504 prev = cur_tx; 2505 2506 /* 2507 * If there's a BPF listener, bounce a copy of this frame 2508 * to him. 2509 */ 2510 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2511 } 2512 2513 /* 2514 * If there are no packets queued, bail. 2515 */ 2516 if (cur_tx == NULL) 2517 return; 2518 2519 /* 2520 * Place the request for the upload interrupt 2521 * in the last descriptor in the chain. This way, if 2522 * we're chaining several packets at once, we'll only 2523 * get an interupt once for the whole chain rather than 2524 * once for each packet. 2525 */ 2526 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2527 XL_TXSTAT_DL_INTR); 2528 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2529 BUS_DMASYNC_PREWRITE); 2530 2531 /* 2532 * Queue the packets. If the TX channel is clear, update 2533 * the downlist pointer register. 2534 */ 2535 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2536 xl_wait(sc); 2537 2538 if (sc->xl_cdata.xl_tx_head != NULL) { 2539 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2540 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2541 htole32(start_tx->xl_phys); 2542 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2543 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2544 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2545 sc->xl_cdata.xl_tx_tail = cur_tx; 2546 } else { 2547 sc->xl_cdata.xl_tx_head = start_tx; 2548 sc->xl_cdata.xl_tx_tail = cur_tx; 2549 } 2550 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2551 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2552 2553 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2554 2555 XL_SEL_WIN(7); 2556 2557 /* 2558 * Set a timeout in case the chip goes out to lunch. 2559 */ 2560 ifp->if_timer = 5; 2561 2562 /* 2563 * XXX Under certain conditions, usually on slower machines 2564 * where interrupts may be dropped, it's possible for the 2565 * adapter to chew up all the buffers in the receive ring 2566 * and stall, without us being able to do anything about it. 2567 * To guard against this, we need to make a pass over the 2568 * RX queue to make sure there aren't any packets pending. 2569 * Doing it here means we can flush the receive ring at the 2570 * same time the chip is DMAing the transmit descriptors we 2571 * just gave it. 2572 * 2573 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2574 * nature of their chips in all their marketing literature; 2575 * we may as well take advantage of it. :) 2576 */ 2577 xl_rxeof(sc); 2578 } 2579 2580 static void 2581 xl_start_90xB_locked(struct ifnet *ifp) 2582 { 2583 struct xl_softc *sc = ifp->if_softc; 2584 struct mbuf *m_head = NULL; 2585 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2586 struct xl_chain *prev_tx; 2587 int error, idx; 2588 2589 XL_LOCK_ASSERT(sc); 2590 2591 if (ifp->if_flags & IFF_OACTIVE) 2592 return; 2593 2594 idx = sc->xl_cdata.xl_tx_prod; 2595 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2596 2597 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { 2598 2599 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2600 ifp->if_flags |= IFF_OACTIVE; 2601 break; 2602 } 2603 2604 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2605 if (m_head == NULL) 2606 break; 2607 2608 prev_tx = cur_tx; 2609 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2610 2611 /* Pack the data into the descriptor. */ 2612 error = xl_encap(sc, cur_tx, m_head); 2613 if (error) { 2614 cur_tx = prev_tx; 2615 continue; 2616 } 2617 2618 /* Chain it together. */ 2619 if (prev != NULL) 2620 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2621 prev = cur_tx; 2622 2623 /* 2624 * If there's a BPF listener, bounce a copy of this frame 2625 * to him. 2626 */ 2627 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2628 2629 XL_INC(idx, XL_TX_LIST_CNT); 2630 sc->xl_cdata.xl_tx_cnt++; 2631 } 2632 2633 /* 2634 * If there are no packets queued, bail. 2635 */ 2636 if (cur_tx == NULL) 2637 return; 2638 2639 /* 2640 * Place the request for the upload interrupt 2641 * in the last descriptor in the chain. This way, if 2642 * we're chaining several packets at once, we'll only 2643 * get an interupt once for the whole chain rather than 2644 * once for each packet. 2645 */ 2646 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2647 XL_TXSTAT_DL_INTR); 2648 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2649 BUS_DMASYNC_PREWRITE); 2650 2651 /* Start transmission */ 2652 sc->xl_cdata.xl_tx_prod = idx; 2653 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2654 2655 /* 2656 * Set a timeout in case the chip goes out to lunch. 2657 */ 2658 ifp->if_timer = 5; 2659 } 2660 2661 static void 2662 xl_init(void *xsc) 2663 { 2664 struct xl_softc *sc = xsc; 2665 2666 XL_LOCK(sc); 2667 xl_init_locked(sc); 2668 XL_UNLOCK(sc); 2669 } 2670 2671 static void 2672 xl_init_locked(struct xl_softc *sc) 2673 { 2674 struct ifnet *ifp = &sc->arpcom.ac_if; 2675 int error, i; 2676 u_int16_t rxfilt = 0; 2677 struct mii_data *mii = NULL; 2678 2679 XL_LOCK_ASSERT(sc); 2680 2681 /* 2682 * Cancel pending I/O and free all RX/TX buffers. 2683 */ 2684 xl_stop(sc); 2685 2686 if (sc->xl_miibus == NULL) { 2687 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2688 xl_wait(sc); 2689 } 2690 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2691 xl_wait(sc); 2692 DELAY(10000); 2693 2694 if (sc->xl_miibus != NULL) 2695 mii = device_get_softc(sc->xl_miibus); 2696 2697 /* Init our MAC address */ 2698 XL_SEL_WIN(2); 2699 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2700 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2701 sc->arpcom.ac_enaddr[i]); 2702 } 2703 2704 /* Clear the station mask. */ 2705 for (i = 0; i < 3; i++) 2706 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2707 #ifdef notdef 2708 /* Reset TX and RX. */ 2709 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2710 xl_wait(sc); 2711 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2712 xl_wait(sc); 2713 #endif 2714 /* Init circular RX list. */ 2715 error = xl_list_rx_init(sc); 2716 if (error) { 2717 if_printf(ifp, "initialization of the rx ring failed (%d)\n", 2718 error); 2719 xl_stop(sc); 2720 return; 2721 } 2722 2723 /* Init TX descriptors. */ 2724 if (sc->xl_type == XL_TYPE_905B) 2725 error = xl_list_tx_init_90xB(sc); 2726 else 2727 error = xl_list_tx_init(sc); 2728 if (error) { 2729 if_printf(ifp, "initialization of the tx ring failed (%d)\n", 2730 error); 2731 xl_stop(sc); 2732 return; 2733 } 2734 2735 /* 2736 * Set the TX freethresh value. 2737 * Note that this has no effect on 3c905B "cyclone" 2738 * cards but is required for 3c900/3c905 "boomerang" 2739 * cards in order to enable the download engine. 2740 */ 2741 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2742 2743 /* Set the TX start threshold for best performance. */ 2744 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 2745 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2746 2747 /* 2748 * If this is a 3c905B, also set the tx reclaim threshold. 2749 * This helps cut down on the number of tx reclaim errors 2750 * that could happen on a busy network. The chip multiplies 2751 * the register value by 16 to obtain the actual threshold 2752 * in bytes, so we divide by 16 when setting the value here. 2753 * The existing threshold value can be examined by reading 2754 * the register at offset 9 in window 5. 2755 */ 2756 if (sc->xl_type == XL_TYPE_905B) { 2757 CSR_WRITE_2(sc, XL_COMMAND, 2758 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2759 } 2760 2761 /* Set RX filter bits. */ 2762 XL_SEL_WIN(5); 2763 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2764 2765 /* Set the individual bit to receive frames for this host only. */ 2766 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2767 2768 /* If we want promiscuous mode, set the allframes bit. */ 2769 if (ifp->if_flags & IFF_PROMISC) { 2770 rxfilt |= XL_RXFILTER_ALLFRAMES; 2771 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2772 } else { 2773 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2774 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2775 } 2776 2777 /* 2778 * Set capture broadcast bit to capture broadcast frames. 2779 */ 2780 if (ifp->if_flags & IFF_BROADCAST) { 2781 rxfilt |= XL_RXFILTER_BROADCAST; 2782 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2783 } else { 2784 rxfilt &= ~XL_RXFILTER_BROADCAST; 2785 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2786 } 2787 2788 /* 2789 * Program the multicast filter, if necessary. 2790 */ 2791 if (sc->xl_type == XL_TYPE_905B) 2792 xl_setmulti_hash(sc); 2793 else 2794 xl_setmulti(sc); 2795 2796 /* 2797 * Load the address of the RX list. We have to 2798 * stall the upload engine before we can manipulate 2799 * the uplist pointer register, then unstall it when 2800 * we're finished. We also have to wait for the 2801 * stall command to complete before proceeding. 2802 * Note that we have to do this after any RX resets 2803 * have completed since the uplist register is cleared 2804 * by a reset. 2805 */ 2806 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2807 xl_wait(sc); 2808 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2809 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2810 xl_wait(sc); 2811 2812 if (sc->xl_type == XL_TYPE_905B) { 2813 /* Set polling interval */ 2814 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2815 /* Load the address of the TX list */ 2816 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2817 xl_wait(sc); 2818 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2819 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2820 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2821 xl_wait(sc); 2822 } 2823 2824 /* 2825 * If the coax transceiver is on, make sure to enable 2826 * the DC-DC converter. 2827 */ 2828 XL_SEL_WIN(3); 2829 if (sc->xl_xcvr == XL_XCVR_COAX) 2830 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2831 else 2832 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2833 2834 /* 2835 * increase packet size to allow reception of 802.1q or ISL packets. 2836 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2837 * control register. For 3c90xB/C chips, use the RX packet size 2838 * register. 2839 */ 2840 2841 if (sc->xl_type == XL_TYPE_905B) 2842 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2843 else { 2844 u_int8_t macctl; 2845 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2846 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2847 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2848 } 2849 2850 /* Clear out the stats counters. */ 2851 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2852 sc->xl_stats_no_timeout = 1; 2853 xl_stats_update_locked(sc); 2854 sc->xl_stats_no_timeout = 0; 2855 XL_SEL_WIN(4); 2856 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2857 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2858 2859 /* 2860 * Enable interrupts. 2861 */ 2862 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2863 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2864 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2865 if (sc->xl_flags & XL_FLAG_FUNCREG) 2866 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2867 2868 /* Set the RX early threshold */ 2869 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2870 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2871 2872 /* Enable receiver and transmitter. */ 2873 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2874 xl_wait(sc); 2875 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2876 xl_wait(sc); 2877 2878 /* XXX Downcall to miibus. */ 2879 if (mii != NULL) 2880 mii_mediachg(mii); 2881 2882 /* Select window 7 for normal operations. */ 2883 XL_SEL_WIN(7); 2884 2885 ifp->if_flags |= IFF_RUNNING; 2886 ifp->if_flags &= ~IFF_OACTIVE; 2887 2888 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz); 2889 } 2890 2891 /* 2892 * Set media options. 2893 */ 2894 static int 2895 xl_ifmedia_upd(struct ifnet *ifp) 2896 { 2897 struct xl_softc *sc = ifp->if_softc; 2898 struct ifmedia *ifm = NULL; 2899 struct mii_data *mii = NULL; 2900 2901 /*XL_LOCK_ASSERT(sc);*/ 2902 2903 if (sc->xl_miibus != NULL) 2904 mii = device_get_softc(sc->xl_miibus); 2905 if (mii == NULL) 2906 ifm = &sc->ifmedia; 2907 else 2908 ifm = &mii->mii_media; 2909 2910 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2911 case IFM_100_FX: 2912 case IFM_10_FL: 2913 case IFM_10_2: 2914 case IFM_10_5: 2915 xl_setmode(sc, ifm->ifm_media); 2916 return (0); 2917 break; 2918 default: 2919 break; 2920 } 2921 2922 if (sc->xl_media & XL_MEDIAOPT_MII || 2923 sc->xl_media & XL_MEDIAOPT_BTX || 2924 sc->xl_media & XL_MEDIAOPT_BT4) { 2925 xl_init(sc); /* XXX */ 2926 } else { 2927 xl_setmode(sc, ifm->ifm_media); 2928 } 2929 2930 return (0); 2931 } 2932 2933 /* 2934 * Report current media status. 2935 */ 2936 static void 2937 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2938 { 2939 struct xl_softc *sc = ifp->if_softc; 2940 u_int32_t icfg; 2941 u_int16_t status = 0; 2942 struct mii_data *mii = NULL; 2943 2944 /*XL_LOCK_ASSERT(sc);*/ 2945 2946 if (sc->xl_miibus != NULL) 2947 mii = device_get_softc(sc->xl_miibus); 2948 2949 XL_SEL_WIN(4); 2950 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 2951 2952 XL_SEL_WIN(3); 2953 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 2954 icfg >>= XL_ICFG_CONNECTOR_BITS; 2955 2956 ifmr->ifm_active = IFM_ETHER; 2957 ifmr->ifm_status = IFM_AVALID; 2958 2959 if ((status & XL_MEDIASTAT_CARRIER) == 0) 2960 ifmr->ifm_status |= IFM_ACTIVE; 2961 2962 switch (icfg) { 2963 case XL_XCVR_10BT: 2964 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2965 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2966 ifmr->ifm_active |= IFM_FDX; 2967 else 2968 ifmr->ifm_active |= IFM_HDX; 2969 break; 2970 case XL_XCVR_AUI: 2971 if (sc->xl_type == XL_TYPE_905B && 2972 sc->xl_media == XL_MEDIAOPT_10FL) { 2973 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 2974 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2975 ifmr->ifm_active |= IFM_FDX; 2976 else 2977 ifmr->ifm_active |= IFM_HDX; 2978 } else 2979 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2980 break; 2981 case XL_XCVR_COAX: 2982 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 2983 break; 2984 /* 2985 * XXX MII and BTX/AUTO should be separate cases. 2986 */ 2987 2988 case XL_XCVR_100BTX: 2989 case XL_XCVR_AUTO: 2990 case XL_XCVR_MII: 2991 if (mii != NULL) { 2992 mii_pollstat(mii); 2993 ifmr->ifm_active = mii->mii_media_active; 2994 ifmr->ifm_status = mii->mii_media_status; 2995 } 2996 break; 2997 case XL_XCVR_100BFX: 2998 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 2999 break; 3000 default: 3001 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3002 break; 3003 } 3004 } 3005 3006 static int 3007 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3008 { 3009 struct xl_softc *sc = ifp->if_softc; 3010 struct ifreq *ifr = (struct ifreq *) data; 3011 int error = 0; 3012 struct mii_data *mii = NULL; 3013 u_int8_t rxfilt; 3014 3015 switch (command) { 3016 case SIOCSIFFLAGS: 3017 XL_LOCK(sc); 3018 3019 XL_SEL_WIN(5); 3020 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3021 if (ifp->if_flags & IFF_UP) { 3022 if (ifp->if_flags & IFF_RUNNING && 3023 ifp->if_flags & IFF_PROMISC && 3024 !(sc->xl_if_flags & IFF_PROMISC)) { 3025 rxfilt |= XL_RXFILTER_ALLFRAMES; 3026 CSR_WRITE_2(sc, XL_COMMAND, 3027 XL_CMD_RX_SET_FILT|rxfilt); 3028 XL_SEL_WIN(7); 3029 } else if (ifp->if_flags & IFF_RUNNING && 3030 !(ifp->if_flags & IFF_PROMISC) && 3031 sc->xl_if_flags & IFF_PROMISC) { 3032 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3033 CSR_WRITE_2(sc, XL_COMMAND, 3034 XL_CMD_RX_SET_FILT|rxfilt); 3035 XL_SEL_WIN(7); 3036 } else 3037 if ((ifp->if_flags & IFF_RUNNING) == 0) { 3038 xl_init_locked(sc); 3039 } 3040 } else { 3041 if (ifp->if_flags & IFF_RUNNING) 3042 xl_stop(sc); 3043 } 3044 sc->xl_if_flags = ifp->if_flags; 3045 XL_UNLOCK(sc); 3046 error = 0; 3047 break; 3048 case SIOCADDMULTI: 3049 case SIOCDELMULTI: 3050 /* XXX Downcall from if_addmulti() possibly with locks held. */ 3051 XL_LOCK(sc); 3052 if (sc->xl_type == XL_TYPE_905B) 3053 xl_setmulti_hash(sc); 3054 else 3055 xl_setmulti(sc); 3056 XL_UNLOCK(sc); 3057 error = 0; 3058 break; 3059 case SIOCGIFMEDIA: 3060 case SIOCSIFMEDIA: 3061 /* XXX Downcall from ifmedia possibly with locks held. */ 3062 /*XL_LOCK(sc);*/ 3063 if (sc->xl_miibus != NULL) 3064 mii = device_get_softc(sc->xl_miibus); 3065 if (mii == NULL) 3066 error = ifmedia_ioctl(ifp, ifr, 3067 &sc->ifmedia, command); 3068 else 3069 error = ifmedia_ioctl(ifp, ifr, 3070 &mii->mii_media, command); 3071 /*XL_UNLOCK(sc);*/ 3072 break; 3073 case SIOCSIFCAP: 3074 XL_LOCK(sc); 3075 ifp->if_capenable = ifr->ifr_reqcap; 3076 if (ifp->if_capenable & IFCAP_TXCSUM) 3077 ifp->if_hwassist = XL905B_CSUM_FEATURES; 3078 else 3079 ifp->if_hwassist = 0; 3080 XL_UNLOCK(sc); 3081 break; 3082 default: 3083 error = ether_ioctl(ifp, command, data); 3084 break; 3085 } 3086 3087 return (error); 3088 } 3089 3090 /* 3091 * XXX: Invoked from ifnet slow timer. Lock coverage needed. 3092 */ 3093 static void 3094 xl_watchdog(struct ifnet *ifp) 3095 { 3096 struct xl_softc *sc = ifp->if_softc; 3097 u_int16_t status = 0; 3098 3099 XL_LOCK(sc); 3100 3101 ifp->if_oerrors++; 3102 XL_SEL_WIN(4); 3103 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3104 if_printf(ifp, "watchdog timeout\n"); 3105 3106 if (status & XL_MEDIASTAT_CARRIER) 3107 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 3108 3109 xl_txeoc(sc); 3110 xl_txeof(sc); 3111 xl_rxeof(sc); 3112 xl_reset(sc); 3113 xl_init_locked(sc); 3114 3115 XL_UNLOCK(sc); 3116 3117 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3118 (*ifp->if_start)(ifp); 3119 } 3120 3121 /* 3122 * Stop the adapter and free any mbufs allocated to the 3123 * RX and TX lists. 3124 */ 3125 static void 3126 xl_stop(struct xl_softc *sc) 3127 { 3128 register int i; 3129 struct ifnet *ifp = &sc->arpcom.ac_if; 3130 3131 XL_LOCK_ASSERT(sc); 3132 3133 ifp->if_timer = 0; 3134 3135 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3136 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3137 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3138 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3139 xl_wait(sc); 3140 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3141 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3142 DELAY(800); 3143 3144 #ifdef foo 3145 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3146 xl_wait(sc); 3147 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3148 xl_wait(sc); 3149 #endif 3150 3151 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3152 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3153 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3154 if (sc->xl_flags & XL_FLAG_FUNCREG) 3155 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3156 3157 /* Stop the stats updater. */ 3158 untimeout(xl_stats_update, sc, sc->xl_stat_ch); 3159 3160 /* 3161 * Free data in the RX lists. 3162 */ 3163 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3164 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3165 bus_dmamap_unload(sc->xl_mtag, 3166 sc->xl_cdata.xl_rx_chain[i].xl_map); 3167 bus_dmamap_destroy(sc->xl_mtag, 3168 sc->xl_cdata.xl_rx_chain[i].xl_map); 3169 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3170 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3171 } 3172 } 3173 if (sc->xl_ldata.xl_rx_list != NULL) 3174 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3175 /* 3176 * Free the TX list buffers. 3177 */ 3178 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3179 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3180 bus_dmamap_unload(sc->xl_mtag, 3181 sc->xl_cdata.xl_tx_chain[i].xl_map); 3182 bus_dmamap_destroy(sc->xl_mtag, 3183 sc->xl_cdata.xl_tx_chain[i].xl_map); 3184 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3185 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3186 } 3187 } 3188 if (sc->xl_ldata.xl_tx_list != NULL) 3189 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3190 3191 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3192 } 3193 3194 /* 3195 * Stop all chip I/O so that the kernel's probe routines don't 3196 * get confused by errant DMAs when rebooting. 3197 */ 3198 static void 3199 xl_shutdown(device_t dev) 3200 { 3201 struct xl_softc *sc; 3202 3203 sc = device_get_softc(dev); 3204 3205 XL_LOCK(sc); 3206 xl_reset(sc); 3207 xl_stop(sc); 3208 XL_UNLOCK(sc); 3209 } 3210 3211 static int 3212 xl_suspend(device_t dev) 3213 { 3214 struct xl_softc *sc; 3215 3216 sc = device_get_softc(dev); 3217 3218 XL_LOCK(sc); 3219 xl_stop(sc); 3220 XL_UNLOCK(sc); 3221 3222 return (0); 3223 } 3224 3225 static int 3226 xl_resume(device_t dev) 3227 { 3228 struct xl_softc *sc; 3229 struct ifnet *ifp; 3230 3231 sc = device_get_softc(dev); 3232 ifp = &sc->arpcom.ac_if; 3233 3234 XL_LOCK(sc); 3235 3236 xl_reset(sc); 3237 if (ifp->if_flags & IFF_UP) 3238 xl_init_locked(sc); 3239 3240 XL_UNLOCK(sc); 3241 3242 return (0); 3243 }
Cache object: 18cf136a9f764e026617f9e117dd57d3
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]