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sys/pci/if_xl.c
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1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: src/sys/pci/if_xl.c,v 1.179.2.8 2006/01/29 15:39:09 emaste Exp $"); 35 36 /* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77 /* 78 * The 3c90x series chips use a bus-master DMA interface for transfering 79 * packets to and from the controller chip. Some of the "vortex" cards 80 * (3c59x) also supported a bus master mode, however for those chips 81 * you could only DMA packets to/from a contiguous memory buffer. For 82 * transmission this would mean copying the contents of the queued mbuf 83 * chain into an mbuf cluster and then DMAing the cluster. This extra 84 * copy would sort of defeat the purpose of the bus master support for 85 * any packet that doesn't fit into a single mbuf. 86 * 87 * By contrast, the 3c90x cards support a fragment-based bus master 88 * mode where mbuf chains can be encapsulated using TX descriptors. 89 * This is similar to other PCI chips such as the Texas Instruments 90 * ThunderLAN and the Intel 82557/82558. 91 * 92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 93 * bus master chips because they maintain the old PIO interface for 94 * backwards compatibility, but starting with the 3c905B and the 95 * "cyclone" chips, the compatibility interface has been dropped. 96 * Since using bus master DMA is a big win, we use this driver to 97 * support the PCI "boomerang" chips even though they work with the 98 * "vortex" driver in order to obtain better performance. 99 * 100 * This driver is in the /sys/pci directory because it only supports 101 * PCI-based NICs. 102 */ 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/sockio.h> 107 #include <sys/endian.h> 108 #include <sys/mbuf.h> 109 #include <sys/kernel.h> 110 #include <sys/module.h> 111 #include <sys/socket.h> 112 113 #include <net/if.h> 114 #include <net/if_arp.h> 115 #include <net/ethernet.h> 116 #include <net/if_dl.h> 117 #include <net/if_media.h> 118 119 #include <net/bpf.h> 120 121 #include <machine/bus_memio.h> 122 #include <machine/bus_pio.h> 123 #include <machine/bus.h> 124 #include <machine/resource.h> 125 #include <sys/bus.h> 126 #include <sys/rman.h> 127 128 #include <dev/mii/mii.h> 129 #include <dev/mii/miivar.h> 130 131 #include <dev/pci/pcireg.h> 132 #include <dev/pci/pcivar.h> 133 134 MODULE_DEPEND(xl, pci, 1, 1, 1); 135 MODULE_DEPEND(xl, ether, 1, 1, 1); 136 MODULE_DEPEND(xl, miibus, 1, 1, 1); 137 138 /* "device miibus" required. See GENERIC if you get errors here. */ 139 #include "miibus_if.h" 140 141 #include <pci/if_xlreg.h> 142 143 /* 144 * TX Checksumming is disabled by default for two reasons: 145 * - TX Checksumming will occasionally produce corrupt packets 146 * - TX Checksumming seems to reduce performance 147 * 148 * Only 905B/C cards were reported to have this problem, it is possible 149 * that later chips _may_ be immune. 150 */ 151 #define XL905B_TXCSUM_BROKEN 1 152 153 #ifdef XL905B_TXCSUM_BROKEN 154 #define XL905B_CSUM_FEATURES 0 155 #else 156 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 157 #endif 158 159 /* 160 * Various supported device vendors/types and their names. 161 */ 162 static struct xl_type xl_devs[] = { 163 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 164 "3Com 3c900-TPO Etherlink XL" }, 165 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 166 "3Com 3c900-COMBO Etherlink XL" }, 167 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 168 "3Com 3c905-TX Fast Etherlink XL" }, 169 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 170 "3Com 3c905-T4 Fast Etherlink XL" }, 171 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 172 "3Com 3c900B-TPO Etherlink XL" }, 173 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 174 "3Com 3c900B-COMBO Etherlink XL" }, 175 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 176 "3Com 3c900B-TPC Etherlink XL" }, 177 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 178 "3Com 3c900B-FL Etherlink XL" }, 179 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 180 "3Com 3c905B-TX Fast Etherlink XL" }, 181 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 182 "3Com 3c905B-T4 Fast Etherlink XL" }, 183 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 184 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 185 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 186 "3Com 3c905B-COMBO Fast Etherlink XL" }, 187 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 188 "3Com 3c905C-TX Fast Etherlink XL" }, 189 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 190 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 191 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM, 192 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" }, 193 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 194 "3Com 3c980 Fast Etherlink XL" }, 195 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 196 "3Com 3c980C Fast Etherlink XL" }, 197 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 198 "3Com 3cSOHO100-TX OfficeConnect" }, 199 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 200 "3Com 3c450-TX HomeConnect" }, 201 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 202 "3Com 3c555 Fast Etherlink XL" }, 203 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 204 "3Com 3c556 Fast Etherlink XL" }, 205 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 206 "3Com 3c556B Fast Etherlink XL" }, 207 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 208 "3Com 3c575TX Fast Etherlink XL" }, 209 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 210 "3Com 3c575B Fast Etherlink XL" }, 211 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 212 "3Com 3c575C Fast Etherlink XL" }, 213 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 214 "3Com 3c656 Fast Etherlink XL" }, 215 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 216 "3Com 3c656B Fast Etherlink XL" }, 217 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 218 "3Com 3c656C Fast Etherlink XL" }, 219 { 0, 0, NULL } 220 }; 221 222 static int xl_probe(device_t); 223 static int xl_attach(device_t); 224 static int xl_detach(device_t); 225 226 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *); 227 static void xl_stats_update(void *); 228 static void xl_stats_update_locked(struct xl_softc *); 229 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf *); 230 static void xl_rxeof(struct xl_softc *); 231 static int xl_rx_resync(struct xl_softc *); 232 static void xl_txeof(struct xl_softc *); 233 static void xl_txeof_90xB(struct xl_softc *); 234 static void xl_txeoc(struct xl_softc *); 235 static void xl_intr(void *); 236 static void xl_start(struct ifnet *); 237 static void xl_start_locked(struct ifnet *); 238 static void xl_start_90xB_locked(struct ifnet *); 239 static int xl_ioctl(struct ifnet *, u_long, caddr_t); 240 static void xl_init(void *); 241 static void xl_init_locked(struct xl_softc *); 242 static void xl_stop(struct xl_softc *); 243 static void xl_watchdog(struct ifnet *); 244 static void xl_shutdown(device_t); 245 static int xl_suspend(device_t); 246 static int xl_resume(device_t); 247 248 #ifdef DEVICE_POLLING 249 static void xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 250 static void xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); 251 #endif /* DEVICE_POLLING */ 252 253 static int xl_ifmedia_upd(struct ifnet *); 254 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 255 256 static int xl_eeprom_wait(struct xl_softc *); 257 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int); 258 static void xl_mii_sync(struct xl_softc *); 259 static void xl_mii_send(struct xl_softc *, u_int32_t, int); 260 static int xl_mii_readreg(struct xl_softc *, struct xl_mii_frame *); 261 static int xl_mii_writereg(struct xl_softc *, struct xl_mii_frame *); 262 263 static void xl_setcfg(struct xl_softc *); 264 static void xl_setmode(struct xl_softc *, int); 265 static void xl_setmulti(struct xl_softc *); 266 static void xl_setmulti_hash(struct xl_softc *); 267 static void xl_reset(struct xl_softc *); 268 static int xl_list_rx_init(struct xl_softc *); 269 static int xl_list_tx_init(struct xl_softc *); 270 static int xl_list_tx_init_90xB(struct xl_softc *); 271 static void xl_wait(struct xl_softc *); 272 static void xl_mediacheck(struct xl_softc *); 273 static void xl_choose_media(struct xl_softc *sc, int *media); 274 static void xl_choose_xcvr(struct xl_softc *, int); 275 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int); 276 static void xl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 277 static void xl_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 278 #ifdef notdef 279 static void xl_testpacket(struct xl_softc *); 280 #endif 281 282 static int xl_miibus_readreg(device_t, int, int); 283 static int xl_miibus_writereg(device_t, int, int, int); 284 static void xl_miibus_statchg(device_t); 285 static void xl_miibus_mediainit(device_t); 286 287 static device_method_t xl_methods[] = { 288 /* Device interface */ 289 DEVMETHOD(device_probe, xl_probe), 290 DEVMETHOD(device_attach, xl_attach), 291 DEVMETHOD(device_detach, xl_detach), 292 DEVMETHOD(device_shutdown, xl_shutdown), 293 DEVMETHOD(device_suspend, xl_suspend), 294 DEVMETHOD(device_resume, xl_resume), 295 296 /* bus interface */ 297 DEVMETHOD(bus_print_child, bus_generic_print_child), 298 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 299 300 /* MII interface */ 301 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 302 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 303 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 304 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 305 306 { 0, 0 } 307 }; 308 309 static driver_t xl_driver = { 310 "xl", 311 xl_methods, 312 sizeof(struct xl_softc) 313 }; 314 315 static devclass_t xl_devclass; 316 317 DRIVER_MODULE(xl, cardbus, xl_driver, xl_devclass, 0, 0); 318 DRIVER_MODULE(xl, pci, xl_driver, xl_devclass, 0, 0); 319 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 320 321 static void 322 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 323 { 324 u_int32_t *paddr; 325 326 paddr = arg; 327 *paddr = segs->ds_addr; 328 } 329 330 static void 331 xl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, 332 bus_size_t mapsize, int error) 333 { 334 u_int32_t *paddr; 335 336 if (error) 337 return; 338 339 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments")); 340 paddr = arg; 341 *paddr = segs->ds_addr; 342 } 343 344 static void 345 xl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 346 bus_size_t mapsize, int error) 347 { 348 struct xl_list *l; 349 int i, total_len; 350 351 if (error) 352 return; 353 354 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments")); 355 356 total_len = 0; 357 l = arg; 358 for (i = 0; i < nseg; i++) { 359 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 360 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr); 361 l->xl_frag[i].xl_len = htole32(segs[i].ds_len); 362 total_len += segs[i].ds_len; 363 } 364 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len | 365 XL_LAST_FRAG); 366 l->xl_status = htole32(total_len); 367 l->xl_next = 0; 368 } 369 370 /* 371 * Murphy's law says that it's possible the chip can wedge and 372 * the 'command in progress' bit may never clear. Hence, we wait 373 * only a finite amount of time to avoid getting caught in an 374 * infinite loop. Normally this delay routine would be a macro, 375 * but it isn't called during normal operation so we can afford 376 * to make it a function. 377 */ 378 static void 379 xl_wait(struct xl_softc *sc) 380 { 381 register int i; 382 383 for (i = 0; i < XL_TIMEOUT; i++) { 384 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0) 385 break; 386 } 387 388 if (i == XL_TIMEOUT) 389 if_printf(&sc->arpcom.ac_if, "command never completed!\n"); 390 } 391 392 /* 393 * MII access routines are provided for adapters with external 394 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 395 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 396 * Note: if you don't perform the MDIO operations just right, 397 * it's possible to end up with code that works correctly with 398 * some chips/CPUs/processor speeds/bus speeds/etc but not 399 * with others. 400 */ 401 #define MII_SET(x) \ 402 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 403 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 404 405 #define MII_CLR(x) \ 406 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 407 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 408 409 /* 410 * Sync the PHYs by setting data bit and strobing the clock 32 times. 411 */ 412 static void 413 xl_mii_sync(struct xl_softc *sc) 414 { 415 register int i; 416 417 XL_SEL_WIN(4); 418 MII_SET(XL_MII_DIR|XL_MII_DATA); 419 420 for (i = 0; i < 32; i++) { 421 MII_SET(XL_MII_CLK); 422 MII_SET(XL_MII_DATA); 423 MII_SET(XL_MII_DATA); 424 MII_CLR(XL_MII_CLK); 425 MII_SET(XL_MII_DATA); 426 MII_SET(XL_MII_DATA); 427 } 428 } 429 430 /* 431 * Clock a series of bits through the MII. 432 */ 433 static void 434 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt) 435 { 436 int i; 437 438 XL_SEL_WIN(4); 439 MII_CLR(XL_MII_CLK); 440 441 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 442 if (bits & i) { 443 MII_SET(XL_MII_DATA); 444 } else { 445 MII_CLR(XL_MII_DATA); 446 } 447 MII_CLR(XL_MII_CLK); 448 MII_SET(XL_MII_CLK); 449 } 450 } 451 452 /* 453 * Read an PHY register through the MII. 454 */ 455 static int 456 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame) 457 { 458 int i, ack; 459 460 /*XL_LOCK_ASSERT(sc);*/ 461 462 /* Set up frame for RX. */ 463 frame->mii_stdelim = XL_MII_STARTDELIM; 464 frame->mii_opcode = XL_MII_READOP; 465 frame->mii_turnaround = 0; 466 frame->mii_data = 0; 467 468 /* Select register window 4. */ 469 XL_SEL_WIN(4); 470 471 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 472 /* Turn on data xmit. */ 473 MII_SET(XL_MII_DIR); 474 475 xl_mii_sync(sc); 476 477 /* Send command/address info. */ 478 xl_mii_send(sc, frame->mii_stdelim, 2); 479 xl_mii_send(sc, frame->mii_opcode, 2); 480 xl_mii_send(sc, frame->mii_phyaddr, 5); 481 xl_mii_send(sc, frame->mii_regaddr, 5); 482 483 /* Idle bit */ 484 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 485 MII_SET(XL_MII_CLK); 486 487 /* Turn off xmit. */ 488 MII_CLR(XL_MII_DIR); 489 490 /* Check for ack */ 491 MII_CLR(XL_MII_CLK); 492 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 493 MII_SET(XL_MII_CLK); 494 495 /* 496 * Now try reading data bits. If the ack failed, we still 497 * need to clock through 16 cycles to keep the PHY(s) in sync. 498 */ 499 if (ack) { 500 for (i = 0; i < 16; i++) { 501 MII_CLR(XL_MII_CLK); 502 MII_SET(XL_MII_CLK); 503 } 504 goto fail; 505 } 506 507 for (i = 0x8000; i; i >>= 1) { 508 MII_CLR(XL_MII_CLK); 509 if (!ack) { 510 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 511 frame->mii_data |= i; 512 } 513 MII_SET(XL_MII_CLK); 514 } 515 516 fail: 517 MII_CLR(XL_MII_CLK); 518 MII_SET(XL_MII_CLK); 519 520 return (ack ? 1 : 0); 521 } 522 523 /* 524 * Write to a PHY register through the MII. 525 */ 526 static int 527 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame) 528 { 529 530 /*XL_LOCK_ASSERT(sc);*/ 531 532 /* Set up frame for TX. */ 533 frame->mii_stdelim = XL_MII_STARTDELIM; 534 frame->mii_opcode = XL_MII_WRITEOP; 535 frame->mii_turnaround = XL_MII_TURNAROUND; 536 537 /* Select the window 4. */ 538 XL_SEL_WIN(4); 539 540 /* Turn on data output. */ 541 MII_SET(XL_MII_DIR); 542 543 xl_mii_sync(sc); 544 545 xl_mii_send(sc, frame->mii_stdelim, 2); 546 xl_mii_send(sc, frame->mii_opcode, 2); 547 xl_mii_send(sc, frame->mii_phyaddr, 5); 548 xl_mii_send(sc, frame->mii_regaddr, 5); 549 xl_mii_send(sc, frame->mii_turnaround, 2); 550 xl_mii_send(sc, frame->mii_data, 16); 551 552 /* Idle bit. */ 553 MII_SET(XL_MII_CLK); 554 MII_CLR(XL_MII_CLK); 555 556 /* Turn off xmit. */ 557 MII_CLR(XL_MII_DIR); 558 559 return (0); 560 } 561 562 static int 563 xl_miibus_readreg(device_t dev, int phy, int reg) 564 { 565 struct xl_softc *sc; 566 struct xl_mii_frame frame; 567 568 sc = device_get_softc(dev); 569 570 /* 571 * Pretend that PHYs are only available at MII address 24. 572 * This is to guard against problems with certain 3Com ASIC 573 * revisions that incorrectly map the internal transceiver 574 * control registers at all MII addresses. This can cause 575 * the miibus code to attach the same PHY several times over. 576 */ 577 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24) 578 return (0); 579 580 bzero((char *)&frame, sizeof(frame)); 581 frame.mii_phyaddr = phy; 582 frame.mii_regaddr = reg; 583 584 xl_mii_readreg(sc, &frame); 585 586 return (frame.mii_data); 587 } 588 589 static int 590 xl_miibus_writereg(device_t dev, int phy, int reg, int data) 591 { 592 struct xl_softc *sc; 593 struct xl_mii_frame frame; 594 595 sc = device_get_softc(dev); 596 597 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24) 598 return (0); 599 600 bzero((char *)&frame, sizeof(frame)); 601 frame.mii_phyaddr = phy; 602 frame.mii_regaddr = reg; 603 frame.mii_data = data; 604 605 xl_mii_writereg(sc, &frame); 606 607 return (0); 608 } 609 610 static void 611 xl_miibus_statchg(device_t dev) 612 { 613 struct xl_softc *sc; 614 struct mii_data *mii; 615 616 sc = device_get_softc(dev); 617 mii = device_get_softc(sc->xl_miibus); 618 619 /*XL_LOCK_ASSERT(sc);*/ 620 621 xl_setcfg(sc); 622 623 /* Set ASIC's duplex mode to match the PHY. */ 624 XL_SEL_WIN(3); 625 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 626 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 627 else 628 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 629 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 630 } 631 632 /* 633 * Special support for the 3c905B-COMBO. This card has 10/100 support 634 * plus BNC and AUI ports. This means we will have both an miibus attached 635 * plus some non-MII media settings. In order to allow this, we have to 636 * add the extra media to the miibus's ifmedia struct, but we can't do 637 * that during xl_attach() because the miibus hasn't been attached yet. 638 * So instead, we wait until the miibus probe/attach is done, at which 639 * point we will get a callback telling is that it's safe to add our 640 * extra media. 641 */ 642 static void 643 xl_miibus_mediainit(device_t dev) 644 { 645 struct xl_softc *sc; 646 struct mii_data *mii; 647 struct ifmedia *ifm; 648 649 sc = device_get_softc(dev); 650 mii = device_get_softc(sc->xl_miibus); 651 ifm = &mii->mii_media; 652 653 /*XL_LOCK_ASSERT(sc);*/ 654 655 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) { 656 /* 657 * Check for a 10baseFL board in disguise. 658 */ 659 if (sc->xl_type == XL_TYPE_905B && 660 sc->xl_media == XL_MEDIAOPT_10FL) { 661 if (bootverbose) 662 if_printf(&sc->arpcom.ac_if, 663 "found 10baseFL\n"); 664 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL); 665 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0, 666 NULL); 667 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 668 ifmedia_add(ifm, 669 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL); 670 } else { 671 if (bootverbose) 672 if_printf(&sc->arpcom.ac_if, "found AUI\n"); 673 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL); 674 } 675 } 676 677 if (sc->xl_media & XL_MEDIAOPT_BNC) { 678 if (bootverbose) 679 if_printf(&sc->arpcom.ac_if, "found BNC\n"); 680 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL); 681 } 682 } 683 684 /* 685 * The EEPROM is slow: give it time to come ready after issuing 686 * it a command. 687 */ 688 static int 689 xl_eeprom_wait(struct xl_softc *sc) 690 { 691 int i; 692 693 for (i = 0; i < 100; i++) { 694 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 695 DELAY(162); 696 else 697 break; 698 } 699 700 if (i == 100) { 701 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n"); 702 return (1); 703 } 704 705 return (0); 706 } 707 708 /* 709 * Read a sequence of words from the EEPROM. Note that ethernet address 710 * data is stored in the EEPROM in network byte order. 711 */ 712 static int 713 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 714 { 715 int err = 0, i; 716 u_int16_t word = 0, *ptr; 717 718 XL_LOCK_ASSERT(sc); 719 720 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 721 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 722 /* 723 * XXX: WARNING! DANGER! 724 * It's easy to accidentally overwrite the rom content! 725 * Note: the 3c575 uses 8bit EEPROM offsets. 726 */ 727 XL_SEL_WIN(0); 728 729 if (xl_eeprom_wait(sc)) 730 return (1); 731 732 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 733 off += 0x30; 734 735 for (i = 0; i < cnt; i++) { 736 if (sc->xl_flags & XL_FLAG_8BITROM) 737 CSR_WRITE_2(sc, XL_W0_EE_CMD, 738 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 739 else 740 CSR_WRITE_2(sc, XL_W0_EE_CMD, 741 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 742 err = xl_eeprom_wait(sc); 743 if (err) 744 break; 745 word = CSR_READ_2(sc, XL_W0_EE_DATA); 746 ptr = (u_int16_t *)(dest + (i * 2)); 747 if (swap) 748 *ptr = ntohs(word); 749 else 750 *ptr = word; 751 } 752 753 return (err ? 1 : 0); 754 } 755 756 /* 757 * NICs older than the 3c905B have only one multicast option, which 758 * is to enable reception of all multicast frames. 759 */ 760 static void 761 xl_setmulti(struct xl_softc *sc) 762 { 763 struct ifnet *ifp = &sc->arpcom.ac_if; 764 struct ifmultiaddr *ifma; 765 u_int8_t rxfilt; 766 int mcnt = 0; 767 768 XL_LOCK_ASSERT(sc); 769 770 XL_SEL_WIN(5); 771 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 772 773 if (ifp->if_flags & IFF_ALLMULTI) { 774 rxfilt |= XL_RXFILTER_ALLMULTI; 775 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 776 return; 777 } 778 779 IF_ADDR_LOCK(ifp); 780 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 781 mcnt++; 782 IF_ADDR_UNLOCK(ifp); 783 784 if (mcnt) 785 rxfilt |= XL_RXFILTER_ALLMULTI; 786 else 787 rxfilt &= ~XL_RXFILTER_ALLMULTI; 788 789 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 790 } 791 792 /* 793 * 3c905B adapters have a hash filter that we can program. 794 */ 795 static void 796 xl_setmulti_hash(struct xl_softc *sc) 797 { 798 struct ifnet *ifp = &sc->arpcom.ac_if; 799 int h = 0, i; 800 struct ifmultiaddr *ifma; 801 u_int8_t rxfilt; 802 int mcnt = 0; 803 804 XL_LOCK_ASSERT(sc); 805 806 XL_SEL_WIN(5); 807 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 808 809 if (ifp->if_flags & IFF_ALLMULTI) { 810 rxfilt |= XL_RXFILTER_ALLMULTI; 811 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 812 return; 813 } else 814 rxfilt &= ~XL_RXFILTER_ALLMULTI; 815 816 /* first, zot all the existing hash bits */ 817 for (i = 0; i < XL_HASHFILT_SIZE; i++) 818 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 819 820 /* now program new ones */ 821 IF_ADDR_LOCK(ifp); 822 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 823 if (ifma->ifma_addr->sa_family != AF_LINK) 824 continue; 825 /* 826 * Note: the 3c905B currently only supports a 64-bit hash 827 * table, which means we really only need 6 bits, but the 828 * manual indicates that future chip revisions will have a 829 * 256-bit hash table, hence the routine is set up to 830 * calculate 8 bits of position info in case we need it some 831 * day. 832 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have 833 * a 256 bit hash table. This means we have to use all 8 bits 834 * regardless. On older cards, the upper 2 bits will be 835 * ignored. Grrrr.... 836 */ 837 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 838 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 839 CSR_WRITE_2(sc, XL_COMMAND, 840 h | XL_CMD_RX_SET_HASH | XL_HASH_SET); 841 mcnt++; 842 } 843 IF_ADDR_UNLOCK(ifp); 844 845 if (mcnt) 846 rxfilt |= XL_RXFILTER_MULTIHASH; 847 else 848 rxfilt &= ~XL_RXFILTER_MULTIHASH; 849 850 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 851 } 852 853 #ifdef notdef 854 static void 855 xl_testpacket(struct xl_softc *sc) 856 { 857 struct mbuf *m; 858 struct ifnet *ifp = &sc->arpcom.ac_if; 859 860 MGETHDR(m, M_DONTWAIT, MT_DATA); 861 862 if (m == NULL) 863 return; 864 865 bcopy(&sc->arpcom.ac_enaddr, 866 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 867 bcopy(&sc->arpcom.ac_enaddr, 868 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 869 mtod(m, struct ether_header *)->ether_type = htons(3); 870 mtod(m, unsigned char *)[14] = 0; 871 mtod(m, unsigned char *)[15] = 0; 872 mtod(m, unsigned char *)[16] = 0xE3; 873 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 874 IFQ_ENQUEUE(&ifp->if_snd, m); 875 xl_start(ifp); 876 } 877 #endif 878 879 static void 880 xl_setcfg(struct xl_softc *sc) 881 { 882 u_int32_t icfg; 883 884 /*XL_LOCK_ASSERT(sc);*/ 885 886 XL_SEL_WIN(3); 887 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 888 icfg &= ~XL_ICFG_CONNECTOR_MASK; 889 if (sc->xl_media & XL_MEDIAOPT_MII || 890 sc->xl_media & XL_MEDIAOPT_BT4) 891 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 892 if (sc->xl_media & XL_MEDIAOPT_BTX) 893 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 894 895 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 896 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 897 } 898 899 static void 900 xl_setmode(struct xl_softc *sc, int media) 901 { 902 u_int32_t icfg; 903 u_int16_t mediastat; 904 char *pmsg = "", *dmsg = ""; 905 906 /*XL_LOCK_ASSERT(sc);*/ 907 908 XL_SEL_WIN(4); 909 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 910 XL_SEL_WIN(3); 911 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 912 913 if (sc->xl_media & XL_MEDIAOPT_BT) { 914 if (IFM_SUBTYPE(media) == IFM_10_T) { 915 pmsg = "10baseT transceiver"; 916 sc->xl_xcvr = XL_XCVR_10BT; 917 icfg &= ~XL_ICFG_CONNECTOR_MASK; 918 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 919 mediastat |= XL_MEDIASTAT_LINKBEAT | 920 XL_MEDIASTAT_JABGUARD; 921 mediastat &= ~XL_MEDIASTAT_SQEENB; 922 } 923 } 924 925 if (sc->xl_media & XL_MEDIAOPT_BFX) { 926 if (IFM_SUBTYPE(media) == IFM_100_FX) { 927 pmsg = "100baseFX port"; 928 sc->xl_xcvr = XL_XCVR_100BFX; 929 icfg &= ~XL_ICFG_CONNECTOR_MASK; 930 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 931 mediastat |= XL_MEDIASTAT_LINKBEAT; 932 mediastat &= ~XL_MEDIASTAT_SQEENB; 933 } 934 } 935 936 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 937 if (IFM_SUBTYPE(media) == IFM_10_5) { 938 pmsg = "AUI port"; 939 sc->xl_xcvr = XL_XCVR_AUI; 940 icfg &= ~XL_ICFG_CONNECTOR_MASK; 941 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 942 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 943 XL_MEDIASTAT_JABGUARD); 944 mediastat |= ~XL_MEDIASTAT_SQEENB; 945 } 946 if (IFM_SUBTYPE(media) == IFM_10_FL) { 947 pmsg = "10baseFL transceiver"; 948 sc->xl_xcvr = XL_XCVR_AUI; 949 icfg &= ~XL_ICFG_CONNECTOR_MASK; 950 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 951 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 952 XL_MEDIASTAT_JABGUARD); 953 mediastat |= ~XL_MEDIASTAT_SQEENB; 954 } 955 } 956 957 if (sc->xl_media & XL_MEDIAOPT_BNC) { 958 if (IFM_SUBTYPE(media) == IFM_10_2) { 959 pmsg = "AUI port"; 960 sc->xl_xcvr = XL_XCVR_COAX; 961 icfg &= ~XL_ICFG_CONNECTOR_MASK; 962 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 963 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 964 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB); 965 } 966 } 967 968 if ((media & IFM_GMASK) == IFM_FDX || 969 IFM_SUBTYPE(media) == IFM_100_FX) { 970 dmsg = "full"; 971 XL_SEL_WIN(3); 972 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 973 } else { 974 dmsg = "half"; 975 XL_SEL_WIN(3); 976 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 977 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 978 } 979 980 if (IFM_SUBTYPE(media) == IFM_10_2) 981 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 982 else 983 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 984 985 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 986 XL_SEL_WIN(4); 987 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 988 989 DELAY(800); 990 XL_SEL_WIN(7); 991 992 if_printf(&sc->arpcom.ac_if, "selecting %s, %s duplex\n", pmsg, dmsg); 993 } 994 995 static void 996 xl_reset(struct xl_softc *sc) 997 { 998 register int i; 999 1000 XL_LOCK_ASSERT(sc); 1001 1002 XL_SEL_WIN(0); 1003 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 1004 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 1005 XL_RESETOPT_DISADVFD:0)); 1006 1007 /* 1008 * If we're using memory mapped register mode, pause briefly 1009 * after issuing the reset command before trying to access any 1010 * other registers. With my 3c575C cardbus card, failing to do 1011 * this results in the system locking up while trying to poll 1012 * the command busy bit in the status register. 1013 */ 1014 if (sc->xl_flags & XL_FLAG_USE_MMIO) 1015 DELAY(100000); 1016 1017 for (i = 0; i < XL_TIMEOUT; i++) { 1018 DELAY(10); 1019 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 1020 break; 1021 } 1022 1023 if (i == XL_TIMEOUT) 1024 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n"); 1025 1026 /* Reset TX and RX. */ 1027 /* Note: the RX reset takes an absurd amount of time 1028 * on newer versions of the Tornado chips such as those 1029 * on the 3c905CX and newer 3c908C cards. We wait an 1030 * extra amount of time so that xl_wait() doesn't complain 1031 * and annoy the users. 1032 */ 1033 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 1034 DELAY(100000); 1035 xl_wait(sc); 1036 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 1037 xl_wait(sc); 1038 1039 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 1040 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 1041 XL_SEL_WIN(2); 1042 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, 1043 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) | 1044 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ? 1045 XL_RESETOPT_INVERT_LED : 0) | 1046 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ? 1047 XL_RESETOPT_INVERT_MII : 0)); 1048 } 1049 1050 /* Wait a little while for the chip to get its brains in order. */ 1051 DELAY(100000); 1052 } 1053 1054 /* 1055 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1056 * IDs against our list and return a device name if we find a match. 1057 */ 1058 static int 1059 xl_probe(device_t dev) 1060 { 1061 struct xl_type *t; 1062 1063 t = xl_devs; 1064 1065 while (t->xl_name != NULL) { 1066 if ((pci_get_vendor(dev) == t->xl_vid) && 1067 (pci_get_device(dev) == t->xl_did)) { 1068 device_set_desc(dev, t->xl_name); 1069 return (BUS_PROBE_DEFAULT); 1070 } 1071 t++; 1072 } 1073 1074 return (ENXIO); 1075 } 1076 1077 /* 1078 * This routine is a kludge to work around possible hardware faults 1079 * or manufacturing defects that can cause the media options register 1080 * (or reset options register, as it's called for the first generation 1081 * 3c90x adapters) to return an incorrect result. I have encountered 1082 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1083 * which doesn't have any of the 'mediaopt' bits set. This screws up 1084 * the attach routine pretty badly because it doesn't know what media 1085 * to look for. If we find ourselves in this predicament, this routine 1086 * will try to guess the media options values and warn the user of a 1087 * possible manufacturing defect with his adapter/system/whatever. 1088 */ 1089 static void 1090 xl_mediacheck(struct xl_softc *sc) 1091 { 1092 1093 XL_LOCK_ASSERT(sc); 1094 1095 /* 1096 * If some of the media options bits are set, assume they are 1097 * correct. If not, try to figure it out down below. 1098 * XXX I should check for 10baseFL, but I don't have an adapter 1099 * to test with. 1100 */ 1101 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1102 /* 1103 * Check the XCVR value. If it's not in the normal range 1104 * of values, we need to fake it up here. 1105 */ 1106 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1107 return; 1108 else { 1109 if_printf(&sc->arpcom.ac_if, 1110 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr); 1111 if_printf(&sc->arpcom.ac_if, 1112 "choosing new default based on card type\n"); 1113 } 1114 } else { 1115 if (sc->xl_type == XL_TYPE_905B && 1116 sc->xl_media & XL_MEDIAOPT_10FL) 1117 return; 1118 if_printf(&sc->arpcom.ac_if, 1119 "WARNING: no media options bits set in the media options register!!\n"); 1120 if_printf(&sc->arpcom.ac_if, 1121 "this could be a manufacturing defect in your adapter or system\n"); 1122 if_printf(&sc->arpcom.ac_if, 1123 "attempting to guess media type; you should probably consult your vendor\n"); 1124 } 1125 1126 xl_choose_xcvr(sc, 1); 1127 } 1128 1129 static void 1130 xl_choose_xcvr(struct xl_softc *sc, int verbose) 1131 { 1132 u_int16_t devid; 1133 1134 /* 1135 * Read the device ID from the EEPROM. 1136 * This is what's loaded into the PCI device ID register, so it has 1137 * to be correct otherwise we wouldn't have gotten this far. 1138 */ 1139 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1140 1141 switch (devid) { 1142 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1143 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1144 sc->xl_media = XL_MEDIAOPT_BT; 1145 sc->xl_xcvr = XL_XCVR_10BT; 1146 if (verbose) 1147 if_printf(&sc->arpcom.ac_if, 1148 "guessing 10BaseT transceiver\n"); 1149 break; 1150 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1151 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1152 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1153 sc->xl_xcvr = XL_XCVR_10BT; 1154 if (verbose) 1155 if_printf(&sc->arpcom.ac_if, 1156 "guessing COMBO (AUI/BNC/TP)\n"); 1157 break; 1158 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1159 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1160 sc->xl_xcvr = XL_XCVR_10BT; 1161 if (verbose) 1162 if_printf(&sc->arpcom.ac_if, "guessing TPC (BNC/TP)\n"); 1163 break; 1164 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1165 sc->xl_media = XL_MEDIAOPT_10FL; 1166 sc->xl_xcvr = XL_XCVR_AUI; 1167 if (verbose) 1168 if_printf(&sc->arpcom.ac_if, "guessing 10baseFL\n"); 1169 break; 1170 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1171 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1172 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1173 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1174 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1175 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1176 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1177 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1178 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1179 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1180 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1181 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */ 1182 sc->xl_media = XL_MEDIAOPT_MII; 1183 sc->xl_xcvr = XL_XCVR_MII; 1184 if (verbose) 1185 if_printf(&sc->arpcom.ac_if, "guessing MII\n"); 1186 break; 1187 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1188 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1189 sc->xl_media = XL_MEDIAOPT_BT4; 1190 sc->xl_xcvr = XL_XCVR_MII; 1191 if (verbose) 1192 if_printf(&sc->arpcom.ac_if, 1193 "guessing 100baseT4/MII\n"); 1194 break; 1195 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1196 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1197 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1198 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1199 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1200 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1201 sc->xl_media = XL_MEDIAOPT_BTX; 1202 sc->xl_xcvr = XL_XCVR_AUTO; 1203 if (verbose) 1204 if_printf(&sc->arpcom.ac_if, 1205 "guessing 10/100 internal\n"); 1206 break; 1207 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1208 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1209 sc->xl_xcvr = XL_XCVR_AUTO; 1210 if (verbose) 1211 if_printf(&sc->arpcom.ac_if, 1212 "guessing 10/100 plus BNC/AUI\n"); 1213 break; 1214 default: 1215 if_printf(&sc->arpcom.ac_if, 1216 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1217 sc->xl_media = XL_MEDIAOPT_BT; 1218 break; 1219 } 1220 } 1221 1222 /* 1223 * Attach the interface. Allocate softc structures, do ifmedia 1224 * setup and ethernet/BPF attach. 1225 */ 1226 static int 1227 xl_attach(device_t dev) 1228 { 1229 u_char eaddr[ETHER_ADDR_LEN]; 1230 u_int16_t xcvr[2]; 1231 struct xl_softc *sc; 1232 struct ifnet *ifp; 1233 int media; 1234 int unit, error = 0, rid, res; 1235 uint16_t did; 1236 1237 sc = device_get_softc(dev); 1238 unit = device_get_unit(dev); 1239 1240 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1241 MTX_DEF); 1242 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1243 1244 did = pci_get_device(dev); 1245 1246 sc->xl_flags = 0; 1247 if (did == TC_DEVICEID_HURRICANE_555) 1248 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1249 if (did == TC_DEVICEID_HURRICANE_556 || 1250 did == TC_DEVICEID_HURRICANE_556B) 1251 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1252 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1253 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1254 if (did == TC_DEVICEID_HURRICANE_555 || 1255 did == TC_DEVICEID_HURRICANE_556) 1256 sc->xl_flags |= XL_FLAG_8BITROM; 1257 if (did == TC_DEVICEID_HURRICANE_556B) 1258 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1259 1260 if (did == TC_DEVICEID_HURRICANE_575A || 1261 did == TC_DEVICEID_HURRICANE_575B || 1262 did == TC_DEVICEID_HURRICANE_575C || 1263 did == TC_DEVICEID_HURRICANE_656B || 1264 did == TC_DEVICEID_TORNADO_656C) 1265 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1266 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM; 1267 if (did == TC_DEVICEID_HURRICANE_656) 1268 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1269 if (did == TC_DEVICEID_HURRICANE_575B) 1270 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1271 if (did == TC_DEVICEID_HURRICANE_575C) 1272 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1273 if (did == TC_DEVICEID_TORNADO_656C) 1274 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1275 if (did == TC_DEVICEID_HURRICANE_656 || 1276 did == TC_DEVICEID_HURRICANE_656B) 1277 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1278 XL_FLAG_INVERT_LED_PWR; 1279 if (did == TC_DEVICEID_TORNADO_10_100BT_920B || 1280 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM) 1281 sc->xl_flags |= XL_FLAG_PHYOK; 1282 1283 switch (did) { 1284 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1285 case TC_DEVICEID_HURRICANE_575A: 1286 case TC_DEVICEID_HURRICANE_575B: 1287 case TC_DEVICEID_HURRICANE_575C: 1288 sc->xl_flags |= XL_FLAG_NO_MMIO; 1289 break; 1290 default: 1291 break; 1292 } 1293 1294 /* 1295 * Map control/status registers. 1296 */ 1297 pci_enable_busmaster(dev); 1298 1299 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) { 1300 rid = XL_PCI_LOMEM; 1301 res = SYS_RES_MEMORY; 1302 1303 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1304 } 1305 1306 if (sc->xl_res != NULL) { 1307 sc->xl_flags |= XL_FLAG_USE_MMIO; 1308 if (bootverbose) 1309 device_printf(dev, "using memory mapped I/O\n"); 1310 } else { 1311 rid = XL_PCI_LOIO; 1312 res = SYS_RES_IOPORT; 1313 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1314 if (sc->xl_res == NULL) { 1315 device_printf(dev, "couldn't map ports/memory\n"); 1316 error = ENXIO; 1317 goto fail; 1318 } 1319 if (bootverbose) 1320 device_printf(dev, "using port I/O\n"); 1321 } 1322 1323 sc->xl_btag = rman_get_bustag(sc->xl_res); 1324 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1325 1326 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1327 rid = XL_PCI_FUNCMEM; 1328 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1329 RF_ACTIVE); 1330 1331 if (sc->xl_fres == NULL) { 1332 device_printf(dev, "couldn't map ports/memory\n"); 1333 error = ENXIO; 1334 goto fail; 1335 } 1336 1337 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1338 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1339 } 1340 1341 /* Allocate interrupt */ 1342 rid = 0; 1343 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1344 RF_SHAREABLE | RF_ACTIVE); 1345 if (sc->xl_irq == NULL) { 1346 device_printf(dev, "couldn't map interrupt\n"); 1347 error = ENXIO; 1348 goto fail; 1349 } 1350 1351 /* Initialize interface name. */ 1352 ifp = &sc->arpcom.ac_if; 1353 ifp->if_softc = sc; 1354 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1355 1356 XL_LOCK(sc); 1357 1358 /* Reset the adapter. */ 1359 xl_reset(sc); 1360 1361 /* 1362 * Get station address from the EEPROM. 1363 */ 1364 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1365 device_printf(dev, "failed to read station address\n"); 1366 error = ENXIO; 1367 XL_UNLOCK(sc); 1368 goto fail; 1369 } 1370 1371 XL_UNLOCK(sc); 1372 1373 sc->xl_unit = unit; 1374 callout_handle_init(&sc->xl_stat_ch); 1375 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1376 1377 /* 1378 * Now allocate a tag for the DMA descriptor lists and a chunk 1379 * of DMA-able memory based on the tag. Also obtain the DMA 1380 * addresses of the RX and TX ring, which we'll need later. 1381 * All of our lists are allocated as a contiguous block 1382 * of memory. 1383 */ 1384 error = bus_dma_tag_create(NULL, 8, 0, 1385 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1386 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL, 1387 &sc->xl_ldata.xl_rx_tag); 1388 if (error) { 1389 device_printf(dev, "failed to allocate rx dma tag\n"); 1390 goto fail; 1391 } 1392 1393 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1394 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1395 &sc->xl_ldata.xl_rx_dmamap); 1396 if (error) { 1397 device_printf(dev, "no memory for rx list buffers!\n"); 1398 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1399 sc->xl_ldata.xl_rx_tag = NULL; 1400 goto fail; 1401 } 1402 1403 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1404 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1405 XL_RX_LIST_SZ, xl_dma_map_addr, 1406 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1407 if (error) { 1408 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1409 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1410 sc->xl_ldata.xl_rx_dmamap); 1411 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1412 sc->xl_ldata.xl_rx_tag = NULL; 1413 goto fail; 1414 } 1415 1416 error = bus_dma_tag_create(NULL, 8, 0, 1417 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1418 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL, 1419 &sc->xl_ldata.xl_tx_tag); 1420 if (error) { 1421 device_printf(dev, "failed to allocate tx dma tag\n"); 1422 goto fail; 1423 } 1424 1425 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1426 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1427 &sc->xl_ldata.xl_tx_dmamap); 1428 if (error) { 1429 device_printf(dev, "no memory for list buffers!\n"); 1430 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1431 sc->xl_ldata.xl_tx_tag = NULL; 1432 goto fail; 1433 } 1434 1435 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1436 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1437 XL_TX_LIST_SZ, xl_dma_map_addr, 1438 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1439 if (error) { 1440 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1441 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1442 sc->xl_ldata.xl_tx_dmamap); 1443 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1444 sc->xl_ldata.xl_tx_tag = NULL; 1445 goto fail; 1446 } 1447 1448 /* 1449 * Allocate a DMA tag for the mapping of mbufs. 1450 */ 1451 error = bus_dma_tag_create(NULL, 1, 0, 1452 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1453 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL, 1454 NULL, &sc->xl_mtag); 1455 if (error) { 1456 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1457 goto fail; 1458 } 1459 1460 /* We need a spare DMA map for the RX ring. */ 1461 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1462 if (error) 1463 goto fail; 1464 1465 XL_LOCK(sc); 1466 1467 /* 1468 * Figure out the card type. 3c905B adapters have the 1469 * 'supportsNoTxLength' bit set in the capabilities 1470 * word in the EEPROM. 1471 * Note: my 3c575C cardbus card lies. It returns a value 1472 * of 0x1578 for its capabilities word, which is somewhat 1473 * nonsensical. Another way to distinguish a 3c90x chip 1474 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1475 * bit. This will only be set for 3c90x boomerage chips. 1476 */ 1477 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1478 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1479 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1480 sc->xl_type = XL_TYPE_905B; 1481 else 1482 sc->xl_type = XL_TYPE_90X; 1483 1484 ifp->if_mtu = ETHERMTU; 1485 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1486 ifp->if_ioctl = xl_ioctl; 1487 ifp->if_capabilities = IFCAP_VLAN_MTU; 1488 if (sc->xl_type == XL_TYPE_905B) { 1489 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1490 #ifdef XL905B_TXCSUM_BROKEN 1491 ifp->if_capabilities |= IFCAP_RXCSUM; 1492 #else 1493 ifp->if_capabilities |= IFCAP_HWCSUM; 1494 #endif 1495 } 1496 #ifdef DEVICE_POLLING 1497 ifp->if_capabilities |= IFCAP_POLLING; 1498 #endif /* DEVICE_POLLING */ 1499 ifp->if_start = xl_start; 1500 ifp->if_watchdog = xl_watchdog; 1501 ifp->if_init = xl_init; 1502 ifp->if_baudrate = 10000000; 1503 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1504 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1; 1505 IFQ_SET_READY(&ifp->if_snd); 1506 ifp->if_capenable = ifp->if_capabilities; 1507 1508 /* 1509 * Now we have to see what sort of media we have. 1510 * This includes probing for an MII interace and a 1511 * possible PHY. 1512 */ 1513 XL_SEL_WIN(3); 1514 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1515 if (bootverbose) 1516 device_printf(dev, "media options word: %x\n", sc->xl_media); 1517 1518 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1519 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1520 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1521 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1522 1523 xl_mediacheck(sc); 1524 1525 /* XXX Downcalls to ifmedia, miibus about to happen. */ 1526 XL_UNLOCK(sc); 1527 1528 if (sc->xl_media & XL_MEDIAOPT_MII || 1529 sc->xl_media & XL_MEDIAOPT_BTX || 1530 sc->xl_media & XL_MEDIAOPT_BT4) { 1531 if (bootverbose) 1532 device_printf(dev, "found MII/AUTO\n"); 1533 xl_setcfg(sc); 1534 if (mii_phy_probe(dev, &sc->xl_miibus, 1535 xl_ifmedia_upd, xl_ifmedia_sts)) { 1536 device_printf(dev, "no PHY found!\n"); 1537 error = ENXIO; 1538 goto fail; 1539 } 1540 goto done; 1541 } 1542 1543 /* 1544 * Sanity check. If the user has selected "auto" and this isn't 1545 * a 10/100 card of some kind, we need to force the transceiver 1546 * type to something sane. 1547 */ 1548 if (sc->xl_xcvr == XL_XCVR_AUTO) { 1549 /* XXX Direct hardware access needs lock coverage. */ 1550 XL_LOCK(sc); 1551 xl_choose_xcvr(sc, bootverbose); 1552 XL_UNLOCK(sc); 1553 } 1554 1555 /* 1556 * Do ifmedia setup. 1557 */ 1558 if (sc->xl_media & XL_MEDIAOPT_BT) { 1559 if (bootverbose) 1560 device_printf(dev, "found 10baseT\n"); 1561 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1562 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1563 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1564 ifmedia_add(&sc->ifmedia, 1565 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1566 } 1567 1568 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1569 /* 1570 * Check for a 10baseFL board in disguise. 1571 */ 1572 if (sc->xl_type == XL_TYPE_905B && 1573 sc->xl_media == XL_MEDIAOPT_10FL) { 1574 if (bootverbose) 1575 device_printf(dev, "found 10baseFL\n"); 1576 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1577 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1578 0, NULL); 1579 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1580 ifmedia_add(&sc->ifmedia, 1581 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1582 } else { 1583 if (bootverbose) 1584 device_printf(dev, "found AUI\n"); 1585 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1586 } 1587 } 1588 1589 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1590 if (bootverbose) 1591 device_printf(dev, "found BNC\n"); 1592 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1593 } 1594 1595 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1596 if (bootverbose) 1597 device_printf(dev, "found 100baseFX\n"); 1598 ifp->if_baudrate = 100000000; 1599 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1600 } 1601 1602 /* XXX: Unlocked, leaf will take lock. */ 1603 media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1604 xl_choose_media(sc, &media); 1605 1606 if (sc->xl_miibus == NULL) 1607 ifmedia_set(&sc->ifmedia, media); 1608 1609 done: 1610 /* XXX: Unlocked hardware access, narrow race. */ 1611 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1612 XL_SEL_WIN(0); 1613 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1614 } 1615 1616 /* 1617 * Call MI attach routine. 1618 */ 1619 ether_ifattach(ifp, eaddr); 1620 1621 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1622 xl_intr, sc, &sc->xl_intrhand); 1623 if (error) { 1624 device_printf(dev, "couldn't set up irq\n"); 1625 ether_ifdetach(ifp); 1626 goto fail; 1627 } 1628 1629 fail: 1630 if (error) 1631 xl_detach(dev); 1632 1633 return (error); 1634 } 1635 1636 /* 1637 * Choose a default media. 1638 * XXX This is a leaf function only called by xl_attach() and 1639 * acquires/releases the non-recursible driver mutex. 1640 */ 1641 static void 1642 xl_choose_media(struct xl_softc *sc, int *media) 1643 { 1644 1645 XL_LOCK(sc); 1646 1647 switch (sc->xl_xcvr) { 1648 case XL_XCVR_10BT: 1649 *media = IFM_ETHER|IFM_10_T; 1650 xl_setmode(sc, *media); 1651 break; 1652 case XL_XCVR_AUI: 1653 if (sc->xl_type == XL_TYPE_905B && 1654 sc->xl_media == XL_MEDIAOPT_10FL) { 1655 *media = IFM_ETHER|IFM_10_FL; 1656 xl_setmode(sc, *media); 1657 } else { 1658 *media = IFM_ETHER|IFM_10_5; 1659 xl_setmode(sc, *media); 1660 } 1661 break; 1662 case XL_XCVR_COAX: 1663 *media = IFM_ETHER|IFM_10_2; 1664 xl_setmode(sc, *media); 1665 break; 1666 case XL_XCVR_AUTO: 1667 case XL_XCVR_100BTX: 1668 case XL_XCVR_MII: 1669 /* Chosen by miibus */ 1670 break; 1671 case XL_XCVR_100BFX: 1672 *media = IFM_ETHER|IFM_100_FX; 1673 break; 1674 default: 1675 if_printf(&sc->arpcom.ac_if, "unknown XCVR type: %d\n", 1676 sc->xl_xcvr); 1677 /* 1678 * This will probably be wrong, but it prevents 1679 * the ifmedia code from panicking. 1680 */ 1681 *media = IFM_ETHER|IFM_10_T; 1682 break; 1683 } 1684 1685 XL_UNLOCK(sc); 1686 } 1687 1688 /* 1689 * Shutdown hardware and free up resources. This can be called any 1690 * time after the mutex has been initialized. It is called in both 1691 * the error case in attach and the normal detach case so it needs 1692 * to be careful about only freeing resources that have actually been 1693 * allocated. 1694 */ 1695 static int 1696 xl_detach(device_t dev) 1697 { 1698 struct xl_softc *sc; 1699 struct ifnet *ifp; 1700 int rid, res; 1701 1702 sc = device_get_softc(dev); 1703 ifp = &sc->arpcom.ac_if; 1704 1705 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized")); 1706 XL_LOCK(sc); 1707 1708 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1709 rid = XL_PCI_LOMEM; 1710 res = SYS_RES_MEMORY; 1711 } else { 1712 rid = XL_PCI_LOIO; 1713 res = SYS_RES_IOPORT; 1714 } 1715 1716 /* These should only be active if attach succeeded */ 1717 if (device_is_attached(dev)) { 1718 xl_reset(sc); 1719 xl_stop(sc); 1720 ether_ifdetach(ifp); 1721 } 1722 if (sc->xl_miibus) 1723 device_delete_child(dev, sc->xl_miibus); 1724 bus_generic_detach(dev); 1725 ifmedia_removeall(&sc->ifmedia); 1726 1727 if (sc->xl_intrhand) 1728 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1729 if (sc->xl_irq) 1730 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1731 if (sc->xl_fres != NULL) 1732 bus_release_resource(dev, SYS_RES_MEMORY, 1733 XL_PCI_FUNCMEM, sc->xl_fres); 1734 if (sc->xl_res) 1735 bus_release_resource(dev, res, rid, sc->xl_res); 1736 1737 if (sc->xl_mtag) { 1738 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1739 bus_dma_tag_destroy(sc->xl_mtag); 1740 } 1741 if (sc->xl_ldata.xl_rx_tag) { 1742 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1743 sc->xl_ldata.xl_rx_dmamap); 1744 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1745 sc->xl_ldata.xl_rx_dmamap); 1746 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1747 } 1748 if (sc->xl_ldata.xl_tx_tag) { 1749 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1750 sc->xl_ldata.xl_tx_dmamap); 1751 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1752 sc->xl_ldata.xl_tx_dmamap); 1753 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1754 } 1755 1756 XL_UNLOCK(sc); 1757 mtx_destroy(&sc->xl_mtx); 1758 1759 return (0); 1760 } 1761 1762 /* 1763 * Initialize the transmit descriptors. 1764 */ 1765 static int 1766 xl_list_tx_init(struct xl_softc *sc) 1767 { 1768 struct xl_chain_data *cd; 1769 struct xl_list_data *ld; 1770 int error, i; 1771 1772 XL_LOCK_ASSERT(sc); 1773 1774 cd = &sc->xl_cdata; 1775 ld = &sc->xl_ldata; 1776 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1777 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1778 error = bus_dmamap_create(sc->xl_mtag, 0, 1779 &cd->xl_tx_chain[i].xl_map); 1780 if (error) 1781 return (error); 1782 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1783 i * sizeof(struct xl_list); 1784 if (i == (XL_TX_LIST_CNT - 1)) 1785 cd->xl_tx_chain[i].xl_next = NULL; 1786 else 1787 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1788 } 1789 1790 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1791 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1792 1793 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1794 return (0); 1795 } 1796 1797 /* 1798 * Initialize the transmit descriptors. 1799 */ 1800 static int 1801 xl_list_tx_init_90xB(struct xl_softc *sc) 1802 { 1803 struct xl_chain_data *cd; 1804 struct xl_list_data *ld; 1805 int error, i; 1806 1807 XL_LOCK_ASSERT(sc); 1808 1809 cd = &sc->xl_cdata; 1810 ld = &sc->xl_ldata; 1811 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1812 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1813 error = bus_dmamap_create(sc->xl_mtag, 0, 1814 &cd->xl_tx_chain[i].xl_map); 1815 if (error) 1816 return (error); 1817 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1818 i * sizeof(struct xl_list); 1819 if (i == (XL_TX_LIST_CNT - 1)) 1820 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1821 else 1822 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1823 if (i == 0) 1824 cd->xl_tx_chain[i].xl_prev = 1825 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1826 else 1827 cd->xl_tx_chain[i].xl_prev = 1828 &cd->xl_tx_chain[i - 1]; 1829 } 1830 1831 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1832 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1833 1834 cd->xl_tx_prod = 1; 1835 cd->xl_tx_cons = 1; 1836 cd->xl_tx_cnt = 0; 1837 1838 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1839 return (0); 1840 } 1841 1842 /* 1843 * Initialize the RX descriptors and allocate mbufs for them. Note that 1844 * we arrange the descriptors in a closed ring, so that the last descriptor 1845 * points back to the first. 1846 */ 1847 static int 1848 xl_list_rx_init(struct xl_softc *sc) 1849 { 1850 struct xl_chain_data *cd; 1851 struct xl_list_data *ld; 1852 int error, i, next; 1853 u_int32_t nextptr; 1854 1855 XL_LOCK_ASSERT(sc); 1856 1857 cd = &sc->xl_cdata; 1858 ld = &sc->xl_ldata; 1859 1860 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1861 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1862 error = bus_dmamap_create(sc->xl_mtag, 0, 1863 &cd->xl_rx_chain[i].xl_map); 1864 if (error) 1865 return (error); 1866 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1867 if (error) 1868 return (error); 1869 if (i == (XL_RX_LIST_CNT - 1)) 1870 next = 0; 1871 else 1872 next = i + 1; 1873 nextptr = ld->xl_rx_dmaaddr + 1874 next * sizeof(struct xl_list_onefrag); 1875 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1876 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1877 } 1878 1879 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1880 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1881 1882 return (0); 1883 } 1884 1885 /* 1886 * Initialize an RX descriptor and attach an MBUF cluster. 1887 * If we fail to do so, we need to leave the old mbuf and 1888 * the old DMA map untouched so that it can be reused. 1889 */ 1890 static int 1891 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) 1892 { 1893 struct mbuf *m_new = NULL; 1894 bus_dmamap_t map; 1895 int error; 1896 u_int32_t baddr; 1897 1898 XL_LOCK_ASSERT(sc); 1899 1900 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1901 if (m_new == NULL) 1902 return (ENOBUFS); 1903 1904 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1905 1906 /* Force longword alignment for packet payload. */ 1907 m_adj(m_new, ETHER_ALIGN); 1908 1909 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new, 1910 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT); 1911 if (error) { 1912 m_freem(m_new); 1913 if_printf(&sc->arpcom.ac_if, "can't map mbuf (error %d)\n", 1914 error); 1915 return (error); 1916 } 1917 1918 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1919 map = c->xl_map; 1920 c->xl_map = sc->xl_tmpmap; 1921 sc->xl_tmpmap = map; 1922 c->xl_mbuf = m_new; 1923 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 1924 c->xl_ptr->xl_status = 0; 1925 c->xl_ptr->xl_frag.xl_addr = htole32(baddr); 1926 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 1927 return (0); 1928 } 1929 1930 static int 1931 xl_rx_resync(struct xl_softc *sc) 1932 { 1933 struct xl_chain_onefrag *pos; 1934 int i; 1935 1936 XL_LOCK_ASSERT(sc); 1937 1938 pos = sc->xl_cdata.xl_rx_head; 1939 1940 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1941 if (pos->xl_ptr->xl_status) 1942 break; 1943 pos = pos->xl_next; 1944 } 1945 1946 if (i == XL_RX_LIST_CNT) 1947 return (0); 1948 1949 sc->xl_cdata.xl_rx_head = pos; 1950 1951 return (EAGAIN); 1952 } 1953 1954 /* 1955 * A frame has been uploaded: pass the resulting mbuf chain up to 1956 * the higher level protocols. 1957 */ 1958 static void 1959 xl_rxeof(struct xl_softc *sc) 1960 { 1961 struct mbuf *m; 1962 struct ifnet *ifp = &sc->arpcom.ac_if; 1963 struct xl_chain_onefrag *cur_rx; 1964 int total_len = 0; 1965 u_int32_t rxstat; 1966 1967 XL_LOCK_ASSERT(sc); 1968 again: 1969 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 1970 BUS_DMASYNC_POSTREAD); 1971 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 1972 #ifdef DEVICE_POLLING 1973 if (ifp->if_flags & IFF_POLLING) { 1974 if (sc->rxcycles <= 0) 1975 break; 1976 sc->rxcycles--; 1977 } 1978 #endif /* DEVICE_POLLING */ 1979 cur_rx = sc->xl_cdata.xl_rx_head; 1980 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1981 total_len = rxstat & XL_RXSTAT_LENMASK; 1982 1983 /* 1984 * Since we have told the chip to allow large frames, 1985 * we need to trap giant frame errors in software. We allow 1986 * a little more than the normal frame size to account for 1987 * frames with VLAN tags. 1988 */ 1989 if (total_len > XL_MAX_FRAMELEN) 1990 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 1991 1992 /* 1993 * If an error occurs, update stats, clear the 1994 * status word and leave the mbuf cluster in place: 1995 * it should simply get re-used next time this descriptor 1996 * comes up in the ring. 1997 */ 1998 if (rxstat & XL_RXSTAT_UP_ERROR) { 1999 ifp->if_ierrors++; 2000 cur_rx->xl_ptr->xl_status = 0; 2001 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2002 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2003 continue; 2004 } 2005 2006 /* 2007 * If the error bit was not set, the upload complete 2008 * bit should be set which means we have a valid packet. 2009 * If not, something truly strange has happened. 2010 */ 2011 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 2012 if_printf(ifp, 2013 "bad receive status -- packet dropped\n"); 2014 ifp->if_ierrors++; 2015 cur_rx->xl_ptr->xl_status = 0; 2016 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2017 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2018 continue; 2019 } 2020 2021 /* No errors; receive the packet. */ 2022 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 2023 BUS_DMASYNC_POSTREAD); 2024 m = cur_rx->xl_mbuf; 2025 2026 /* 2027 * Try to conjure up a new mbuf cluster. If that 2028 * fails, it means we have an out of memory condition and 2029 * should leave the buffer in place and continue. This will 2030 * result in a lost packet, but there's little else we 2031 * can do in this situation. 2032 */ 2033 if (xl_newbuf(sc, cur_rx)) { 2034 ifp->if_ierrors++; 2035 cur_rx->xl_ptr->xl_status = 0; 2036 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2037 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2038 continue; 2039 } 2040 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2041 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2042 2043 ifp->if_ipackets++; 2044 m->m_pkthdr.rcvif = ifp; 2045 m->m_pkthdr.len = m->m_len = total_len; 2046 2047 if (ifp->if_capenable & IFCAP_RXCSUM) { 2048 /* Do IP checksum checking. */ 2049 if (rxstat & XL_RXSTAT_IPCKOK) 2050 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2051 if (!(rxstat & XL_RXSTAT_IPCKERR)) 2052 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2053 if ((rxstat & XL_RXSTAT_TCPCOK && 2054 !(rxstat & XL_RXSTAT_TCPCKERR)) || 2055 (rxstat & XL_RXSTAT_UDPCKOK && 2056 !(rxstat & XL_RXSTAT_UDPCKERR))) { 2057 m->m_pkthdr.csum_flags |= 2058 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2059 m->m_pkthdr.csum_data = 0xffff; 2060 } 2061 } 2062 2063 XL_UNLOCK(sc); 2064 (*ifp->if_input)(ifp, m); 2065 XL_LOCK(sc); 2066 } 2067 2068 /* 2069 * Handle the 'end of channel' condition. When the upload 2070 * engine hits the end of the RX ring, it will stall. This 2071 * is our cue to flush the RX ring, reload the uplist pointer 2072 * register and unstall the engine. 2073 * XXX This is actually a little goofy. With the ThunderLAN 2074 * chip, you get an interrupt when the receiver hits the end 2075 * of the receive ring, which tells you exactly when you 2076 * you need to reload the ring pointer. Here we have to 2077 * fake it. I'm mad at myself for not being clever enough 2078 * to avoid the use of a goto here. 2079 */ 2080 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2081 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2082 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2083 xl_wait(sc); 2084 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2085 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2086 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2087 goto again; 2088 } 2089 } 2090 2091 /* 2092 * A frame was downloaded to the chip. It's safe for us to clean up 2093 * the list buffers. 2094 */ 2095 static void 2096 xl_txeof(struct xl_softc *sc) 2097 { 2098 struct xl_chain *cur_tx; 2099 struct ifnet *ifp = &sc->arpcom.ac_if; 2100 2101 XL_LOCK_ASSERT(sc); 2102 2103 /* Clear the timeout timer. */ 2104 ifp->if_timer = 0; 2105 2106 /* 2107 * Go through our tx list and free mbufs for those 2108 * frames that have been uploaded. Note: the 3c905B 2109 * sets a special bit in the status word to let us 2110 * know that a frame has been downloaded, but the 2111 * original 3c900/3c905 adapters don't do that. 2112 * Consequently, we have to use a different test if 2113 * xl_type != XL_TYPE_905B. 2114 */ 2115 while (sc->xl_cdata.xl_tx_head != NULL) { 2116 cur_tx = sc->xl_cdata.xl_tx_head; 2117 2118 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2119 break; 2120 2121 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2122 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2123 BUS_DMASYNC_POSTWRITE); 2124 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2125 m_freem(cur_tx->xl_mbuf); 2126 cur_tx->xl_mbuf = NULL; 2127 ifp->if_opackets++; 2128 2129 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2130 sc->xl_cdata.xl_tx_free = cur_tx; 2131 } 2132 2133 if (sc->xl_cdata.xl_tx_head == NULL) { 2134 ifp->if_flags &= ~IFF_OACTIVE; 2135 sc->xl_cdata.xl_tx_tail = NULL; 2136 } else { 2137 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2138 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2139 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2140 sc->xl_cdata.xl_tx_head->xl_phys); 2141 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2142 } 2143 } 2144 } 2145 2146 static void 2147 xl_txeof_90xB(struct xl_softc *sc) 2148 { 2149 struct xl_chain *cur_tx = NULL; 2150 struct ifnet *ifp = &sc->arpcom.ac_if; 2151 int idx; 2152 2153 XL_LOCK_ASSERT(sc); 2154 2155 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2156 BUS_DMASYNC_POSTREAD); 2157 idx = sc->xl_cdata.xl_tx_cons; 2158 while (idx != sc->xl_cdata.xl_tx_prod) { 2159 2160 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2161 2162 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2163 XL_TXSTAT_DL_COMPLETE)) 2164 break; 2165 2166 if (cur_tx->xl_mbuf != NULL) { 2167 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2168 BUS_DMASYNC_POSTWRITE); 2169 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2170 m_freem(cur_tx->xl_mbuf); 2171 cur_tx->xl_mbuf = NULL; 2172 } 2173 2174 ifp->if_opackets++; 2175 2176 sc->xl_cdata.xl_tx_cnt--; 2177 XL_INC(idx, XL_TX_LIST_CNT); 2178 ifp->if_timer = 0; 2179 } 2180 2181 sc->xl_cdata.xl_tx_cons = idx; 2182 2183 if (cur_tx != NULL) 2184 ifp->if_flags &= ~IFF_OACTIVE; 2185 } 2186 2187 /* 2188 * TX 'end of channel' interrupt handler. Actually, we should 2189 * only get a 'TX complete' interrupt if there's a transmit error, 2190 * so this is really TX error handler. 2191 */ 2192 static void 2193 xl_txeoc(struct xl_softc *sc) 2194 { 2195 u_int8_t txstat; 2196 2197 XL_LOCK_ASSERT(sc); 2198 2199 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2200 if (txstat & XL_TXSTATUS_UNDERRUN || 2201 txstat & XL_TXSTATUS_JABBER || 2202 txstat & XL_TXSTATUS_RECLAIM) { 2203 if_printf(&sc->arpcom.ac_if, 2204 "transmission error: %x\n", txstat); 2205 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2206 xl_wait(sc); 2207 if (sc->xl_type == XL_TYPE_905B) { 2208 if (sc->xl_cdata.xl_tx_cnt) { 2209 int i; 2210 struct xl_chain *c; 2211 2212 i = sc->xl_cdata.xl_tx_cons; 2213 c = &sc->xl_cdata.xl_tx_chain[i]; 2214 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2215 c->xl_phys); 2216 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2217 } 2218 } else { 2219 if (sc->xl_cdata.xl_tx_head != NULL) 2220 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2221 sc->xl_cdata.xl_tx_head->xl_phys); 2222 } 2223 /* 2224 * Remember to set this for the 2225 * first generation 3c90X chips. 2226 */ 2227 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2228 if (txstat & XL_TXSTATUS_UNDERRUN && 2229 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2230 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2231 if_printf(&sc->arpcom.ac_if, 2232 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh); 2233 } 2234 CSR_WRITE_2(sc, XL_COMMAND, 2235 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2236 if (sc->xl_type == XL_TYPE_905B) { 2237 CSR_WRITE_2(sc, XL_COMMAND, 2238 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2239 } 2240 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2241 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2242 } else { 2243 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2244 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2245 } 2246 /* 2247 * Write an arbitrary byte to the TX_STATUS register 2248 * to clear this interrupt/error and advance to the next. 2249 */ 2250 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2251 } 2252 } 2253 2254 static void 2255 xl_intr(void *arg) 2256 { 2257 struct xl_softc *sc = arg; 2258 struct ifnet *ifp = &sc->arpcom.ac_if; 2259 u_int16_t status; 2260 2261 XL_LOCK(sc); 2262 2263 #ifdef DEVICE_POLLING 2264 if (ifp->if_flags & IFF_POLLING) { 2265 XL_UNLOCK(sc); 2266 return; 2267 } 2268 2269 if ((ifp->if_capenable & IFCAP_POLLING) && 2270 ether_poll_register(xl_poll, ifp)) { 2271 /* Disable interrupts. */ 2272 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 2273 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2274 if (sc->xl_flags & XL_FLAG_FUNCREG) 2275 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 2276 4, 0x8000); 2277 xl_poll_locked(ifp, 0, 1); 2278 XL_UNLOCK(sc); 2279 return; 2280 } 2281 #endif /* DEVICE_POLLING */ 2282 2283 while ((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && 2284 status != 0xFFFF) { 2285 CSR_WRITE_2(sc, XL_COMMAND, 2286 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2287 2288 if (status & XL_STAT_UP_COMPLETE) { 2289 int curpkts; 2290 2291 curpkts = ifp->if_ipackets; 2292 xl_rxeof(sc); 2293 if (curpkts == ifp->if_ipackets) { 2294 while (xl_rx_resync(sc)) 2295 xl_rxeof(sc); 2296 } 2297 } 2298 2299 if (status & XL_STAT_DOWN_COMPLETE) { 2300 if (sc->xl_type == XL_TYPE_905B) 2301 xl_txeof_90xB(sc); 2302 else 2303 xl_txeof(sc); 2304 } 2305 2306 if (status & XL_STAT_TX_COMPLETE) { 2307 ifp->if_oerrors++; 2308 xl_txeoc(sc); 2309 } 2310 2311 if (status & XL_STAT_ADFAIL) { 2312 xl_reset(sc); 2313 xl_init_locked(sc); 2314 } 2315 2316 if (status & XL_STAT_STATSOFLOW) { 2317 sc->xl_stats_no_timeout = 1; 2318 xl_stats_update_locked(sc); 2319 sc->xl_stats_no_timeout = 0; 2320 } 2321 } 2322 2323 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2324 if (sc->xl_type == XL_TYPE_905B) 2325 xl_start_90xB_locked(ifp); 2326 else 2327 xl_start_locked(ifp); 2328 } 2329 2330 XL_UNLOCK(sc); 2331 } 2332 2333 #ifdef DEVICE_POLLING 2334 static void 2335 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2336 { 2337 struct xl_softc *sc = ifp->if_softc; 2338 2339 XL_LOCK(sc); 2340 xl_poll_locked(ifp, cmd, count); 2341 XL_UNLOCK(sc); 2342 } 2343 2344 static void 2345 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2346 { 2347 struct xl_softc *sc = ifp->if_softc; 2348 2349 XL_LOCK_ASSERT(sc); 2350 2351 if (!(ifp->if_capenable & IFCAP_POLLING)) { 2352 ether_poll_deregister(ifp); 2353 cmd = POLL_DEREGISTER; 2354 } 2355 2356 if (cmd == POLL_DEREGISTER) { 2357 /* Final call; enable interrupts. */ 2358 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2359 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2360 if (sc->xl_flags & XL_FLAG_FUNCREG) 2361 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 2362 4, 0x8000); 2363 return; 2364 } 2365 2366 sc->rxcycles = count; 2367 xl_rxeof(sc); 2368 if (sc->xl_type == XL_TYPE_905B) 2369 xl_txeof_90xB(sc); 2370 else 2371 xl_txeof(sc); 2372 2373 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2374 if (sc->xl_type == XL_TYPE_905B) 2375 xl_start_90xB_locked(ifp); 2376 else 2377 xl_start_locked(ifp); 2378 } 2379 2380 if (cmd == POLL_AND_CHECK_STATUS) { 2381 u_int16_t status; 2382 2383 status = CSR_READ_2(sc, XL_STATUS); 2384 if (status & XL_INTRS && status != 0xFFFF) { 2385 CSR_WRITE_2(sc, XL_COMMAND, 2386 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2387 2388 if (status & XL_STAT_TX_COMPLETE) { 2389 ifp->if_oerrors++; 2390 xl_txeoc(sc); 2391 } 2392 2393 if (status & XL_STAT_ADFAIL) { 2394 xl_reset(sc); 2395 xl_init_locked(sc); 2396 } 2397 2398 if (status & XL_STAT_STATSOFLOW) { 2399 sc->xl_stats_no_timeout = 1; 2400 xl_stats_update_locked(sc); 2401 sc->xl_stats_no_timeout = 0; 2402 } 2403 } 2404 } 2405 } 2406 #endif /* DEVICE_POLLING */ 2407 2408 /* 2409 * XXX: This is an entry point for callout which needs to take the lock. 2410 */ 2411 static void 2412 xl_stats_update(void *xsc) 2413 { 2414 struct xl_softc *sc = xsc; 2415 2416 XL_LOCK(sc); 2417 xl_stats_update_locked(sc); 2418 XL_UNLOCK(sc); 2419 } 2420 2421 static void 2422 xl_stats_update_locked(struct xl_softc *sc) 2423 { 2424 struct ifnet *ifp = &sc->arpcom.ac_if; 2425 struct xl_stats xl_stats; 2426 u_int8_t *p; 2427 int i; 2428 struct mii_data *mii = NULL; 2429 2430 XL_LOCK_ASSERT(sc); 2431 2432 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2433 2434 if (sc->xl_miibus != NULL) 2435 mii = device_get_softc(sc->xl_miibus); 2436 2437 p = (u_int8_t *)&xl_stats; 2438 2439 /* Read all the stats registers. */ 2440 XL_SEL_WIN(6); 2441 2442 for (i = 0; i < 16; i++) 2443 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2444 2445 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2446 2447 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2448 xl_stats.xl_tx_single_collision + xl_stats.xl_tx_late_collision; 2449 2450 /* 2451 * Boomerang and cyclone chips have an extra stats counter 2452 * in window 4 (BadSSD). We have to read this too in order 2453 * to clear out all the stats registers and avoid a statsoflow 2454 * interrupt. 2455 */ 2456 XL_SEL_WIN(4); 2457 CSR_READ_1(sc, XL_W4_BADSSD); 2458 2459 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2460 mii_tick(mii); 2461 2462 XL_SEL_WIN(7); 2463 2464 if (!sc->xl_stats_no_timeout) 2465 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz); 2466 } 2467 2468 /* 2469 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2470 * pointers to the fragment pointers. 2471 */ 2472 static int 2473 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head) 2474 { 2475 int error; 2476 u_int32_t status; 2477 struct ifnet *ifp = &sc->arpcom.ac_if; 2478 2479 XL_LOCK_ASSERT(sc); 2480 2481 /* 2482 * Start packing the mbufs in this chain into 2483 * the fragment pointers. Stop when we run out 2484 * of fragments or hit the end of the mbuf chain. 2485 */ 2486 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head, 2487 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2488 2489 if (error && error != EFBIG) { 2490 m_freem(m_head); 2491 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2492 return (1); 2493 } 2494 2495 /* 2496 * Handle special case: we used up all 63 fragments, 2497 * but we have more mbufs left in the chain. Copy the 2498 * data into an mbuf cluster. Note that we don't 2499 * bother clearing the values in the other fragment 2500 * pointers/counters; it wouldn't gain us anything, 2501 * and would waste cycles. 2502 */ 2503 if (error) { 2504 struct mbuf *m_new; 2505 2506 m_new = m_defrag(m_head, M_DONTWAIT); 2507 if (m_new == NULL) { 2508 m_freem(m_head); 2509 return (1); 2510 } else { 2511 m_head = m_new; 2512 } 2513 2514 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, 2515 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2516 if (error) { 2517 m_freem(m_head); 2518 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2519 return (1); 2520 } 2521 } 2522 2523 if (sc->xl_type == XL_TYPE_905B) { 2524 status = XL_TXSTAT_RND_DEFEAT; 2525 2526 #ifndef XL905B_TXCSUM_BROKEN 2527 if (m_head->m_pkthdr.csum_flags) { 2528 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2529 status |= XL_TXSTAT_IPCKSUM; 2530 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2531 status |= XL_TXSTAT_TCPCKSUM; 2532 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2533 status |= XL_TXSTAT_UDPCKSUM; 2534 } 2535 #endif 2536 c->xl_ptr->xl_status = htole32(status); 2537 } 2538 2539 c->xl_mbuf = m_head; 2540 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2541 return (0); 2542 } 2543 2544 /* 2545 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2546 * to the mbuf data regions directly in the transmit lists. We also save a 2547 * copy of the pointers since the transmit list fragment pointers are 2548 * physical addresses. 2549 */ 2550 2551 static void 2552 xl_start(struct ifnet *ifp) 2553 { 2554 struct xl_softc *sc = ifp->if_softc; 2555 2556 XL_LOCK(sc); 2557 2558 if (sc->xl_type == XL_TYPE_905B) 2559 xl_start_90xB_locked(ifp); 2560 else 2561 xl_start_locked(ifp); 2562 2563 XL_UNLOCK(sc); 2564 } 2565 2566 static void 2567 xl_start_locked(struct ifnet *ifp) 2568 { 2569 struct xl_softc *sc = ifp->if_softc; 2570 struct mbuf *m_head = NULL; 2571 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2572 struct xl_chain *prev_tx; 2573 u_int32_t status; 2574 int error; 2575 2576 XL_LOCK_ASSERT(sc); 2577 2578 /* 2579 * Check for an available queue slot. If there are none, 2580 * punt. 2581 */ 2582 if (sc->xl_cdata.xl_tx_free == NULL) { 2583 xl_txeoc(sc); 2584 xl_txeof(sc); 2585 if (sc->xl_cdata.xl_tx_free == NULL) { 2586 ifp->if_flags |= IFF_OACTIVE; 2587 return; 2588 } 2589 } 2590 2591 start_tx = sc->xl_cdata.xl_tx_free; 2592 2593 while (sc->xl_cdata.xl_tx_free != NULL) { 2594 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2595 if (m_head == NULL) 2596 break; 2597 2598 /* Pick a descriptor off the free list. */ 2599 prev_tx = cur_tx; 2600 cur_tx = sc->xl_cdata.xl_tx_free; 2601 2602 /* Pack the data into the descriptor. */ 2603 error = xl_encap(sc, cur_tx, m_head); 2604 if (error) { 2605 cur_tx = prev_tx; 2606 continue; 2607 } 2608 2609 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2610 cur_tx->xl_next = NULL; 2611 2612 /* Chain it together. */ 2613 if (prev != NULL) { 2614 prev->xl_next = cur_tx; 2615 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2616 } 2617 prev = cur_tx; 2618 2619 /* 2620 * If there's a BPF listener, bounce a copy of this frame 2621 * to him. 2622 */ 2623 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2624 } 2625 2626 /* 2627 * If there are no packets queued, bail. 2628 */ 2629 if (cur_tx == NULL) 2630 return; 2631 2632 /* 2633 * Place the request for the upload interrupt 2634 * in the last descriptor in the chain. This way, if 2635 * we're chaining several packets at once, we'll only 2636 * get an interupt once for the whole chain rather than 2637 * once for each packet. 2638 */ 2639 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2640 XL_TXSTAT_DL_INTR); 2641 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2642 BUS_DMASYNC_PREWRITE); 2643 2644 /* 2645 * Queue the packets. If the TX channel is clear, update 2646 * the downlist pointer register. 2647 */ 2648 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2649 xl_wait(sc); 2650 2651 if (sc->xl_cdata.xl_tx_head != NULL) { 2652 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2653 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2654 htole32(start_tx->xl_phys); 2655 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2656 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2657 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2658 sc->xl_cdata.xl_tx_tail = cur_tx; 2659 } else { 2660 sc->xl_cdata.xl_tx_head = start_tx; 2661 sc->xl_cdata.xl_tx_tail = cur_tx; 2662 } 2663 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2664 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2665 2666 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2667 2668 XL_SEL_WIN(7); 2669 2670 /* 2671 * Set a timeout in case the chip goes out to lunch. 2672 */ 2673 ifp->if_timer = 5; 2674 2675 /* 2676 * XXX Under certain conditions, usually on slower machines 2677 * where interrupts may be dropped, it's possible for the 2678 * adapter to chew up all the buffers in the receive ring 2679 * and stall, without us being able to do anything about it. 2680 * To guard against this, we need to make a pass over the 2681 * RX queue to make sure there aren't any packets pending. 2682 * Doing it here means we can flush the receive ring at the 2683 * same time the chip is DMAing the transmit descriptors we 2684 * just gave it. 2685 * 2686 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2687 * nature of their chips in all their marketing literature; 2688 * we may as well take advantage of it. :) 2689 */ 2690 xl_rxeof(sc); 2691 } 2692 2693 static void 2694 xl_start_90xB_locked(struct ifnet *ifp) 2695 { 2696 struct xl_softc *sc = ifp->if_softc; 2697 struct mbuf *m_head = NULL; 2698 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2699 struct xl_chain *prev_tx; 2700 int error, idx; 2701 2702 XL_LOCK_ASSERT(sc); 2703 2704 if (ifp->if_flags & IFF_OACTIVE) 2705 return; 2706 2707 idx = sc->xl_cdata.xl_tx_prod; 2708 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2709 2710 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { 2711 2712 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2713 ifp->if_flags |= IFF_OACTIVE; 2714 break; 2715 } 2716 2717 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2718 if (m_head == NULL) 2719 break; 2720 2721 prev_tx = cur_tx; 2722 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2723 2724 /* Pack the data into the descriptor. */ 2725 error = xl_encap(sc, cur_tx, m_head); 2726 if (error) { 2727 cur_tx = prev_tx; 2728 continue; 2729 } 2730 2731 /* Chain it together. */ 2732 if (prev != NULL) 2733 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2734 prev = cur_tx; 2735 2736 /* 2737 * If there's a BPF listener, bounce a copy of this frame 2738 * to him. 2739 */ 2740 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2741 2742 XL_INC(idx, XL_TX_LIST_CNT); 2743 sc->xl_cdata.xl_tx_cnt++; 2744 } 2745 2746 /* 2747 * If there are no packets queued, bail. 2748 */ 2749 if (cur_tx == NULL) 2750 return; 2751 2752 /* 2753 * Place the request for the upload interrupt 2754 * in the last descriptor in the chain. This way, if 2755 * we're chaining several packets at once, we'll only 2756 * get an interupt once for the whole chain rather than 2757 * once for each packet. 2758 */ 2759 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2760 XL_TXSTAT_DL_INTR); 2761 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2762 BUS_DMASYNC_PREWRITE); 2763 2764 /* Start transmission */ 2765 sc->xl_cdata.xl_tx_prod = idx; 2766 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2767 2768 /* 2769 * Set a timeout in case the chip goes out to lunch. 2770 */ 2771 ifp->if_timer = 5; 2772 } 2773 2774 static void 2775 xl_init(void *xsc) 2776 { 2777 struct xl_softc *sc = xsc; 2778 2779 XL_LOCK(sc); 2780 xl_init_locked(sc); 2781 XL_UNLOCK(sc); 2782 } 2783 2784 static void 2785 xl_init_locked(struct xl_softc *sc) 2786 { 2787 struct ifnet *ifp = &sc->arpcom.ac_if; 2788 int error, i; 2789 u_int16_t rxfilt = 0; 2790 struct mii_data *mii = NULL; 2791 2792 XL_LOCK_ASSERT(sc); 2793 2794 /* 2795 * Cancel pending I/O and free all RX/TX buffers. 2796 */ 2797 xl_stop(sc); 2798 2799 if (sc->xl_miibus == NULL) { 2800 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2801 xl_wait(sc); 2802 } 2803 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2804 xl_wait(sc); 2805 DELAY(10000); 2806 2807 if (sc->xl_miibus != NULL) 2808 mii = device_get_softc(sc->xl_miibus); 2809 2810 /* Init our MAC address */ 2811 XL_SEL_WIN(2); 2812 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2813 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2814 sc->arpcom.ac_enaddr[i]); 2815 } 2816 2817 /* Clear the station mask. */ 2818 for (i = 0; i < 3; i++) 2819 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2820 #ifdef notdef 2821 /* Reset TX and RX. */ 2822 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2823 xl_wait(sc); 2824 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2825 xl_wait(sc); 2826 #endif 2827 /* Init circular RX list. */ 2828 error = xl_list_rx_init(sc); 2829 if (error) { 2830 if_printf(ifp, "initialization of the rx ring failed (%d)\n", 2831 error); 2832 xl_stop(sc); 2833 return; 2834 } 2835 2836 /* Init TX descriptors. */ 2837 if (sc->xl_type == XL_TYPE_905B) 2838 error = xl_list_tx_init_90xB(sc); 2839 else 2840 error = xl_list_tx_init(sc); 2841 if (error) { 2842 if_printf(ifp, "initialization of the tx ring failed (%d)\n", 2843 error); 2844 xl_stop(sc); 2845 return; 2846 } 2847 2848 /* 2849 * Set the TX freethresh value. 2850 * Note that this has no effect on 3c905B "cyclone" 2851 * cards but is required for 3c900/3c905 "boomerang" 2852 * cards in order to enable the download engine. 2853 */ 2854 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2855 2856 /* Set the TX start threshold for best performance. */ 2857 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 2858 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2859 2860 /* 2861 * If this is a 3c905B, also set the tx reclaim threshold. 2862 * This helps cut down on the number of tx reclaim errors 2863 * that could happen on a busy network. The chip multiplies 2864 * the register value by 16 to obtain the actual threshold 2865 * in bytes, so we divide by 16 when setting the value here. 2866 * The existing threshold value can be examined by reading 2867 * the register at offset 9 in window 5. 2868 */ 2869 if (sc->xl_type == XL_TYPE_905B) { 2870 CSR_WRITE_2(sc, XL_COMMAND, 2871 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2872 } 2873 2874 /* Set RX filter bits. */ 2875 XL_SEL_WIN(5); 2876 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2877 2878 /* Set the individual bit to receive frames for this host only. */ 2879 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2880 2881 /* If we want promiscuous mode, set the allframes bit. */ 2882 if (ifp->if_flags & IFF_PROMISC) { 2883 rxfilt |= XL_RXFILTER_ALLFRAMES; 2884 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2885 } else { 2886 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2887 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2888 } 2889 2890 /* 2891 * Set capture broadcast bit to capture broadcast frames. 2892 */ 2893 if (ifp->if_flags & IFF_BROADCAST) { 2894 rxfilt |= XL_RXFILTER_BROADCAST; 2895 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2896 } else { 2897 rxfilt &= ~XL_RXFILTER_BROADCAST; 2898 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2899 } 2900 2901 /* 2902 * Program the multicast filter, if necessary. 2903 */ 2904 if (sc->xl_type == XL_TYPE_905B) 2905 xl_setmulti_hash(sc); 2906 else 2907 xl_setmulti(sc); 2908 2909 /* 2910 * Load the address of the RX list. We have to 2911 * stall the upload engine before we can manipulate 2912 * the uplist pointer register, then unstall it when 2913 * we're finished. We also have to wait for the 2914 * stall command to complete before proceeding. 2915 * Note that we have to do this after any RX resets 2916 * have completed since the uplist register is cleared 2917 * by a reset. 2918 */ 2919 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2920 xl_wait(sc); 2921 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2922 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2923 xl_wait(sc); 2924 2925 if (sc->xl_type == XL_TYPE_905B) { 2926 /* Set polling interval */ 2927 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2928 /* Load the address of the TX list */ 2929 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2930 xl_wait(sc); 2931 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2932 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2933 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2934 xl_wait(sc); 2935 } 2936 2937 /* 2938 * If the coax transceiver is on, make sure to enable 2939 * the DC-DC converter. 2940 */ 2941 XL_SEL_WIN(3); 2942 if (sc->xl_xcvr == XL_XCVR_COAX) 2943 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2944 else 2945 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2946 2947 /* 2948 * increase packet size to allow reception of 802.1q or ISL packets. 2949 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2950 * control register. For 3c90xB/C chips, use the RX packet size 2951 * register. 2952 */ 2953 2954 if (sc->xl_type == XL_TYPE_905B) 2955 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2956 else { 2957 u_int8_t macctl; 2958 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2959 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2960 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2961 } 2962 2963 /* Clear out the stats counters. */ 2964 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2965 sc->xl_stats_no_timeout = 1; 2966 xl_stats_update_locked(sc); 2967 sc->xl_stats_no_timeout = 0; 2968 XL_SEL_WIN(4); 2969 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2970 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2971 2972 /* 2973 * Enable interrupts. 2974 */ 2975 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2976 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2977 #ifdef DEVICE_POLLING 2978 /* Disable interrupts if we are polling. */ 2979 if (ifp->if_flags & IFF_POLLING) 2980 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 2981 else 2982 #endif /* DEVICE_POLLING */ 2983 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2984 if (sc->xl_flags & XL_FLAG_FUNCREG) 2985 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2986 2987 /* Set the RX early threshold */ 2988 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2989 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2990 2991 /* Enable receiver and transmitter. */ 2992 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2993 xl_wait(sc); 2994 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2995 xl_wait(sc); 2996 2997 /* XXX Downcall to miibus. */ 2998 if (mii != NULL) 2999 mii_mediachg(mii); 3000 3001 /* Select window 7 for normal operations. */ 3002 XL_SEL_WIN(7); 3003 3004 ifp->if_flags |= IFF_RUNNING; 3005 ifp->if_flags &= ~IFF_OACTIVE; 3006 3007 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz); 3008 } 3009 3010 /* 3011 * Set media options. 3012 */ 3013 static int 3014 xl_ifmedia_upd(struct ifnet *ifp) 3015 { 3016 struct xl_softc *sc = ifp->if_softc; 3017 struct ifmedia *ifm = NULL; 3018 struct mii_data *mii = NULL; 3019 3020 /*XL_LOCK_ASSERT(sc);*/ 3021 3022 if (sc->xl_miibus != NULL) 3023 mii = device_get_softc(sc->xl_miibus); 3024 if (mii == NULL) 3025 ifm = &sc->ifmedia; 3026 else 3027 ifm = &mii->mii_media; 3028 3029 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3030 case IFM_100_FX: 3031 case IFM_10_FL: 3032 case IFM_10_2: 3033 case IFM_10_5: 3034 xl_setmode(sc, ifm->ifm_media); 3035 return (0); 3036 break; 3037 default: 3038 break; 3039 } 3040 3041 if (sc->xl_media & XL_MEDIAOPT_MII || 3042 sc->xl_media & XL_MEDIAOPT_BTX || 3043 sc->xl_media & XL_MEDIAOPT_BT4) { 3044 xl_init(sc); /* XXX */ 3045 } else { 3046 xl_setmode(sc, ifm->ifm_media); 3047 } 3048 3049 return (0); 3050 } 3051 3052 /* 3053 * Report current media status. 3054 */ 3055 static void 3056 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3057 { 3058 struct xl_softc *sc = ifp->if_softc; 3059 u_int32_t icfg; 3060 u_int16_t status = 0; 3061 struct mii_data *mii = NULL; 3062 3063 /*XL_LOCK_ASSERT(sc);*/ 3064 3065 if (sc->xl_miibus != NULL) 3066 mii = device_get_softc(sc->xl_miibus); 3067 3068 XL_SEL_WIN(4); 3069 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3070 3071 XL_SEL_WIN(3); 3072 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 3073 icfg >>= XL_ICFG_CONNECTOR_BITS; 3074 3075 ifmr->ifm_active = IFM_ETHER; 3076 ifmr->ifm_status = IFM_AVALID; 3077 3078 if ((status & XL_MEDIASTAT_CARRIER) == 0) 3079 ifmr->ifm_status |= IFM_ACTIVE; 3080 3081 switch (icfg) { 3082 case XL_XCVR_10BT: 3083 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 3084 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3085 ifmr->ifm_active |= IFM_FDX; 3086 else 3087 ifmr->ifm_active |= IFM_HDX; 3088 break; 3089 case XL_XCVR_AUI: 3090 if (sc->xl_type == XL_TYPE_905B && 3091 sc->xl_media == XL_MEDIAOPT_10FL) { 3092 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 3093 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3094 ifmr->ifm_active |= IFM_FDX; 3095 else 3096 ifmr->ifm_active |= IFM_HDX; 3097 } else 3098 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3099 break; 3100 case XL_XCVR_COAX: 3101 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3102 break; 3103 /* 3104 * XXX MII and BTX/AUTO should be separate cases. 3105 */ 3106 3107 case XL_XCVR_100BTX: 3108 case XL_XCVR_AUTO: 3109 case XL_XCVR_MII: 3110 if (mii != NULL) { 3111 mii_pollstat(mii); 3112 ifmr->ifm_active = mii->mii_media_active; 3113 ifmr->ifm_status = mii->mii_media_status; 3114 } 3115 break; 3116 case XL_XCVR_100BFX: 3117 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3118 break; 3119 default: 3120 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3121 break; 3122 } 3123 } 3124 3125 static int 3126 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3127 { 3128 struct xl_softc *sc = ifp->if_softc; 3129 struct ifreq *ifr = (struct ifreq *) data; 3130 int error = 0; 3131 struct mii_data *mii = NULL; 3132 u_int8_t rxfilt; 3133 3134 switch (command) { 3135 case SIOCSIFFLAGS: 3136 XL_LOCK(sc); 3137 3138 XL_SEL_WIN(5); 3139 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3140 if (ifp->if_flags & IFF_UP) { 3141 if (ifp->if_flags & IFF_RUNNING && 3142 ifp->if_flags & IFF_PROMISC && 3143 !(sc->xl_if_flags & IFF_PROMISC)) { 3144 rxfilt |= XL_RXFILTER_ALLFRAMES; 3145 CSR_WRITE_2(sc, XL_COMMAND, 3146 XL_CMD_RX_SET_FILT|rxfilt); 3147 XL_SEL_WIN(7); 3148 } else if (ifp->if_flags & IFF_RUNNING && 3149 !(ifp->if_flags & IFF_PROMISC) && 3150 sc->xl_if_flags & IFF_PROMISC) { 3151 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3152 CSR_WRITE_2(sc, XL_COMMAND, 3153 XL_CMD_RX_SET_FILT|rxfilt); 3154 XL_SEL_WIN(7); 3155 } else { 3156 if ((ifp->if_flags & IFF_RUNNING) == 0) 3157 xl_init_locked(sc); 3158 } 3159 } else { 3160 if (ifp->if_flags & IFF_RUNNING) 3161 xl_stop(sc); 3162 } 3163 sc->xl_if_flags = ifp->if_flags; 3164 XL_UNLOCK(sc); 3165 error = 0; 3166 break; 3167 case SIOCADDMULTI: 3168 case SIOCDELMULTI: 3169 /* XXX Downcall from if_addmulti() possibly with locks held. */ 3170 XL_LOCK(sc); 3171 if (sc->xl_type == XL_TYPE_905B) 3172 xl_setmulti_hash(sc); 3173 else 3174 xl_setmulti(sc); 3175 XL_UNLOCK(sc); 3176 error = 0; 3177 break; 3178 case SIOCGIFMEDIA: 3179 case SIOCSIFMEDIA: 3180 /* XXX Downcall from ifmedia possibly with locks held. */ 3181 /*XL_LOCK(sc);*/ 3182 if (sc->xl_miibus != NULL) 3183 mii = device_get_softc(sc->xl_miibus); 3184 if (mii == NULL) 3185 error = ifmedia_ioctl(ifp, ifr, 3186 &sc->ifmedia, command); 3187 else 3188 error = ifmedia_ioctl(ifp, ifr, 3189 &mii->mii_media, command); 3190 /*XL_UNLOCK(sc);*/ 3191 break; 3192 case SIOCSIFCAP: 3193 XL_LOCK(sc); 3194 ifp->if_capenable = ifr->ifr_reqcap; 3195 if (ifp->if_capenable & IFCAP_TXCSUM) 3196 ifp->if_hwassist = XL905B_CSUM_FEATURES; 3197 else 3198 ifp->if_hwassist = 0; 3199 XL_UNLOCK(sc); 3200 break; 3201 default: 3202 error = ether_ioctl(ifp, command, data); 3203 break; 3204 } 3205 3206 return (error); 3207 } 3208 3209 /* 3210 * XXX: Invoked from ifnet slow timer. Lock coverage needed. 3211 */ 3212 static void 3213 xl_watchdog(struct ifnet *ifp) 3214 { 3215 struct xl_softc *sc = ifp->if_softc; 3216 u_int16_t status = 0; 3217 3218 XL_LOCK(sc); 3219 3220 ifp->if_oerrors++; 3221 XL_SEL_WIN(4); 3222 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3223 if_printf(ifp, "watchdog timeout\n"); 3224 3225 if (status & XL_MEDIASTAT_CARRIER) 3226 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 3227 3228 xl_txeoc(sc); 3229 xl_txeof(sc); 3230 xl_rxeof(sc); 3231 xl_reset(sc); 3232 xl_init_locked(sc); 3233 3234 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 3235 if (sc->xl_type == XL_TYPE_905B) 3236 xl_start_90xB_locked(ifp); 3237 else 3238 xl_start_locked(ifp); 3239 } 3240 3241 XL_UNLOCK(sc); 3242 } 3243 3244 /* 3245 * Stop the adapter and free any mbufs allocated to the 3246 * RX and TX lists. 3247 */ 3248 static void 3249 xl_stop(struct xl_softc *sc) 3250 { 3251 register int i; 3252 struct ifnet *ifp = &sc->arpcom.ac_if; 3253 3254 XL_LOCK_ASSERT(sc); 3255 3256 ifp->if_timer = 0; 3257 #ifdef DEVICE_POLLING 3258 ether_poll_deregister(ifp); 3259 #endif /* DEVICE_POLLING */ 3260 3261 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3262 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3263 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3264 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3265 xl_wait(sc); 3266 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3267 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3268 DELAY(800); 3269 3270 #ifdef foo 3271 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3272 xl_wait(sc); 3273 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3274 xl_wait(sc); 3275 #endif 3276 3277 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3278 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3279 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3280 if (sc->xl_flags & XL_FLAG_FUNCREG) 3281 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3282 3283 /* Stop the stats updater. */ 3284 untimeout(xl_stats_update, sc, sc->xl_stat_ch); 3285 3286 /* 3287 * Free data in the RX lists. 3288 */ 3289 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3290 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3291 bus_dmamap_unload(sc->xl_mtag, 3292 sc->xl_cdata.xl_rx_chain[i].xl_map); 3293 bus_dmamap_destroy(sc->xl_mtag, 3294 sc->xl_cdata.xl_rx_chain[i].xl_map); 3295 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3296 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3297 } 3298 } 3299 if (sc->xl_ldata.xl_rx_list != NULL) 3300 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3301 /* 3302 * Free the TX list buffers. 3303 */ 3304 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3305 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3306 bus_dmamap_unload(sc->xl_mtag, 3307 sc->xl_cdata.xl_tx_chain[i].xl_map); 3308 bus_dmamap_destroy(sc->xl_mtag, 3309 sc->xl_cdata.xl_tx_chain[i].xl_map); 3310 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3311 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3312 } 3313 } 3314 if (sc->xl_ldata.xl_tx_list != NULL) 3315 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3316 3317 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3318 } 3319 3320 /* 3321 * Stop all chip I/O so that the kernel's probe routines don't 3322 * get confused by errant DMAs when rebooting. 3323 */ 3324 static void 3325 xl_shutdown(device_t dev) 3326 { 3327 struct xl_softc *sc; 3328 3329 sc = device_get_softc(dev); 3330 3331 XL_LOCK(sc); 3332 xl_reset(sc); 3333 xl_stop(sc); 3334 XL_UNLOCK(sc); 3335 } 3336 3337 static int 3338 xl_suspend(device_t dev) 3339 { 3340 struct xl_softc *sc; 3341 3342 sc = device_get_softc(dev); 3343 3344 XL_LOCK(sc); 3345 xl_stop(sc); 3346 XL_UNLOCK(sc); 3347 3348 return (0); 3349 } 3350 3351 static int 3352 xl_resume(device_t dev) 3353 { 3354 struct xl_softc *sc; 3355 struct ifnet *ifp; 3356 3357 sc = device_get_softc(dev); 3358 ifp = &sc->arpcom.ac_if; 3359 3360 XL_LOCK(sc); 3361 3362 xl_reset(sc); 3363 if (ifp->if_flags & IFF_UP) 3364 xl_init_locked(sc); 3365 3366 XL_UNLOCK(sc); 3367 3368 return (0); 3369 }
Cache object: 5b2998743a4430b3ab051038ad732231
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