Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/pci/if_xl.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/6.2/sys/pci/if_xl.c 161378 2006-08-17 00:13:07Z yongari $"); 35 36 /* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77 /* 78 * The 3c90x series chips use a bus-master DMA interface for transfering 79 * packets to and from the controller chip. Some of the "vortex" cards 80 * (3c59x) also supported a bus master mode, however for those chips 81 * you could only DMA packets to/from a contiguous memory buffer. For 82 * transmission this would mean copying the contents of the queued mbuf 83 * chain into an mbuf cluster and then DMAing the cluster. This extra 84 * copy would sort of defeat the purpose of the bus master support for 85 * any packet that doesn't fit into a single mbuf. 86 * 87 * By contrast, the 3c90x cards support a fragment-based bus master 88 * mode where mbuf chains can be encapsulated using TX descriptors. 89 * This is similar to other PCI chips such as the Texas Instruments 90 * ThunderLAN and the Intel 82557/82558. 91 * 92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 93 * bus master chips because they maintain the old PIO interface for 94 * backwards compatibility, but starting with the 3c905B and the 95 * "cyclone" chips, the compatibility interface has been dropped. 96 * Since using bus master DMA is a big win, we use this driver to 97 * support the PCI "boomerang" chips even though they work with the 98 * "vortex" driver in order to obtain better performance. 99 * 100 * This driver is in the /sys/pci directory because it only supports 101 * PCI-based NICs. 102 */ 103 104 #ifdef HAVE_KERNEL_OPTION_HEADERS 105 #include "opt_device_polling.h" 106 #endif 107 108 #include <sys/param.h> 109 #include <sys/systm.h> 110 #include <sys/sockio.h> 111 #include <sys/endian.h> 112 #include <sys/mbuf.h> 113 #include <sys/kernel.h> 114 #include <sys/module.h> 115 #include <sys/socket.h> 116 #include <sys/taskqueue.h> 117 118 #include <net/if.h> 119 #include <net/if_arp.h> 120 #include <net/ethernet.h> 121 #include <net/if_dl.h> 122 #include <net/if_media.h> 123 #include <net/if_types.h> 124 125 #include <net/bpf.h> 126 127 #include <machine/bus.h> 128 #include <machine/resource.h> 129 #include <sys/bus.h> 130 #include <sys/rman.h> 131 132 #include <dev/mii/mii.h> 133 #include <dev/mii/miivar.h> 134 135 #include <dev/pci/pcireg.h> 136 #include <dev/pci/pcivar.h> 137 138 MODULE_DEPEND(xl, pci, 1, 1, 1); 139 MODULE_DEPEND(xl, ether, 1, 1, 1); 140 MODULE_DEPEND(xl, miibus, 1, 1, 1); 141 142 /* "device miibus" required. See GENERIC if you get errors here. */ 143 #include "miibus_if.h" 144 145 #include <pci/if_xlreg.h> 146 147 /* 148 * TX Checksumming is disabled by default for two reasons: 149 * - TX Checksumming will occasionally produce corrupt packets 150 * - TX Checksumming seems to reduce performance 151 * 152 * Only 905B/C cards were reported to have this problem, it is possible 153 * that later chips _may_ be immune. 154 */ 155 #define XL905B_TXCSUM_BROKEN 1 156 157 #ifdef XL905B_TXCSUM_BROKEN 158 #define XL905B_CSUM_FEATURES 0 159 #else 160 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 161 #endif 162 163 /* 164 * Various supported device vendors/types and their names. 165 */ 166 static struct xl_type xl_devs[] = { 167 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 168 "3Com 3c900-TPO Etherlink XL" }, 169 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 170 "3Com 3c900-COMBO Etherlink XL" }, 171 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 172 "3Com 3c905-TX Fast Etherlink XL" }, 173 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 174 "3Com 3c905-T4 Fast Etherlink XL" }, 175 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 176 "3Com 3c900B-TPO Etherlink XL" }, 177 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 178 "3Com 3c900B-COMBO Etherlink XL" }, 179 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 180 "3Com 3c900B-TPC Etherlink XL" }, 181 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 182 "3Com 3c900B-FL Etherlink XL" }, 183 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 184 "3Com 3c905B-TX Fast Etherlink XL" }, 185 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 186 "3Com 3c905B-T4 Fast Etherlink XL" }, 187 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 188 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 189 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 190 "3Com 3c905B-COMBO Fast Etherlink XL" }, 191 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 192 "3Com 3c905C-TX Fast Etherlink XL" }, 193 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 194 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 195 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM, 196 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" }, 197 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 198 "3Com 3c980 Fast Etherlink XL" }, 199 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 200 "3Com 3c980C Fast Etherlink XL" }, 201 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 202 "3Com 3cSOHO100-TX OfficeConnect" }, 203 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 204 "3Com 3c450-TX HomeConnect" }, 205 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 206 "3Com 3c555 Fast Etherlink XL" }, 207 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 208 "3Com 3c556 Fast Etherlink XL" }, 209 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 210 "3Com 3c556B Fast Etherlink XL" }, 211 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 212 "3Com 3c575TX Fast Etherlink XL" }, 213 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 214 "3Com 3c575B Fast Etherlink XL" }, 215 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 216 "3Com 3c575C Fast Etherlink XL" }, 217 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 218 "3Com 3c656 Fast Etherlink XL" }, 219 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 220 "3Com 3c656B Fast Etherlink XL" }, 221 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 222 "3Com 3c656C Fast Etherlink XL" }, 223 { 0, 0, NULL } 224 }; 225 226 static int xl_probe(device_t); 227 static int xl_attach(device_t); 228 static int xl_detach(device_t); 229 230 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *); 231 static void xl_stats_update(void *); 232 static void xl_stats_update_locked(struct xl_softc *); 233 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf *); 234 static void xl_rxeof(struct xl_softc *); 235 static void xl_rxeof_task(void *, int); 236 static int xl_rx_resync(struct xl_softc *); 237 static void xl_txeof(struct xl_softc *); 238 static void xl_txeof_90xB(struct xl_softc *); 239 static void xl_txeoc(struct xl_softc *); 240 static void xl_intr(void *); 241 static void xl_start(struct ifnet *); 242 static void xl_start_locked(struct ifnet *); 243 static void xl_start_90xB_locked(struct ifnet *); 244 static int xl_ioctl(struct ifnet *, u_long, caddr_t); 245 static void xl_init(void *); 246 static void xl_init_locked(struct xl_softc *); 247 static void xl_stop(struct xl_softc *); 248 static void xl_watchdog(struct ifnet *); 249 static void xl_shutdown(device_t); 250 static int xl_suspend(device_t); 251 static int xl_resume(device_t); 252 253 #ifdef DEVICE_POLLING 254 static void xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 255 static void xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); 256 #endif 257 258 static int xl_ifmedia_upd(struct ifnet *); 259 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 260 261 static int xl_eeprom_wait(struct xl_softc *); 262 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int); 263 static void xl_mii_sync(struct xl_softc *); 264 static void xl_mii_send(struct xl_softc *, u_int32_t, int); 265 static int xl_mii_readreg(struct xl_softc *, struct xl_mii_frame *); 266 static int xl_mii_writereg(struct xl_softc *, struct xl_mii_frame *); 267 268 static void xl_setcfg(struct xl_softc *); 269 static void xl_setmode(struct xl_softc *, int); 270 static void xl_setmulti(struct xl_softc *); 271 static void xl_setmulti_hash(struct xl_softc *); 272 static void xl_reset(struct xl_softc *); 273 static int xl_list_rx_init(struct xl_softc *); 274 static int xl_list_tx_init(struct xl_softc *); 275 static int xl_list_tx_init_90xB(struct xl_softc *); 276 static void xl_wait(struct xl_softc *); 277 static void xl_mediacheck(struct xl_softc *); 278 static void xl_choose_media(struct xl_softc *sc, int *media); 279 static void xl_choose_xcvr(struct xl_softc *, int); 280 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int); 281 static void xl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 282 static void xl_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 283 #ifdef notdef 284 static void xl_testpacket(struct xl_softc *); 285 #endif 286 287 static int xl_miibus_readreg(device_t, int, int); 288 static int xl_miibus_writereg(device_t, int, int, int); 289 static void xl_miibus_statchg(device_t); 290 static void xl_miibus_mediainit(device_t); 291 292 static device_method_t xl_methods[] = { 293 /* Device interface */ 294 DEVMETHOD(device_probe, xl_probe), 295 DEVMETHOD(device_attach, xl_attach), 296 DEVMETHOD(device_detach, xl_detach), 297 DEVMETHOD(device_shutdown, xl_shutdown), 298 DEVMETHOD(device_suspend, xl_suspend), 299 DEVMETHOD(device_resume, xl_resume), 300 301 /* bus interface */ 302 DEVMETHOD(bus_print_child, bus_generic_print_child), 303 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 304 305 /* MII interface */ 306 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 307 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 308 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 309 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 310 311 { 0, 0 } 312 }; 313 314 static driver_t xl_driver = { 315 "xl", 316 xl_methods, 317 sizeof(struct xl_softc) 318 }; 319 320 static devclass_t xl_devclass; 321 322 DRIVER_MODULE(xl, cardbus, xl_driver, xl_devclass, 0, 0); 323 DRIVER_MODULE(xl, pci, xl_driver, xl_devclass, 0, 0); 324 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 325 326 static void 327 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 328 { 329 u_int32_t *paddr; 330 331 paddr = arg; 332 *paddr = segs->ds_addr; 333 } 334 335 static void 336 xl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, 337 bus_size_t mapsize, int error) 338 { 339 u_int32_t *paddr; 340 341 if (error) 342 return; 343 344 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments")); 345 paddr = arg; 346 *paddr = segs->ds_addr; 347 } 348 349 static void 350 xl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 351 bus_size_t mapsize, int error) 352 { 353 struct xl_list *l; 354 int i, total_len; 355 356 if (error) 357 return; 358 359 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments")); 360 361 total_len = 0; 362 l = arg; 363 for (i = 0; i < nseg; i++) { 364 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 365 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr); 366 l->xl_frag[i].xl_len = htole32(segs[i].ds_len); 367 total_len += segs[i].ds_len; 368 } 369 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len | 370 XL_LAST_FRAG); 371 l->xl_status = htole32(total_len); 372 l->xl_next = 0; 373 } 374 375 /* 376 * Murphy's law says that it's possible the chip can wedge and 377 * the 'command in progress' bit may never clear. Hence, we wait 378 * only a finite amount of time to avoid getting caught in an 379 * infinite loop. Normally this delay routine would be a macro, 380 * but it isn't called during normal operation so we can afford 381 * to make it a function. 382 */ 383 static void 384 xl_wait(struct xl_softc *sc) 385 { 386 register int i; 387 388 for (i = 0; i < XL_TIMEOUT; i++) { 389 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0) 390 break; 391 } 392 393 if (i == XL_TIMEOUT) 394 if_printf(sc->xl_ifp, "command never completed!\n"); 395 } 396 397 /* 398 * MII access routines are provided for adapters with external 399 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 400 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 401 * Note: if you don't perform the MDIO operations just right, 402 * it's possible to end up with code that works correctly with 403 * some chips/CPUs/processor speeds/bus speeds/etc but not 404 * with others. 405 */ 406 #define MII_SET(x) \ 407 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 408 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 409 410 #define MII_CLR(x) \ 411 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 412 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 413 414 /* 415 * Sync the PHYs by setting data bit and strobing the clock 32 times. 416 */ 417 static void 418 xl_mii_sync(struct xl_softc *sc) 419 { 420 register int i; 421 422 XL_SEL_WIN(4); 423 MII_SET(XL_MII_DIR|XL_MII_DATA); 424 425 for (i = 0; i < 32; i++) { 426 MII_SET(XL_MII_CLK); 427 MII_SET(XL_MII_DATA); 428 MII_SET(XL_MII_DATA); 429 MII_CLR(XL_MII_CLK); 430 MII_SET(XL_MII_DATA); 431 MII_SET(XL_MII_DATA); 432 } 433 } 434 435 /* 436 * Clock a series of bits through the MII. 437 */ 438 static void 439 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt) 440 { 441 int i; 442 443 XL_SEL_WIN(4); 444 MII_CLR(XL_MII_CLK); 445 446 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 447 if (bits & i) { 448 MII_SET(XL_MII_DATA); 449 } else { 450 MII_CLR(XL_MII_DATA); 451 } 452 MII_CLR(XL_MII_CLK); 453 MII_SET(XL_MII_CLK); 454 } 455 } 456 457 /* 458 * Read an PHY register through the MII. 459 */ 460 static int 461 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame) 462 { 463 int i, ack; 464 465 /* Set up frame for RX. */ 466 frame->mii_stdelim = XL_MII_STARTDELIM; 467 frame->mii_opcode = XL_MII_READOP; 468 frame->mii_turnaround = 0; 469 frame->mii_data = 0; 470 471 /* Select register window 4. */ 472 XL_SEL_WIN(4); 473 474 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 475 /* Turn on data xmit. */ 476 MII_SET(XL_MII_DIR); 477 478 xl_mii_sync(sc); 479 480 /* Send command/address info. */ 481 xl_mii_send(sc, frame->mii_stdelim, 2); 482 xl_mii_send(sc, frame->mii_opcode, 2); 483 xl_mii_send(sc, frame->mii_phyaddr, 5); 484 xl_mii_send(sc, frame->mii_regaddr, 5); 485 486 /* Idle bit */ 487 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 488 MII_SET(XL_MII_CLK); 489 490 /* Turn off xmit. */ 491 MII_CLR(XL_MII_DIR); 492 493 /* Check for ack */ 494 MII_CLR(XL_MII_CLK); 495 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 496 MII_SET(XL_MII_CLK); 497 498 /* 499 * Now try reading data bits. If the ack failed, we still 500 * need to clock through 16 cycles to keep the PHY(s) in sync. 501 */ 502 if (ack) { 503 for (i = 0; i < 16; i++) { 504 MII_CLR(XL_MII_CLK); 505 MII_SET(XL_MII_CLK); 506 } 507 goto fail; 508 } 509 510 for (i = 0x8000; i; i >>= 1) { 511 MII_CLR(XL_MII_CLK); 512 if (!ack) { 513 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 514 frame->mii_data |= i; 515 } 516 MII_SET(XL_MII_CLK); 517 } 518 519 fail: 520 MII_CLR(XL_MII_CLK); 521 MII_SET(XL_MII_CLK); 522 523 return (ack ? 1 : 0); 524 } 525 526 /* 527 * Write to a PHY register through the MII. 528 */ 529 static int 530 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame) 531 { 532 533 /* Set up frame for TX. */ 534 frame->mii_stdelim = XL_MII_STARTDELIM; 535 frame->mii_opcode = XL_MII_WRITEOP; 536 frame->mii_turnaround = XL_MII_TURNAROUND; 537 538 /* Select the window 4. */ 539 XL_SEL_WIN(4); 540 541 /* Turn on data output. */ 542 MII_SET(XL_MII_DIR); 543 544 xl_mii_sync(sc); 545 546 xl_mii_send(sc, frame->mii_stdelim, 2); 547 xl_mii_send(sc, frame->mii_opcode, 2); 548 xl_mii_send(sc, frame->mii_phyaddr, 5); 549 xl_mii_send(sc, frame->mii_regaddr, 5); 550 xl_mii_send(sc, frame->mii_turnaround, 2); 551 xl_mii_send(sc, frame->mii_data, 16); 552 553 /* Idle bit. */ 554 MII_SET(XL_MII_CLK); 555 MII_CLR(XL_MII_CLK); 556 557 /* Turn off xmit. */ 558 MII_CLR(XL_MII_DIR); 559 560 return (0); 561 } 562 563 static int 564 xl_miibus_readreg(device_t dev, int phy, int reg) 565 { 566 struct xl_softc *sc; 567 struct xl_mii_frame frame; 568 569 sc = device_get_softc(dev); 570 571 /* 572 * Pretend that PHYs are only available at MII address 24. 573 * This is to guard against problems with certain 3Com ASIC 574 * revisions that incorrectly map the internal transceiver 575 * control registers at all MII addresses. This can cause 576 * the miibus code to attach the same PHY several times over. 577 */ 578 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24) 579 return (0); 580 581 bzero((char *)&frame, sizeof(frame)); 582 frame.mii_phyaddr = phy; 583 frame.mii_regaddr = reg; 584 585 xl_mii_readreg(sc, &frame); 586 587 return (frame.mii_data); 588 } 589 590 static int 591 xl_miibus_writereg(device_t dev, int phy, int reg, int data) 592 { 593 struct xl_softc *sc; 594 struct xl_mii_frame frame; 595 596 sc = device_get_softc(dev); 597 598 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24) 599 return (0); 600 601 bzero((char *)&frame, sizeof(frame)); 602 frame.mii_phyaddr = phy; 603 frame.mii_regaddr = reg; 604 frame.mii_data = data; 605 606 xl_mii_writereg(sc, &frame); 607 608 return (0); 609 } 610 611 static void 612 xl_miibus_statchg(device_t dev) 613 { 614 struct xl_softc *sc; 615 struct mii_data *mii; 616 617 sc = device_get_softc(dev); 618 mii = device_get_softc(sc->xl_miibus); 619 620 xl_setcfg(sc); 621 622 /* Set ASIC's duplex mode to match the PHY. */ 623 XL_SEL_WIN(3); 624 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 625 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 626 else 627 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 628 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 629 } 630 631 /* 632 * Special support for the 3c905B-COMBO. This card has 10/100 support 633 * plus BNC and AUI ports. This means we will have both an miibus attached 634 * plus some non-MII media settings. In order to allow this, we have to 635 * add the extra media to the miibus's ifmedia struct, but we can't do 636 * that during xl_attach() because the miibus hasn't been attached yet. 637 * So instead, we wait until the miibus probe/attach is done, at which 638 * point we will get a callback telling is that it's safe to add our 639 * extra media. 640 */ 641 static void 642 xl_miibus_mediainit(device_t dev) 643 { 644 struct xl_softc *sc; 645 struct mii_data *mii; 646 struct ifmedia *ifm; 647 648 sc = device_get_softc(dev); 649 mii = device_get_softc(sc->xl_miibus); 650 ifm = &mii->mii_media; 651 652 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) { 653 /* 654 * Check for a 10baseFL board in disguise. 655 */ 656 if (sc->xl_type == XL_TYPE_905B && 657 sc->xl_media == XL_MEDIAOPT_10FL) { 658 if (bootverbose) 659 if_printf(sc->xl_ifp, 660 "found 10baseFL\n"); 661 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL); 662 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0, 663 NULL); 664 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 665 ifmedia_add(ifm, 666 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL); 667 } else { 668 if (bootverbose) 669 if_printf(sc->xl_ifp, "found AUI\n"); 670 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL); 671 } 672 } 673 674 if (sc->xl_media & XL_MEDIAOPT_BNC) { 675 if (bootverbose) 676 if_printf(sc->xl_ifp, "found BNC\n"); 677 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL); 678 } 679 } 680 681 /* 682 * The EEPROM is slow: give it time to come ready after issuing 683 * it a command. 684 */ 685 static int 686 xl_eeprom_wait(struct xl_softc *sc) 687 { 688 int i; 689 690 for (i = 0; i < 100; i++) { 691 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 692 DELAY(162); 693 else 694 break; 695 } 696 697 if (i == 100) { 698 if_printf(sc->xl_ifp, "eeprom failed to come ready\n"); 699 return (1); 700 } 701 702 return (0); 703 } 704 705 /* 706 * Read a sequence of words from the EEPROM. Note that ethernet address 707 * data is stored in the EEPROM in network byte order. 708 */ 709 static int 710 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 711 { 712 int err = 0, i; 713 u_int16_t word = 0, *ptr; 714 715 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 716 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 717 /* 718 * XXX: WARNING! DANGER! 719 * It's easy to accidentally overwrite the rom content! 720 * Note: the 3c575 uses 8bit EEPROM offsets. 721 */ 722 XL_SEL_WIN(0); 723 724 if (xl_eeprom_wait(sc)) 725 return (1); 726 727 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 728 off += 0x30; 729 730 for (i = 0; i < cnt; i++) { 731 if (sc->xl_flags & XL_FLAG_8BITROM) 732 CSR_WRITE_2(sc, XL_W0_EE_CMD, 733 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 734 else 735 CSR_WRITE_2(sc, XL_W0_EE_CMD, 736 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 737 err = xl_eeprom_wait(sc); 738 if (err) 739 break; 740 word = CSR_READ_2(sc, XL_W0_EE_DATA); 741 ptr = (u_int16_t *)(dest + (i * 2)); 742 if (swap) 743 *ptr = ntohs(word); 744 else 745 *ptr = word; 746 } 747 748 return (err ? 1 : 0); 749 } 750 751 /* 752 * NICs older than the 3c905B have only one multicast option, which 753 * is to enable reception of all multicast frames. 754 */ 755 static void 756 xl_setmulti(struct xl_softc *sc) 757 { 758 struct ifnet *ifp = sc->xl_ifp; 759 struct ifmultiaddr *ifma; 760 u_int8_t rxfilt; 761 int mcnt = 0; 762 763 XL_LOCK_ASSERT(sc); 764 765 XL_SEL_WIN(5); 766 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 767 768 if (ifp->if_flags & IFF_ALLMULTI) { 769 rxfilt |= XL_RXFILTER_ALLMULTI; 770 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 771 return; 772 } 773 774 IF_ADDR_LOCK(ifp); 775 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 776 mcnt++; 777 IF_ADDR_UNLOCK(ifp); 778 779 if (mcnt) 780 rxfilt |= XL_RXFILTER_ALLMULTI; 781 else 782 rxfilt &= ~XL_RXFILTER_ALLMULTI; 783 784 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 785 } 786 787 /* 788 * 3c905B adapters have a hash filter that we can program. 789 */ 790 static void 791 xl_setmulti_hash(struct xl_softc *sc) 792 { 793 struct ifnet *ifp = sc->xl_ifp; 794 int h = 0, i; 795 struct ifmultiaddr *ifma; 796 u_int8_t rxfilt; 797 int mcnt = 0; 798 799 XL_LOCK_ASSERT(sc); 800 801 XL_SEL_WIN(5); 802 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 803 804 if (ifp->if_flags & IFF_ALLMULTI) { 805 rxfilt |= XL_RXFILTER_ALLMULTI; 806 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 807 return; 808 } else 809 rxfilt &= ~XL_RXFILTER_ALLMULTI; 810 811 /* first, zot all the existing hash bits */ 812 for (i = 0; i < XL_HASHFILT_SIZE; i++) 813 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 814 815 /* now program new ones */ 816 IF_ADDR_LOCK(ifp); 817 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 818 if (ifma->ifma_addr->sa_family != AF_LINK) 819 continue; 820 /* 821 * Note: the 3c905B currently only supports a 64-bit hash 822 * table, which means we really only need 6 bits, but the 823 * manual indicates that future chip revisions will have a 824 * 256-bit hash table, hence the routine is set up to 825 * calculate 8 bits of position info in case we need it some 826 * day. 827 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have 828 * a 256 bit hash table. This means we have to use all 8 bits 829 * regardless. On older cards, the upper 2 bits will be 830 * ignored. Grrrr.... 831 */ 832 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 833 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 834 CSR_WRITE_2(sc, XL_COMMAND, 835 h | XL_CMD_RX_SET_HASH | XL_HASH_SET); 836 mcnt++; 837 } 838 IF_ADDR_UNLOCK(ifp); 839 840 if (mcnt) 841 rxfilt |= XL_RXFILTER_MULTIHASH; 842 else 843 rxfilt &= ~XL_RXFILTER_MULTIHASH; 844 845 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 846 } 847 848 #ifdef notdef 849 static void 850 xl_testpacket(struct xl_softc *sc) 851 { 852 struct mbuf *m; 853 struct ifnet *ifp = sc->xl_ifp; 854 855 MGETHDR(m, M_DONTWAIT, MT_DATA); 856 857 if (m == NULL) 858 return; 859 860 bcopy(&IFP2ENADDR(sc->xl_ifp), 861 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 862 bcopy(&IFP2ENADDR(sc->xl_ifp), 863 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 864 mtod(m, struct ether_header *)->ether_type = htons(3); 865 mtod(m, unsigned char *)[14] = 0; 866 mtod(m, unsigned char *)[15] = 0; 867 mtod(m, unsigned char *)[16] = 0xE3; 868 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 869 IFQ_ENQUEUE(&ifp->if_snd, m); 870 xl_start(ifp); 871 } 872 #endif 873 874 static void 875 xl_setcfg(struct xl_softc *sc) 876 { 877 u_int32_t icfg; 878 879 /*XL_LOCK_ASSERT(sc);*/ 880 881 XL_SEL_WIN(3); 882 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 883 icfg &= ~XL_ICFG_CONNECTOR_MASK; 884 if (sc->xl_media & XL_MEDIAOPT_MII || 885 sc->xl_media & XL_MEDIAOPT_BT4) 886 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 887 if (sc->xl_media & XL_MEDIAOPT_BTX) 888 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 889 890 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 891 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 892 } 893 894 static void 895 xl_setmode(struct xl_softc *sc, int media) 896 { 897 u_int32_t icfg; 898 u_int16_t mediastat; 899 char *pmsg = "", *dmsg = ""; 900 901 XL_LOCK_ASSERT(sc); 902 903 XL_SEL_WIN(4); 904 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 905 XL_SEL_WIN(3); 906 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 907 908 if (sc->xl_media & XL_MEDIAOPT_BT) { 909 if (IFM_SUBTYPE(media) == IFM_10_T) { 910 pmsg = "10baseT transceiver"; 911 sc->xl_xcvr = XL_XCVR_10BT; 912 icfg &= ~XL_ICFG_CONNECTOR_MASK; 913 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 914 mediastat |= XL_MEDIASTAT_LINKBEAT | 915 XL_MEDIASTAT_JABGUARD; 916 mediastat &= ~XL_MEDIASTAT_SQEENB; 917 } 918 } 919 920 if (sc->xl_media & XL_MEDIAOPT_BFX) { 921 if (IFM_SUBTYPE(media) == IFM_100_FX) { 922 pmsg = "100baseFX port"; 923 sc->xl_xcvr = XL_XCVR_100BFX; 924 icfg &= ~XL_ICFG_CONNECTOR_MASK; 925 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 926 mediastat |= XL_MEDIASTAT_LINKBEAT; 927 mediastat &= ~XL_MEDIASTAT_SQEENB; 928 } 929 } 930 931 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 932 if (IFM_SUBTYPE(media) == IFM_10_5) { 933 pmsg = "AUI port"; 934 sc->xl_xcvr = XL_XCVR_AUI; 935 icfg &= ~XL_ICFG_CONNECTOR_MASK; 936 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 937 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 938 XL_MEDIASTAT_JABGUARD); 939 mediastat |= ~XL_MEDIASTAT_SQEENB; 940 } 941 if (IFM_SUBTYPE(media) == IFM_10_FL) { 942 pmsg = "10baseFL transceiver"; 943 sc->xl_xcvr = XL_XCVR_AUI; 944 icfg &= ~XL_ICFG_CONNECTOR_MASK; 945 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 946 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 947 XL_MEDIASTAT_JABGUARD); 948 mediastat |= ~XL_MEDIASTAT_SQEENB; 949 } 950 } 951 952 if (sc->xl_media & XL_MEDIAOPT_BNC) { 953 if (IFM_SUBTYPE(media) == IFM_10_2) { 954 pmsg = "AUI port"; 955 sc->xl_xcvr = XL_XCVR_COAX; 956 icfg &= ~XL_ICFG_CONNECTOR_MASK; 957 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 958 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 959 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB); 960 } 961 } 962 963 if ((media & IFM_GMASK) == IFM_FDX || 964 IFM_SUBTYPE(media) == IFM_100_FX) { 965 dmsg = "full"; 966 XL_SEL_WIN(3); 967 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 968 } else { 969 dmsg = "half"; 970 XL_SEL_WIN(3); 971 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 972 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 973 } 974 975 if (IFM_SUBTYPE(media) == IFM_10_2) 976 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 977 else 978 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 979 980 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 981 XL_SEL_WIN(4); 982 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 983 984 DELAY(800); 985 XL_SEL_WIN(7); 986 987 if_printf(sc->xl_ifp, "selecting %s, %s duplex\n", pmsg, dmsg); 988 } 989 990 static void 991 xl_reset(struct xl_softc *sc) 992 { 993 register int i; 994 995 XL_LOCK_ASSERT(sc); 996 997 XL_SEL_WIN(0); 998 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 999 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 1000 XL_RESETOPT_DISADVFD:0)); 1001 1002 /* 1003 * If we're using memory mapped register mode, pause briefly 1004 * after issuing the reset command before trying to access any 1005 * other registers. With my 3c575C cardbus card, failing to do 1006 * this results in the system locking up while trying to poll 1007 * the command busy bit in the status register. 1008 */ 1009 if (sc->xl_flags & XL_FLAG_USE_MMIO) 1010 DELAY(100000); 1011 1012 for (i = 0; i < XL_TIMEOUT; i++) { 1013 DELAY(10); 1014 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 1015 break; 1016 } 1017 1018 if (i == XL_TIMEOUT) 1019 if_printf(sc->xl_ifp, "reset didn't complete\n"); 1020 1021 /* Reset TX and RX. */ 1022 /* Note: the RX reset takes an absurd amount of time 1023 * on newer versions of the Tornado chips such as those 1024 * on the 3c905CX and newer 3c908C cards. We wait an 1025 * extra amount of time so that xl_wait() doesn't complain 1026 * and annoy the users. 1027 */ 1028 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 1029 DELAY(100000); 1030 xl_wait(sc); 1031 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 1032 xl_wait(sc); 1033 1034 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 1035 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 1036 XL_SEL_WIN(2); 1037 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, 1038 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) | 1039 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ? 1040 XL_RESETOPT_INVERT_LED : 0) | 1041 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ? 1042 XL_RESETOPT_INVERT_MII : 0)); 1043 } 1044 1045 /* Wait a little while for the chip to get its brains in order. */ 1046 DELAY(100000); 1047 } 1048 1049 /* 1050 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1051 * IDs against our list and return a device name if we find a match. 1052 */ 1053 static int 1054 xl_probe(device_t dev) 1055 { 1056 struct xl_type *t; 1057 1058 t = xl_devs; 1059 1060 while (t->xl_name != NULL) { 1061 if ((pci_get_vendor(dev) == t->xl_vid) && 1062 (pci_get_device(dev) == t->xl_did)) { 1063 device_set_desc(dev, t->xl_name); 1064 return (BUS_PROBE_DEFAULT); 1065 } 1066 t++; 1067 } 1068 1069 return (ENXIO); 1070 } 1071 1072 /* 1073 * This routine is a kludge to work around possible hardware faults 1074 * or manufacturing defects that can cause the media options register 1075 * (or reset options register, as it's called for the first generation 1076 * 3c90x adapters) to return an incorrect result. I have encountered 1077 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1078 * which doesn't have any of the 'mediaopt' bits set. This screws up 1079 * the attach routine pretty badly because it doesn't know what media 1080 * to look for. If we find ourselves in this predicament, this routine 1081 * will try to guess the media options values and warn the user of a 1082 * possible manufacturing defect with his adapter/system/whatever. 1083 */ 1084 static void 1085 xl_mediacheck(struct xl_softc *sc) 1086 { 1087 1088 /* 1089 * If some of the media options bits are set, assume they are 1090 * correct. If not, try to figure it out down below. 1091 * XXX I should check for 10baseFL, but I don't have an adapter 1092 * to test with. 1093 */ 1094 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1095 /* 1096 * Check the XCVR value. If it's not in the normal range 1097 * of values, we need to fake it up here. 1098 */ 1099 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1100 return; 1101 else { 1102 if_printf(sc->xl_ifp, 1103 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr); 1104 if_printf(sc->xl_ifp, 1105 "choosing new default based on card type\n"); 1106 } 1107 } else { 1108 if (sc->xl_type == XL_TYPE_905B && 1109 sc->xl_media & XL_MEDIAOPT_10FL) 1110 return; 1111 if_printf(sc->xl_ifp, 1112 "WARNING: no media options bits set in the media options register!!\n"); 1113 if_printf(sc->xl_ifp, 1114 "this could be a manufacturing defect in your adapter or system\n"); 1115 if_printf(sc->xl_ifp, 1116 "attempting to guess media type; you should probably consult your vendor\n"); 1117 } 1118 1119 xl_choose_xcvr(sc, 1); 1120 } 1121 1122 static void 1123 xl_choose_xcvr(struct xl_softc *sc, int verbose) 1124 { 1125 u_int16_t devid; 1126 1127 /* 1128 * Read the device ID from the EEPROM. 1129 * This is what's loaded into the PCI device ID register, so it has 1130 * to be correct otherwise we wouldn't have gotten this far. 1131 */ 1132 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1133 1134 switch (devid) { 1135 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1136 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1137 sc->xl_media = XL_MEDIAOPT_BT; 1138 sc->xl_xcvr = XL_XCVR_10BT; 1139 if (verbose) 1140 if_printf(sc->xl_ifp, 1141 "guessing 10BaseT transceiver\n"); 1142 break; 1143 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1144 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1145 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1146 sc->xl_xcvr = XL_XCVR_10BT; 1147 if (verbose) 1148 if_printf(sc->xl_ifp, 1149 "guessing COMBO (AUI/BNC/TP)\n"); 1150 break; 1151 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1152 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1153 sc->xl_xcvr = XL_XCVR_10BT; 1154 if (verbose) 1155 if_printf(sc->xl_ifp, "guessing TPC (BNC/TP)\n"); 1156 break; 1157 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1158 sc->xl_media = XL_MEDIAOPT_10FL; 1159 sc->xl_xcvr = XL_XCVR_AUI; 1160 if (verbose) 1161 if_printf(sc->xl_ifp, "guessing 10baseFL\n"); 1162 break; 1163 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1164 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1165 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1166 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1167 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1168 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1169 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1170 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1171 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1172 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1173 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1174 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */ 1175 sc->xl_media = XL_MEDIAOPT_MII; 1176 sc->xl_xcvr = XL_XCVR_MII; 1177 if (verbose) 1178 if_printf(sc->xl_ifp, "guessing MII\n"); 1179 break; 1180 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1181 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1182 sc->xl_media = XL_MEDIAOPT_BT4; 1183 sc->xl_xcvr = XL_XCVR_MII; 1184 if (verbose) 1185 if_printf(sc->xl_ifp, 1186 "guessing 100baseT4/MII\n"); 1187 break; 1188 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1189 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1190 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1191 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1192 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1193 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1194 sc->xl_media = XL_MEDIAOPT_BTX; 1195 sc->xl_xcvr = XL_XCVR_AUTO; 1196 if (verbose) 1197 if_printf(sc->xl_ifp, 1198 "guessing 10/100 internal\n"); 1199 break; 1200 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1201 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1202 sc->xl_xcvr = XL_XCVR_AUTO; 1203 if (verbose) 1204 if_printf(sc->xl_ifp, 1205 "guessing 10/100 plus BNC/AUI\n"); 1206 break; 1207 default: 1208 if_printf(sc->xl_ifp, 1209 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1210 sc->xl_media = XL_MEDIAOPT_BT; 1211 break; 1212 } 1213 } 1214 1215 /* 1216 * Attach the interface. Allocate softc structures, do ifmedia 1217 * setup and ethernet/BPF attach. 1218 */ 1219 static int 1220 xl_attach(device_t dev) 1221 { 1222 u_char eaddr[ETHER_ADDR_LEN]; 1223 u_int16_t xcvr[2]; 1224 struct xl_softc *sc; 1225 struct ifnet *ifp; 1226 int media; 1227 int unit, error = 0, rid, res; 1228 uint16_t did; 1229 1230 sc = device_get_softc(dev); 1231 unit = device_get_unit(dev); 1232 1233 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1234 MTX_DEF); 1235 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1236 1237 did = pci_get_device(dev); 1238 1239 sc->xl_flags = 0; 1240 if (did == TC_DEVICEID_HURRICANE_555) 1241 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1242 if (did == TC_DEVICEID_HURRICANE_556 || 1243 did == TC_DEVICEID_HURRICANE_556B) 1244 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1245 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1246 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1247 if (did == TC_DEVICEID_HURRICANE_555 || 1248 did == TC_DEVICEID_HURRICANE_556) 1249 sc->xl_flags |= XL_FLAG_8BITROM; 1250 if (did == TC_DEVICEID_HURRICANE_556B) 1251 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1252 1253 if (did == TC_DEVICEID_HURRICANE_575A || 1254 did == TC_DEVICEID_HURRICANE_575B || 1255 did == TC_DEVICEID_HURRICANE_575C || 1256 did == TC_DEVICEID_HURRICANE_656B || 1257 did == TC_DEVICEID_TORNADO_656C) 1258 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1259 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM; 1260 if (did == TC_DEVICEID_HURRICANE_656) 1261 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1262 if (did == TC_DEVICEID_HURRICANE_575B) 1263 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1264 if (did == TC_DEVICEID_HURRICANE_575C) 1265 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1266 if (did == TC_DEVICEID_TORNADO_656C) 1267 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1268 if (did == TC_DEVICEID_HURRICANE_656 || 1269 did == TC_DEVICEID_HURRICANE_656B) 1270 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1271 XL_FLAG_INVERT_LED_PWR; 1272 if (did == TC_DEVICEID_TORNADO_10_100BT_920B || 1273 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM) 1274 sc->xl_flags |= XL_FLAG_PHYOK; 1275 1276 switch (did) { 1277 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1278 case TC_DEVICEID_HURRICANE_575A: 1279 case TC_DEVICEID_HURRICANE_575B: 1280 case TC_DEVICEID_HURRICANE_575C: 1281 sc->xl_flags |= XL_FLAG_NO_MMIO; 1282 break; 1283 default: 1284 break; 1285 } 1286 1287 /* 1288 * Map control/status registers. 1289 */ 1290 pci_enable_busmaster(dev); 1291 1292 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) { 1293 rid = XL_PCI_LOMEM; 1294 res = SYS_RES_MEMORY; 1295 1296 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1297 } 1298 1299 if (sc->xl_res != NULL) { 1300 sc->xl_flags |= XL_FLAG_USE_MMIO; 1301 if (bootverbose) 1302 device_printf(dev, "using memory mapped I/O\n"); 1303 } else { 1304 rid = XL_PCI_LOIO; 1305 res = SYS_RES_IOPORT; 1306 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1307 if (sc->xl_res == NULL) { 1308 device_printf(dev, "couldn't map ports/memory\n"); 1309 error = ENXIO; 1310 goto fail; 1311 } 1312 if (bootverbose) 1313 device_printf(dev, "using port I/O\n"); 1314 } 1315 1316 sc->xl_btag = rman_get_bustag(sc->xl_res); 1317 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1318 1319 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1320 rid = XL_PCI_FUNCMEM; 1321 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1322 RF_ACTIVE); 1323 1324 if (sc->xl_fres == NULL) { 1325 device_printf(dev, "couldn't map ports/memory\n"); 1326 error = ENXIO; 1327 goto fail; 1328 } 1329 1330 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1331 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1332 } 1333 1334 /* Allocate interrupt */ 1335 rid = 0; 1336 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1337 RF_SHAREABLE | RF_ACTIVE); 1338 if (sc->xl_irq == NULL) { 1339 device_printf(dev, "couldn't map interrupt\n"); 1340 error = ENXIO; 1341 goto fail; 1342 } 1343 1344 /* Initialize interface name. */ 1345 ifp = sc->xl_ifp = if_alloc(IFT_ETHER); 1346 if (ifp == NULL) { 1347 device_printf(dev, "can not if_alloc()\n"); 1348 error = ENOSPC; 1349 goto fail; 1350 } 1351 ifp->if_softc = sc; 1352 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1353 1354 /* Reset the adapter. */ 1355 XL_LOCK(sc); 1356 xl_reset(sc); 1357 XL_UNLOCK(sc); 1358 1359 /* 1360 * Get station address from the EEPROM. 1361 */ 1362 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1363 device_printf(dev, "failed to read station address\n"); 1364 error = ENXIO; 1365 goto fail; 1366 } 1367 1368 sc->xl_unit = unit; 1369 callout_init_mtx(&sc->xl_stat_callout, &sc->xl_mtx, 0); 1370 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc); 1371 1372 /* 1373 * Now allocate a tag for the DMA descriptor lists and a chunk 1374 * of DMA-able memory based on the tag. Also obtain the DMA 1375 * addresses of the RX and TX ring, which we'll need later. 1376 * All of our lists are allocated as a contiguous block 1377 * of memory. 1378 */ 1379 error = bus_dma_tag_create(NULL, 8, 0, 1380 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1381 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL, 1382 &sc->xl_ldata.xl_rx_tag); 1383 if (error) { 1384 device_printf(dev, "failed to allocate rx dma tag\n"); 1385 goto fail; 1386 } 1387 1388 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1389 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1390 &sc->xl_ldata.xl_rx_dmamap); 1391 if (error) { 1392 device_printf(dev, "no memory for rx list buffers!\n"); 1393 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1394 sc->xl_ldata.xl_rx_tag = NULL; 1395 goto fail; 1396 } 1397 1398 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1399 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1400 XL_RX_LIST_SZ, xl_dma_map_addr, 1401 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1402 if (error) { 1403 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1404 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1405 sc->xl_ldata.xl_rx_dmamap); 1406 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1407 sc->xl_ldata.xl_rx_tag = NULL; 1408 goto fail; 1409 } 1410 1411 error = bus_dma_tag_create(NULL, 8, 0, 1412 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1413 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL, 1414 &sc->xl_ldata.xl_tx_tag); 1415 if (error) { 1416 device_printf(dev, "failed to allocate tx dma tag\n"); 1417 goto fail; 1418 } 1419 1420 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1421 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1422 &sc->xl_ldata.xl_tx_dmamap); 1423 if (error) { 1424 device_printf(dev, "no memory for list buffers!\n"); 1425 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1426 sc->xl_ldata.xl_tx_tag = NULL; 1427 goto fail; 1428 } 1429 1430 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1431 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1432 XL_TX_LIST_SZ, xl_dma_map_addr, 1433 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1434 if (error) { 1435 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1436 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1437 sc->xl_ldata.xl_tx_dmamap); 1438 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1439 sc->xl_ldata.xl_tx_tag = NULL; 1440 goto fail; 1441 } 1442 1443 /* 1444 * Allocate a DMA tag for the mapping of mbufs. 1445 */ 1446 error = bus_dma_tag_create(NULL, 1, 0, 1447 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1448 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL, 1449 NULL, &sc->xl_mtag); 1450 if (error) { 1451 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1452 goto fail; 1453 } 1454 1455 /* We need a spare DMA map for the RX ring. */ 1456 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1457 if (error) 1458 goto fail; 1459 1460 /* 1461 * Figure out the card type. 3c905B adapters have the 1462 * 'supportsNoTxLength' bit set in the capabilities 1463 * word in the EEPROM. 1464 * Note: my 3c575C cardbus card lies. It returns a value 1465 * of 0x1578 for its capabilities word, which is somewhat 1466 * nonsensical. Another way to distinguish a 3c90x chip 1467 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1468 * bit. This will only be set for 3c90x boomerage chips. 1469 */ 1470 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1471 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1472 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1473 sc->xl_type = XL_TYPE_905B; 1474 else 1475 sc->xl_type = XL_TYPE_90X; 1476 1477 /* Set the TX start threshold for best performance. */ 1478 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 1479 1480 ifp->if_mtu = ETHERMTU; 1481 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1482 ifp->if_ioctl = xl_ioctl; 1483 ifp->if_capabilities = IFCAP_VLAN_MTU; 1484 if (sc->xl_type == XL_TYPE_905B) { 1485 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1486 #ifdef XL905B_TXCSUM_BROKEN 1487 ifp->if_capabilities |= IFCAP_RXCSUM; 1488 #else 1489 ifp->if_capabilities |= IFCAP_HWCSUM; 1490 #endif 1491 } 1492 ifp->if_capenable = ifp->if_capabilities; 1493 #ifdef DEVICE_POLLING 1494 ifp->if_capabilities |= IFCAP_POLLING; 1495 #endif 1496 ifp->if_start = xl_start; 1497 ifp->if_watchdog = xl_watchdog; 1498 ifp->if_init = xl_init; 1499 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1500 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1; 1501 IFQ_SET_READY(&ifp->if_snd); 1502 1503 /* 1504 * Now we have to see what sort of media we have. 1505 * This includes probing for an MII interace and a 1506 * possible PHY. 1507 */ 1508 XL_SEL_WIN(3); 1509 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1510 if (bootverbose) 1511 device_printf(dev, "media options word: %x\n", sc->xl_media); 1512 1513 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1514 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1515 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1516 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1517 1518 xl_mediacheck(sc); 1519 1520 if (sc->xl_media & XL_MEDIAOPT_MII || 1521 sc->xl_media & XL_MEDIAOPT_BTX || 1522 sc->xl_media & XL_MEDIAOPT_BT4) { 1523 if (bootverbose) 1524 device_printf(dev, "found MII/AUTO\n"); 1525 xl_setcfg(sc); 1526 if (mii_phy_probe(dev, &sc->xl_miibus, 1527 xl_ifmedia_upd, xl_ifmedia_sts)) { 1528 device_printf(dev, "no PHY found!\n"); 1529 error = ENXIO; 1530 goto fail; 1531 } 1532 goto done; 1533 } 1534 1535 /* 1536 * Sanity check. If the user has selected "auto" and this isn't 1537 * a 10/100 card of some kind, we need to force the transceiver 1538 * type to something sane. 1539 */ 1540 if (sc->xl_xcvr == XL_XCVR_AUTO) 1541 xl_choose_xcvr(sc, bootverbose); 1542 1543 /* 1544 * Do ifmedia setup. 1545 */ 1546 if (sc->xl_media & XL_MEDIAOPT_BT) { 1547 if (bootverbose) 1548 device_printf(dev, "found 10baseT\n"); 1549 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1550 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1551 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1552 ifmedia_add(&sc->ifmedia, 1553 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1554 } 1555 1556 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1557 /* 1558 * Check for a 10baseFL board in disguise. 1559 */ 1560 if (sc->xl_type == XL_TYPE_905B && 1561 sc->xl_media == XL_MEDIAOPT_10FL) { 1562 if (bootverbose) 1563 device_printf(dev, "found 10baseFL\n"); 1564 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1565 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1566 0, NULL); 1567 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1568 ifmedia_add(&sc->ifmedia, 1569 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1570 } else { 1571 if (bootverbose) 1572 device_printf(dev, "found AUI\n"); 1573 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1574 } 1575 } 1576 1577 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1578 if (bootverbose) 1579 device_printf(dev, "found BNC\n"); 1580 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1581 } 1582 1583 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1584 if (bootverbose) 1585 device_printf(dev, "found 100baseFX\n"); 1586 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1587 } 1588 1589 media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1590 xl_choose_media(sc, &media); 1591 1592 if (sc->xl_miibus == NULL) 1593 ifmedia_set(&sc->ifmedia, media); 1594 1595 done: 1596 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1597 XL_SEL_WIN(0); 1598 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1599 } 1600 1601 /* 1602 * Call MI attach routine. 1603 */ 1604 ether_ifattach(ifp, eaddr); 1605 1606 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1607 xl_intr, sc, &sc->xl_intrhand); 1608 if (error) { 1609 device_printf(dev, "couldn't set up irq\n"); 1610 ether_ifdetach(ifp); 1611 goto fail; 1612 } 1613 1614 fail: 1615 if (error) 1616 xl_detach(dev); 1617 1618 return (error); 1619 } 1620 1621 /* 1622 * Choose a default media. 1623 * XXX This is a leaf function only called by xl_attach() and 1624 * acquires/releases the non-recursible driver mutex to 1625 * satisfy lock assertions. 1626 */ 1627 static void 1628 xl_choose_media(struct xl_softc *sc, int *media) 1629 { 1630 1631 XL_LOCK(sc); 1632 1633 switch (sc->xl_xcvr) { 1634 case XL_XCVR_10BT: 1635 *media = IFM_ETHER|IFM_10_T; 1636 xl_setmode(sc, *media); 1637 break; 1638 case XL_XCVR_AUI: 1639 if (sc->xl_type == XL_TYPE_905B && 1640 sc->xl_media == XL_MEDIAOPT_10FL) { 1641 *media = IFM_ETHER|IFM_10_FL; 1642 xl_setmode(sc, *media); 1643 } else { 1644 *media = IFM_ETHER|IFM_10_5; 1645 xl_setmode(sc, *media); 1646 } 1647 break; 1648 case XL_XCVR_COAX: 1649 *media = IFM_ETHER|IFM_10_2; 1650 xl_setmode(sc, *media); 1651 break; 1652 case XL_XCVR_AUTO: 1653 case XL_XCVR_100BTX: 1654 case XL_XCVR_MII: 1655 /* Chosen by miibus */ 1656 break; 1657 case XL_XCVR_100BFX: 1658 *media = IFM_ETHER|IFM_100_FX; 1659 break; 1660 default: 1661 if_printf(sc->xl_ifp, "unknown XCVR type: %d\n", 1662 sc->xl_xcvr); 1663 /* 1664 * This will probably be wrong, but it prevents 1665 * the ifmedia code from panicking. 1666 */ 1667 *media = IFM_ETHER|IFM_10_T; 1668 break; 1669 } 1670 1671 XL_UNLOCK(sc); 1672 } 1673 1674 /* 1675 * Shutdown hardware and free up resources. This can be called any 1676 * time after the mutex has been initialized. It is called in both 1677 * the error case in attach and the normal detach case so it needs 1678 * to be careful about only freeing resources that have actually been 1679 * allocated. 1680 */ 1681 static int 1682 xl_detach(device_t dev) 1683 { 1684 struct xl_softc *sc; 1685 struct ifnet *ifp; 1686 int rid, res; 1687 1688 sc = device_get_softc(dev); 1689 ifp = sc->xl_ifp; 1690 1691 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized")); 1692 1693 #ifdef DEVICE_POLLING 1694 if (ifp && ifp->if_capenable & IFCAP_POLLING) 1695 ether_poll_deregister(ifp); 1696 #endif 1697 1698 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1699 rid = XL_PCI_LOMEM; 1700 res = SYS_RES_MEMORY; 1701 } else { 1702 rid = XL_PCI_LOIO; 1703 res = SYS_RES_IOPORT; 1704 } 1705 1706 /* These should only be active if attach succeeded */ 1707 if (device_is_attached(dev)) { 1708 XL_LOCK(sc); 1709 xl_reset(sc); 1710 xl_stop(sc); 1711 XL_UNLOCK(sc); 1712 taskqueue_drain(taskqueue_swi, &sc->xl_task); 1713 callout_drain(&sc->xl_stat_callout); 1714 ether_ifdetach(ifp); 1715 } 1716 if (ifp) 1717 if_free(ifp); 1718 if (sc->xl_miibus) 1719 device_delete_child(dev, sc->xl_miibus); 1720 bus_generic_detach(dev); 1721 ifmedia_removeall(&sc->ifmedia); 1722 1723 if (sc->xl_intrhand) 1724 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1725 if (sc->xl_irq) 1726 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1727 if (sc->xl_fres != NULL) 1728 bus_release_resource(dev, SYS_RES_MEMORY, 1729 XL_PCI_FUNCMEM, sc->xl_fres); 1730 if (sc->xl_res) 1731 bus_release_resource(dev, res, rid, sc->xl_res); 1732 1733 if (sc->xl_mtag) { 1734 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1735 bus_dma_tag_destroy(sc->xl_mtag); 1736 } 1737 if (sc->xl_ldata.xl_rx_tag) { 1738 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1739 sc->xl_ldata.xl_rx_dmamap); 1740 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1741 sc->xl_ldata.xl_rx_dmamap); 1742 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1743 } 1744 if (sc->xl_ldata.xl_tx_tag) { 1745 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1746 sc->xl_ldata.xl_tx_dmamap); 1747 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1748 sc->xl_ldata.xl_tx_dmamap); 1749 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1750 } 1751 1752 mtx_destroy(&sc->xl_mtx); 1753 1754 return (0); 1755 } 1756 1757 /* 1758 * Initialize the transmit descriptors. 1759 */ 1760 static int 1761 xl_list_tx_init(struct xl_softc *sc) 1762 { 1763 struct xl_chain_data *cd; 1764 struct xl_list_data *ld; 1765 int error, i; 1766 1767 XL_LOCK_ASSERT(sc); 1768 1769 cd = &sc->xl_cdata; 1770 ld = &sc->xl_ldata; 1771 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1772 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1773 error = bus_dmamap_create(sc->xl_mtag, 0, 1774 &cd->xl_tx_chain[i].xl_map); 1775 if (error) 1776 return (error); 1777 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1778 i * sizeof(struct xl_list); 1779 if (i == (XL_TX_LIST_CNT - 1)) 1780 cd->xl_tx_chain[i].xl_next = NULL; 1781 else 1782 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1783 } 1784 1785 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1786 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1787 1788 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1789 return (0); 1790 } 1791 1792 /* 1793 * Initialize the transmit descriptors. 1794 */ 1795 static int 1796 xl_list_tx_init_90xB(struct xl_softc *sc) 1797 { 1798 struct xl_chain_data *cd; 1799 struct xl_list_data *ld; 1800 int error, i; 1801 1802 XL_LOCK_ASSERT(sc); 1803 1804 cd = &sc->xl_cdata; 1805 ld = &sc->xl_ldata; 1806 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1807 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1808 error = bus_dmamap_create(sc->xl_mtag, 0, 1809 &cd->xl_tx_chain[i].xl_map); 1810 if (error) 1811 return (error); 1812 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1813 i * sizeof(struct xl_list); 1814 if (i == (XL_TX_LIST_CNT - 1)) 1815 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1816 else 1817 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1818 if (i == 0) 1819 cd->xl_tx_chain[i].xl_prev = 1820 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1821 else 1822 cd->xl_tx_chain[i].xl_prev = 1823 &cd->xl_tx_chain[i - 1]; 1824 } 1825 1826 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1827 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1828 1829 cd->xl_tx_prod = 1; 1830 cd->xl_tx_cons = 1; 1831 cd->xl_tx_cnt = 0; 1832 1833 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1834 return (0); 1835 } 1836 1837 /* 1838 * Initialize the RX descriptors and allocate mbufs for them. Note that 1839 * we arrange the descriptors in a closed ring, so that the last descriptor 1840 * points back to the first. 1841 */ 1842 static int 1843 xl_list_rx_init(struct xl_softc *sc) 1844 { 1845 struct xl_chain_data *cd; 1846 struct xl_list_data *ld; 1847 int error, i, next; 1848 u_int32_t nextptr; 1849 1850 XL_LOCK_ASSERT(sc); 1851 1852 cd = &sc->xl_cdata; 1853 ld = &sc->xl_ldata; 1854 1855 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1856 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1857 error = bus_dmamap_create(sc->xl_mtag, 0, 1858 &cd->xl_rx_chain[i].xl_map); 1859 if (error) 1860 return (error); 1861 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1862 if (error) 1863 return (error); 1864 if (i == (XL_RX_LIST_CNT - 1)) 1865 next = 0; 1866 else 1867 next = i + 1; 1868 nextptr = ld->xl_rx_dmaaddr + 1869 next * sizeof(struct xl_list_onefrag); 1870 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1871 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1872 } 1873 1874 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1875 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1876 1877 return (0); 1878 } 1879 1880 /* 1881 * Initialize an RX descriptor and attach an MBUF cluster. 1882 * If we fail to do so, we need to leave the old mbuf and 1883 * the old DMA map untouched so that it can be reused. 1884 */ 1885 static int 1886 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) 1887 { 1888 struct mbuf *m_new = NULL; 1889 bus_dmamap_t map; 1890 int error; 1891 u_int32_t baddr; 1892 1893 XL_LOCK_ASSERT(sc); 1894 1895 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1896 if (m_new == NULL) 1897 return (ENOBUFS); 1898 1899 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1900 1901 /* Force longword alignment for packet payload. */ 1902 m_adj(m_new, ETHER_ALIGN); 1903 1904 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new, 1905 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT); 1906 if (error) { 1907 m_freem(m_new); 1908 if_printf(sc->xl_ifp, "can't map mbuf (error %d)\n", 1909 error); 1910 return (error); 1911 } 1912 1913 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1914 map = c->xl_map; 1915 c->xl_map = sc->xl_tmpmap; 1916 sc->xl_tmpmap = map; 1917 c->xl_mbuf = m_new; 1918 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 1919 c->xl_ptr->xl_status = 0; 1920 c->xl_ptr->xl_frag.xl_addr = htole32(baddr); 1921 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 1922 return (0); 1923 } 1924 1925 static int 1926 xl_rx_resync(struct xl_softc *sc) 1927 { 1928 struct xl_chain_onefrag *pos; 1929 int i; 1930 1931 XL_LOCK_ASSERT(sc); 1932 1933 pos = sc->xl_cdata.xl_rx_head; 1934 1935 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1936 if (pos->xl_ptr->xl_status) 1937 break; 1938 pos = pos->xl_next; 1939 } 1940 1941 if (i == XL_RX_LIST_CNT) 1942 return (0); 1943 1944 sc->xl_cdata.xl_rx_head = pos; 1945 1946 return (EAGAIN); 1947 } 1948 1949 /* 1950 * A frame has been uploaded: pass the resulting mbuf chain up to 1951 * the higher level protocols. 1952 */ 1953 static void 1954 xl_rxeof(struct xl_softc *sc) 1955 { 1956 struct mbuf *m; 1957 struct ifnet *ifp = sc->xl_ifp; 1958 struct xl_chain_onefrag *cur_rx; 1959 int total_len = 0; 1960 u_int32_t rxstat; 1961 1962 XL_LOCK_ASSERT(sc); 1963 again: 1964 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 1965 BUS_DMASYNC_POSTREAD); 1966 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 1967 #ifdef DEVICE_POLLING 1968 if (ifp->if_capenable & IFCAP_POLLING) { 1969 if (sc->rxcycles <= 0) 1970 break; 1971 sc->rxcycles--; 1972 } 1973 #endif 1974 cur_rx = sc->xl_cdata.xl_rx_head; 1975 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1976 total_len = rxstat & XL_RXSTAT_LENMASK; 1977 1978 /* 1979 * Since we have told the chip to allow large frames, 1980 * we need to trap giant frame errors in software. We allow 1981 * a little more than the normal frame size to account for 1982 * frames with VLAN tags. 1983 */ 1984 if (total_len > XL_MAX_FRAMELEN) 1985 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 1986 1987 /* 1988 * If an error occurs, update stats, clear the 1989 * status word and leave the mbuf cluster in place: 1990 * it should simply get re-used next time this descriptor 1991 * comes up in the ring. 1992 */ 1993 if (rxstat & XL_RXSTAT_UP_ERROR) { 1994 ifp->if_ierrors++; 1995 cur_rx->xl_ptr->xl_status = 0; 1996 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1997 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1998 continue; 1999 } 2000 2001 /* 2002 * If the error bit was not set, the upload complete 2003 * bit should be set which means we have a valid packet. 2004 * If not, something truly strange has happened. 2005 */ 2006 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 2007 if_printf(ifp, 2008 "bad receive status -- packet dropped\n"); 2009 ifp->if_ierrors++; 2010 cur_rx->xl_ptr->xl_status = 0; 2011 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2012 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2013 continue; 2014 } 2015 2016 /* No errors; receive the packet. */ 2017 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 2018 BUS_DMASYNC_POSTREAD); 2019 m = cur_rx->xl_mbuf; 2020 2021 /* 2022 * Try to conjure up a new mbuf cluster. If that 2023 * fails, it means we have an out of memory condition and 2024 * should leave the buffer in place and continue. This will 2025 * result in a lost packet, but there's little else we 2026 * can do in this situation. 2027 */ 2028 if (xl_newbuf(sc, cur_rx)) { 2029 ifp->if_ierrors++; 2030 cur_rx->xl_ptr->xl_status = 0; 2031 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2032 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2033 continue; 2034 } 2035 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2036 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2037 2038 ifp->if_ipackets++; 2039 m->m_pkthdr.rcvif = ifp; 2040 m->m_pkthdr.len = m->m_len = total_len; 2041 2042 if (ifp->if_capenable & IFCAP_RXCSUM) { 2043 /* Do IP checksum checking. */ 2044 if (rxstat & XL_RXSTAT_IPCKOK) 2045 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2046 if (!(rxstat & XL_RXSTAT_IPCKERR)) 2047 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2048 if ((rxstat & XL_RXSTAT_TCPCOK && 2049 !(rxstat & XL_RXSTAT_TCPCKERR)) || 2050 (rxstat & XL_RXSTAT_UDPCKOK && 2051 !(rxstat & XL_RXSTAT_UDPCKERR))) { 2052 m->m_pkthdr.csum_flags |= 2053 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2054 m->m_pkthdr.csum_data = 0xffff; 2055 } 2056 } 2057 2058 XL_UNLOCK(sc); 2059 (*ifp->if_input)(ifp, m); 2060 XL_LOCK(sc); 2061 2062 /* 2063 * If we are running from the taskqueue, the interface 2064 * might have been stopped while we were passing the last 2065 * packet up the network stack. 2066 */ 2067 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 2068 return; 2069 } 2070 2071 /* 2072 * Handle the 'end of channel' condition. When the upload 2073 * engine hits the end of the RX ring, it will stall. This 2074 * is our cue to flush the RX ring, reload the uplist pointer 2075 * register and unstall the engine. 2076 * XXX This is actually a little goofy. With the ThunderLAN 2077 * chip, you get an interrupt when the receiver hits the end 2078 * of the receive ring, which tells you exactly when you 2079 * you need to reload the ring pointer. Here we have to 2080 * fake it. I'm mad at myself for not being clever enough 2081 * to avoid the use of a goto here. 2082 */ 2083 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2084 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2085 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2086 xl_wait(sc); 2087 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2088 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2089 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2090 goto again; 2091 } 2092 } 2093 2094 /* 2095 * Taskqueue wrapper for xl_rxeof(). 2096 */ 2097 static void 2098 xl_rxeof_task(void *arg, int pending) 2099 { 2100 struct xl_softc *sc = (struct xl_softc *)arg; 2101 2102 NET_LOCK_GIANT(); 2103 XL_LOCK(sc); 2104 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING) 2105 xl_rxeof(sc); 2106 XL_UNLOCK(sc); 2107 NET_UNLOCK_GIANT(); 2108 } 2109 2110 /* 2111 * A frame was downloaded to the chip. It's safe for us to clean up 2112 * the list buffers. 2113 */ 2114 static void 2115 xl_txeof(struct xl_softc *sc) 2116 { 2117 struct xl_chain *cur_tx; 2118 struct ifnet *ifp = sc->xl_ifp; 2119 2120 XL_LOCK_ASSERT(sc); 2121 2122 /* 2123 * Go through our tx list and free mbufs for those 2124 * frames that have been uploaded. Note: the 3c905B 2125 * sets a special bit in the status word to let us 2126 * know that a frame has been downloaded, but the 2127 * original 3c900/3c905 adapters don't do that. 2128 * Consequently, we have to use a different test if 2129 * xl_type != XL_TYPE_905B. 2130 */ 2131 while (sc->xl_cdata.xl_tx_head != NULL) { 2132 cur_tx = sc->xl_cdata.xl_tx_head; 2133 2134 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2135 break; 2136 2137 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2138 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2139 BUS_DMASYNC_POSTWRITE); 2140 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2141 m_freem(cur_tx->xl_mbuf); 2142 cur_tx->xl_mbuf = NULL; 2143 ifp->if_opackets++; 2144 2145 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2146 sc->xl_cdata.xl_tx_free = cur_tx; 2147 } 2148 2149 if (sc->xl_cdata.xl_tx_head == NULL) { 2150 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2151 /* Clear the timeout timer. */ 2152 ifp->if_timer = 0; 2153 sc->xl_cdata.xl_tx_tail = NULL; 2154 } else { 2155 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2156 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2157 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2158 sc->xl_cdata.xl_tx_head->xl_phys); 2159 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2160 } 2161 } 2162 } 2163 2164 static void 2165 xl_txeof_90xB(struct xl_softc *sc) 2166 { 2167 struct xl_chain *cur_tx = NULL; 2168 struct ifnet *ifp = sc->xl_ifp; 2169 int idx; 2170 2171 XL_LOCK_ASSERT(sc); 2172 2173 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2174 BUS_DMASYNC_POSTREAD); 2175 idx = sc->xl_cdata.xl_tx_cons; 2176 while (idx != sc->xl_cdata.xl_tx_prod) { 2177 2178 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2179 2180 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2181 XL_TXSTAT_DL_COMPLETE)) 2182 break; 2183 2184 if (cur_tx->xl_mbuf != NULL) { 2185 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2186 BUS_DMASYNC_POSTWRITE); 2187 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2188 m_freem(cur_tx->xl_mbuf); 2189 cur_tx->xl_mbuf = NULL; 2190 } 2191 2192 ifp->if_opackets++; 2193 2194 sc->xl_cdata.xl_tx_cnt--; 2195 XL_INC(idx, XL_TX_LIST_CNT); 2196 } 2197 2198 if (sc->xl_cdata.xl_tx_cnt == 0) 2199 ifp->if_timer = 0; 2200 sc->xl_cdata.xl_tx_cons = idx; 2201 2202 if (cur_tx != NULL) 2203 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2204 } 2205 2206 /* 2207 * TX 'end of channel' interrupt handler. Actually, we should 2208 * only get a 'TX complete' interrupt if there's a transmit error, 2209 * so this is really TX error handler. 2210 */ 2211 static void 2212 xl_txeoc(struct xl_softc *sc) 2213 { 2214 u_int8_t txstat; 2215 2216 XL_LOCK_ASSERT(sc); 2217 2218 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2219 if (txstat & XL_TXSTATUS_UNDERRUN || 2220 txstat & XL_TXSTATUS_JABBER || 2221 txstat & XL_TXSTATUS_RECLAIM) { 2222 if_printf(sc->xl_ifp, 2223 "transmission error: %x\n", txstat); 2224 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2225 xl_wait(sc); 2226 if (sc->xl_type == XL_TYPE_905B) { 2227 if (sc->xl_cdata.xl_tx_cnt) { 2228 int i; 2229 struct xl_chain *c; 2230 2231 i = sc->xl_cdata.xl_tx_cons; 2232 c = &sc->xl_cdata.xl_tx_chain[i]; 2233 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2234 c->xl_phys); 2235 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2236 } 2237 } else { 2238 if (sc->xl_cdata.xl_tx_head != NULL) 2239 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2240 sc->xl_cdata.xl_tx_head->xl_phys); 2241 } 2242 /* 2243 * Remember to set this for the 2244 * first generation 3c90X chips. 2245 */ 2246 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2247 if (txstat & XL_TXSTATUS_UNDERRUN && 2248 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2249 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2250 if_printf(sc->xl_ifp, 2251 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh); 2252 } 2253 CSR_WRITE_2(sc, XL_COMMAND, 2254 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2255 if (sc->xl_type == XL_TYPE_905B) { 2256 CSR_WRITE_2(sc, XL_COMMAND, 2257 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2258 } 2259 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2260 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2261 } else { 2262 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2263 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2264 } 2265 /* 2266 * Write an arbitrary byte to the TX_STATUS register 2267 * to clear this interrupt/error and advance to the next. 2268 */ 2269 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2270 } 2271 } 2272 2273 static void 2274 xl_intr(void *arg) 2275 { 2276 struct xl_softc *sc = arg; 2277 struct ifnet *ifp = sc->xl_ifp; 2278 u_int16_t status; 2279 2280 XL_LOCK(sc); 2281 2282 #ifdef DEVICE_POLLING 2283 if (ifp->if_capenable & IFCAP_POLLING) { 2284 XL_UNLOCK(sc); 2285 return; 2286 } 2287 #endif 2288 2289 while ((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && 2290 status != 0xFFFF) { 2291 CSR_WRITE_2(sc, XL_COMMAND, 2292 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2293 2294 if (status & XL_STAT_UP_COMPLETE) { 2295 int curpkts; 2296 2297 curpkts = ifp->if_ipackets; 2298 xl_rxeof(sc); 2299 if (curpkts == ifp->if_ipackets) { 2300 while (xl_rx_resync(sc)) 2301 xl_rxeof(sc); 2302 } 2303 } 2304 2305 if (status & XL_STAT_DOWN_COMPLETE) { 2306 if (sc->xl_type == XL_TYPE_905B) 2307 xl_txeof_90xB(sc); 2308 else 2309 xl_txeof(sc); 2310 } 2311 2312 if (status & XL_STAT_TX_COMPLETE) { 2313 ifp->if_oerrors++; 2314 xl_txeoc(sc); 2315 } 2316 2317 if (status & XL_STAT_ADFAIL) { 2318 xl_reset(sc); 2319 xl_init_locked(sc); 2320 } 2321 2322 if (status & XL_STAT_STATSOFLOW) { 2323 sc->xl_stats_no_timeout = 1; 2324 xl_stats_update_locked(sc); 2325 sc->xl_stats_no_timeout = 0; 2326 } 2327 } 2328 2329 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2330 if (sc->xl_type == XL_TYPE_905B) 2331 xl_start_90xB_locked(ifp); 2332 else 2333 xl_start_locked(ifp); 2334 } 2335 2336 XL_UNLOCK(sc); 2337 } 2338 2339 #ifdef DEVICE_POLLING 2340 static void 2341 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2342 { 2343 struct xl_softc *sc = ifp->if_softc; 2344 2345 XL_LOCK(sc); 2346 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2347 xl_poll_locked(ifp, cmd, count); 2348 XL_UNLOCK(sc); 2349 } 2350 2351 static void 2352 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2353 { 2354 struct xl_softc *sc = ifp->if_softc; 2355 2356 XL_LOCK_ASSERT(sc); 2357 2358 sc->rxcycles = count; 2359 xl_rxeof(sc); 2360 if (sc->xl_type == XL_TYPE_905B) 2361 xl_txeof_90xB(sc); 2362 else 2363 xl_txeof(sc); 2364 2365 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2366 if (sc->xl_type == XL_TYPE_905B) 2367 xl_start_90xB_locked(ifp); 2368 else 2369 xl_start_locked(ifp); 2370 } 2371 2372 if (cmd == POLL_AND_CHECK_STATUS) { 2373 u_int16_t status; 2374 2375 status = CSR_READ_2(sc, XL_STATUS); 2376 if (status & XL_INTRS && status != 0xFFFF) { 2377 CSR_WRITE_2(sc, XL_COMMAND, 2378 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2379 2380 if (status & XL_STAT_TX_COMPLETE) { 2381 ifp->if_oerrors++; 2382 xl_txeoc(sc); 2383 } 2384 2385 if (status & XL_STAT_ADFAIL) { 2386 xl_reset(sc); 2387 xl_init_locked(sc); 2388 } 2389 2390 if (status & XL_STAT_STATSOFLOW) { 2391 sc->xl_stats_no_timeout = 1; 2392 xl_stats_update_locked(sc); 2393 sc->xl_stats_no_timeout = 0; 2394 } 2395 } 2396 } 2397 } 2398 #endif /* DEVICE_POLLING */ 2399 2400 /* 2401 * XXX: This is an entry point for callout which needs to take the lock. 2402 */ 2403 static void 2404 xl_stats_update(void *xsc) 2405 { 2406 struct xl_softc *sc = xsc; 2407 2408 XL_LOCK_ASSERT(sc); 2409 xl_stats_update_locked(sc); 2410 } 2411 2412 static void 2413 xl_stats_update_locked(struct xl_softc *sc) 2414 { 2415 struct ifnet *ifp = sc->xl_ifp; 2416 struct xl_stats xl_stats; 2417 u_int8_t *p; 2418 int i; 2419 struct mii_data *mii = NULL; 2420 2421 XL_LOCK_ASSERT(sc); 2422 2423 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2424 2425 if (sc->xl_miibus != NULL) 2426 mii = device_get_softc(sc->xl_miibus); 2427 2428 p = (u_int8_t *)&xl_stats; 2429 2430 /* Read all the stats registers. */ 2431 XL_SEL_WIN(6); 2432 2433 for (i = 0; i < 16; i++) 2434 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2435 2436 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2437 2438 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2439 xl_stats.xl_tx_single_collision + xl_stats.xl_tx_late_collision; 2440 2441 /* 2442 * Boomerang and cyclone chips have an extra stats counter 2443 * in window 4 (BadSSD). We have to read this too in order 2444 * to clear out all the stats registers and avoid a statsoflow 2445 * interrupt. 2446 */ 2447 XL_SEL_WIN(4); 2448 CSR_READ_1(sc, XL_W4_BADSSD); 2449 2450 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2451 mii_tick(mii); 2452 2453 XL_SEL_WIN(7); 2454 2455 if (!sc->xl_stats_no_timeout) 2456 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc); 2457 } 2458 2459 /* 2460 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2461 * pointers to the fragment pointers. 2462 */ 2463 static int 2464 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head) 2465 { 2466 int error; 2467 u_int32_t status; 2468 struct ifnet *ifp = sc->xl_ifp; 2469 2470 XL_LOCK_ASSERT(sc); 2471 2472 /* 2473 * Start packing the mbufs in this chain into 2474 * the fragment pointers. Stop when we run out 2475 * of fragments or hit the end of the mbuf chain. 2476 */ 2477 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head, 2478 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2479 2480 if (error && error != EFBIG) { 2481 m_freem(m_head); 2482 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2483 return (1); 2484 } 2485 2486 /* 2487 * Handle special case: we used up all 63 fragments, 2488 * but we have more mbufs left in the chain. Copy the 2489 * data into an mbuf cluster. Note that we don't 2490 * bother clearing the values in the other fragment 2491 * pointers/counters; it wouldn't gain us anything, 2492 * and would waste cycles. 2493 */ 2494 if (error) { 2495 struct mbuf *m_new; 2496 2497 m_new = m_defrag(m_head, M_DONTWAIT); 2498 if (m_new == NULL) { 2499 m_freem(m_head); 2500 return (1); 2501 } else { 2502 m_head = m_new; 2503 } 2504 2505 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, 2506 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2507 if (error) { 2508 m_freem(m_head); 2509 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2510 return (1); 2511 } 2512 } 2513 2514 if (sc->xl_type == XL_TYPE_905B) { 2515 status = XL_TXSTAT_RND_DEFEAT; 2516 2517 #ifndef XL905B_TXCSUM_BROKEN 2518 if (m_head->m_pkthdr.csum_flags) { 2519 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2520 status |= XL_TXSTAT_IPCKSUM; 2521 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2522 status |= XL_TXSTAT_TCPCKSUM; 2523 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2524 status |= XL_TXSTAT_UDPCKSUM; 2525 } 2526 #endif 2527 c->xl_ptr->xl_status = htole32(status); 2528 } 2529 2530 c->xl_mbuf = m_head; 2531 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2532 return (0); 2533 } 2534 2535 /* 2536 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2537 * to the mbuf data regions directly in the transmit lists. We also save a 2538 * copy of the pointers since the transmit list fragment pointers are 2539 * physical addresses. 2540 */ 2541 2542 static void 2543 xl_start(struct ifnet *ifp) 2544 { 2545 struct xl_softc *sc = ifp->if_softc; 2546 2547 XL_LOCK(sc); 2548 2549 if (sc->xl_type == XL_TYPE_905B) 2550 xl_start_90xB_locked(ifp); 2551 else 2552 xl_start_locked(ifp); 2553 2554 XL_UNLOCK(sc); 2555 } 2556 2557 static void 2558 xl_start_locked(struct ifnet *ifp) 2559 { 2560 struct xl_softc *sc = ifp->if_softc; 2561 struct mbuf *m_head = NULL; 2562 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2563 struct xl_chain *prev_tx; 2564 u_int32_t status; 2565 int error; 2566 2567 XL_LOCK_ASSERT(sc); 2568 2569 /* 2570 * Check for an available queue slot. If there are none, 2571 * punt. 2572 */ 2573 if (sc->xl_cdata.xl_tx_free == NULL) { 2574 xl_txeoc(sc); 2575 xl_txeof(sc); 2576 if (sc->xl_cdata.xl_tx_free == NULL) { 2577 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2578 return; 2579 } 2580 } 2581 2582 start_tx = sc->xl_cdata.xl_tx_free; 2583 2584 while (sc->xl_cdata.xl_tx_free != NULL) { 2585 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2586 if (m_head == NULL) 2587 break; 2588 2589 /* Pick a descriptor off the free list. */ 2590 prev_tx = cur_tx; 2591 cur_tx = sc->xl_cdata.xl_tx_free; 2592 2593 /* Pack the data into the descriptor. */ 2594 error = xl_encap(sc, cur_tx, m_head); 2595 if (error) { 2596 cur_tx = prev_tx; 2597 continue; 2598 } 2599 2600 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2601 cur_tx->xl_next = NULL; 2602 2603 /* Chain it together. */ 2604 if (prev != NULL) { 2605 prev->xl_next = cur_tx; 2606 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2607 } 2608 prev = cur_tx; 2609 2610 /* 2611 * If there's a BPF listener, bounce a copy of this frame 2612 * to him. 2613 */ 2614 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2615 } 2616 2617 /* 2618 * If there are no packets queued, bail. 2619 */ 2620 if (cur_tx == NULL) 2621 return; 2622 2623 /* 2624 * Place the request for the upload interrupt 2625 * in the last descriptor in the chain. This way, if 2626 * we're chaining several packets at once, we'll only 2627 * get an interupt once for the whole chain rather than 2628 * once for each packet. 2629 */ 2630 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2631 XL_TXSTAT_DL_INTR); 2632 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2633 BUS_DMASYNC_PREWRITE); 2634 2635 /* 2636 * Queue the packets. If the TX channel is clear, update 2637 * the downlist pointer register. 2638 */ 2639 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2640 xl_wait(sc); 2641 2642 if (sc->xl_cdata.xl_tx_head != NULL) { 2643 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2644 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2645 htole32(start_tx->xl_phys); 2646 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2647 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2648 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2649 sc->xl_cdata.xl_tx_tail = cur_tx; 2650 } else { 2651 sc->xl_cdata.xl_tx_head = start_tx; 2652 sc->xl_cdata.xl_tx_tail = cur_tx; 2653 } 2654 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2655 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2656 2657 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2658 2659 XL_SEL_WIN(7); 2660 2661 /* 2662 * Set a timeout in case the chip goes out to lunch. 2663 */ 2664 ifp->if_timer = 5; 2665 2666 /* 2667 * XXX Under certain conditions, usually on slower machines 2668 * where interrupts may be dropped, it's possible for the 2669 * adapter to chew up all the buffers in the receive ring 2670 * and stall, without us being able to do anything about it. 2671 * To guard against this, we need to make a pass over the 2672 * RX queue to make sure there aren't any packets pending. 2673 * Doing it here means we can flush the receive ring at the 2674 * same time the chip is DMAing the transmit descriptors we 2675 * just gave it. 2676 * 2677 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2678 * nature of their chips in all their marketing literature; 2679 * we may as well take advantage of it. :) 2680 */ 2681 taskqueue_enqueue(taskqueue_swi, &sc->xl_task); 2682 } 2683 2684 static void 2685 xl_start_90xB_locked(struct ifnet *ifp) 2686 { 2687 struct xl_softc *sc = ifp->if_softc; 2688 struct mbuf *m_head = NULL; 2689 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2690 struct xl_chain *prev_tx; 2691 int error, idx; 2692 2693 XL_LOCK_ASSERT(sc); 2694 2695 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 2696 return; 2697 2698 idx = sc->xl_cdata.xl_tx_prod; 2699 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2700 2701 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { 2702 2703 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2704 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2705 break; 2706 } 2707 2708 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2709 if (m_head == NULL) 2710 break; 2711 2712 prev_tx = cur_tx; 2713 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2714 2715 /* Pack the data into the descriptor. */ 2716 error = xl_encap(sc, cur_tx, m_head); 2717 if (error) { 2718 cur_tx = prev_tx; 2719 continue; 2720 } 2721 2722 /* Chain it together. */ 2723 if (prev != NULL) 2724 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2725 prev = cur_tx; 2726 2727 /* 2728 * If there's a BPF listener, bounce a copy of this frame 2729 * to him. 2730 */ 2731 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2732 2733 XL_INC(idx, XL_TX_LIST_CNT); 2734 sc->xl_cdata.xl_tx_cnt++; 2735 } 2736 2737 /* 2738 * If there are no packets queued, bail. 2739 */ 2740 if (cur_tx == NULL) 2741 return; 2742 2743 /* 2744 * Place the request for the upload interrupt 2745 * in the last descriptor in the chain. This way, if 2746 * we're chaining several packets at once, we'll only 2747 * get an interupt once for the whole chain rather than 2748 * once for each packet. 2749 */ 2750 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2751 XL_TXSTAT_DL_INTR); 2752 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2753 BUS_DMASYNC_PREWRITE); 2754 2755 /* Start transmission */ 2756 sc->xl_cdata.xl_tx_prod = idx; 2757 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2758 2759 /* 2760 * Set a timeout in case the chip goes out to lunch. 2761 */ 2762 ifp->if_timer = 5; 2763 } 2764 2765 static void 2766 xl_init(void *xsc) 2767 { 2768 struct xl_softc *sc = xsc; 2769 2770 XL_LOCK(sc); 2771 xl_init_locked(sc); 2772 XL_UNLOCK(sc); 2773 } 2774 2775 static void 2776 xl_init_locked(struct xl_softc *sc) 2777 { 2778 struct ifnet *ifp = sc->xl_ifp; 2779 int error, i; 2780 u_int16_t rxfilt = 0; 2781 struct mii_data *mii = NULL; 2782 2783 XL_LOCK_ASSERT(sc); 2784 2785 /* 2786 * Cancel pending I/O and free all RX/TX buffers. 2787 */ 2788 xl_stop(sc); 2789 2790 if (sc->xl_miibus == NULL) { 2791 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2792 xl_wait(sc); 2793 } 2794 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2795 xl_wait(sc); 2796 DELAY(10000); 2797 2798 if (sc->xl_miibus != NULL) 2799 mii = device_get_softc(sc->xl_miibus); 2800 2801 /* Init our MAC address */ 2802 XL_SEL_WIN(2); 2803 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2804 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2805 IFP2ENADDR(sc->xl_ifp)[i]); 2806 } 2807 2808 /* Clear the station mask. */ 2809 for (i = 0; i < 3; i++) 2810 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2811 #ifdef notdef 2812 /* Reset TX and RX. */ 2813 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2814 xl_wait(sc); 2815 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2816 xl_wait(sc); 2817 #endif 2818 /* Init circular RX list. */ 2819 error = xl_list_rx_init(sc); 2820 if (error) { 2821 if_printf(ifp, "initialization of the rx ring failed (%d)\n", 2822 error); 2823 xl_stop(sc); 2824 return; 2825 } 2826 2827 /* Init TX descriptors. */ 2828 if (sc->xl_type == XL_TYPE_905B) 2829 error = xl_list_tx_init_90xB(sc); 2830 else 2831 error = xl_list_tx_init(sc); 2832 if (error) { 2833 if_printf(ifp, "initialization of the tx ring failed (%d)\n", 2834 error); 2835 xl_stop(sc); 2836 return; 2837 } 2838 2839 /* 2840 * Set the TX freethresh value. 2841 * Note that this has no effect on 3c905B "cyclone" 2842 * cards but is required for 3c900/3c905 "boomerang" 2843 * cards in order to enable the download engine. 2844 */ 2845 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2846 2847 /* Set the TX start threshold for best performance. */ 2848 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2849 2850 /* 2851 * If this is a 3c905B, also set the tx reclaim threshold. 2852 * This helps cut down on the number of tx reclaim errors 2853 * that could happen on a busy network. The chip multiplies 2854 * the register value by 16 to obtain the actual threshold 2855 * in bytes, so we divide by 16 when setting the value here. 2856 * The existing threshold value can be examined by reading 2857 * the register at offset 9 in window 5. 2858 */ 2859 if (sc->xl_type == XL_TYPE_905B) { 2860 CSR_WRITE_2(sc, XL_COMMAND, 2861 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2862 } 2863 2864 /* Set RX filter bits. */ 2865 XL_SEL_WIN(5); 2866 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2867 2868 /* Set the individual bit to receive frames for this host only. */ 2869 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2870 2871 /* If we want promiscuous mode, set the allframes bit. */ 2872 if (ifp->if_flags & IFF_PROMISC) { 2873 rxfilt |= XL_RXFILTER_ALLFRAMES; 2874 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2875 } else { 2876 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2877 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2878 } 2879 2880 /* 2881 * Set capture broadcast bit to capture broadcast frames. 2882 */ 2883 if (ifp->if_flags & IFF_BROADCAST) { 2884 rxfilt |= XL_RXFILTER_BROADCAST; 2885 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2886 } else { 2887 rxfilt &= ~XL_RXFILTER_BROADCAST; 2888 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2889 } 2890 2891 /* 2892 * Program the multicast filter, if necessary. 2893 */ 2894 if (sc->xl_type == XL_TYPE_905B) 2895 xl_setmulti_hash(sc); 2896 else 2897 xl_setmulti(sc); 2898 2899 /* 2900 * Load the address of the RX list. We have to 2901 * stall the upload engine before we can manipulate 2902 * the uplist pointer register, then unstall it when 2903 * we're finished. We also have to wait for the 2904 * stall command to complete before proceeding. 2905 * Note that we have to do this after any RX resets 2906 * have completed since the uplist register is cleared 2907 * by a reset. 2908 */ 2909 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2910 xl_wait(sc); 2911 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2912 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2913 xl_wait(sc); 2914 2915 if (sc->xl_type == XL_TYPE_905B) { 2916 /* Set polling interval */ 2917 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2918 /* Load the address of the TX list */ 2919 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2920 xl_wait(sc); 2921 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2922 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2923 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2924 xl_wait(sc); 2925 } 2926 2927 /* 2928 * If the coax transceiver is on, make sure to enable 2929 * the DC-DC converter. 2930 */ 2931 XL_SEL_WIN(3); 2932 if (sc->xl_xcvr == XL_XCVR_COAX) 2933 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2934 else 2935 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2936 2937 /* 2938 * increase packet size to allow reception of 802.1q or ISL packets. 2939 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2940 * control register. For 3c90xB/C chips, use the RX packet size 2941 * register. 2942 */ 2943 2944 if (sc->xl_type == XL_TYPE_905B) 2945 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2946 else { 2947 u_int8_t macctl; 2948 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2949 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2950 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2951 } 2952 2953 /* Clear out the stats counters. */ 2954 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2955 sc->xl_stats_no_timeout = 1; 2956 xl_stats_update_locked(sc); 2957 sc->xl_stats_no_timeout = 0; 2958 XL_SEL_WIN(4); 2959 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2960 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2961 2962 /* 2963 * Enable interrupts. 2964 */ 2965 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2966 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2967 #ifdef DEVICE_POLLING 2968 /* Disable interrupts if we are polling. */ 2969 if (ifp->if_capenable & IFCAP_POLLING) 2970 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 2971 else 2972 #endif 2973 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2974 if (sc->xl_flags & XL_FLAG_FUNCREG) 2975 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2976 2977 /* Set the RX early threshold */ 2978 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2979 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2980 2981 /* Enable receiver and transmitter. */ 2982 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2983 xl_wait(sc); 2984 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2985 xl_wait(sc); 2986 2987 /* XXX Downcall to miibus. */ 2988 if (mii != NULL) 2989 mii_mediachg(mii); 2990 2991 /* Select window 7 for normal operations. */ 2992 XL_SEL_WIN(7); 2993 2994 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2995 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2996 2997 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc); 2998 } 2999 3000 /* 3001 * Set media options. 3002 */ 3003 static int 3004 xl_ifmedia_upd(struct ifnet *ifp) 3005 { 3006 struct xl_softc *sc = ifp->if_softc; 3007 struct ifmedia *ifm = NULL; 3008 struct mii_data *mii = NULL; 3009 3010 XL_LOCK(sc); 3011 3012 if (sc->xl_miibus != NULL) 3013 mii = device_get_softc(sc->xl_miibus); 3014 if (mii == NULL) 3015 ifm = &sc->ifmedia; 3016 else 3017 ifm = &mii->mii_media; 3018 3019 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3020 case IFM_100_FX: 3021 case IFM_10_FL: 3022 case IFM_10_2: 3023 case IFM_10_5: 3024 xl_setmode(sc, ifm->ifm_media); 3025 return (0); 3026 break; 3027 default: 3028 break; 3029 } 3030 3031 if (sc->xl_media & XL_MEDIAOPT_MII || 3032 sc->xl_media & XL_MEDIAOPT_BTX || 3033 sc->xl_media & XL_MEDIAOPT_BT4) { 3034 xl_init_locked(sc); 3035 } else { 3036 xl_setmode(sc, ifm->ifm_media); 3037 } 3038 3039 XL_UNLOCK(sc); 3040 3041 return (0); 3042 } 3043 3044 /* 3045 * Report current media status. 3046 */ 3047 static void 3048 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3049 { 3050 struct xl_softc *sc = ifp->if_softc; 3051 u_int32_t icfg; 3052 u_int16_t status = 0; 3053 struct mii_data *mii = NULL; 3054 3055 XL_LOCK(sc); 3056 3057 if (sc->xl_miibus != NULL) 3058 mii = device_get_softc(sc->xl_miibus); 3059 3060 XL_SEL_WIN(4); 3061 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3062 3063 XL_SEL_WIN(3); 3064 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 3065 icfg >>= XL_ICFG_CONNECTOR_BITS; 3066 3067 ifmr->ifm_active = IFM_ETHER; 3068 ifmr->ifm_status = IFM_AVALID; 3069 3070 if ((status & XL_MEDIASTAT_CARRIER) == 0) 3071 ifmr->ifm_status |= IFM_ACTIVE; 3072 3073 switch (icfg) { 3074 case XL_XCVR_10BT: 3075 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 3076 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3077 ifmr->ifm_active |= IFM_FDX; 3078 else 3079 ifmr->ifm_active |= IFM_HDX; 3080 break; 3081 case XL_XCVR_AUI: 3082 if (sc->xl_type == XL_TYPE_905B && 3083 sc->xl_media == XL_MEDIAOPT_10FL) { 3084 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 3085 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3086 ifmr->ifm_active |= IFM_FDX; 3087 else 3088 ifmr->ifm_active |= IFM_HDX; 3089 } else 3090 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3091 break; 3092 case XL_XCVR_COAX: 3093 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3094 break; 3095 /* 3096 * XXX MII and BTX/AUTO should be separate cases. 3097 */ 3098 3099 case XL_XCVR_100BTX: 3100 case XL_XCVR_AUTO: 3101 case XL_XCVR_MII: 3102 if (mii != NULL) { 3103 mii_pollstat(mii); 3104 ifmr->ifm_active = mii->mii_media_active; 3105 ifmr->ifm_status = mii->mii_media_status; 3106 } 3107 break; 3108 case XL_XCVR_100BFX: 3109 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3110 break; 3111 default: 3112 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3113 break; 3114 } 3115 3116 XL_UNLOCK(sc); 3117 } 3118 3119 static int 3120 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3121 { 3122 struct xl_softc *sc = ifp->if_softc; 3123 struct ifreq *ifr = (struct ifreq *) data; 3124 int error = 0; 3125 struct mii_data *mii = NULL; 3126 u_int8_t rxfilt; 3127 3128 switch (command) { 3129 case SIOCSIFFLAGS: 3130 XL_LOCK(sc); 3131 3132 XL_SEL_WIN(5); 3133 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3134 if (ifp->if_flags & IFF_UP) { 3135 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3136 ifp->if_flags & IFF_PROMISC && 3137 !(sc->xl_if_flags & IFF_PROMISC)) { 3138 rxfilt |= XL_RXFILTER_ALLFRAMES; 3139 CSR_WRITE_2(sc, XL_COMMAND, 3140 XL_CMD_RX_SET_FILT|rxfilt); 3141 XL_SEL_WIN(7); 3142 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3143 !(ifp->if_flags & IFF_PROMISC) && 3144 sc->xl_if_flags & IFF_PROMISC) { 3145 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3146 CSR_WRITE_2(sc, XL_COMMAND, 3147 XL_CMD_RX_SET_FILT|rxfilt); 3148 XL_SEL_WIN(7); 3149 } else { 3150 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3151 xl_init_locked(sc); 3152 } 3153 } else { 3154 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3155 xl_stop(sc); 3156 } 3157 sc->xl_if_flags = ifp->if_flags; 3158 XL_UNLOCK(sc); 3159 error = 0; 3160 break; 3161 case SIOCADDMULTI: 3162 case SIOCDELMULTI: 3163 /* XXX Downcall from if_addmulti() possibly with locks held. */ 3164 XL_LOCK(sc); 3165 if (sc->xl_type == XL_TYPE_905B) 3166 xl_setmulti_hash(sc); 3167 else 3168 xl_setmulti(sc); 3169 XL_UNLOCK(sc); 3170 error = 0; 3171 break; 3172 case SIOCGIFMEDIA: 3173 case SIOCSIFMEDIA: 3174 if (sc->xl_miibus != NULL) 3175 mii = device_get_softc(sc->xl_miibus); 3176 if (mii == NULL) 3177 error = ifmedia_ioctl(ifp, ifr, 3178 &sc->ifmedia, command); 3179 else 3180 error = ifmedia_ioctl(ifp, ifr, 3181 &mii->mii_media, command); 3182 break; 3183 case SIOCSIFCAP: 3184 #ifdef DEVICE_POLLING 3185 if (ifr->ifr_reqcap & IFCAP_POLLING && 3186 !(ifp->if_capenable & IFCAP_POLLING)) { 3187 error = ether_poll_register(xl_poll, ifp); 3188 if (error) 3189 return(error); 3190 XL_LOCK(sc); 3191 /* Disable interrupts */ 3192 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3193 ifp->if_capenable |= IFCAP_POLLING; 3194 XL_UNLOCK(sc); 3195 return (error); 3196 3197 } 3198 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3199 ifp->if_capenable & IFCAP_POLLING) { 3200 error = ether_poll_deregister(ifp); 3201 /* Enable interrupts. */ 3202 XL_LOCK(sc); 3203 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 3204 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 3205 if (sc->xl_flags & XL_FLAG_FUNCREG) 3206 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 3207 4, 0x8000); 3208 ifp->if_capenable &= ~IFCAP_POLLING; 3209 XL_UNLOCK(sc); 3210 return (error); 3211 } 3212 #endif /* DEVICE_POLLING */ 3213 XL_LOCK(sc); 3214 ifp->if_capenable = ifr->ifr_reqcap; 3215 if (ifp->if_capenable & IFCAP_TXCSUM) 3216 ifp->if_hwassist = XL905B_CSUM_FEATURES; 3217 else 3218 ifp->if_hwassist = 0; 3219 XL_UNLOCK(sc); 3220 break; 3221 default: 3222 error = ether_ioctl(ifp, command, data); 3223 break; 3224 } 3225 3226 return (error); 3227 } 3228 3229 /* 3230 * XXX: Invoked from ifnet slow timer. Lock coverage needed. 3231 */ 3232 static void 3233 xl_watchdog(struct ifnet *ifp) 3234 { 3235 struct xl_softc *sc = ifp->if_softc; 3236 u_int16_t status = 0; 3237 3238 XL_LOCK(sc); 3239 3240 ifp->if_oerrors++; 3241 XL_SEL_WIN(4); 3242 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3243 if_printf(ifp, "watchdog timeout\n"); 3244 3245 if (status & XL_MEDIASTAT_CARRIER) 3246 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 3247 3248 xl_txeoc(sc); 3249 xl_txeof(sc); 3250 xl_rxeof(sc); 3251 xl_reset(sc); 3252 xl_init_locked(sc); 3253 3254 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 3255 if (sc->xl_type == XL_TYPE_905B) 3256 xl_start_90xB_locked(ifp); 3257 else 3258 xl_start_locked(ifp); 3259 } 3260 3261 XL_UNLOCK(sc); 3262 } 3263 3264 /* 3265 * Stop the adapter and free any mbufs allocated to the 3266 * RX and TX lists. 3267 */ 3268 static void 3269 xl_stop(struct xl_softc *sc) 3270 { 3271 register int i; 3272 struct ifnet *ifp = sc->xl_ifp; 3273 3274 XL_LOCK_ASSERT(sc); 3275 3276 ifp->if_timer = 0; 3277 3278 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3279 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3280 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3281 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3282 xl_wait(sc); 3283 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3284 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3285 DELAY(800); 3286 3287 #ifdef foo 3288 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3289 xl_wait(sc); 3290 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3291 xl_wait(sc); 3292 #endif 3293 3294 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3295 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3296 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3297 if (sc->xl_flags & XL_FLAG_FUNCREG) 3298 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3299 3300 /* Stop the stats updater. */ 3301 callout_stop(&sc->xl_stat_callout); 3302 3303 /* 3304 * Free data in the RX lists. 3305 */ 3306 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3307 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3308 bus_dmamap_unload(sc->xl_mtag, 3309 sc->xl_cdata.xl_rx_chain[i].xl_map); 3310 bus_dmamap_destroy(sc->xl_mtag, 3311 sc->xl_cdata.xl_rx_chain[i].xl_map); 3312 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3313 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3314 } 3315 } 3316 if (sc->xl_ldata.xl_rx_list != NULL) 3317 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3318 /* 3319 * Free the TX list buffers. 3320 */ 3321 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3322 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3323 bus_dmamap_unload(sc->xl_mtag, 3324 sc->xl_cdata.xl_tx_chain[i].xl_map); 3325 bus_dmamap_destroy(sc->xl_mtag, 3326 sc->xl_cdata.xl_tx_chain[i].xl_map); 3327 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3328 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3329 } 3330 } 3331 if (sc->xl_ldata.xl_tx_list != NULL) 3332 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3333 3334 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3335 } 3336 3337 /* 3338 * Stop all chip I/O so that the kernel's probe routines don't 3339 * get confused by errant DMAs when rebooting. 3340 */ 3341 static void 3342 xl_shutdown(device_t dev) 3343 { 3344 struct xl_softc *sc; 3345 3346 sc = device_get_softc(dev); 3347 3348 XL_LOCK(sc); 3349 xl_reset(sc); 3350 xl_stop(sc); 3351 XL_UNLOCK(sc); 3352 } 3353 3354 static int 3355 xl_suspend(device_t dev) 3356 { 3357 struct xl_softc *sc; 3358 3359 sc = device_get_softc(dev); 3360 3361 XL_LOCK(sc); 3362 xl_stop(sc); 3363 XL_UNLOCK(sc); 3364 3365 return (0); 3366 } 3367 3368 static int 3369 xl_resume(device_t dev) 3370 { 3371 struct xl_softc *sc; 3372 struct ifnet *ifp; 3373 3374 sc = device_get_softc(dev); 3375 ifp = sc->xl_ifp; 3376 3377 XL_LOCK(sc); 3378 3379 xl_reset(sc); 3380 if (ifp->if_flags & IFF_UP) 3381 xl_init_locked(sc); 3382 3383 XL_UNLOCK(sc); 3384 3385 return (0); 3386 }
Cache object: cdcf7f2b7cac72aee4a9237b014a9515
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]