FreeBSD/Linux Kernel Cross Reference
sys/pci/if_xlreg.h
1 /*-
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: releng/7.4/sys/pci/if_xlreg.h 213121 2010-09-24 19:11:22Z yongari $
33 */
34
35 #define XL_EE_READ 0x0080 /* read, 5 bit address */
36 #define XL_EE_WRITE 0x0040 /* write, 5 bit address */
37 #define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */
38 #define XL_EE_EWEN 0x0030 /* erase, no data needed */
39 #define XL_EE_8BIT_READ 0x0200 /* read, 8 bit address */
40 #define XL_EE_BUSY 0x8000
41
42 #define XL_EE_EADDR0 0x00 /* station address, first word */
43 #define XL_EE_EADDR1 0x01 /* station address, next word, */
44 #define XL_EE_EADDR2 0x02 /* station address, last word */
45 #define XL_EE_PRODID 0x03 /* product ID code */
46 #define XL_EE_MDATA_DATE 0x04 /* manufacturing data, date */
47 #define XL_EE_MDATA_DIV 0x05 /* manufacturing data, division */
48 #define XL_EE_MDATA_PCODE 0x06 /* manufacturing data, product code */
49 #define XL_EE_MFG_ID 0x07
50 #define XL_EE_PCI_PARM 0x08
51 #define XL_EE_ROM_ONFO 0x09
52 #define XL_EE_OEM_ADR0 0x0A
53 #define XL_EE_OEM_ADR1 0x0B
54 #define XL_EE_OEM_ADR2 0x0C
55 #define XL_EE_SOFTINFO1 0x0D
56 #define XL_EE_COMPAT 0x0E
57 #define XL_EE_SOFTINFO2 0x0F
58 #define XL_EE_CAPS 0x10 /* capabilities word */
59 #define XL_EE_RSVD0 0x11
60 #define XL_EE_ICFG_0 0x12
61 #define XL_EE_ICFG_1 0x13
62 #define XL_EE_RSVD1 0x14
63 #define XL_EE_SOFTINFO3 0x15
64 #define XL_EE_RSVD_2 0x16
65
66 /*
67 * Bits in the capabilities word
68 */
69 #define XL_CAPS_PNP 0x0001
70 #define XL_CAPS_FULL_DUPLEX 0x0002
71 #define XL_CAPS_LARGE_PKTS 0x0004
72 #define XL_CAPS_SLAVE_DMA 0x0008
73 #define XL_CAPS_SECOND_DMA 0x0010
74 #define XL_CAPS_FULL_BM 0x0020
75 #define XL_CAPS_FRAG_BM 0x0040
76 #define XL_CAPS_CRC_PASSTHRU 0x0080
77 #define XL_CAPS_TXDONE 0x0100
78 #define XL_CAPS_NO_TXLENGTH 0x0200
79 #define XL_CAPS_RX_REPEAT 0x0400
80 #define XL_CAPS_SNOOPING 0x0800
81 #define XL_CAPS_100MBPS 0x1000
82 #define XL_CAPS_PWRMGMT 0x2000
83
84 /*
85 * Bits in the software information 2 word
86 */
87 #define XL_SINFO2_FIXED_BCAST_RX_BUG 0x0002
88 #define XL_SINFO2_FIXED_ENDEC_LOOP_BUG 0x0004
89 #define XL_SINFO2_AUX_WOL_CON 0x0008
90 #define XL_SINFO2_PME_PULSED 0x0010
91 #define XL_SINFO2_FIXED_MWI_BUG 0x0020
92 #define XL_SINFO2_WOL_AFTER_PWR_LOSS 0x0040
93 #define XL_SINFO2_AUTO_RST_TO_D0 0x0080
94
95 #define XL_PACKET_SIZE 1540
96 #define XL_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)
97
98 /*
99 * Register layouts.
100 */
101 #define XL_COMMAND 0x0E
102 #define XL_STATUS 0x0E
103
104 #define XL_TX_STATUS 0x1B
105 #define XL_TX_FREE 0x1C
106 #define XL_DMACTL 0x20
107 #define XL_DOWNLIST_PTR 0x24
108 #define XL_DOWN_POLL 0x2D /* 3c90xB only */
109 #define XL_TX_FREETHRESH 0x2F
110 #define XL_UPLIST_PTR 0x38
111 #define XL_UPLIST_STATUS 0x30
112 #define XL_UP_POLL 0x3D /* 3c90xB only */
113
114 #define XL_PKTSTAT_UP_STALLED 0x00002000
115 #define XL_PKTSTAT_UP_ERROR 0x00004000
116 #define XL_PKTSTAT_UP_CMPLT 0x00008000
117
118 #define XL_DMACTL_DN_CMPLT_REQ 0x00000002
119 #define XL_DMACTL_DOWN_STALLED 0x00000004
120 #define XL_DMACTL_UP_CMPLT 0x00000008
121 #define XL_DMACTL_DOWN_CMPLT 0x00000010
122 #define XL_DMACTL_UP_RX_EARLY 0x00000020
123 #define XL_DMACTL_ARM_COUNTDOWN 0x00000040
124 #define XL_DMACTL_DOWN_INPROG 0x00000080
125 #define XL_DMACTL_COUNTER_SPEED 0x00000100
126 #define XL_DMACTL_DOWNDOWN_MODE 0x00000200
127 #define XL_DMACTL_TARGET_ABORT 0x40000000
128 #define XL_DMACTL_MASTER_ABORT 0x80000000
129
130 /*
131 * Command codes. Some command codes require that we wait for
132 * the CMD_BUSY flag to clear. Those codes are marked as 'mustwait.'
133 */
134 #define XL_CMD_RESET 0x0000 /* mustwait */
135 #define XL_CMD_WINSEL 0x0800
136 #define XL_CMD_COAX_START 0x1000
137 #define XL_CMD_RX_DISABLE 0x1800
138 #define XL_CMD_RX_ENABLE 0x2000
139 #define XL_CMD_RX_RESET 0x2800 /* mustwait */
140 #define XL_CMD_UP_STALL 0x3000 /* mustwait */
141 #define XL_CMD_UP_UNSTALL 0x3001
142 #define XL_CMD_DOWN_STALL 0x3002 /* mustwait */
143 #define XL_CMD_DOWN_UNSTALL 0x3003
144 #define XL_CMD_RX_DISCARD 0x4000
145 #define XL_CMD_TX_ENABLE 0x4800
146 #define XL_CMD_TX_DISABLE 0x5000
147 #define XL_CMD_TX_RESET 0x5800 /* mustwait */
148 #define XL_CMD_INTR_FAKE 0x6000
149 #define XL_CMD_INTR_ACK 0x6800
150 #define XL_CMD_INTR_ENB 0x7000
151 #define XL_CMD_STAT_ENB 0x7800
152 #define XL_CMD_RX_SET_FILT 0x8000
153 #define XL_CMD_RX_SET_THRESH 0x8800
154 #define XL_CMD_TX_SET_THRESH 0x9000
155 #define XL_CMD_TX_SET_START 0x9800
156 #define XL_CMD_DMA_UP 0xA000
157 #define XL_CMD_DMA_STOP 0xA001
158 #define XL_CMD_STATS_ENABLE 0xA800
159 #define XL_CMD_STATS_DISABLE 0xB000
160 #define XL_CMD_COAX_STOP 0xB800
161
162 #define XL_CMD_SET_TX_RECLAIM 0xC000 /* 3c905B only */
163 #define XL_CMD_RX_SET_HASH 0xC800 /* 3c905B only */
164
165 #define XL_HASH_SET 0x0400
166 #define XL_HASHFILT_SIZE 256
167
168 /*
169 * status codes
170 * Note that bits 15 to 13 indicate the currently visible register window
171 * which may be anything from 0 to 7.
172 */
173 #define XL_STAT_INTLATCH 0x0001 /* 0 */
174 #define XL_STAT_ADFAIL 0x0002 /* 1 */
175 #define XL_STAT_TX_COMPLETE 0x0004 /* 2 */
176 #define XL_STAT_TX_AVAIL 0x0008 /* 3 first generation */
177 #define XL_STAT_RX_COMPLETE 0x0010 /* 4 */
178 #define XL_STAT_RX_EARLY 0x0020 /* 5 */
179 #define XL_STAT_INTREQ 0x0040 /* 6 */
180 #define XL_STAT_STATSOFLOW 0x0080 /* 7 */
181 #define XL_STAT_DMADONE 0x0100 /* 8 first generation */
182 #define XL_STAT_LINKSTAT 0x0100 /* 8 3c509B */
183 #define XL_STAT_DOWN_COMPLETE 0x0200 /* 9 */
184 #define XL_STAT_UP_COMPLETE 0x0400 /* 10 */
185 #define XL_STAT_DMABUSY 0x0800 /* 11 first generation */
186 #define XL_STAT_CMDBUSY 0x1000 /* 12 */
187
188 /*
189 * Interrupts we normally want enabled.
190 */
191 #define XL_INTRS \
192 (XL_STAT_UP_COMPLETE|XL_STAT_STATSOFLOW|XL_STAT_ADFAIL| \
193 XL_STAT_DOWN_COMPLETE|XL_STAT_TX_COMPLETE|XL_STAT_INTLATCH)
194
195 /*
196 * Window 0 registers
197 */
198 #define XL_W0_EE_DATA 0x0C
199 #define XL_W0_EE_CMD 0x0A
200 #define XL_W0_RSRC_CFG 0x08
201 #define XL_W0_ADDR_CFG 0x06
202 #define XL_W0_CFG_CTRL 0x04
203
204 #define XL_W0_PROD_ID 0x02
205 #define XL_W0_MFG_ID 0x00
206
207 /*
208 * Window 1
209 */
210
211 #define XL_W1_TX_FIFO 0x10
212
213 #define XL_W1_FREE_TX 0x0C
214 #define XL_W1_TX_STATUS 0x0B
215 #define XL_W1_TX_TIMER 0x0A
216 #define XL_W1_RX_STATUS 0x08
217 #define XL_W1_RX_FIFO 0x00
218
219 /*
220 * RX status codes
221 */
222 #define XL_RXSTATUS_OVERRUN 0x01
223 #define XL_RXSTATUS_RUNT 0x02
224 #define XL_RXSTATUS_ALIGN 0x04
225 #define XL_RXSTATUS_CRC 0x08
226 #define XL_RXSTATUS_OVERSIZE 0x10
227 #define XL_RXSTATUS_DRIBBLE 0x20
228
229 /*
230 * TX status codes
231 */
232 #define XL_TXSTATUS_RECLAIM 0x02 /* 3c905B only */
233 #define XL_TXSTATUS_OVERFLOW 0x04
234 #define XL_TXSTATUS_MAXCOLS 0x08
235 #define XL_TXSTATUS_UNDERRUN 0x10
236 #define XL_TXSTATUS_JABBER 0x20
237 #define XL_TXSTATUS_INTREQ 0x40
238 #define XL_TXSTATUS_COMPLETE 0x80
239
240 /*
241 * Window 2
242 */
243 #define XL_W2_RESET_OPTIONS 0x0C /* 3c905B only */
244 #define XL_W2_STATION_MASK_HI 0x0A
245 #define XL_W2_STATION_MASK_MID 0x08
246 #define XL_W2_STATION_MASK_LO 0x06
247 #define XL_W2_STATION_ADDR_HI 0x04
248 #define XL_W2_STATION_ADDR_MID 0x02
249 #define XL_W2_STATION_ADDR_LO 0x00
250
251 #define XL_RESETOPT_FEATUREMASK (0x0001 | 0x0002 | 0x004)
252 #define XL_RESETOPT_D3RESETDIS 0x0008
253 #define XL_RESETOPT_DISADVFD 0x0010
254 #define XL_RESETOPT_DISADV100 0x0020
255 #define XL_RESETOPT_DISAUTONEG 0x0040
256 #define XL_RESETOPT_DEBUGMODE 0x0080
257 #define XL_RESETOPT_FASTAUTO 0x0100
258 #define XL_RESETOPT_FASTEE 0x0200
259 #define XL_RESETOPT_FORCEDCONF 0x0400
260 #define XL_RESETOPT_TESTPDTPDR 0x0800
261 #define XL_RESETOPT_TEST100TX 0x1000
262 #define XL_RESETOPT_TEST100RX 0x2000
263
264 #define XL_RESETOPT_INVERT_LED 0x0010
265 #define XL_RESETOPT_INVERT_MII 0x4000
266
267 /*
268 * Window 3 (fifo management)
269 */
270 #define XL_W3_INTERNAL_CFG 0x00
271 #define XL_W3_MAXPKTSIZE 0x04 /* 3c905B only */
272 #define XL_W3_RESET_OPT 0x08
273 #define XL_W3_FREE_TX 0x0C
274 #define XL_W3_FREE_RX 0x0A
275 #define XL_W3_MAC_CTRL 0x06
276
277 #define XL_ICFG_CONNECTOR_MASK 0x00F00000
278 #define XL_ICFG_CONNECTOR_BITS 20
279
280 #define XL_ICFG_RAMSIZE_MASK 0x00000007
281 #define XL_ICFG_RAMWIDTH 0x00000008
282 #define XL_ICFG_ROMSIZE_MASK (0x00000040 | 0x00000080)
283 #define XL_ICFG_DISABLE_BASSD 0x00000100
284 #define XL_ICFG_RAMLOC 0x00000200
285 #define XL_ICFG_RAMPART (0x00010000 | 0x00020000)
286 #define XL_ICFG_XCVRSEL (0x00100000 | 0x00200000 | 0x00400000)
287 #define XL_ICFG_AUTOSEL 0x01000000
288
289 #define XL_XCVR_10BT 0x00
290 #define XL_XCVR_AUI 0x01
291 #define XL_XCVR_RSVD_0 0x02
292 #define XL_XCVR_COAX 0x03
293 #define XL_XCVR_100BTX 0x04
294 #define XL_XCVR_100BFX 0x05
295 #define XL_XCVR_MII 0x06
296 #define XL_XCVR_RSVD_1 0x07
297 #define XL_XCVR_AUTO 0x08 /* 3c905B only */
298
299 #define XL_MACCTRL_DEFER_EXT_END 0x0001
300 #define XL_MACCTRL_DEFER_0 0x0002
301 #define XL_MACCTRL_DEFER_1 0x0004
302 #define XL_MACCTRL_DEFER_2 0x0008
303 #define XL_MACCTRL_DEFER_3 0x0010
304 #define XL_MACCTRL_DUPLEX 0x0020
305 #define XL_MACCTRL_ALLOW_LARGE_PACK 0x0040
306 #define XL_MACCTRL_EXTEND_AFTER_COL 0x0080 /* 3c905B only */
307 #define XL_MACCTRL_FLOW_CONTROL_ENB 0x0100 /* 3c905B only */
308 #define XL_MACCTRL_VLT_END 0x0200 /* 3c905B only */
309
310 /*
311 * The 'reset options' register contains power-on reset values
312 * loaded from the EEPROM. This includes the supported media
313 * types on the card. It is also known as the media options register.
314 */
315 #define XL_W3_MEDIA_OPT 0x08
316
317 #define XL_MEDIAOPT_BT4 0x0001 /* MII */
318 #define XL_MEDIAOPT_BTX 0x0002 /* on-chip */
319 #define XL_MEDIAOPT_BFX 0x0004 /* on-chip */
320 #define XL_MEDIAOPT_BT 0x0008 /* on-chip */
321 #define XL_MEDIAOPT_BNC 0x0010 /* on-chip */
322 #define XL_MEDIAOPT_AUI 0x0020 /* on-chip */
323 #define XL_MEDIAOPT_MII 0x0040 /* MII */
324 #define XL_MEDIAOPT_VCO 0x0100 /* 1st gen chip only */
325
326 #define XL_MEDIAOPT_10FL 0x0100 /* 3x905B only, on-chip */
327 #define XL_MEDIAOPT_MASK 0x01FF
328
329 /*
330 * Window 4 (diagnostics)
331 */
332 #define XL_W4_UPPERBYTESOK 0x0D
333 #define XL_W4_BADSSD 0x0C
334 #define XL_W4_MEDIA_STATUS 0x0A
335 #define XL_W4_PHY_MGMT 0x08
336 #define XL_W4_NET_DIAG 0x06
337 #define XL_W4_FIFO_DIAG 0x04
338 #define XL_W4_VCO_DIAG 0x02
339
340 #define XL_W4_CTRLR_STAT 0x08
341 #define XL_W4_TX_DIAG 0x00
342
343 #define XL_MII_CLK 0x01
344 #define XL_MII_DATA 0x02
345 #define XL_MII_DIR 0x04
346
347 #define XL_MEDIA_SQE 0x0008
348 #define XL_MEDIA_10TP 0x00C0
349 #define XL_MEDIA_LNK 0x0080
350 #define XL_MEDIA_LNKBEAT 0x0800
351
352 #define XL_MEDIASTAT_CRCSTRIP 0x0004
353 #define XL_MEDIASTAT_SQEENB 0x0008
354 #define XL_MEDIASTAT_COLDET 0x0010
355 #define XL_MEDIASTAT_CARRIER 0x0020
356 #define XL_MEDIASTAT_JABGUARD 0x0040
357 #define XL_MEDIASTAT_LINKBEAT 0x0080
358 #define XL_MEDIASTAT_JABDETECT 0x0200
359 #define XL_MEDIASTAT_POLREVERS 0x0400
360 #define XL_MEDIASTAT_LINKDETECT 0x0800
361 #define XL_MEDIASTAT_TXINPROG 0x1000
362 #define XL_MEDIASTAT_DCENB 0x4000
363 #define XL_MEDIASTAT_AUIDIS 0x8000
364
365 #define XL_NETDIAG_TEST_LOWVOLT 0x0001
366 #define XL_NETDIAG_ASIC_REVMASK \
367 (0x0002 | 0x0004 | 0x0008 | 0x0010 | 0x0020)
368 #define XL_NETDIAG_UPPER_BYTES_ENABLE 0x0040
369 #define XL_NETDIAG_STATS_ENABLED 0x0080
370 #define XL_NETDIAG_TX_FATALERR 0x0100
371 #define XL_NETDIAG_TRANSMITTING 0x0200
372 #define XL_NETDIAG_RX_ENABLED 0x0400
373 #define XL_NETDIAG_TX_ENABLED 0x0800
374 #define XL_NETDIAG_FIFO_LOOPBACK 0x1000
375 #define XL_NETDIAG_MAC_LOOPBACK 0x2000
376 #define XL_NETDIAG_ENDEC_LOOPBACK 0x4000
377 #define XL_NETDIAG_EXTERNAL_LOOP 0x8000
378
379 /*
380 * Window 5
381 */
382 #define XL_W5_STAT_ENB 0x0C
383 #define XL_W5_INTR_ENB 0x0A
384 #define XL_W5_RECLAIM_THRESH 0x09 /* 3c905B only */
385 #define XL_W5_RX_FILTER 0x08
386 #define XL_W5_RX_EARLYTHRESH 0x06
387 #define XL_W5_TX_AVAILTHRESH 0x02
388 #define XL_W5_TX_STARTTHRESH 0x00
389
390 /*
391 * RX filter bits
392 */
393 #define XL_RXFILTER_INDIVIDUAL 0x01
394 #define XL_RXFILTER_ALLMULTI 0x02
395 #define XL_RXFILTER_BROADCAST 0x04
396 #define XL_RXFILTER_ALLFRAMES 0x08
397 #define XL_RXFILTER_MULTIHASH 0x10 /* 3c905B only */
398
399 /*
400 * Window 6 (stats)
401 */
402 #define XL_W6_TX_BYTES_OK 0x0C
403 #define XL_W6_RX_BYTES_OK 0x0A
404 #define XL_W6_UPPER_FRAMES_OK 0x09
405 #define XL_W6_DEFERRED 0x08
406 #define XL_W6_RX_OK 0x07
407 #define XL_W6_TX_OK 0x06
408 #define XL_W6_RX_OVERRUN 0x05
409 #define XL_W6_COL_LATE 0x04
410 #define XL_W6_COL_SINGLE 0x03
411 #define XL_W6_COL_MULTIPLE 0x02
412 #define XL_W6_SQE_ERRORS 0x01
413 #define XL_W6_CARRIER_LOST 0x00
414
415 /*
416 * Window 7 (bus master control)
417 */
418 #define XL_W7_BM_ADDR 0x00
419 #define XL_W7_BM_LEN 0x06
420 #define XL_W7_BM_STATUS 0x0B
421 #define XL_W7_BM_TIMEr 0x0A
422 #define XL_W7_BM_PME 0x0C
423
424 #define XL_BM_PME_WAKE 0x0001
425 #define XL_BM_PME_MAGIC 0x0002
426 #define XL_BM_PME_LINKCHG 0x0004
427 #define XL_BM_PME_WAKETIMER 0x0008
428 /*
429 * bus master control registers
430 */
431 #define XL_BM_PKTSTAT 0x20
432 #define XL_BM_DOWNLISTPTR 0x24
433 #define XL_BM_FRAGADDR 0x28
434 #define XL_BM_FRAGLEN 0x2C
435 #define XL_BM_TXFREETHRESH 0x2F
436 #define XL_BM_UPPKTSTAT 0x30
437 #define XL_BM_UPLISTPTR 0x38
438
439 #define XL_LAST_FRAG 0x80000000
440
441 #define XL_MAXFRAGS 63
442 #define XL_RX_LIST_CNT 128
443 #define XL_TX_LIST_CNT 256
444 #define XL_RX_LIST_SZ \
445 (XL_RX_LIST_CNT * sizeof(struct xl_list_onefrag))
446 #define XL_TX_LIST_SZ \
447 (XL_TX_LIST_CNT * sizeof(struct xl_list))
448 #define XL_MIN_FRAMELEN 60
449 #define ETHER_ALIGN 2
450 #define XL_INC(x, y) (x) = (x + 1) % y
451
452 /*
453 * Boomerang/Cyclone TX/RX list structure.
454 * For the TX lists, bits 0 to 12 of the status word indicate
455 * length.
456 * This looks suspiciously like the ThunderLAN, doesn't it.
457 */
458 struct xl_frag {
459 u_int32_t xl_addr; /* 63 addr/len pairs */
460 u_int32_t xl_len;
461 };
462
463 struct xl_list {
464 u_int32_t xl_next; /* final entry has 0 nextptr */
465 u_int32_t xl_status;
466 struct xl_frag xl_frag[XL_MAXFRAGS];
467 };
468
469 struct xl_list_onefrag {
470 u_int32_t xl_next; /* final entry has 0 nextptr */
471 u_int32_t xl_status;
472 struct xl_frag xl_frag;
473 };
474
475 struct xl_list_data {
476 struct xl_list_onefrag *xl_rx_list;
477 struct xl_list *xl_tx_list;
478 u_int32_t xl_rx_dmaaddr;
479 bus_dma_tag_t xl_rx_tag;
480 bus_dmamap_t xl_rx_dmamap;
481 u_int32_t xl_tx_dmaaddr;
482 bus_dma_tag_t xl_tx_tag;
483 bus_dmamap_t xl_tx_dmamap;
484 };
485
486 struct xl_chain {
487 struct xl_list *xl_ptr;
488 struct mbuf *xl_mbuf;
489 struct xl_chain *xl_next;
490 struct xl_chain *xl_prev;
491 u_int32_t xl_phys;
492 bus_dmamap_t xl_map;
493 };
494
495 struct xl_chain_onefrag {
496 struct xl_list_onefrag *xl_ptr;
497 struct mbuf *xl_mbuf;
498 struct xl_chain_onefrag *xl_next;
499 bus_dmamap_t xl_map;
500 };
501
502 struct xl_chain_data {
503 struct xl_chain_onefrag xl_rx_chain[XL_RX_LIST_CNT];
504 struct xl_chain xl_tx_chain[XL_TX_LIST_CNT];
505 bus_dma_segment_t xl_tx_segs[XL_MAXFRAGS];
506
507 struct xl_chain_onefrag *xl_rx_head;
508
509 /* 3c90x "boomerang" queuing stuff */
510 struct xl_chain *xl_tx_head;
511 struct xl_chain *xl_tx_tail;
512 struct xl_chain *xl_tx_free;
513
514 /* 3c90xB "cyclone/hurricane/tornado" stuff */
515 int xl_tx_prod;
516 int xl_tx_cons;
517 int xl_tx_cnt;
518 };
519
520 #define XL_RXSTAT_LENMASK 0x00001FFF
521 #define XL_RXSTAT_UP_ERROR 0x00004000
522 #define XL_RXSTAT_UP_CMPLT 0x00008000
523 #define XL_RXSTAT_UP_OVERRUN 0x00010000
524 #define XL_RXSTAT_RUNT 0x00020000
525 #define XL_RXSTAT_ALIGN 0x00040000
526 #define XL_RXSTAT_CRC 0x00080000
527 #define XL_RXSTAT_OVERSIZE 0x00100000
528 #define XL_RXSTAT_DRIBBLE 0x00800000
529 #define XL_RXSTAT_UP_OFLOW 0x01000000
530 #define XL_RXSTAT_IPCKERR 0x02000000 /* 3c905B only */
531 #define XL_RXSTAT_TCPCKERR 0x04000000 /* 3c905B only */
532 #define XL_RXSTAT_UDPCKERR 0x08000000 /* 3c905B only */
533 #define XL_RXSTAT_BUFEN 0x10000000 /* 3c905B only */
534 #define XL_RXSTAT_IPCKOK 0x20000000 /* 3c905B only */
535 #define XL_RXSTAT_TCPCOK 0x40000000 /* 3c905B only */
536 #define XL_RXSTAT_UDPCKOK 0x80000000 /* 3c905B only */
537
538 #define XL_TXSTAT_LENMASK 0x00001FFF
539 #define XL_TXSTAT_CRCDIS 0x00002000
540 #define XL_TXSTAT_TX_INTR 0x00008000
541 #define XL_TXSTAT_DL_COMPLETE 0x00010000
542 #define XL_TXSTAT_IPCKSUM 0x02000000 /* 3c905B only */
543 #define XL_TXSTAT_TCPCKSUM 0x04000000 /* 3c905B only */
544 #define XL_TXSTAT_UDPCKSUM 0x08000000 /* 3c905B only */
545 #define XL_TXSTAT_RND_DEFEAT 0x10000000 /* 3c905B only */
546 #define XL_TXSTAT_EMPTY 0x20000000 /* 3c905B only */
547 #define XL_TXSTAT_DL_INTR 0x80000000
548
549 #define XL_CAPABILITY_BM 0x20
550
551 struct xl_type {
552 u_int16_t xl_vid;
553 u_int16_t xl_did;
554 char *xl_name;
555 };
556
557 struct xl_mii_frame {
558 u_int8_t mii_stdelim;
559 u_int8_t mii_opcode;
560 u_int8_t mii_phyaddr;
561 u_int8_t mii_regaddr;
562 u_int8_t mii_turnaround;
563 u_int16_t mii_data;
564 };
565
566 /*
567 * MII constants
568 */
569 #define XL_MII_STARTDELIM 0x01
570 #define XL_MII_READOP 0x02
571 #define XL_MII_WRITEOP 0x01
572 #define XL_MII_TURNAROUND 0x02
573
574 /*
575 * The 3C905B adapters implement a few features that we want to
576 * take advantage of, namely the multicast hash filter. With older
577 * chips, you only have the option of turning on reception of all
578 * multicast frames, which is kind of lame.
579 *
580 * We also use this to decide on a transmit strategy. For the 3c90xB
581 * cards, we can use polled descriptor mode, which reduces CPU overhead.
582 */
583 #define XL_TYPE_905B 1
584 #define XL_TYPE_90X 2
585
586 #define XL_FLAG_FUNCREG 0x0001
587 #define XL_FLAG_PHYOK 0x0002
588 #define XL_FLAG_EEPROM_OFFSET_30 0x0004
589 #define XL_FLAG_WEIRDRESET 0x0008
590 #define XL_FLAG_8BITROM 0x0010
591 #define XL_FLAG_INVERT_LED_PWR 0x0020
592 #define XL_FLAG_INVERT_MII_PWR 0x0040
593 #define XL_FLAG_NO_XCVR_PWR 0x0080
594 #define XL_FLAG_USE_MMIO 0x0100
595 #define XL_FLAG_NO_MMIO 0x0200
596 #define XL_FLAG_WOL 0x0400
597
598 #define XL_NO_XCVR_PWR_MAGICBITS 0x0900
599
600 struct xl_softc {
601 struct ifnet *xl_ifp; /* interface info */
602 device_t xl_dev; /* device info */
603 struct ifmedia ifmedia; /* media info */
604 bus_space_handle_t xl_bhandle;
605 bus_space_tag_t xl_btag;
606 void *xl_intrhand;
607 struct resource *xl_irq;
608 struct resource *xl_res;
609 device_t xl_miibus;
610 const struct xl_type *xl_info; /* 3Com adapter info */
611 bus_dma_tag_t xl_mtag;
612 bus_dmamap_t xl_tmpmap; /* spare DMA map */
613 u_int8_t xl_unit; /* interface number */
614 u_int8_t xl_type;
615 u_int32_t xl_xcvr;
616 u_int16_t xl_media;
617 u_int16_t xl_caps;
618 u_int8_t xl_stats_no_timeout;
619 u_int16_t xl_tx_thresh;
620 int xl_pmcap;
621 int xl_if_flags;
622 struct xl_list_data xl_ldata;
623 struct xl_chain_data xl_cdata;
624 struct callout xl_stat_callout;
625 int xl_wdog_timer;
626 int xl_flags;
627 struct resource *xl_fres;
628 bus_space_handle_t xl_fhandle;
629 bus_space_tag_t xl_ftag;
630 struct mtx xl_mtx;
631 struct task xl_task;
632 #ifdef DEVICE_POLLING
633 int rxcycles;
634 #endif
635 };
636
637 #define XL_LOCK(_sc) mtx_lock(&(_sc)->xl_mtx)
638 #define XL_UNLOCK(_sc) mtx_unlock(&(_sc)->xl_mtx)
639 #define XL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->xl_mtx, MA_OWNED)
640
641 #define xl_rx_goodframes(x) \
642 ((x.xl_upper_frames_ok & 0x03) << 8) | x.xl_rx_frames_ok
643
644 #define xl_tx_goodframes(x) \
645 ((x.xl_upper_frames_ok & 0x30) << 4) | x.xl_tx_frames_ok
646
647 struct xl_stats {
648 u_int8_t xl_carrier_lost;
649 u_int8_t xl_sqe_errs;
650 u_int8_t xl_tx_multi_collision;
651 u_int8_t xl_tx_single_collision;
652 u_int8_t xl_tx_late_collision;
653 u_int8_t xl_rx_overrun;
654 u_int8_t xl_tx_frames_ok;
655 u_int8_t xl_rx_frames_ok;
656 u_int8_t xl_tx_deferred;
657 u_int8_t xl_upper_frames_ok;
658 u_int16_t xl_rx_bytes_ok;
659 u_int16_t xl_tx_bytes_ok;
660 u_int16_t status;
661 };
662
663 /*
664 * register space access macros
665 */
666 #define CSR_WRITE_4(sc, reg, val) \
667 bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val)
668 #define CSR_WRITE_2(sc, reg, val) \
669 bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val)
670 #define CSR_WRITE_1(sc, reg, val) \
671 bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val)
672
673 #define CSR_READ_4(sc, reg) \
674 bus_space_read_4(sc->xl_btag, sc->xl_bhandle, reg)
675 #define CSR_READ_2(sc, reg) \
676 bus_space_read_2(sc->xl_btag, sc->xl_bhandle, reg)
677 #define CSR_READ_1(sc, reg) \
678 bus_space_read_1(sc->xl_btag, sc->xl_bhandle, reg)
679
680 #define XL_SEL_WIN(x) \
681 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x)
682 #define XL_TIMEOUT 1000
683
684 /*
685 * General constants that are fun to know.
686 *
687 * 3Com PCI vendor ID
688 */
689 #define TC_VENDORID 0x10B7
690
691 /*
692 * 3Com chip device IDs.
693 */
694 #define TC_DEVICEID_BOOMERANG_10BT 0x9000
695 #define TC_DEVICEID_BOOMERANG_10BT_COMBO 0x9001
696 #define TC_DEVICEID_BOOMERANG_10_100BT 0x9050
697 #define TC_DEVICEID_BOOMERANG_100BT4 0x9051
698 #define TC_DEVICEID_KRAKATOA_10BT 0x9004
699 #define TC_DEVICEID_KRAKATOA_10BT_COMBO 0x9005
700 #define TC_DEVICEID_KRAKATOA_10BT_TPC 0x9006
701 #define TC_DEVICEID_CYCLONE_10FL 0x900A
702 #define TC_DEVICEID_HURRICANE_10_100BT 0x9055
703 #define TC_DEVICEID_CYCLONE_10_100BT4 0x9056
704 #define TC_DEVICEID_CYCLONE_10_100_COMBO 0x9058
705 #define TC_DEVICEID_CYCLONE_10_100FX 0x905A
706 #define TC_DEVICEID_TORNADO_10_100BT 0x9200
707 #define TC_DEVICEID_TORNADO_10_100BT_920B 0x9201
708 #define TC_DEVICEID_TORNADO_10_100BT_920B_WNM 0x9202
709 #define TC_DEVICEID_HURRICANE_10_100BT_SERV 0x9800
710 #define TC_DEVICEID_TORNADO_10_100BT_SERV 0x9805
711 #define TC_DEVICEID_HURRICANE_SOHO100TX 0x7646
712 #define TC_DEVICEID_TORNADO_HOMECONNECT 0x4500
713 #define TC_DEVICEID_HURRICANE_555 0x5055
714 #define TC_DEVICEID_HURRICANE_556 0x6055
715 #define TC_DEVICEID_HURRICANE_556B 0x6056
716 #define TC_DEVICEID_HURRICANE_575A 0x5057
717 #define TC_DEVICEID_HURRICANE_575B 0x5157
718 #define TC_DEVICEID_HURRICANE_575C 0x5257
719 #define TC_DEVICEID_HURRICANE_656 0x6560
720 #define TC_DEVICEID_HURRICANE_656B 0x6562
721 #define TC_DEVICEID_TORNADO_656C 0x6564
722
723 /*
724 * PCI low memory base and low I/O base register, and
725 * other PCI registers. Note: some are only available on
726 * the 3c905B, in particular those that related to power management.
727 */
728 #define XL_PCI_VENDOR_ID 0x00
729 #define XL_PCI_DEVICE_ID 0x02
730 #define XL_PCI_COMMAND 0x04
731 #define XL_PCI_STATUS 0x06
732 #define XL_PCI_CLASSCODE 0x09
733 #define XL_PCI_LATENCY_TIMER 0x0D
734 #define XL_PCI_HEADER_TYPE 0x0E
735 #define XL_PCI_LOIO 0x10
736 #define XL_PCI_LOMEM 0x14
737 #define XL_PCI_FUNCMEM 0x18
738 #define XL_PCI_BIOSROM 0x30
739 #define XL_PCI_INTLINE 0x3C
740 #define XL_PCI_INTPIN 0x3D
741 #define XL_PCI_MINGNT 0x3E
742 #define XL_PCI_MINLAT 0x0F
743 #define XL_PCI_RESETOPT 0x48
744 #define XL_PCI_EEPROM_DATA 0x4C
745
746 /* 3c905B-only registers */
747 #define XL_PCI_CAPID 0xDC /* 8 bits */
748 #define XL_PCI_NEXTPTR 0xDD /* 8 bits */
749 #define XL_PCI_PWRMGMTCAP 0xDE /* 16 bits */
750 #define XL_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */
751
752 #define XL_PSTATE_MASK 0x0003
753 #define XL_PSTATE_D0 0x0000
754 #define XL_PSTATE_D1 0x0002
755 #define XL_PSTATE_D2 0x0002
756 #define XL_PSTATE_D3 0x0003
757 #define XL_PME_EN 0x0010
758 #define XL_PME_STATUS 0x8000
759
760 #ifndef IFM_10_FL
761 #define IFM_10_FL 13 /* 10baseFL - Fiber */
762 #endif
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