FreeBSD/Linux Kernel Cross Reference
sys/pci/if_xlreg.h
1 /*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_xlreg.h,v 1.3.2.8 1999/09/05 08:21:16 peter Exp $
33 */
34
35 #define XL_EE_READ 0x0080 /* read, 5 bit address */
36 #define XL_EE_WRITE 0x0040 /* write, 5 bit address */
37 #define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */
38 #define XL_EE_EWEN 0x0030 /* erase, no data needed */
39 #define XL_EE_BUSY 0x8000
40
41 #define XL_EE_EADDR0 0x00 /* station address, first word */
42 #define XL_EE_EADDR1 0x01 /* station address, next word, */
43 #define XL_EE_EADDR2 0x02 /* station address, last word */
44 #define XL_EE_PRODID 0x03 /* product ID code */
45 #define XL_EE_MDATA_DATE 0x04 /* manufacturing data, date */
46 #define XL_EE_MDATA_DIV 0x05 /* manufacturing data, division */
47 #define XL_EE_MDATA_PCODE 0x06 /* manufacturing data, product code */
48 #define XL_EE_MFG_ID 0x07
49 #define XL_EE_PCI_PARM 0x08
50 #define XL_EE_ROM_ONFO 0x09
51 #define XL_EE_OEM_ADR0 0x0A
52 #define XL_EE_OEM_ADR1 0x0B
53 #define XL_EE_OEM_ADR2 0x0C
54 #define XL_EE_SOFTINFO1 0x0D
55 #define XL_EE_COMPAT 0x0E
56 #define XL_EE_SOFTINFO2 0x0F
57 #define XL_EE_CAPS 0x10 /* capabilities word */
58 #define XL_EE_RSVD0 0x11
59 #define XL_EE_ICFG_0 0x12
60 #define XL_EE_ICFG_1 0x13
61 #define XL_EE_RSVD1 0x14
62 #define XL_EE_SOFTINFO3 0x15
63 #define XL_EE_RSVD_2 0x16
64
65 /*
66 * Bits in the capabilities word
67 */
68 #define XL_CAPS_PNP 0x0001
69 #define XL_CAPS_FULL_DUPLEX 0x0002
70 #define XL_CAPS_LARGE_PKTS 0x0004
71 #define XL_CAPS_SLAVE_DMA 0x0008
72 #define XL_CAPS_SECOND_DMA 0x0010
73 #define XL_CAPS_FULL_BM 0x0020
74 #define XL_CAPS_FRAG_BM 0x0040
75 #define XL_CAPS_CRC_PASSTHRU 0x0080
76 #define XL_CAPS_TXDONE 0x0100
77 #define XL_CAPS_NO_TXLENGTH 0x0200
78 #define XL_CAPS_RX_REPEAT 0x0400
79 #define XL_CAPS_SNOOPING 0x0800
80 #define XL_CAPS_100MBPS 0x1000
81 #define XL_CAPS_PWRMGMT 0x2000
82
83 #define XL_PACKET_SIZE 1536
84
85 /*
86 * Register layouts.
87 */
88 #define XL_COMMAND 0x0E
89 #define XL_STATUS 0x0E
90
91 #define XL_TX_STATUS 0x1B
92 #define XL_TX_FREE 0x1C
93 #define XL_DMACTL 0x20
94 #define XL_DOWNLIST_PTR 0x24
95 #define XL_TX_FREETHRESH 0x2F
96 #define XL_UPLIST_PTR 0x38
97 #define XL_UPLIST_STATUS 0x30
98
99 #define XL_PKTSTAT_UP_STALLED 0x00002000
100 #define XL_PKTSTAT_UP_ERROR 0x00004000
101 #define XL_PKTSTAT_UP_CMPLT 0x00008000
102
103 #define XL_DMACTL_DN_CMPLT_REQ 0x00000002
104 #define XL_DMACTL_DOWN_STALLED 0x00000004
105 #define XL_DMACTL_UP_CMPLT 0x00000008
106 #define XL_DMACTL_DOWN_CMPLT 0x00000010
107 #define XL_DMACTL_UP_RX_EARLY 0x00000020
108 #define XL_DMACTL_ARM_COUNTDOWN 0x00000040
109 #define XL_DMACTL_DOWN_INPROG 0x00000080
110 #define XL_DMACTL_COUNTER_SPEED 0x00000100
111 #define XL_DMACTL_DOWNDOWN_MODE 0x00000200
112 #define XL_DMACTL_TARGET_ABORT 0x40000000
113 #define XL_DMACTL_MASTER_ABORT 0x80000000
114
115 /*
116 * Command codes. Some command codes require that we wait for
117 * the CMD_BUSY flag to clear. Those codes are marked as 'mustwait.'
118 */
119 #define XL_CMD_RESET 0x0000 /* mustwait */
120 #define XL_CMD_WINSEL 0x0800
121 #define XL_CMD_COAX_START 0x1000
122 #define XL_CMD_RX_DISABLE 0x1800
123 #define XL_CMD_RX_ENABLE 0x2000
124 #define XL_CMD_RX_RESET 0x2800 /* mustwait */
125 #define XL_CMD_UP_STALL 0x3000 /* mustwait */
126 #define XL_CMD_UP_UNSTALL 0x3001
127 #define XL_CMD_DOWN_STALL 0x3002 /* mustwait */
128 #define XL_CMD_DOWN_UNSTALL 0x3003
129 #define XL_CMD_RX_DISCARD 0x4000
130 #define XL_CMD_TX_ENABLE 0x4800
131 #define XL_CMD_TX_DISABLE 0x5000
132 #define XL_CMD_TX_RESET 0x5800 /* mustwait */
133 #define XL_CMD_INTR_FAKE 0x6000
134 #define XL_CMD_INTR_ACK 0x6800
135 #define XL_CMD_INTR_ENB 0x7000
136 #define XL_CMD_STAT_ENB 0x7800
137 #define XL_CMD_RX_SET_FILT 0x8000
138 #define XL_CMD_RX_SET_THRESH 0x8800
139 #define XL_CMD_TX_SET_THRESH 0x9000
140 #define XL_CMD_TX_SET_START 0x9800
141 #define XL_CMD_DMA_UP 0xA000
142 #define XL_CMD_DMA_STOP 0xA001
143 #define XL_CMD_STATS_ENABLE 0xA800
144 #define XL_CMD_STATS_DISABLE 0xB000
145 #define XL_CMD_COAX_STOP 0xB800
146
147 #define XL_CMD_SET_TX_RECLAIM 0xC000 /* 3c905B only */
148 #define XL_CMD_RX_SET_HASH 0xC800 /* 3c905B only */
149
150 #define XL_HASH_SET 0x0400
151 #define XL_HASHFILT_SIZE 256
152
153 /*
154 * status codes
155 * Note that bits 15 to 13 indicate the currently visible register window
156 * which may be anything from 0 to 7.
157 */
158 #define XL_STAT_INTLATCH 0x0001 /* 0 */
159 #define XL_STAT_ADFAIL 0x0002 /* 1 */
160 #define XL_STAT_TX_COMPLETE 0x0004 /* 2 */
161 #define XL_STAT_TX_AVAIL 0x0008 /* 3 first generation */
162 #define XL_STAT_RX_COMPLETE 0x0010 /* 4 */
163 #define XL_STAT_RX_EARLY 0x0020 /* 5 */
164 #define XL_STAT_INTREQ 0x0040 /* 6 */
165 #define XL_STAT_STATSOFLOW 0x0080 /* 7 */
166 #define XL_STAT_DMADONE 0x0100 /* 8 first generation */
167 #define XL_STAT_LINKSTAT 0x0100 /* 8 3c509B */
168 #define XL_STAT_DOWN_COMPLETE 0x0200 /* 9 */
169 #define XL_STAT_UP_COMPLETE 0x0400 /* 10 */
170 #define XL_STAT_DMABUSY 0x0800 /* 11 first generation */
171 #define XL_STAT_CMDBUSY 0x1000 /* 12 */
172
173 /*
174 * Interrupts we normally want enabled.
175 */
176 #define XL_INTRS \
177 (XL_STAT_UP_COMPLETE|XL_STAT_STATSOFLOW|XL_STAT_ADFAIL| \
178 XL_STAT_DOWN_COMPLETE|XL_STAT_TX_COMPLETE|XL_STAT_INTLATCH)
179
180 /*
181 * Window 0 registers
182 */
183 #define XL_W0_EE_DATA 0x0C
184 #define XL_W0_EE_CMD 0x0A
185 #define XL_W0_RSRC_CFG 0x08
186 #define XL_W0_ADDR_CFG 0x06
187 #define XL_W0_CFG_CTRL 0x04
188
189 #define XL_W0_PROD_ID 0x02
190 #define XL_W0_MFG_ID 0x00
191
192 /*
193 * Window 1
194 */
195
196 #define XL_W1_TX_FIFO 0x10
197
198 #define XL_W1_FREE_TX 0x0C
199 #define XL_W1_TX_STATUS 0x0B
200 #define XL_W1_TX_TIMER 0x0A
201 #define XL_W1_RX_STATUS 0x08
202 #define XL_W1_RX_FIFO 0x00
203
204 /*
205 * RX status codes
206 */
207 #define XL_RXSTATUS_OVERRUN 0x01
208 #define XL_RXSTATUS_RUNT 0x02
209 #define XL_RXSTATUS_ALIGN 0x04
210 #define XL_RXSTATUS_CRC 0x08
211 #define XL_RXSTATUS_OVERSIZE 0x10
212 #define XL_RXSTATUS_DRIBBLE 0x20
213
214 /*
215 * TX status codes
216 */
217 #define XL_TXSTATUS_RECLAIM 0x02 /* 3c905B only */
218 #define XL_TXSTATUS_OVERFLOW 0x04
219 #define XL_TXSTATUS_MAXCOLS 0x08
220 #define XL_TXSTATUS_UNDERRUN 0x10
221 #define XL_TXSTATUS_JABBER 0x20
222 #define XL_TXSTATUS_INTREQ 0x40
223 #define XL_TXSTATUS_COMPLETE 0x80
224
225 /*
226 * Window 2
227 */
228 #define XL_W2_RESET_OPTIONS 0x0C /* 3c905B only */
229 #define XL_W2_STATION_MASK_HI 0x0A
230 #define XL_W2_STATION_MASK_MID 0x08
231 #define XL_W2_STATION_MASK_LO 0x06
232 #define XL_W2_STATION_ADDR_HI 0x04
233 #define XL_W2_STATION_ADDR_MID 0x02
234 #define XL_W2_STATION_ADDR_LO 0x00
235
236 #define XL_RESETOPT_FEATUREMASK 0x0001|0x0002|0x004
237 #define XL_RESETOPT_D3RESETDIS 0x0008
238 #define XL_RESETOPT_DISADVFD 0x0010
239 #define XL_RESETOPT_DISADV100 0x0020
240 #define XL_RESETOPT_DISAUTONEG 0x0040
241 #define XL_RESETOPT_DEBUGMODE 0x0080
242 #define XL_RESETOPT_FASTAUTO 0x0100
243 #define XL_RESETOPT_FASTEE 0x0200
244 #define XL_RESETOPT_FORCEDCONF 0x0400
245 #define XL_RESETOPT_TESTPDTPDR 0x0800
246 #define XL_RESETOPT_TEST100TX 0x1000
247 #define XL_RESETOPT_TEST100RX 0x2000
248
249 /*
250 * Window 3 (fifo management)
251 */
252 #define XL_W3_INTERNAL_CFG 0x00
253 #define XL_W3_RESET_OPT 0x08
254 #define XL_W3_FREE_TX 0x0C
255 #define XL_W3_FREE_RX 0x0A
256 #define XL_W3_MAC_CTRL 0x06
257
258 #define XL_ICFG_CONNECTOR_MASK 0x00F00000
259 #define XL_ICFG_CONNECTOR_BITS 20
260
261 #define XL_ICFG_RAMSIZE_MASK 0x00000007
262 #define XL_ICFG_RAMWIDTH 0x00000008
263 #define XL_ICFG_ROMSIZE_MASK (0x00000040|0x00000080)
264 #define XL_ICFG_DISABLE_BASSD 0x00000100
265 #define XL_ICFG_RAMLOC 0x00000200
266 #define XL_ICFG_RAMPART (0x00010000|0x00020000)
267 #define XL_ICFG_XCVRSEL (0x00100000|0x00200000|0x00400000)
268 #define XL_ICFG_AUTOSEL 0x01000000
269
270 #define XL_XCVR_10BT 0x00
271 #define XL_XCVR_AUI 0x01
272 #define XL_XCVR_RSVD_0 0x02
273 #define XL_XCVR_COAX 0x03
274 #define XL_XCVR_100BTX 0x04
275 #define XL_XCVR_100BFX 0x05
276 #define XL_XCVR_MII 0x06
277 #define XL_XCVR_RSVD_1 0x07
278 #define XL_XCVR_AUTO 0x08 /* 3c905B only */
279
280 #define XL_MACCTRL_DEFER_EXT_END 0x0001
281 #define XL_MACCTRL_DEFER_0 0x0002
282 #define XL_MACCTRL_DEFER_1 0x0004
283 #define XL_MACCTRL_DEFER_2 0x0008
284 #define XL_MACCTRL_DEFER_3 0x0010
285 #define XL_MACCTRL_DUPLEX 0x0020
286 #define XL_MACCTRL_ALLOW_LARGE_PACK 0x0040
287 #define XL_MACCTRL_EXTEND_AFTER_COL 0x0080 (3c905B only)
288 #define XL_MACCTRL_FLOW_CONTROL_ENB 0x0100 (3c905B only)
289 #define XL_MACCTRL_VLT_END 0x0200 (3c905B only)
290
291 /*
292 * The 'reset options' register contains power-on reset values
293 * loaded from the EEPROM. This includes the supported media
294 * types on the card. It is also known as the media options register.
295 */
296 #define XL_W3_MEDIA_OPT 0x08
297
298 #define XL_MEDIAOPT_BT4 0x0001 /* MII */
299 #define XL_MEDIAOPT_BTX 0x0002 /* on-chip */
300 #define XL_MEDIAOPT_BFX 0x0004 /* on-chip */
301 #define XL_MEDIAOPT_BT 0x0008 /* on-chip */
302 #define XL_MEDIAOPT_BNC 0x0010 /* on-chip */
303 #define XL_MEDIAOPT_AUI 0x0020 /* on-chip */
304 #define XL_MEDIAOPT_MII 0x0040 /* MII */
305 #define XL_MEDIAOPT_VCO 0x0100 /* 1st gen chip only */
306
307 #define XL_MEDIAOPT_10FL 0x0100 /* 3x905B only, on-chip */
308 #define XL_MEDIAOPT_MASK 0x01FF
309
310 /*
311 * Window 4 (diagnostics)
312 */
313 #define XL_W4_UPPERBYTESOK 0x0D
314 #define XL_W4_BADSSD 0x0C
315 #define XL_W4_MEDIA_STATUS 0x0A
316 #define XL_W4_PHY_MGMT 0x08
317 #define XL_W4_NET_DIAG 0x06
318 #define XL_W4_FIFO_DIAG 0x04
319 #define XL_W4_VCO_DIAG 0x02
320
321 #define XL_W4_CTRLR_STAT 0x08
322 #define XL_W4_TX_DIAG 0x00
323
324 #define XL_MII_CLK 0x01
325 #define XL_MII_DATA 0x02
326 #define XL_MII_DIR 0x04
327
328 #define XL_MEDIA_SQE 0x0008
329 #define XL_MEDIA_10TP 0x00C0
330 #define XL_MEDIA_LNK 0x0080
331 #define XL_MEDIA_LNKBEAT 0x0800
332
333 #define XL_MEDIASTAT_CRCSTRIP 0x0004
334 #define XL_MEDIASTAT_SQEENB 0x0008
335 #define XL_MEDIASTAT_COLDET 0x0010
336 #define XL_MEDIASTAT_CARRIER 0x0020
337 #define XL_MEDIASTAT_JABGUARD 0x0040
338 #define XL_MEDIASTAT_LINKBEAT 0x0080
339 #define XL_MEDIASTAT_JABDETECT 0x0200
340 #define XL_MEDIASTAT_POLREVERS 0x0400
341 #define XL_MEDIASTAT_LINKDETECT 0x0800
342 #define XL_MEDIASTAT_TXINPROG 0x1000
343 #define XL_MEDIASTAT_DCENB 0x4000
344 #define XL_MEDIASTAT_AUIDIS 0x8000
345
346 #define XL_NETDIAG_TEST_LOWVOLT 0x0001
347 #define XL_NETDIAG_ASIC_REVMASK (0x0002|0x0004|0x0008|0x0010|0x0020)
348 #define XL_NETDIAG_UPPER_BYTES_ENABLE 0x0040
349 #define XL_NETDIAG_STATS_ENABLED 0x0080
350 #define XL_NETDIAG_TX_FATALERR 0x0100
351 #define XL_NETDIAG_TRANSMITTING 0x0200
352 #define XL_NETDIAG_RX_ENABLED 0x0400
353 #define XL_NETDIAG_TX_ENABLED 0x0800
354 #define XL_NETDIAG_FIFO_LOOPBACK 0x1000
355 #define XL_NETDIAG_MAC_LOOPBACK 0x2000
356 #define XL_NETDIAG_ENDEC_LOOPBACK 0x4000
357 #define XL_NETDIAG_EXTERNAL_LOOP 0x8000
358
359 /*
360 * Window 5
361 */
362 #define XL_W5_STAT_ENB 0x0C
363 #define XL_W5_INTR_ENB 0x0A
364 #define XL_W5_RECLAIM_THRESH 0x09 /* 3c905B only */
365 #define XL_W5_RX_FILTER 0x08
366 #define XL_W5_RX_EARLYTHRESH 0x06
367 #define XL_W5_TX_AVAILTHRESH 0x02
368 #define XL_W5_TX_STARTTHRESH 0x00
369
370 /*
371 * RX filter bits
372 */
373 #define XL_RXFILTER_INDIVIDUAL 0x01
374 #define XL_RXFILTER_ALLMULTI 0x02
375 #define XL_RXFILTER_BROADCAST 0x04
376 #define XL_RXFILTER_ALLFRAMES 0x08
377 #define XL_RXFILTER_MULTIHASH 0x10 /* 3c905B only */
378
379 /*
380 * Window 6 (stats)
381 */
382 #define XL_W6_TX_BYTES_OK 0x0C
383 #define XL_W6_RX_BYTES_OK 0x0A
384 #define XL_W6_UPPER_FRAMES_OK 0x09
385 #define XL_W6_DEFERRED 0x08
386 #define XL_W6_RX_OK 0x07
387 #define XL_W6_TX_OK 0x06
388 #define XL_W6_RX_OVERRUN 0x05
389 #define XL_W6_COL_LATE 0x04
390 #define XL_W6_COL_SINGLE 0x03
391 #define XL_W6_COL_MULTIPLE 0x02
392 #define XL_W6_SQE_ERRORS 0x01
393 #define XL_W6_CARRIER_LOST 0x00
394
395 /*
396 * Window 7 (bus master control)
397 */
398 #define XL_W7_BM_ADDR 0x00
399 #define XL_W7_BM_LEN 0x06
400 #define XL_W7_BM_STATUS 0x0B
401 #define XL_W7_BM_TIMEr 0x0A
402
403 /*
404 * bus master control registers
405 */
406 #define XL_BM_PKTSTAT 0x20
407 #define XL_BM_DOWNLISTPTR 0x24
408 #define XL_BM_FRAGADDR 0x28
409 #define XL_BM_FRAGLEN 0x2C
410 #define XL_BM_TXFREETHRESH 0x2F
411 #define XL_BM_UPPKTSTAT 0x30
412 #define XL_BM_UPLISTPTR 0x38
413
414 #define XL_LAST_FRAG 0x80000000
415
416 /*
417 * Boomerang/Cyclone TX/RX list structure.
418 * For the TX lists, bits 0 to 12 of the status word indicate
419 * length.
420 * This looks suspiciously like the ThunderLAN, doesn't it.
421 */
422 struct xl_frag {
423 u_int32_t xl_addr; /* 63 addr/len pairs */
424 u_int32_t xl_len;
425 };
426
427 struct xl_list {
428 u_int32_t xl_next; /* final entry has 0 nextptr */
429 u_int32_t xl_status;
430 struct xl_frag xl_frag[63];
431 };
432
433 struct xl_list_onefrag {
434 u_int32_t xl_next; /* final entry has 0 nextptr */
435 u_int32_t xl_status;
436 struct xl_frag xl_frag;
437 };
438
439 #define XL_MAXFRAGS 63
440 #define XL_RX_LIST_CNT 16
441 #define XL_TX_LIST_CNT 16
442 #define XL_MIN_FRAMELEN 60
443
444 struct xl_list_data {
445 struct xl_list_onefrag xl_rx_list[XL_RX_LIST_CNT];
446 struct xl_list xl_tx_list[XL_TX_LIST_CNT];
447 unsigned char xl_pad[XL_MIN_FRAMELEN];
448 };
449
450 struct xl_chain {
451 struct xl_list *xl_ptr;
452 struct mbuf *xl_mbuf;
453 struct xl_chain *xl_next;
454 };
455
456 struct xl_chain_onefrag {
457 struct xl_list_onefrag *xl_ptr;
458 struct mbuf *xl_mbuf;
459 struct xl_chain_onefrag *xl_next;
460 };
461
462 struct xl_chain_data {
463 struct xl_chain_onefrag xl_rx_chain[XL_RX_LIST_CNT];
464 struct xl_chain xl_tx_chain[XL_TX_LIST_CNT];
465
466 struct xl_chain_onefrag *xl_rx_head;
467
468 struct xl_chain *xl_tx_head;
469 struct xl_chain *xl_tx_tail;
470 struct xl_chain *xl_tx_free;
471 };
472
473 #define XL_RXSTAT_LENMASK 0x00001FFF
474 #define XL_RXSTAT_UP_ERROR 0x00004000
475 #define XL_RXSTAT_UP_CMPLT 0x00008000
476 #define XL_RXSTAT_UP_OVERRUN 0x00010000
477 #define XL_RXSTAT_RUNT 0x00020000
478 #define XL_RXSTAT_ALIGN 0x00040000
479 #define XL_RXSTAT_CRC 0x00080000
480 #define XL_RXSTAT_OVERSIZE 0x00100000
481 #define XL_RXSTAT_DRIBBLE 0x00800000
482 #define XL_RXSTAT_UP_OFLOW 0x01000000
483 #define XL_RXSTAT_IPCKERR 0x02000000 /* 3c905B only */
484 #define XL_RXSTAT_TCPCKERR 0x04000000 /* 3c905B only */
485 #define XL_RXSTAT_UDPCKERR 0x08000000 /* 3c905B only */
486 #define XL_RXSTAT_BUFEN 0x10000000 /* 3c905B only */
487 #define XL_RXSTAT_IPCKOK 0x20000000 /* 3c905B only */
488 #define XL_RXSTAT_TCPCOK 0x40000000 /* 3c905B only */
489 #define XL_RXSTAT_UDPCKOK 0x80000000 /* 3c905B only */
490
491 #define XL_TXSTAT_LENMASK 0x00001FFF
492 #define XL_TXSTAT_CRCDIS 0x00002000
493 #define XL_TXSTAT_TX_INTR 0x00008000
494 #define XL_TXSTAT_DL_COMPLETE 0x00010000
495 #define XL_TXSTAT_IPCKSUM 0x02000000 /* 3c905B only */
496 #define XL_TXSTAT_TCPCKSUM 0x04000000 /* 3c905B only */
497 #define XL_TXSTAT_UDPCKSUM 0x08000000 /* 3c905B only */
498 #define XL_TXSTAT_DL_INTR 0x80000000
499
500 #define XL_CAPABILITY_BM 0x20
501
502
503 struct xl_type {
504 u_int16_t xl_vid;
505 u_int16_t xl_did;
506 char *xl_name;
507 };
508
509 struct xl_mii_frame {
510 u_int8_t mii_stdelim;
511 u_int8_t mii_opcode;
512 u_int8_t mii_phyaddr;
513 u_int8_t mii_regaddr;
514 u_int8_t mii_turnaround;
515 u_int16_t mii_data;
516 };
517
518 /*
519 * MII constants
520 */
521 #define XL_MII_STARTDELIM 0x01
522 #define XL_MII_READOP 0x02
523 #define XL_MII_WRITEOP 0x01
524 #define XL_MII_TURNAROUND 0x02
525
526 /*
527 * The 3C905B adapters implement a few features that we want to
528 * take advantage of, namely the multicast hash filter. With older
529 * chips, you only have the option of turning on reception of all
530 * multicast frames, which is kind of lame.
531 */
532 #define XL_TYPE_905B 1
533 #define XL_TYPE_90X 2
534
535 #define XL_FLAG_FORCEDELAY 1
536 #define XL_FLAG_SCHEDDELAY 2
537 #define XL_FLAG_DELAYTIMEO 3
538
539 struct xl_softc {
540 struct arpcom arpcom; /* interface info */
541 struct ifmedia ifmedia; /* media info */
542 u_int32_t iobase; /* pointer to PIO space */
543 #ifndef XL_USEIOSPACE
544 volatile caddr_t csr; /* pointer to register map */
545 #endif
546 struct xl_type *xl_info; /* 3Com adapter info */
547 struct xl_type *xl_pinfo; /* phy info */
548 u_int8_t xl_unit; /* interface number */
549 u_int8_t xl_type;
550 u_int8_t xl_phy_addr; /* PHY address */
551 u_int32_t xl_xcvr;
552 u_int16_t xl_media;
553 u_int16_t xl_caps;
554 u_int8_t xl_tx_pend; /* TX pending */
555 u_int8_t xl_want_auto;
556 u_int8_t xl_autoneg;
557 u_int8_t xl_stats_no_timeout;
558 caddr_t xl_ldata_ptr;
559 struct xl_list_data *xl_ldata;
560 struct xl_chain_data xl_cdata;
561 };
562
563 #define xl_rx_goodframes(x) \
564 ((x.xl_upper_frames_ok & 0x03) << 8) | x.xl_rx_frames_ok
565
566 #define xl_tx_goodframes(x) \
567 ((x.xl_upper_frames_ok & 0x30) << 4) | x.xl_tx_frames_ok
568
569 struct xl_stats {
570 u_int8_t xl_carrier_lost;
571 u_int8_t xl_sqe_errs;
572 u_int8_t xl_tx_multi_collision;
573 u_int8_t xl_tx_single_collision;
574 u_int8_t xl_tx_late_collision;
575 u_int8_t xl_rx_overrun;
576 u_int8_t xl_tx_frames_ok;
577 u_int8_t xl_rx_frames_ok;
578 u_int8_t xl_tx_deferred;
579 u_int8_t xl_upper_frames_ok;
580 u_int16_t xl_rx_bytes_ok;
581 u_int16_t xl_tx_bytes_ok;
582 u_int16_t status;
583 };
584
585 /*
586 * register space access macros
587 */
588 #ifdef XL_USEIOSPACE
589 #define CSR_WRITE_4(sc, reg, val) \
590 outl(sc->iobase + (u_int32_t)(reg), val)
591 #define CSR_WRITE_2(sc, reg, val) \
592 outw(sc->iobase + (u_int32_t)(reg), val)
593 #define CSR_WRITE_1(sc, reg, val) \
594 outb(sc->iobase + (u_int32_t)(reg), val)
595
596 #define CSR_READ_4(sc, reg) \
597 inl(sc->iobase + (u_int32_t)(reg))
598 #define CSR_READ_2(sc, reg) \
599 inw(sc->iobase + (u_int32_t)(reg))
600 #define CSR_READ_1(sc, reg) \
601 inb(sc->iobase + (u_int32_t)(reg))
602 #else
603 #define CSR_WRITE_4(sc, reg, val) \
604 ((*(u_int32_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int32_t)(val))
605 #define CSR_WRITE_2(sc, reg, val) \
606 ((*(u_int16_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int16_t)(val))
607 #define CSR_WRITE_1(sc, reg, val) \
608 ((*(u_int8_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int8_t)(val))
609
610 #define CSR_READ_4(sc, reg) \
611 (*(u_int32_t *)((sc)->csr + (u_int32_t)(reg)))
612 #define CSR_READ_2(sc, reg) \
613 (*(u_int16_t *)((sc)->csr + (u_int32_t)(reg)))
614 #define CSR_READ_1(sc, reg) \
615 (*(u_int8_t *)((sc)->csr + (u_int32_t)(reg)))
616 #endif
617
618 #define XL_SEL_WIN(x) \
619 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x)
620 #define XL_TIMEOUT 1000
621
622 /*
623 * General constants that are fun to know.
624 *
625 * 3Com PCI vendor ID
626 */
627 #define TC_VENDORID 0x10B7
628
629 /*
630 * 3Com chip device IDs.
631 */
632 #define TC_DEVICEID_BOOMERANG_10BT 0x9000
633 #define TC_DEVICEID_BOOMERANG_10BT_COMBO 0x9001
634 #define TC_DEVICEID_BOOMERANG_10_100BT 0x9050
635 #define TC_DEVICEID_BOOMERANG_100BT4 0x9051
636 #define TC_DEVICEID_CYCLONE_10BT 0x9004
637 #define TC_DEVICEID_CYCLONE_10BT_COMBO 0x9005
638 #define TC_DEVICEID_CYCLONE_10_100BT 0x9055
639 #define TC_DEVICEID_CYCLONE_10_100BT4 0x9056
640 #define TC_DEVICEID_CYCLONE_10_100FX 0x905A
641 #define TC_DEVICEID_CYCLONE_10_100BT_SERV 0x9800
642
643 /*
644 * Texas Instruments PHY identifiers
645 *
646 * The ThunderLAN manual has a curious and confusing error in it.
647 * In chapter 7, which describes PHYs, it says that TI PHYs have
648 * the following ID codes, where xx denotes a revision:
649 *
650 * 0x4000501xx internal 10baseT PHY
651 * 0x4000502xx TNETE211 100VG-AnyLan PMI
652 *
653 * The problem here is that these are not valid 32-bit hex numbers:
654 * there's one digit too many. My guess is that they mean the internal
655 * 10baseT PHY is 0x4000501x and the TNETE211 is 0x4000502x since these
656 * are the only numbers that make sense.
657 */
658 #define TI_PHY_VENDORID 0x4000
659 #define TI_PHY_10BT 0x501F
660 #define TI_PHY_100VGPMI 0x502F
661
662 /*
663 * These ID values are for the NS DP83840A 10/100 PHY
664 */
665 #define NS_PHY_VENDORID 0x2000
666 #define NS_PHY_83840A 0x5C0F
667
668 /*
669 * Level 1 10/100 PHY
670 */
671 #define LEVEL1_PHY_VENDORID 0x7810
672 #define LEVEL1_PHY_LXT970 0x000F
673
674 /*
675 * Intel 82555 10/100 PHY
676 */
677 #define INTEL_PHY_VENDORID 0x0A28
678 #define INTEL_PHY_82555 0x015F
679
680 /*
681 * SEEQ 80220 10/100 PHY
682 */
683 #define SEEQ_PHY_VENDORID 0x0016
684 #define SEEQ_PHY_80220 0xF83F
685
686
687 /*
688 * PCI low memory base and low I/O base register, and
689 * other PCI registers. Note: some are only available on
690 * the 3c905B, in particular those that related to power management.
691 */
692
693 #define XL_PCI_VENDOR_ID 0x00
694 #define XL_PCI_DEVICE_ID 0x02
695 #define XL_PCI_COMMAND 0x04
696 #define XL_PCI_STATUS 0x06
697 #define XL_PCI_CLASSCODE 0x09
698 #define XL_PCI_LATENCY_TIMER 0x0D
699 #define XL_PCI_HEADER_TYPE 0x0E
700 #define XL_PCI_LOIO 0x10
701 #define XL_PCI_LOMEM 0x14
702 #define XL_PCI_BIOSROM 0x30
703 #define XL_PCI_INTLINE 0x3C
704 #define XL_PCI_INTPIN 0x3D
705 #define XL_PCI_MINGNT 0x3E
706 #define XL_PCI_MINLAT 0x0F
707 #define XL_PCI_RESETOPT 0x48
708 #define XL_PCI_EEPROM_DATA 0x4C
709
710 /* 3c905B-only registers */
711 #define XL_PCI_CAPID 0xDC /* 8 bits */
712 #define XL_PCI_NEXTPTR 0xDD /* 8 bits */
713 #define XL_PCI_PWRMGMTCAP 0xDE /* 16 bits */
714 #define XL_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */
715
716 #define XL_PSTATE_MASK 0x0003
717 #define XL_PSTATE_D0 0x0000
718 #define XL_PSTATE_D1 0x0002
719 #define XL_PSTATE_D2 0x0002
720 #define XL_PSTATE_D3 0x0003
721 #define XL_PME_EN 0x0010
722 #define XL_PME_STATUS 0x8000
723
724 #define PHY_UNKNOWN 6
725
726 #define XL_PHYADDR_MIN 0x00
727 #define XL_PHYADDR_MAX 0x1F
728
729 #define XL_PHY_GENCTL 0x00
730 #define XL_PHY_GENSTS 0x01
731 #define XL_PHY_VENID 0x02
732 #define XL_PHY_DEVID 0x03
733 #define XL_PHY_ANAR 0x04
734 #define XL_PHY_LPAR 0x05
735 #define XL_PHY_ANEXP 0x06
736
737 #define PHY_ANAR_NEXTPAGE 0x8000
738 #define PHY_ANAR_RSVD0 0x4000
739 #define PHY_ANAR_TLRFLT 0x2000
740 #define PHY_ANAR_RSVD1 0x1000
741 #define PHY_ANAR_RSVD2 0x0800
742 #define PHY_ANAR_RSVD3 0x0400
743 #define PHY_ANAR_100BT4 0x0200
744 #define PHY_ANAR_100BTXFULL 0x0100
745 #define PHY_ANAR_100BTXHALF 0x0080
746 #define PHY_ANAR_10BTFULL 0x0040
747 #define PHY_ANAR_10BTHALF 0x0020
748 #define PHY_ANAR_PROTO4 0x0010
749 #define PHY_ANAR_PROTO3 0x0008
750 #define PHY_ANAR_PROTO2 0x0004
751 #define PHY_ANAR_PROTO1 0x0002
752 #define PHY_ANAR_PROTO0 0x0001
753
754 /*
755 * These are the register definitions for the PHY (physical layer
756 * interface chip).
757 */
758 /*
759 * PHY BMCR Basic Mode Control Register
760 */
761 #define PHY_BMCR 0x00
762 #define PHY_BMCR_RESET 0x8000
763 #define PHY_BMCR_LOOPBK 0x4000
764 #define PHY_BMCR_SPEEDSEL 0x2000
765 #define PHY_BMCR_AUTONEGENBL 0x1000
766 #define PHY_BMCR_RSVD0 0x0800 /* write as zero */
767 #define PHY_BMCR_ISOLATE 0x0400
768 #define PHY_BMCR_AUTONEGRSTR 0x0200
769 #define PHY_BMCR_DUPLEX 0x0100
770 #define PHY_BMCR_COLLTEST 0x0080
771 #define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */
772 #define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */
773 #define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */
774 #define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */
775 #define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */
776 #define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */
777 #define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */
778 /*
779 * RESET: 1 == software reset, 0 == normal operation
780 * Resets status and control registers to default values.
781 * Relatches all hardware config values.
782 *
783 * LOOPBK: 1 == loopback operation enabled, 0 == normal operation
784 *
785 * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
786 * Link speed is selected byt his bit or if auto-negotiation if bit
787 * 12 (AUTONEGENBL) is set (in which case the value of this register
788 * is ignored).
789 *
790 * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
791 * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
792 * determine speed and mode. Should be cleared and then set if PHY configured
793 * for no autoneg on startup.
794 *
795 * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
796 *
797 * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
798 *
799 * DUPLEX: 1 == full duplex mode, 0 == half duplex mode
800 *
801 * COLLTEST: 1 == collision test enabled, 0 == normal operation
802 */
803
804 /*
805 * PHY, BMSR Basic Mode Status Register
806 */
807 #define PHY_BMSR 0x01
808 #define PHY_BMSR_100BT4 0x8000
809 #define PHY_BMSR_100BTXFULL 0x4000
810 #define PHY_BMSR_100BTXHALF 0x2000
811 #define PHY_BMSR_10BTFULL 0x1000
812 #define PHY_BMSR_10BTHALF 0x0800
813 #define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */
814 #define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */
815 #define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */
816 #define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */
817 #define PHY_BMSR_MFPRESUP 0x0040
818 #define PHY_BMSR_AUTONEGCOMP 0x0020
819 #define PHY_BMSR_REMFAULT 0x0010
820 #define PHY_BMSR_CANAUTONEG 0x0008
821 #define PHY_BMSR_LINKSTAT 0x0004
822 #define PHY_BMSR_JABBER 0x0002
823 #define PHY_BMSR_EXTENDED 0x0001
Cache object: 23468e6332b9c0383365098fa3ac4e9e
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