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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_xlreg.h

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    1 /*
    2  * Copyright (c) 1997, 1998
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  *
   32  * $FreeBSD: src/sys/pci/if_xlreg.h,v 1.9.2.10 1999/12/17 15:58:14 wpaul Exp $
   33  */
   34 
   35 #define XL_EE_READ      0x0080  /* read, 5 bit address */
   36 #define XL_EE_WRITE     0x0040  /* write, 5 bit address */
   37 #define XL_EE_ERASE     0x00c0  /* erase, 5 bit address */
   38 #define XL_EE_EWEN      0x0030  /* erase, no data needed */
   39 #define XL_EE_BUSY      0x8000
   40 
   41 #define XL_EE_EADDR0    0x00    /* station address, first word */
   42 #define XL_EE_EADDR1    0x01    /* station address, next word, */
   43 #define XL_EE_EADDR2    0x02    /* station address, last word */
   44 #define XL_EE_PRODID    0x03    /* product ID code */
   45 #define XL_EE_MDATA_DATE        0x04    /* manufacturing data, date */
   46 #define XL_EE_MDATA_DIV         0x05    /* manufacturing data, division */
   47 #define XL_EE_MDATA_PCODE       0x06    /* manufacturing data, product code */
   48 #define XL_EE_MFG_ID    0x07
   49 #define XL_EE_PCI_PARM  0x08
   50 #define XL_EE_ROM_ONFO  0x09
   51 #define XL_EE_OEM_ADR0  0x0A
   52 #define XL_EE_OEM_ADR1  0x0B
   53 #define XL_EE_OEM_ADR2  0x0C
   54 #define XL_EE_SOFTINFO1 0x0D
   55 #define XL_EE_COMPAT    0x0E
   56 #define XL_EE_SOFTINFO2 0x0F
   57 #define XL_EE_CAPS      0x10    /* capabilities word */
   58 #define XL_EE_RSVD0     0x11
   59 #define XL_EE_ICFG_0    0x12
   60 #define XL_EE_ICFG_1    0x13
   61 #define XL_EE_RSVD1     0x14
   62 #define XL_EE_SOFTINFO3 0x15
   63 #define XL_EE_RSVD_2    0x16
   64 
   65 /*
   66  * Bits in the capabilities word
   67  */
   68 #define XL_CAPS_PNP             0x0001
   69 #define XL_CAPS_FULL_DUPLEX     0x0002
   70 #define XL_CAPS_LARGE_PKTS      0x0004
   71 #define XL_CAPS_SLAVE_DMA       0x0008
   72 #define XL_CAPS_SECOND_DMA      0x0010
   73 #define XL_CAPS_FULL_BM         0x0020
   74 #define XL_CAPS_FRAG_BM         0x0040
   75 #define XL_CAPS_CRC_PASSTHRU    0x0080
   76 #define XL_CAPS_TXDONE          0x0100
   77 #define XL_CAPS_NO_TXLENGTH     0x0200
   78 #define XL_CAPS_RX_REPEAT       0x0400
   79 #define XL_CAPS_SNOOPING        0x0800
   80 #define XL_CAPS_100MBPS         0x1000
   81 #define XL_CAPS_PWRMGMT         0x2000
   82 
   83 #define XL_PACKET_SIZE 1536
   84         
   85 /*
   86  * Register layouts.
   87  */
   88 #define XL_COMMAND              0x0E
   89 #define XL_STATUS               0x0E
   90 
   91 #define XL_TX_STATUS            0x1B
   92 #define XL_TX_FREE              0x1C
   93 #define XL_DMACTL               0x20
   94 #define XL_DOWNLIST_PTR         0x24
   95 #define XL_DOWN_POLL            0x2D /* 3c90xB only */
   96 #define XL_TX_FREETHRESH        0x2F
   97 #define XL_UPLIST_PTR           0x38
   98 #define XL_UPLIST_STATUS        0x30
   99 #define XL_UP_POLL              0x3D /* 3c90xB only */
  100 
  101 #define XL_PKTSTAT_UP_STALLED           0x00002000
  102 #define XL_PKTSTAT_UP_ERROR             0x00004000
  103 #define XL_PKTSTAT_UP_CMPLT             0x00008000
  104 
  105 #define XL_DMACTL_DN_CMPLT_REQ          0x00000002
  106 #define XL_DMACTL_DOWN_STALLED          0x00000004
  107 #define XL_DMACTL_UP_CMPLT              0x00000008
  108 #define XL_DMACTL_DOWN_CMPLT            0x00000010
  109 #define XL_DMACTL_UP_RX_EARLY           0x00000020
  110 #define XL_DMACTL_ARM_COUNTDOWN         0x00000040
  111 #define XL_DMACTL_DOWN_INPROG           0x00000080
  112 #define XL_DMACTL_COUNTER_SPEED         0x00000100
  113 #define XL_DMACTL_DOWNDOWN_MODE         0x00000200
  114 #define XL_DMACTL_TARGET_ABORT          0x40000000
  115 #define XL_DMACTL_MASTER_ABORT          0x80000000
  116 
  117 /*
  118  * Command codes. Some command codes require that we wait for
  119  * the CMD_BUSY flag to clear. Those codes are marked as 'mustwait.'
  120  */
  121 #define XL_CMD_RESET            0x0000  /* mustwait */
  122 #define XL_CMD_WINSEL           0x0800
  123 #define XL_CMD_COAX_START       0x1000
  124 #define XL_CMD_RX_DISABLE       0x1800
  125 #define XL_CMD_RX_ENABLE        0x2000
  126 #define XL_CMD_RX_RESET         0x2800  /* mustwait */
  127 #define XL_CMD_UP_STALL         0x3000  /* mustwait */
  128 #define XL_CMD_UP_UNSTALL       0x3001
  129 #define XL_CMD_DOWN_STALL       0x3002  /* mustwait */
  130 #define XL_CMD_DOWN_UNSTALL     0x3003
  131 #define XL_CMD_RX_DISCARD       0x4000
  132 #define XL_CMD_TX_ENABLE        0x4800
  133 #define XL_CMD_TX_DISABLE       0x5000
  134 #define XL_CMD_TX_RESET         0x5800  /* mustwait */
  135 #define XL_CMD_INTR_FAKE        0x6000
  136 #define XL_CMD_INTR_ACK         0x6800
  137 #define XL_CMD_INTR_ENB         0x7000
  138 #define XL_CMD_STAT_ENB         0x7800
  139 #define XL_CMD_RX_SET_FILT      0x8000
  140 #define XL_CMD_RX_SET_THRESH    0x8800
  141 #define XL_CMD_TX_SET_THRESH    0x9000
  142 #define XL_CMD_TX_SET_START     0x9800
  143 #define XL_CMD_DMA_UP           0xA000
  144 #define XL_CMD_DMA_STOP         0xA001
  145 #define XL_CMD_STATS_ENABLE     0xA800
  146 #define XL_CMD_STATS_DISABLE    0xB000
  147 #define XL_CMD_COAX_STOP        0xB800
  148 
  149 #define XL_CMD_SET_TX_RECLAIM   0xC000 /* 3c905B only */
  150 #define XL_CMD_RX_SET_HASH      0xC800 /* 3c905B only */
  151 
  152 #define XL_HASH_SET             0x0400
  153 #define XL_HASHFILT_SIZE        256
  154 
  155 /*
  156  * status codes
  157  * Note that bits 15 to 13 indicate the currently visible register window
  158  * which may be anything from 0 to 7.
  159  */
  160 #define XL_STAT_INTLATCH        0x0001  /* 0 */
  161 #define XL_STAT_ADFAIL          0x0002  /* 1 */
  162 #define XL_STAT_TX_COMPLETE     0x0004  /* 2 */
  163 #define XL_STAT_TX_AVAIL        0x0008  /* 3 first generation */
  164 #define XL_STAT_RX_COMPLETE     0x0010  /* 4 */
  165 #define XL_STAT_RX_EARLY        0x0020  /* 5 */
  166 #define XL_STAT_INTREQ          0x0040  /* 6 */
  167 #define XL_STAT_STATSOFLOW      0x0080  /* 7 */
  168 #define XL_STAT_DMADONE         0x0100  /* 8 first generation */
  169 #define XL_STAT_LINKSTAT        0x0100  /* 8 3c509B */
  170 #define XL_STAT_DOWN_COMPLETE   0x0200  /* 9 */
  171 #define XL_STAT_UP_COMPLETE     0x0400  /* 10 */
  172 #define XL_STAT_DMABUSY         0x0800  /* 11 first generation */
  173 #define XL_STAT_CMDBUSY         0x1000  /* 12 */
  174 
  175 /*
  176  * Interrupts we normally want enabled.
  177  */
  178 #define XL_INTRS                                                        \
  179         (XL_STAT_UP_COMPLETE|XL_STAT_STATSOFLOW|XL_STAT_ADFAIL|         \
  180          XL_STAT_DOWN_COMPLETE|XL_STAT_TX_COMPLETE|XL_STAT_INTLATCH)
  181 
  182 /*
  183  * Window 0 registers
  184  */
  185 #define XL_W0_EE_DATA           0x0C
  186 #define XL_W0_EE_CMD            0x0A
  187 #define XL_W0_RSRC_CFG          0x08
  188 #define XL_W0_ADDR_CFG          0x06
  189 #define XL_W0_CFG_CTRL          0x04
  190 
  191 #define XL_W0_PROD_ID           0x02
  192 #define XL_W0_MFG_ID            0x00
  193 
  194 /*
  195  * Window 1
  196  */
  197 
  198 #define XL_W1_TX_FIFO           0x10
  199 
  200 #define XL_W1_FREE_TX           0x0C
  201 #define XL_W1_TX_STATUS         0x0B
  202 #define XL_W1_TX_TIMER          0x0A
  203 #define XL_W1_RX_STATUS         0x08
  204 #define XL_W1_RX_FIFO           0x00
  205 
  206 /*
  207  * RX status codes
  208  */
  209 #define XL_RXSTATUS_OVERRUN     0x01
  210 #define XL_RXSTATUS_RUNT        0x02
  211 #define XL_RXSTATUS_ALIGN       0x04
  212 #define XL_RXSTATUS_CRC         0x08
  213 #define XL_RXSTATUS_OVERSIZE    0x10
  214 #define XL_RXSTATUS_DRIBBLE     0x20
  215 
  216 /*
  217  * TX status codes
  218  */
  219 #define XL_TXSTATUS_RECLAIM     0x02 /* 3c905B only */
  220 #define XL_TXSTATUS_OVERFLOW    0x04
  221 #define XL_TXSTATUS_MAXCOLS     0x08
  222 #define XL_TXSTATUS_UNDERRUN    0x10
  223 #define XL_TXSTATUS_JABBER      0x20
  224 #define XL_TXSTATUS_INTREQ      0x40
  225 #define XL_TXSTATUS_COMPLETE    0x80
  226 
  227 /*
  228  * Window 2
  229  */
  230 #define XL_W2_RESET_OPTIONS     0x0C    /* 3c905B only */
  231 #define XL_W2_STATION_MASK_HI   0x0A
  232 #define XL_W2_STATION_MASK_MID  0x08
  233 #define XL_W2_STATION_MASK_LO   0x06
  234 #define XL_W2_STATION_ADDR_HI   0x04
  235 #define XL_W2_STATION_ADDR_MID  0x02
  236 #define XL_W2_STATION_ADDR_LO   0x00
  237 
  238 #define XL_RESETOPT_FEATUREMASK 0x0001|0x0002|0x004
  239 #define XL_RESETOPT_D3RESETDIS  0x0008
  240 #define XL_RESETOPT_DISADVFD    0x0010
  241 #define XL_RESETOPT_DISADV100   0x0020
  242 #define XL_RESETOPT_DISAUTONEG  0x0040
  243 #define XL_RESETOPT_DEBUGMODE   0x0080
  244 #define XL_RESETOPT_FASTAUTO    0x0100
  245 #define XL_RESETOPT_FASTEE      0x0200
  246 #define XL_RESETOPT_FORCEDCONF  0x0400
  247 #define XL_RESETOPT_TESTPDTPDR  0x0800
  248 #define XL_RESETOPT_TEST100TX   0x1000
  249 #define XL_RESETOPT_TEST100RX   0x2000
  250 
  251 /*
  252  * Window 3 (fifo management)
  253  */
  254 #define XL_W3_INTERNAL_CFG      0x00
  255 #define XL_W3_RESET_OPT         0x08
  256 #define XL_W3_FREE_TX           0x0C
  257 #define XL_W3_FREE_RX           0x0A
  258 #define XL_W3_MAC_CTRL          0x06
  259 
  260 #define XL_ICFG_CONNECTOR_MASK  0x00F00000
  261 #define XL_ICFG_CONNECTOR_BITS  20
  262 
  263 #define XL_ICFG_RAMSIZE_MASK    0x00000007
  264 #define XL_ICFG_RAMWIDTH        0x00000008
  265 #define XL_ICFG_ROMSIZE_MASK    (0x00000040|0x00000080)
  266 #define XL_ICFG_DISABLE_BASSD   0x00000100
  267 #define XL_ICFG_RAMLOC          0x00000200
  268 #define XL_ICFG_RAMPART         (0x00010000|0x00020000)
  269 #define XL_ICFG_XCVRSEL         (0x00100000|0x00200000|0x00400000)
  270 #define XL_ICFG_AUTOSEL         0x01000000
  271 
  272 #define XL_XCVR_10BT            0x00
  273 #define XL_XCVR_AUI             0x01
  274 #define XL_XCVR_RSVD_0          0x02
  275 #define XL_XCVR_COAX            0x03
  276 #define XL_XCVR_100BTX          0x04
  277 #define XL_XCVR_100BFX          0x05
  278 #define XL_XCVR_MII             0x06
  279 #define XL_XCVR_RSVD_1          0x07
  280 #define XL_XCVR_AUTO            0x08    /* 3c905B only */
  281 
  282 #define XL_MACCTRL_DEFER_EXT_END        0x0001
  283 #define XL_MACCTRL_DEFER_0              0x0002
  284 #define XL_MACCTRL_DEFER_1              0x0004
  285 #define XL_MACCTRL_DEFER_2              0x0008
  286 #define XL_MACCTRL_DEFER_3              0x0010
  287 #define XL_MACCTRL_DUPLEX               0x0020
  288 #define XL_MACCTRL_ALLOW_LARGE_PACK     0x0040
  289 #define XL_MACCTRL_EXTEND_AFTER_COL     0x0080 (3c905B only)
  290 #define XL_MACCTRL_FLOW_CONTROL_ENB     0x0100 (3c905B only)
  291 #define XL_MACCTRL_VLT_END              0x0200 (3c905B only)
  292 
  293 /*
  294  * The 'reset options' register contains power-on reset values
  295  * loaded from the EEPROM. This includes the supported media
  296  * types on the card. It is also known as the media options register.
  297  */
  298 #define XL_W3_MEDIA_OPT         0x08
  299 
  300 #define XL_MEDIAOPT_BT4         0x0001  /* MII */
  301 #define XL_MEDIAOPT_BTX         0x0002  /* on-chip */
  302 #define XL_MEDIAOPT_BFX         0x0004  /* on-chip */
  303 #define XL_MEDIAOPT_BT          0x0008  /* on-chip */
  304 #define XL_MEDIAOPT_BNC         0x0010  /* on-chip */
  305 #define XL_MEDIAOPT_AUI         0x0020  /* on-chip */
  306 #define XL_MEDIAOPT_MII         0x0040  /* MII */
  307 #define XL_MEDIAOPT_VCO         0x0100  /* 1st gen chip only */
  308 
  309 #define XL_MEDIAOPT_10FL        0x0100  /* 3x905B only, on-chip */
  310 #define XL_MEDIAOPT_MASK        0x01FF
  311 
  312 /*
  313  * Window 4 (diagnostics)
  314  */
  315 #define XL_W4_UPPERBYTESOK      0x0D
  316 #define XL_W4_BADSSD            0x0C
  317 #define XL_W4_MEDIA_STATUS      0x0A
  318 #define XL_W4_PHY_MGMT          0x08
  319 #define XL_W4_NET_DIAG          0x06
  320 #define XL_W4_FIFO_DIAG         0x04
  321 #define XL_W4_VCO_DIAG          0x02
  322 
  323 #define XL_W4_CTRLR_STAT        0x08
  324 #define XL_W4_TX_DIAG           0x00
  325 
  326 #define XL_MII_CLK              0x01
  327 #define XL_MII_DATA             0x02
  328 #define XL_MII_DIR              0x04
  329 
  330 #define XL_MEDIA_SQE            0x0008
  331 #define XL_MEDIA_10TP           0x00C0
  332 #define XL_MEDIA_LNK            0x0080
  333 #define XL_MEDIA_LNKBEAT        0x0800
  334 
  335 #define XL_MEDIASTAT_CRCSTRIP   0x0004
  336 #define XL_MEDIASTAT_SQEENB     0x0008
  337 #define XL_MEDIASTAT_COLDET     0x0010
  338 #define XL_MEDIASTAT_CARRIER    0x0020
  339 #define XL_MEDIASTAT_JABGUARD   0x0040
  340 #define XL_MEDIASTAT_LINKBEAT   0x0080
  341 #define XL_MEDIASTAT_JABDETECT  0x0200
  342 #define XL_MEDIASTAT_POLREVERS  0x0400
  343 #define XL_MEDIASTAT_LINKDETECT 0x0800
  344 #define XL_MEDIASTAT_TXINPROG   0x1000
  345 #define XL_MEDIASTAT_DCENB      0x4000
  346 #define XL_MEDIASTAT_AUIDIS     0x8000
  347 
  348 #define XL_NETDIAG_TEST_LOWVOLT         0x0001
  349 #define XL_NETDIAG_ASIC_REVMASK         (0x0002|0x0004|0x0008|0x0010|0x0020)
  350 #define XL_NETDIAG_UPPER_BYTES_ENABLE   0x0040
  351 #define XL_NETDIAG_STATS_ENABLED        0x0080
  352 #define XL_NETDIAG_TX_FATALERR          0x0100
  353 #define XL_NETDIAG_TRANSMITTING         0x0200
  354 #define XL_NETDIAG_RX_ENABLED           0x0400
  355 #define XL_NETDIAG_TX_ENABLED           0x0800
  356 #define XL_NETDIAG_FIFO_LOOPBACK        0x1000
  357 #define XL_NETDIAG_MAC_LOOPBACK         0x2000
  358 #define XL_NETDIAG_ENDEC_LOOPBACK       0x4000
  359 #define XL_NETDIAG_EXTERNAL_LOOP        0x8000
  360 
  361 /*
  362  * Window 5
  363  */
  364 #define XL_W5_STAT_ENB          0x0C
  365 #define XL_W5_INTR_ENB          0x0A
  366 #define XL_W5_RECLAIM_THRESH    0x09    /* 3c905B only */
  367 #define XL_W5_RX_FILTER         0x08
  368 #define XL_W5_RX_EARLYTHRESH    0x06
  369 #define XL_W5_TX_AVAILTHRESH    0x02
  370 #define XL_W5_TX_STARTTHRESH    0x00
  371 
  372 /*
  373  * RX filter bits
  374  */
  375 #define XL_RXFILTER_INDIVIDUAL  0x01
  376 #define XL_RXFILTER_ALLMULTI    0x02
  377 #define XL_RXFILTER_BROADCAST   0x04
  378 #define XL_RXFILTER_ALLFRAMES   0x08
  379 #define XL_RXFILTER_MULTIHASH   0x10 /* 3c905B only */
  380 
  381 /*
  382  * Window 6 (stats)
  383  */
  384 #define XL_W6_TX_BYTES_OK       0x0C
  385 #define XL_W6_RX_BYTES_OK       0x0A
  386 #define XL_W6_UPPER_FRAMES_OK   0x09
  387 #define XL_W6_DEFERRED          0x08
  388 #define XL_W6_RX_OK             0x07
  389 #define XL_W6_TX_OK             0x06
  390 #define XL_W6_RX_OVERRUN        0x05
  391 #define XL_W6_COL_LATE          0x04
  392 #define XL_W6_COL_SINGLE        0x03
  393 #define XL_W6_COL_MULTIPLE      0x02
  394 #define XL_W6_SQE_ERRORS        0x01
  395 #define XL_W6_CARRIER_LOST      0x00
  396 
  397 /*
  398  * Window 7 (bus master control)
  399  */
  400 #define XL_W7_BM_ADDR           0x00
  401 #define XL_W7_BM_LEN            0x06
  402 #define XL_W7_BM_STATUS         0x0B
  403 #define XL_W7_BM_TIMEr          0x0A
  404 
  405 /*
  406  * bus master control registers
  407  */
  408 #define XL_BM_PKTSTAT           0x20
  409 #define XL_BM_DOWNLISTPTR       0x24
  410 #define XL_BM_FRAGADDR          0x28
  411 #define XL_BM_FRAGLEN           0x2C
  412 #define XL_BM_TXFREETHRESH      0x2F
  413 #define XL_BM_UPPKTSTAT         0x30
  414 #define XL_BM_UPLISTPTR         0x38
  415 
  416 #define XL_LAST_FRAG            0x80000000
  417 
  418 /*
  419  * Boomerang/Cyclone TX/RX list structure.
  420  * For the TX lists, bits 0 to 12 of the status word indicate
  421  * length.
  422  * This looks suspiciously like the ThunderLAN, doesn't it.
  423  */
  424 struct xl_frag {
  425         u_int32_t               xl_addr;        /* 63 addr/len pairs */
  426         u_int32_t               xl_len;
  427 };
  428 
  429 struct xl_list {
  430         u_int32_t               xl_next;        /* final entry has 0 nextptr */
  431         u_int32_t               xl_status;
  432         struct xl_frag          xl_frag[63];
  433 };
  434 
  435 struct xl_list_onefrag {
  436         u_int32_t               xl_next;        /* final entry has 0 nextptr */
  437         u_int32_t               xl_status;
  438         struct xl_frag          xl_frag;
  439 };
  440 
  441 #define XL_MAXFRAGS             63
  442 #define XL_RX_LIST_CNT          128
  443 #define XL_TX_LIST_CNT          256
  444 #define XL_MIN_FRAMELEN         60
  445 #define ETHER_ALIGN             2
  446 #define XL_INC(x, y)            (x) = (x + 1) % y
  447 
  448 struct xl_list_data {
  449         struct xl_list_onefrag  xl_rx_list[XL_RX_LIST_CNT];
  450         struct xl_list          xl_tx_list[XL_TX_LIST_CNT];
  451         unsigned char           xl_pad[XL_MIN_FRAMELEN];
  452 };
  453 
  454 struct xl_chain {
  455         struct xl_list          *xl_ptr;
  456         struct mbuf             *xl_mbuf;
  457         struct xl_chain         *xl_next;
  458         struct xl_chain         *xl_prev;
  459         u_int32_t               xl_phys;
  460 };
  461 
  462 struct xl_chain_onefrag {
  463         struct xl_list_onefrag  *xl_ptr;
  464         struct mbuf             *xl_mbuf;
  465         struct xl_chain_onefrag *xl_next;
  466 };
  467 
  468 struct xl_chain_data {
  469         struct xl_chain_onefrag xl_rx_chain[XL_RX_LIST_CNT];
  470         struct xl_chain         xl_tx_chain[XL_TX_LIST_CNT];
  471 
  472         struct xl_chain_onefrag *xl_rx_head;
  473 
  474         /* 3c90x "boomerang" queuing stuff */
  475         struct xl_chain         *xl_tx_head;
  476         struct xl_chain         *xl_tx_tail;
  477         struct xl_chain         *xl_tx_free;
  478 
  479         /* 3c90xB "cyclone/hurricane/tornado" stuff */
  480         int                     xl_tx_prod;
  481         int                     xl_tx_cons;
  482         int                     xl_tx_cnt;
  483 };
  484 
  485 #define XL_RXSTAT_LENMASK       0x00001FFF
  486 #define XL_RXSTAT_UP_ERROR      0x00004000
  487 #define XL_RXSTAT_UP_CMPLT      0x00008000
  488 #define XL_RXSTAT_UP_OVERRUN    0x00010000
  489 #define XL_RXSTAT_RUNT          0x00020000
  490 #define XL_RXSTAT_ALIGN         0x00040000
  491 #define XL_RXSTAT_CRC           0x00080000
  492 #define XL_RXSTAT_OVERSIZE      0x00100000
  493 #define XL_RXSTAT_DRIBBLE       0x00800000
  494 #define XL_RXSTAT_UP_OFLOW      0x01000000
  495 #define XL_RXSTAT_IPCKERR       0x02000000      /* 3c905B only */
  496 #define XL_RXSTAT_TCPCKERR      0x04000000      /* 3c905B only */
  497 #define XL_RXSTAT_UDPCKERR      0x08000000      /* 3c905B only */
  498 #define XL_RXSTAT_BUFEN         0x10000000      /* 3c905B only */
  499 #define XL_RXSTAT_IPCKOK        0x20000000      /* 3c905B only */
  500 #define XL_RXSTAT_TCPCOK        0x40000000      /* 3c905B only */
  501 #define XL_RXSTAT_UDPCKOK       0x80000000      /* 3c905B only */
  502 
  503 #define XL_TXSTAT_LENMASK       0x00001FFF
  504 #define XL_TXSTAT_CRCDIS        0x00002000
  505 #define XL_TXSTAT_TX_INTR       0x00008000
  506 #define XL_TXSTAT_DL_COMPLETE   0x00010000
  507 #define XL_TXSTAT_IPCKSUM       0x02000000      /* 3c905B only */
  508 #define XL_TXSTAT_TCPCKSUM      0x04000000      /* 3c905B only */
  509 #define XL_TXSTAT_UDPCKSUM      0x08000000      /* 3c905B only */
  510 #define XL_TXSTAT_RND_DEFEAT    0x10000000      /* 3c905B only */
  511 #define XL_TXSTAT_EMPTY         0x20000000      /* 3c905B only */
  512 #define XL_TXSTAT_DL_INTR       0x80000000
  513 
  514 #define XL_CAPABILITY_BM        0x20
  515 
  516 struct xl_type {
  517         u_int16_t               xl_vid;
  518         u_int16_t               xl_did;
  519         char                    *xl_name;
  520 };
  521 
  522 struct xl_mii_frame {
  523         u_int8_t                mii_stdelim;
  524         u_int8_t                mii_opcode;
  525         u_int8_t                mii_phyaddr;
  526         u_int8_t                mii_regaddr;
  527         u_int8_t                mii_turnaround;
  528         u_int16_t               mii_data;
  529 };
  530 
  531 /*
  532  * MII constants
  533  */
  534 #define XL_MII_STARTDELIM       0x01
  535 #define XL_MII_READOP           0x02
  536 #define XL_MII_WRITEOP          0x01
  537 #define XL_MII_TURNAROUND       0x02
  538 
  539 /*
  540  * The 3C905B adapters implement a few features that we want to
  541  * take advantage of, namely the multicast hash filter. With older
  542  * chips, you only have the option of turning on reception of all
  543  * multicast frames, which is kind of lame.
  544  *
  545  * We also use this to decide on a transmit strategy. For the 3c90xB
  546  * cards, we can use polled descriptor mode, which reduces CPU overhead.
  547  */
  548 #define XL_TYPE_905B    1
  549 #define XL_TYPE_90X     2
  550 
  551 #define XL_FLAG_FORCEDELAY      1
  552 #define XL_FLAG_SCHEDDELAY      2
  553 #define XL_FLAG_DELAYTIMEO      3       
  554 
  555 struct xl_softc {
  556         struct arpcom           arpcom;         /* interface info */
  557         struct ifmedia          ifmedia;        /* media info */
  558         bus_space_handle_t      xl_bhandle;
  559         bus_space_tag_t         xl_btag;
  560         struct xl_type          *xl_info;       /* 3Com adapter info */
  561         struct xl_type          *xl_pinfo;      /* phy info */
  562         u_int8_t                xl_unit;        /* interface number */
  563         u_int8_t                xl_type;
  564         u_int8_t                xl_phy_addr;    /* PHY address */
  565         u_int32_t               xl_xcvr;
  566         u_int16_t               xl_media;
  567         u_int16_t               xl_caps;
  568         u_int8_t                xl_tx_pend;     /* TX pending */
  569         u_int8_t                xl_want_auto;
  570         u_int8_t                xl_autoneg;
  571         u_int8_t                xl_stats_no_timeout;
  572         u_int16_t               xl_tx_thresh;
  573         int                     xl_if_flags;
  574         struct xl_list_data     *xl_ldata;
  575         struct xl_chain_data    xl_cdata;
  576         struct callout_handle   xl_stat_ch;
  577 };
  578 
  579 #define xl_rx_goodframes(x) \
  580         ((x.xl_upper_frames_ok & 0x03) << 8) | x.xl_rx_frames_ok
  581 
  582 #define xl_tx_goodframes(x) \
  583         ((x.xl_upper_frames_ok & 0x30) << 4) | x.xl_tx_frames_ok
  584 
  585 struct xl_stats {
  586         u_int8_t                xl_carrier_lost;
  587         u_int8_t                xl_sqe_errs;
  588         u_int8_t                xl_tx_multi_collision;
  589         u_int8_t                xl_tx_single_collision;
  590         u_int8_t                xl_tx_late_collision;
  591         u_int8_t                xl_rx_overrun;
  592         u_int8_t                xl_tx_frames_ok;
  593         u_int8_t                xl_rx_frames_ok;
  594         u_int8_t                xl_tx_deferred;
  595         u_int8_t                xl_upper_frames_ok;
  596         u_int16_t               xl_rx_bytes_ok;
  597         u_int16_t               xl_tx_bytes_ok;
  598         u_int16_t               status;
  599 };
  600 
  601 /*
  602  * register space access macros
  603  */
  604 #define CSR_WRITE_4(sc, reg, val)       \
  605         bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val)
  606 #define CSR_WRITE_2(sc, reg, val)       \
  607         bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val)
  608 #define CSR_WRITE_1(sc, reg, val)       \
  609         bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val)
  610 
  611 #define CSR_READ_4(sc, reg)             \
  612         bus_space_read_4(sc->xl_btag, sc->xl_bhandle, reg)
  613 #define CSR_READ_2(sc, reg)             \
  614         bus_space_read_2(sc->xl_btag, sc->xl_bhandle, reg)
  615 #define CSR_READ_1(sc, reg)             \
  616         bus_space_read_1(sc->xl_btag, sc->xl_bhandle, reg)
  617 
  618 #define XL_SEL_WIN(x)   \
  619         CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x)
  620 #define XL_TIMEOUT              1000
  621 
  622 /*
  623  * General constants that are fun to know.
  624  *
  625  * 3Com PCI vendor ID
  626  */
  627 #define TC_VENDORID             0x10B7
  628 
  629 /*
  630  * 3Com chip device IDs.
  631  */
  632 #define TC_DEVICEID_BOOMERANG_10BT              0x9000
  633 #define TC_DEVICEID_BOOMERANG_10BT_COMBO        0x9001
  634 #define TC_DEVICEID_BOOMERANG_10_100BT          0x9050
  635 #define TC_DEVICEID_BOOMERANG_100BT4            0x9051
  636 #define TC_DEVICEID_KRAKATOA_10BT               0x9004
  637 #define TC_DEVICEID_KRAKATOA_10BT_COMBO         0x9005
  638 #define TC_DEVICEID_KRAKATOA_10BT_TPC           0x9006
  639 #define TC_DEVICEID_CYCLONE_10FL                0x900A
  640 #define TC_DEVICEID_HURRICANE_10_100BT          0x9055
  641 #define TC_DEVICEID_CYCLONE_10_100BT4           0x9056
  642 #define TC_DEVICEID_CYCLONE_10_100_COMBO        0x9058
  643 #define TC_DEVICEID_CYCLONE_10_100FX            0x905A
  644 #define TC_DEVICEID_TORNADO_10_100BT            0x9200
  645 #define TC_DEVICEID_HURRICANE_10_100BT_SERV     0x9800
  646 #define TC_DEVICEID_TORNADO_10_100BT_SERV       0x9805
  647 #define TC_DEVICEID_HURRICANE_SOHO100TX         0x7646
  648 #define TC_DEVICEID_TORNADO_HOMECONNECT         0x4500
  649 
  650 /*
  651  * Texas Instruments PHY identifiers
  652  *
  653  * The ThunderLAN manual has a curious and confusing error in it.
  654  * In chapter 7, which describes PHYs, it says that TI PHYs have
  655  * the following ID codes, where xx denotes a revision:
  656  *
  657  * 0x4000501xx                  internal 10baseT PHY
  658  * 0x4000502xx                  TNETE211 100VG-AnyLan PMI
  659  *
  660  * The problem here is that these are not valid 32-bit hex numbers:
  661  * there's one digit too many. My guess is that they mean the internal
  662  * 10baseT PHY is 0x4000501x and the TNETE211 is 0x4000502x since these
  663  * are the only numbers that make sense.
  664  */
  665 #define TI_PHY_VENDORID         0x4000
  666 #define TI_PHY_10BT             0x501F
  667 #define TI_PHY_100VGPMI         0x502F
  668 
  669 /*
  670  * These ID values are for the NS DP83840A 10/100 PHY
  671  */
  672 #define NS_PHY_VENDORID         0x2000
  673 #define NS_PHY_83840A           0x5C0F
  674 
  675 /*
  676  * Level 1 10/100 PHY
  677  */
  678 #define LEVEL1_PHY_VENDORID     0x7810
  679 #define LEVEL1_PHY_LXT970       0x000F
  680 
  681 /*
  682  * Intel 82555 10/100 PHY
  683  */
  684 #define INTEL_PHY_VENDORID      0x0A28
  685 #define INTEL_PHY_82555         0x015F
  686 
  687 /*
  688  * SEEQ 80220 10/100 PHY
  689  */
  690 #define SEEQ_PHY_VENDORID       0x0016
  691 #define SEEQ_PHY_80220          0xF83F
  692 
  693 
  694 /*
  695  * PCI low memory base and low I/O base register, and
  696  * other PCI registers. Note: some are only available on
  697  * the 3c905B, in particular those that related to power management.
  698  */
  699 
  700 #define XL_PCI_VENDOR_ID        0x00
  701 #define XL_PCI_DEVICE_ID        0x02
  702 #define XL_PCI_COMMAND          0x04
  703 #define XL_PCI_STATUS           0x06
  704 #define XL_PCI_CLASSCODE        0x09
  705 #define XL_PCI_LATENCY_TIMER    0x0D
  706 #define XL_PCI_HEADER_TYPE      0x0E
  707 #define XL_PCI_LOIO             0x10
  708 #define XL_PCI_LOMEM            0x14
  709 #define XL_PCI_BIOSROM          0x30
  710 #define XL_PCI_INTLINE          0x3C
  711 #define XL_PCI_INTPIN           0x3D
  712 #define XL_PCI_MINGNT           0x3E
  713 #define XL_PCI_MINLAT           0x0F
  714 #define XL_PCI_RESETOPT         0x48
  715 #define XL_PCI_EEPROM_DATA      0x4C
  716 
  717 /* 3c905B-only registers */
  718 #define XL_PCI_CAPID            0xDC /* 8 bits */
  719 #define XL_PCI_NEXTPTR          0xDD /* 8 bits */
  720 #define XL_PCI_PWRMGMTCAP       0xDE /* 16 bits */
  721 #define XL_PCI_PWRMGMTCTRL      0xE0 /* 16 bits */
  722 
  723 #define XL_PSTATE_MASK          0x0003
  724 #define XL_PSTATE_D0            0x0000
  725 #define XL_PSTATE_D1            0x0002
  726 #define XL_PSTATE_D2            0x0002
  727 #define XL_PSTATE_D3            0x0003
  728 #define XL_PME_EN               0x0010
  729 #define XL_PME_STATUS           0x8000
  730 
  731 #define PHY_UNKNOWN             6
  732 
  733 #define XL_PHYADDR_MIN          0x00
  734 #define XL_PHYADDR_MAX          0x1F
  735 
  736 #define XL_PHY_GENCTL           0x00
  737 #define XL_PHY_GENSTS           0x01
  738 #define XL_PHY_VENID            0x02
  739 #define XL_PHY_DEVID            0x03
  740 #define XL_PHY_ANAR             0x04
  741 #define XL_PHY_LPAR             0x05
  742 #define XL_PHY_ANEXP            0x06
  743 
  744 #define PHY_ANAR_NEXTPAGE       0x8000
  745 #define PHY_ANAR_RSVD0          0x4000
  746 #define PHY_ANAR_TLRFLT         0x2000
  747 #define PHY_ANAR_RSVD1          0x1000
  748 #define PHY_ANAR_RSVD2          0x0800
  749 #define PHY_ANAR_RSVD3          0x0400
  750 #define PHY_ANAR_100BT4         0x0200
  751 #define PHY_ANAR_100BTXFULL     0x0100
  752 #define PHY_ANAR_100BTXHALF     0x0080
  753 #define PHY_ANAR_10BTFULL       0x0040
  754 #define PHY_ANAR_10BTHALF       0x0020
  755 #define PHY_ANAR_PROTO4         0x0010
  756 #define PHY_ANAR_PROTO3         0x0008
  757 #define PHY_ANAR_PROTO2         0x0004
  758 #define PHY_ANAR_PROTO1         0x0002
  759 #define PHY_ANAR_PROTO0         0x0001
  760 
  761 /*
  762  * These are the register definitions for the PHY (physical layer
  763  * interface chip).
  764  */
  765 /*
  766  * PHY BMCR Basic Mode Control Register
  767  */
  768 #define PHY_BMCR                        0x00
  769 #define PHY_BMCR_RESET                  0x8000
  770 #define PHY_BMCR_LOOPBK                 0x4000
  771 #define PHY_BMCR_SPEEDSEL               0x2000
  772 #define PHY_BMCR_AUTONEGENBL            0x1000
  773 #define PHY_BMCR_RSVD0                  0x0800  /* write as zero */
  774 #define PHY_BMCR_ISOLATE                0x0400
  775 #define PHY_BMCR_AUTONEGRSTR            0x0200
  776 #define PHY_BMCR_DUPLEX                 0x0100
  777 #define PHY_BMCR_COLLTEST               0x0080
  778 #define PHY_BMCR_RSVD1                  0x0040  /* write as zero, don't care */
  779 #define PHY_BMCR_RSVD2                  0x0020  /* write as zero, don't care */
  780 #define PHY_BMCR_RSVD3                  0x0010  /* write as zero, don't care */
  781 #define PHY_BMCR_RSVD4                  0x0008  /* write as zero, don't care */
  782 #define PHY_BMCR_RSVD5                  0x0004  /* write as zero, don't care */
  783 #define PHY_BMCR_RSVD6                  0x0002  /* write as zero, don't care */
  784 #define PHY_BMCR_RSVD7                  0x0001  /* write as zero, don't care */
  785 /*
  786  * RESET: 1 == software reset, 0 == normal operation
  787  * Resets status and control registers to default values.
  788  * Relatches all hardware config values.
  789  *
  790  * LOOPBK: 1 == loopback operation enabled, 0 == normal operation
  791  *
  792  * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
  793  * Link speed is selected byt his bit or if auto-negotiation if bit
  794  * 12 (AUTONEGENBL) is set (in which case the value of this register
  795  * is ignored).
  796  *
  797  * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
  798  * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
  799  * determine speed and mode. Should be cleared and then set if PHY configured
  800  * for no autoneg on startup.
  801  *
  802  * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
  803  *
  804  * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
  805  *
  806  * DUPLEX: 1 == full duplex mode, 0 == half duplex mode
  807  *
  808  * COLLTEST: 1 == collision test enabled, 0 == normal operation
  809  */
  810 
  811 /* 
  812  * PHY, BMSR Basic Mode Status Register 
  813  */   
  814 #define PHY_BMSR                        0x01
  815 #define PHY_BMSR_100BT4                 0x8000
  816 #define PHY_BMSR_100BTXFULL             0x4000
  817 #define PHY_BMSR_100BTXHALF             0x2000
  818 #define PHY_BMSR_10BTFULL               0x1000
  819 #define PHY_BMSR_10BTHALF               0x0800
  820 #define PHY_BMSR_RSVD1                  0x0400  /* write as zero, don't care */
  821 #define PHY_BMSR_RSVD2                  0x0200  /* write as zero, don't care */
  822 #define PHY_BMSR_RSVD3                  0x0100  /* write as zero, don't care */
  823 #define PHY_BMSR_RSVD4                  0x0080  /* write as zero, don't care */
  824 #define PHY_BMSR_MFPRESUP               0x0040
  825 #define PHY_BMSR_AUTONEGCOMP            0x0020
  826 #define PHY_BMSR_REMFAULT               0x0010
  827 #define PHY_BMSR_CANAUTONEG             0x0008
  828 #define PHY_BMSR_LINKSTAT               0x0004
  829 #define PHY_BMSR_JABBER                 0x0002
  830 #define PHY_BMSR_EXTENDED               0x0001
  831 
  832 #ifdef __alpha__
  833 #undef vtophys
  834 #define vtophys(va)             (pmap_kextract(((vm_offset_t) (va))) \
  835                                         + 1*1024*1024*1024)
  836 #endif
  837 
  838 #ifndef IFM_10_FL
  839 #define IFM_10_FL       13              /* 10baseFL - Fiber */
  840 #endif

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