The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/pci/intpmreg.h

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    1 /*-
    2  * Copyright (c) 1998, 1999 Takanori Watanabe
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *        notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *        notice, this list of conditions and the following disclaimer in the
   12  *        documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.    IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  * $FreeBSD: stable/9/sys/pci/intpmreg.h 197128 2009-09-12 18:24:31Z avg $
   27  */
   28 
   29 #ifndef __INTPMREG_H__
   30 #define __INTPMREG_H__
   31 
   32 /* Register definitions for non-ICH Intel Chipset SMBUS controllers. */
   33 
   34 /* PCI Config Registers. */
   35 #define PCI_BASE_ADDR_SMB       0x90    /* IO BAR. */
   36 #define PCI_BASE_ADDR_PM        0x40
   37 #define PCI_HST_CFG_SMB         0xd2    /* Host Configuration */
   38 #define PCI_INTR_SMB_MASK       0xe
   39 #define PCI_INTR_SMB_SMI        0
   40 #define PCI_INTR_SMB_IRQ_PCI    2
   41 #define PCI_INTR_SMB_IRQ9       8
   42 #define PCI_INTR_SMB_ENABLE     1
   43 #define PCI_SLV_CMD_SMB         0xd3 /*SLAVE COMMAND*/
   44 #define PCI_SLV_SDW_SMB_1       0xd4 /*SLAVE SHADOW PORT 1*/
   45 #define PCI_SLV_SDW_SMB_2       0xd5 /*SLAVE SHADOW PORT 2*/
   46 #define PCI_REVID_SMB           0xd6
   47 
   48 /* PIXX4 SMBus Registers in the SMB BAR. */
   49 #define PIIX4_SMBHSTSTS         0x00
   50 #define PIIX4_SMBHSTSTAT_BUSY   (1<<0)
   51 #define PIIX4_SMBHSTSTAT_INTR   (1<<1)
   52 #define PIIX4_SMBHSTSTAT_ERR    (1<<2)
   53 #define PIIX4_SMBHSTSTAT_BUSC   (1<<3)
   54 #define PIIX4_SMBHSTSTAT_FAIL   (1<<4)
   55 #define PIIX4_SMBSLVSTS         0x01
   56 #define PIIX4_SMBSLVSTS_ALART   (1<<5)
   57 #define PIIX4_SMBSLVSTS_SDW2    (1<<4)
   58 #define PIIX4_SMBSLVSTS_SDW1    (1<<3)
   59 #define PIIX4_SMBSLVSTS_SLV     (1<<2)
   60 #define PIIX4_SMBSLVSTS_BUSY    (1<<0)
   61 #define PIIX4_SMBHSTCNT         0x02
   62 #define PIIX4_SMBHSTCNT_START   (1<<6)
   63 #define PIIX4_SMBHSTCNT_PROT_QUICK      0
   64 #define PIIX4_SMBHSTCNT_PROT_BYTE       (1<<2)
   65 #define PIIX4_SMBHSTCNT_PROT_BDATA      (2<<2)
   66 #define PIIX4_SMBHSTCNT_PROT_WDATA      (3<<2)
   67 #define PIIX4_SMBHSTCNT_PROT_BLOCK      (5<<2)
   68 #define PIIX4_SMBHSTCNT_KILL    (1<<1)
   69 #define PIIX4_SMBHSTCNT_INTREN  (1)
   70 #define PIIX4_SMBHSTCMD         0x03
   71 #define PIIX4_SMBHSTADD         0x04
   72 #define LSB                     0x1
   73 #define PIIX4_SMBHSTDAT0        0x05
   74 #define PIIX4_SMBHSTDAT1        0x06
   75 #define PIIX4_SMBBLKDAT         0x07
   76 #define PIIX4_SMBSLVCNT         0x08
   77 #define PIIX4_SMBSLVCNT_ALTEN   (1<<3)
   78 #define PIIX4_SMBSLVCNT_SD2EN   (1<<2)
   79 #define PIIX4_SMBSLVCNT_SD1EN   (1<<1)
   80 #define PIIX4_SMBSLVCNT_SLVEN   (1)
   81 #define PIIX4_SMBSLVCMD         0x09
   82 #define PIIX4_SMBSLVEVT         0x0a
   83 #define PIIX4_SMBSLVDAT         0x0c
   84 
   85 /* SMBus alert response address. */
   86 #define SMBALTRESP              0x18
   87 
   88 #define SMBBLOCKTRANS_MAX       32
   89 
   90 #endif /* !__INTPMREG_H__ */

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