FreeBSD/Linux Kernel Cross Reference
sys/pci/ncr.c
1 /**************************************************************************
2 **
3 ** $FreeBSD$
4 **
5 ** Device driver for the NCR 53C8XX PCI-SCSI-Controller Family.
6 **
7 **-------------------------------------------------------------------------
8 **
9 ** Written for 386bsd and FreeBSD by
10 ** Wolfgang Stanglmeier <wolf@cologne.de>
11 ** Stefan Esser <se@mi.Uni-Koeln.de>
12 **
13 **-------------------------------------------------------------------------
14 **
15 ** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved.
16 **
17 ** Redistribution and use in source and binary forms, with or without
18 ** modification, are permitted provided that the following conditions
19 ** are met:
20 ** 1. Redistributions of source code must retain the above copyright
21 ** notice, this list of conditions and the following disclaimer.
22 ** 2. Redistributions in binary form must reproduce the above copyright
23 ** notice, this list of conditions and the following disclaimer in the
24 ** documentation and/or other materials provided with the distribution.
25 ** 3. The name of the author may not be used to endorse or promote products
26 ** derived from this software without specific prior written permission.
27 **
28 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
29 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
30 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
31 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
32 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
33 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
37 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 **
39 ***************************************************************************
40 */
41
42 #define NCR_DATE "pl30 98/1/1"
43
44 #define NCR_VERSION (2)
45 #define MAX_UNITS (16)
46
47 #define NCR_GETCC_WITHMSG
48
49 #if defined (__FreeBSD__) && defined(_KERNEL)
50 #include "opt_ncr.h"
51 #endif
52
53 /*==========================================================
54 **
55 ** Configuration and Debugging
56 **
57 ** May be overwritten in <arch/conf/xxxx>
58 **
59 **==========================================================
60 */
61
62 /*
63 ** SCSI address of this device.
64 ** The boot routines should have set it.
65 ** If not, use this.
66 */
67
68 #ifndef SCSI_NCR_MYADDR
69 #define SCSI_NCR_MYADDR (7)
70 #endif /* SCSI_NCR_MYADDR */
71
72 /*
73 ** The default synchronous period factor
74 ** (0=asynchronous)
75 ** If maximum synchronous frequency is defined, use it instead.
76 */
77
78 #ifndef SCSI_NCR_MAX_SYNC
79
80 #ifndef SCSI_NCR_DFLT_SYNC
81 #define SCSI_NCR_DFLT_SYNC (12)
82 #endif /* SCSI_NCR_DFLT_SYNC */
83
84 #else
85
86 #if SCSI_NCR_MAX_SYNC == 0
87 #define SCSI_NCR_DFLT_SYNC 0
88 #else
89 #define SCSI_NCR_DFLT_SYNC (250000 / SCSI_NCR_MAX_SYNC)
90 #endif
91
92 #endif
93
94 /*
95 ** The minimal asynchronous pre-scaler period (ns)
96 ** Shall be 40.
97 */
98
99 #ifndef SCSI_NCR_MIN_ASYNC
100 #define SCSI_NCR_MIN_ASYNC (40)
101 #endif /* SCSI_NCR_MIN_ASYNC */
102
103 /*
104 ** The maximal bus with (in log2 byte)
105 ** (0=8 bit, 1=16 bit)
106 */
107
108 #ifndef SCSI_NCR_MAX_WIDE
109 #define SCSI_NCR_MAX_WIDE (1)
110 #endif /* SCSI_NCR_MAX_WIDE */
111
112 /*==========================================================
113 **
114 ** Configuration and Debugging
115 **
116 **==========================================================
117 */
118
119 /*
120 ** Number of targets supported by the driver.
121 ** n permits target numbers 0..n-1.
122 ** Default is 7, meaning targets #0..#6.
123 ** #7 .. is myself.
124 */
125
126 #define MAX_TARGET (16)
127
128 /*
129 ** Number of logic units supported by the driver.
130 ** n enables logic unit numbers 0..n-1.
131 ** The common SCSI devices require only
132 ** one lun, so take 1 as the default.
133 */
134
135 #ifndef MAX_LUN
136 #define MAX_LUN (8)
137 #endif /* MAX_LUN */
138
139 /*
140 ** The maximum number of jobs scheduled for starting.
141 ** There should be one slot per target, and one slot
142 ** for each tag of each target in use.
143 */
144
145 #define MAX_START (256)
146
147 /*
148 ** The maximum number of segments a transfer is split into.
149 */
150
151 #define MAX_SCATTER (33)
152
153 /*
154 ** The maximum transfer length (should be >= 64k).
155 ** MUST NOT be greater than (MAX_SCATTER-1) * PAGE_SIZE.
156 */
157
158 #define MAX_SIZE ((MAX_SCATTER-1) * (long) PAGE_SIZE)
159
160 /*
161 ** other
162 */
163
164 #define NCR_SNOOP_TIMEOUT (1000000)
165
166 /*==========================================================
167 **
168 ** Include files
169 **
170 **==========================================================
171 */
172
173 #include <sys/param.h>
174 #include <sys/time.h>
175
176 #ifdef _KERNEL
177 #include <sys/systm.h>
178 #include <sys/malloc.h>
179 #include <sys/buf.h>
180 #include <sys/kernel.h>
181 #include <sys/sysctl.h>
182 #include <sys/bus.h>
183 #include <machine/clock.h>
184 #include <machine/md_var.h>
185 #include <machine/bus.h>
186 #include <machine/resource.h>
187 #include <sys/rman.h>
188 #include <vm/vm.h>
189 #include <vm/pmap.h>
190 #include <vm/vm_extern.h>
191 #endif
192
193 #include <pci/pcivar.h>
194 #include <pci/pcireg.h>
195 #include <pci/ncrreg.h>
196
197 #include <cam/cam.h>
198 #include <cam/cam_ccb.h>
199 #include <cam/cam_sim.h>
200 #include <cam/cam_xpt_sim.h>
201 #include <cam/cam_debug.h>
202
203 #include <cam/scsi/scsi_all.h>
204 #include <cam/scsi/scsi_message.h>
205
206 /*==========================================================
207 **
208 ** Debugging tags
209 **
210 **==========================================================
211 */
212
213 #define DEBUG_ALLOC (0x0001)
214 #define DEBUG_PHASE (0x0002)
215 #define DEBUG_POLL (0x0004)
216 #define DEBUG_QUEUE (0x0008)
217 #define DEBUG_RESULT (0x0010)
218 #define DEBUG_SCATTER (0x0020)
219 #define DEBUG_SCRIPT (0x0040)
220 #define DEBUG_TINY (0x0080)
221 #define DEBUG_TIMING (0x0100)
222 #define DEBUG_NEGO (0x0200)
223 #define DEBUG_TAGS (0x0400)
224 #define DEBUG_FREEZE (0x0800)
225 #define DEBUG_RESTART (0x1000)
226
227 /*
228 ** Enable/Disable debug messages.
229 ** Can be changed at runtime too.
230 */
231 #ifdef SCSI_NCR_DEBUG
232 #define DEBUG_FLAGS ncr_debug
233 #else /* SCSI_NCR_DEBUG */
234 #define SCSI_NCR_DEBUG 0
235 #define DEBUG_FLAGS 0
236 #endif /* SCSI_NCR_DEBUG */
237
238
239
240 /*==========================================================
241 **
242 ** assert ()
243 **
244 **==========================================================
245 **
246 ** modified copy from 386bsd:/usr/include/sys/assert.h
247 **
248 **----------------------------------------------------------
249 */
250
251 #ifdef DIAGNOSTIC
252 #define assert(expression) { \
253 if (!(expression)) { \
254 (void)printf("assertion \"%s\" failed: " \
255 "file \"%s\", line %d\n", \
256 #expression, __FILE__, __LINE__); \
257 Debugger(""); \
258 } \
259 }
260 #else
261 #define assert(expression) { \
262 if (!(expression)) { \
263 (void)printf("assertion \"%s\" failed: " \
264 "file \"%s\", line %d\n", \
265 #expression, __FILE__, __LINE__); \
266 } \
267 }
268 #endif
269
270 /*==========================================================
271 **
272 ** Access to the controller chip.
273 **
274 **==========================================================
275 */
276
277 #ifdef __alpha__
278 /* XXX */
279 #undef vtophys
280 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
281 #endif
282
283 #define INB(r) bus_space_read_1(np->bst, np->bsh, offsetof(struct ncr_reg, r))
284 #define INW(r) bus_space_read_2(np->bst, np->bsh, offsetof(struct ncr_reg, r))
285 #define INL(r) bus_space_read_4(np->bst, np->bsh, offsetof(struct ncr_reg, r))
286
287 #define OUTB(r, val) bus_space_write_1(np->bst, np->bsh, \
288 offsetof(struct ncr_reg, r), val)
289 #define OUTW(r, val) bus_space_write_2(np->bst, np->bsh, \
290 offsetof(struct ncr_reg, r), val)
291 #define OUTL(r, val) bus_space_write_4(np->bst, np->bsh, \
292 offsetof(struct ncr_reg, r), val)
293 #define OUTL_OFF(o, val) bus_space_write_4(np->bst, np->bsh, o, val)
294
295 #define INB_OFF(o) bus_space_read_1(np->bst, np->bsh, o)
296 #define INW_OFF(o) bus_space_read_2(np->bst, np->bsh, o)
297 #define INL_OFF(o) bus_space_read_4(np->bst, np->bsh, o)
298
299 #define READSCRIPT_OFF(base, off) \
300 (base ? *((volatile u_int32_t *)((volatile char *)base + (off))) : \
301 bus_space_read_4(np->bst2, np->bsh2, off))
302
303 #define WRITESCRIPT_OFF(base, off, val) \
304 do { \
305 if (base) \
306 *((volatile u_int32_t *) \
307 ((volatile char *)base + (off))) = (val); \
308 else \
309 bus_space_write_4(np->bst2, np->bsh2, off, val); \
310 } while (0)
311
312 #define READSCRIPT(r) \
313 READSCRIPT_OFF(np->script, offsetof(struct script, r))
314
315 #define WRITESCRIPT(r, val) \
316 WRITESCRIPT_OFF(np->script, offsetof(struct script, r), val)
317
318 /*
319 ** Set bit field ON, OFF
320 */
321
322 #define OUTONB(r, m) OUTB(r, INB(r) | (m))
323 #define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m))
324 #define OUTONW(r, m) OUTW(r, INW(r) | (m))
325 #define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m))
326 #define OUTONL(r, m) OUTL(r, INL(r) | (m))
327 #define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m))
328
329 /*==========================================================
330 **
331 ** Command control block states.
332 **
333 **==========================================================
334 */
335
336 #define HS_IDLE (0)
337 #define HS_BUSY (1)
338 #define HS_NEGOTIATE (2) /* sync/wide data transfer*/
339 #define HS_DISCONNECT (3) /* Disconnected by target */
340
341 #define HS_COMPLETE (4)
342 #define HS_SEL_TIMEOUT (5) /* Selection timeout */
343 #define HS_RESET (6) /* SCSI reset */
344 #define HS_ABORTED (7) /* Transfer aborted */
345 #define HS_TIMEOUT (8) /* Software timeout */
346 #define HS_FAIL (9) /* SCSI or PCI bus errors */
347 #define HS_UNEXPECTED (10) /* Unexpected disconnect */
348 #define HS_STALL (11) /* QUEUE FULL or BUSY */
349
350 #define HS_DONEMASK (0xfc)
351
352 /*==========================================================
353 **
354 ** Software Interrupt Codes
355 **
356 **==========================================================
357 */
358
359 #define SIR_SENSE_RESTART (1)
360 #define SIR_SENSE_FAILED (2)
361 #define SIR_STALL_RESTART (3)
362 #define SIR_STALL_QUEUE (4)
363 #define SIR_NEGO_SYNC (5)
364 #define SIR_NEGO_WIDE (6)
365 #define SIR_NEGO_FAILED (7)
366 #define SIR_NEGO_PROTO (8)
367 #define SIR_REJECT_RECEIVED (9)
368 #define SIR_REJECT_SENT (10)
369 #define SIR_IGN_RESIDUE (11)
370 #define SIR_MISSING_SAVE (12)
371 #define SIR_MAX (12)
372
373 /*==========================================================
374 **
375 ** Extended error codes.
376 ** xerr_status field of struct nccb.
377 **
378 **==========================================================
379 */
380
381 #define XE_OK (0)
382 #define XE_EXTRA_DATA (1) /* unexpected data phase */
383 #define XE_BAD_PHASE (2) /* illegal phase (4/5) */
384
385 /*==========================================================
386 **
387 ** Negotiation status.
388 ** nego_status field of struct nccb.
389 **
390 **==========================================================
391 */
392
393 #define NS_SYNC (1)
394 #define NS_WIDE (2)
395
396 /*==========================================================
397 **
398 ** XXX These are no longer used. Remove once the
399 ** script is updated.
400 ** "Special features" of targets.
401 ** quirks field of struct tcb.
402 ** actualquirks field of struct nccb.
403 **
404 **==========================================================
405 */
406
407 #define QUIRK_AUTOSAVE (0x01)
408 #define QUIRK_NOMSG (0x02)
409 #define QUIRK_NOSYNC (0x10)
410 #define QUIRK_NOWIDE16 (0x20)
411 #define QUIRK_NOTAGS (0x40)
412 #define QUIRK_UPDATE (0x80)
413
414 /*==========================================================
415 **
416 ** Misc.
417 **
418 **==========================================================
419 */
420
421 #define CCB_MAGIC (0xf2691ad2)
422 #define MAX_TAGS (32) /* hard limit */
423
424 /*==========================================================
425 **
426 ** OS dependencies.
427 **
428 **==========================================================
429 */
430
431 #define PRINT_ADDR(ccb) xpt_print_path((ccb)->ccb_h.path)
432
433 /*==========================================================
434 **
435 ** Declaration of structs.
436 **
437 **==========================================================
438 */
439
440 struct tcb;
441 struct lcb;
442 struct nccb;
443 struct ncb;
444 struct script;
445
446 typedef struct ncb * ncb_p;
447 typedef struct tcb * tcb_p;
448 typedef struct lcb * lcb_p;
449 typedef struct nccb * nccb_p;
450
451 struct link {
452 ncrcmd l_cmd;
453 ncrcmd l_paddr;
454 };
455
456 struct usrcmd {
457 u_long target;
458 u_long lun;
459 u_long data;
460 u_long cmd;
461 };
462
463 #define UC_SETSYNC 10
464 #define UC_SETTAGS 11
465 #define UC_SETDEBUG 12
466 #define UC_SETORDER 13
467 #define UC_SETWIDE 14
468 #define UC_SETFLAG 15
469
470 #define UF_TRACE (0x01)
471
472 /*---------------------------------------
473 **
474 ** Timestamps for profiling
475 **
476 **---------------------------------------
477 */
478
479 /* Type of the kernel variable `ticks'. XXX should be declared with the var. */
480 typedef int ticks_t;
481
482 struct tstamp {
483 ticks_t start;
484 ticks_t end;
485 ticks_t select;
486 ticks_t command;
487 ticks_t data;
488 ticks_t status;
489 ticks_t disconnect;
490 };
491
492 /*
493 ** profiling data (per device)
494 */
495
496 struct profile {
497 u_long num_trans;
498 u_long num_bytes;
499 u_long num_disc;
500 u_long num_break;
501 u_long num_int;
502 u_long num_fly;
503 u_long ms_setup;
504 u_long ms_data;
505 u_long ms_disc;
506 u_long ms_post;
507 };
508
509 /*==========================================================
510 **
511 ** Declaration of structs: target control block
512 **
513 **==========================================================
514 */
515
516 #define NCR_TRANS_CUR 0x01 /* Modify current neogtiation status */
517 #define NCR_TRANS_ACTIVE 0x03 /* Assume this is the active target */
518 #define NCR_TRANS_GOAL 0x04 /* Modify negotiation goal */
519 #define NCR_TRANS_USER 0x08 /* Modify user negotiation settings */
520
521 struct ncr_transinfo {
522 u_int8_t width;
523 u_int8_t period;
524 u_int8_t offset;
525 };
526
527 struct ncr_target_tinfo {
528 /* Hardware version of our sync settings */
529 u_int8_t disc_tag;
530 #define NCR_CUR_DISCENB 0x01
531 #define NCR_CUR_TAGENB 0x02
532 #define NCR_USR_DISCENB 0x04
533 #define NCR_USR_TAGENB 0x08
534 u_int8_t sval;
535 struct ncr_transinfo current;
536 struct ncr_transinfo goal;
537 struct ncr_transinfo user;
538 /* Hardware version of our wide settings */
539 u_int8_t wval;
540 };
541
542 struct tcb {
543 /*
544 ** during reselection the ncr jumps to this point
545 ** with SFBR set to the encoded target number
546 ** with bit 7 set.
547 ** if it's not this target, jump to the next.
548 **
549 ** JUMP IF (SFBR != #target#)
550 ** @(next tcb)
551 */
552
553 struct link jump_tcb;
554
555 /*
556 ** load the actual values for the sxfer and the scntl3
557 ** register (sync/wide mode).
558 **
559 ** SCR_COPY (1);
560 ** @(sval field of this tcb)
561 ** @(sxfer register)
562 ** SCR_COPY (1);
563 ** @(wval field of this tcb)
564 ** @(scntl3 register)
565 */
566
567 ncrcmd getscr[6];
568
569 /*
570 ** if next message is "identify"
571 ** then load the message to SFBR,
572 ** else load 0 to SFBR.
573 **
574 ** CALL
575 ** <RESEL_LUN>
576 */
577
578 struct link call_lun;
579
580 /*
581 ** now look for the right lun.
582 **
583 ** JUMP
584 ** @(first nccb of this lun)
585 */
586
587 struct link jump_lcb;
588
589 /*
590 ** pointer to interrupted getcc nccb
591 */
592
593 nccb_p hold_cp;
594
595 /*
596 ** pointer to nccb used for negotiating.
597 ** Avoid to start a nego for all queued commands
598 ** when tagged command queuing is enabled.
599 */
600
601 nccb_p nego_cp;
602
603 /*
604 ** statistical data
605 */
606
607 u_long transfers;
608 u_long bytes;
609
610 /*
611 ** user settable limits for sync transfer
612 ** and tagged commands.
613 */
614
615 struct ncr_target_tinfo tinfo;
616
617 /*
618 ** the lcb's of this tcb
619 */
620
621 lcb_p lp[MAX_LUN];
622 };
623
624 /*==========================================================
625 **
626 ** Declaration of structs: lun control block
627 **
628 **==========================================================
629 */
630
631 struct lcb {
632 /*
633 ** during reselection the ncr jumps to this point
634 ** with SFBR set to the "Identify" message.
635 ** if it's not this lun, jump to the next.
636 **
637 ** JUMP IF (SFBR != #lun#)
638 ** @(next lcb of this target)
639 */
640
641 struct link jump_lcb;
642
643 /*
644 ** if next message is "simple tag",
645 ** then load the tag to SFBR,
646 ** else load 0 to SFBR.
647 **
648 ** CALL
649 ** <RESEL_TAG>
650 */
651
652 struct link call_tag;
653
654 /*
655 ** now look for the right nccb.
656 **
657 ** JUMP
658 ** @(first nccb of this lun)
659 */
660
661 struct link jump_nccb;
662
663 /*
664 ** start of the nccb chain
665 */
666
667 nccb_p next_nccb;
668
669 /*
670 ** Control of tagged queueing
671 */
672
673 u_char reqnccbs;
674 u_char reqlink;
675 u_char actlink;
676 u_char usetags;
677 u_char lasttag;
678 };
679
680 /*==========================================================
681 **
682 ** Declaration of structs: COMMAND control block
683 **
684 **==========================================================
685 **
686 ** This substructure is copied from the nccb to a
687 ** global address after selection (or reselection)
688 ** and copied back before disconnect.
689 **
690 ** These fields are accessible to the script processor.
691 **
692 **----------------------------------------------------------
693 */
694
695 struct head {
696 /*
697 ** Execution of a nccb starts at this point.
698 ** It's a jump to the "SELECT" label
699 ** of the script.
700 **
701 ** After successful selection the script
702 ** processor overwrites it with a jump to
703 ** the IDLE label of the script.
704 */
705
706 struct link launch;
707
708 /*
709 ** Saved data pointer.
710 ** Points to the position in the script
711 ** responsible for the actual transfer
712 ** of data.
713 ** It's written after reception of a
714 ** "SAVE_DATA_POINTER" message.
715 ** The goalpointer points after
716 ** the last transfer command.
717 */
718
719 u_int32_t savep;
720 u_int32_t lastp;
721 u_int32_t goalp;
722
723 /*
724 ** The virtual address of the nccb
725 ** containing this header.
726 */
727
728 nccb_p cp;
729
730 /*
731 ** space for some timestamps to gather
732 ** profiling data about devices and this driver.
733 */
734
735 struct tstamp stamp;
736
737 /*
738 ** status fields.
739 */
740
741 u_char status[8];
742 };
743
744 /*
745 ** The status bytes are used by the host and the script processor.
746 **
747 ** The first four byte are copied to the scratchb register
748 ** (declared as scr0..scr3 in ncr_reg.h) just after the select/reselect,
749 ** and copied back just after disconnecting.
750 ** Inside the script the XX_REG are used.
751 **
752 ** The last four bytes are used inside the script by "COPY" commands.
753 ** Because source and destination must have the same alignment
754 ** in a longword, the fields HAVE to be at the choosen offsets.
755 ** xerr_st (4) 0 (0x34) scratcha
756 ** sync_st (5) 1 (0x05) sxfer
757 ** wide_st (7) 3 (0x03) scntl3
758 */
759
760 /*
761 ** First four bytes (script)
762 */
763 #define QU_REG scr0
764 #define HS_REG scr1
765 #define HS_PRT nc_scr1
766 #define SS_REG scr2
767 #define PS_REG scr3
768
769 /*
770 ** First four bytes (host)
771 */
772 #define actualquirks phys.header.status[0]
773 #define host_status phys.header.status[1]
774 #define s_status phys.header.status[2]
775 #define parity_status phys.header.status[3]
776
777 /*
778 ** Last four bytes (script)
779 */
780 #define xerr_st header.status[4] /* MUST be ==0 mod 4 */
781 #define sync_st header.status[5] /* MUST be ==1 mod 4 */
782 #define nego_st header.status[6]
783 #define wide_st header.status[7] /* MUST be ==3 mod 4 */
784
785 /*
786 ** Last four bytes (host)
787 */
788 #define xerr_status phys.xerr_st
789 #define sync_status phys.sync_st
790 #define nego_status phys.nego_st
791 #define wide_status phys.wide_st
792
793 /*==========================================================
794 **
795 ** Declaration of structs: Data structure block
796 **
797 **==========================================================
798 **
799 ** During execution of a nccb by the script processor,
800 ** the DSA (data structure address) register points
801 ** to this substructure of the nccb.
802 ** This substructure contains the header with
803 ** the script-processor-changable data and
804 ** data blocks for the indirect move commands.
805 **
806 **----------------------------------------------------------
807 */
808
809 struct dsb {
810
811 /*
812 ** Header.
813 ** Has to be the first entry,
814 ** because it's jumped to by the
815 ** script processor
816 */
817
818 struct head header;
819
820 /*
821 ** Table data for Script
822 */
823
824 struct scr_tblsel select;
825 struct scr_tblmove smsg ;
826 struct scr_tblmove smsg2 ;
827 struct scr_tblmove cmd ;
828 struct scr_tblmove scmd ;
829 struct scr_tblmove sense ;
830 struct scr_tblmove data [MAX_SCATTER];
831 };
832
833 /*==========================================================
834 **
835 ** Declaration of structs: Command control block.
836 **
837 **==========================================================
838 **
839 ** During execution of a nccb by the script processor,
840 ** the DSA (data structure address) register points
841 ** to this substructure of the nccb.
842 ** This substructure contains the header with
843 ** the script-processor-changable data and then
844 ** data blocks for the indirect move commands.
845 **
846 **----------------------------------------------------------
847 */
848
849
850 struct nccb {
851 /*
852 ** This filler ensures that the global header is
853 ** cache line size aligned.
854 */
855 ncrcmd filler[4];
856
857 /*
858 ** during reselection the ncr jumps to this point.
859 ** If a "SIMPLE_TAG" message was received,
860 ** then SFBR is set to the tag.
861 ** else SFBR is set to 0
862 ** If looking for another tag, jump to the next nccb.
863 **
864 ** JUMP IF (SFBR != #TAG#)
865 ** @(next nccb of this lun)
866 */
867
868 struct link jump_nccb;
869
870 /*
871 ** After execution of this call, the return address
872 ** (in the TEMP register) points to the following
873 ** data structure block.
874 ** So copy it to the DSA register, and start
875 ** processing of this data structure.
876 **
877 ** CALL
878 ** <RESEL_TMP>
879 */
880
881 struct link call_tmp;
882
883 /*
884 ** This is the data structure which is
885 ** to be executed by the script processor.
886 */
887
888 struct dsb phys;
889
890 /*
891 ** If a data transfer phase is terminated too early
892 ** (after reception of a message (i.e. DISCONNECT)),
893 ** we have to prepare a mini script to transfer
894 ** the rest of the data.
895 */
896
897 ncrcmd patch[8];
898
899 /*
900 ** The general SCSI driver provides a
901 ** pointer to a control block.
902 */
903
904 union ccb *ccb;
905
906 /*
907 ** We prepare a message to be sent after selection,
908 ** and a second one to be sent after getcc selection.
909 ** Contents are IDENTIFY and SIMPLE_TAG.
910 ** While negotiating sync or wide transfer,
911 ** a SDTM or WDTM message is appended.
912 */
913
914 u_char scsi_smsg [8];
915 u_char scsi_smsg2[8];
916
917 /*
918 ** Lock this nccb.
919 ** Flag is used while looking for a free nccb.
920 */
921
922 u_long magic;
923
924 /*
925 ** Physical address of this instance of nccb
926 */
927
928 u_long p_nccb;
929
930 /*
931 ** Completion time out for this job.
932 ** It's set to time of start + allowed number of seconds.
933 */
934
935 time_t tlimit;
936
937 /*
938 ** All nccbs of one hostadapter are chained.
939 */
940
941 nccb_p link_nccb;
942
943 /*
944 ** All nccbs of one target/lun are chained.
945 */
946
947 nccb_p next_nccb;
948
949 /*
950 ** Sense command
951 */
952
953 u_char sensecmd[6];
954
955 /*
956 ** Tag for this transfer.
957 ** It's patched into jump_nccb.
958 ** If it's not zero, a SIMPLE_TAG
959 ** message is included in smsg.
960 */
961
962 u_char tag;
963 };
964
965 #define CCB_PHYS(cp,lbl) (cp->p_nccb + offsetof(struct nccb, lbl))
966
967 /*==========================================================
968 **
969 ** Declaration of structs: NCR device descriptor
970 **
971 **==========================================================
972 */
973
974 struct ncb {
975 /*
976 ** The global header.
977 ** Accessible to both the host and the
978 ** script-processor.
979 ** We assume it is cache line size aligned.
980 */
981 struct head header;
982
983 int unit;
984
985 /*-----------------------------------------------
986 ** Scripts ..
987 **-----------------------------------------------
988 **
989 ** During reselection the ncr jumps to this point.
990 ** The SFBR register is loaded with the encoded target id.
991 **
992 ** Jump to the first target.
993 **
994 ** JUMP
995 ** @(next tcb)
996 */
997 struct link jump_tcb;
998
999 /*-----------------------------------------------
1000 ** Configuration ..
1001 **-----------------------------------------------
1002 **
1003 ** virtual and physical addresses
1004 ** of the 53c810 chip.
1005 */
1006 int reg_rid;
1007 struct resource *reg_res;
1008 bus_space_tag_t bst;
1009 bus_space_handle_t bsh;
1010
1011 int sram_rid;
1012 struct resource *sram_res;
1013 bus_space_tag_t bst2;
1014 bus_space_handle_t bsh2;
1015
1016 struct resource *irq_res;
1017 void *irq_handle;
1018
1019 /*
1020 ** Scripts instance virtual address.
1021 */
1022 struct script *script;
1023 struct scripth *scripth;
1024
1025 /*
1026 ** Scripts instance physical address.
1027 */
1028 u_long p_script;
1029 u_long p_scripth;
1030
1031 /*
1032 ** The SCSI address of the host adapter.
1033 */
1034 u_char myaddr;
1035
1036 /*
1037 ** timing parameters
1038 */
1039 u_char minsync; /* Minimum sync period factor */
1040 u_char maxsync; /* Maximum sync period factor */
1041 u_char maxoffs; /* Max scsi offset */
1042 u_char clock_divn; /* Number of clock divisors */
1043 u_long clock_khz; /* SCSI clock frequency in KHz */
1044 u_long features; /* Chip features map */
1045 u_char multiplier; /* Clock multiplier (1,2,4) */
1046
1047 u_char maxburst; /* log base 2 of dwords burst */
1048
1049 /*
1050 ** BIOS supplied PCI bus options
1051 */
1052 u_char rv_scntl3;
1053 u_char rv_dcntl;
1054 u_char rv_dmode;
1055 u_char rv_ctest3;
1056 u_char rv_ctest4;
1057 u_char rv_ctest5;
1058 u_char rv_gpcntl;
1059 u_char rv_stest2;
1060
1061 /*-----------------------------------------------
1062 ** CAM SIM information for this instance
1063 **-----------------------------------------------
1064 */
1065
1066 struct cam_sim *sim;
1067 struct cam_path *path;
1068
1069 /*-----------------------------------------------
1070 ** Job control
1071 **-----------------------------------------------
1072 **
1073 ** Commands from user
1074 */
1075 struct usrcmd user;
1076
1077 /*
1078 ** Target data
1079 */
1080 struct tcb target[MAX_TARGET];
1081
1082 /*
1083 ** Start queue.
1084 */
1085 u_int32_t squeue [MAX_START];
1086 u_short squeueput;
1087
1088 /*
1089 ** Timeout handler
1090 */
1091 time_t heartbeat;
1092 u_short ticks;
1093 u_short latetime;
1094 time_t lasttime;
1095 struct callout_handle timeout_ch;
1096
1097 /*-----------------------------------------------
1098 ** Debug and profiling
1099 **-----------------------------------------------
1100 **
1101 ** register dump
1102 */
1103 struct ncr_reg regdump;
1104 time_t regtime;
1105
1106 /*
1107 ** Profiling data
1108 */
1109 struct profile profile;
1110 u_long disc_phys;
1111 u_long disc_ref;
1112
1113 /*
1114 ** Head of list of all nccbs for this controller.
1115 */
1116 nccb_p link_nccb;
1117
1118 /*
1119 ** message buffers.
1120 ** Should be longword aligned,
1121 ** because they're written with a
1122 ** COPY script command.
1123 */
1124 u_char msgout[8];
1125 u_char msgin [8];
1126 u_int32_t lastmsg;
1127
1128 /*
1129 ** Buffer for STATUS_IN phase.
1130 */
1131 u_char scratch;
1132
1133 /*
1134 ** controller chip dependent maximal transfer width.
1135 */
1136 u_char maxwide;
1137
1138 #ifdef NCR_IOMAPPED
1139 /*
1140 ** address of the ncr control registers in io space
1141 */
1142 pci_port_t port;
1143 #endif
1144 };
1145
1146 #define NCB_SCRIPT_PHYS(np,lbl) (np->p_script + offsetof (struct script, lbl))
1147 #define NCB_SCRIPTH_PHYS(np,lbl) (np->p_scripth + offsetof (struct scripth,lbl))
1148
1149 /*==========================================================
1150 **
1151 **
1152 ** Script for NCR-Processor.
1153 **
1154 ** Use ncr_script_fill() to create the variable parts.
1155 ** Use ncr_script_copy_and_bind() to make a copy and
1156 ** bind to physical addresses.
1157 **
1158 **
1159 **==========================================================
1160 **
1161 ** We have to know the offsets of all labels before
1162 ** we reach them (for forward jumps).
1163 ** Therefore we declare a struct here.
1164 ** If you make changes inside the script,
1165 ** DONT FORGET TO CHANGE THE LENGTHS HERE!
1166 **
1167 **----------------------------------------------------------
1168 */
1169
1170 /*
1171 ** Script fragments which are loaded into the on-board RAM
1172 ** of 825A, 875 and 895 chips.
1173 */
1174 struct script {
1175 ncrcmd start [ 7];
1176 ncrcmd start0 [ 2];
1177 ncrcmd start1 [ 3];
1178 ncrcmd startpos [ 1];
1179 ncrcmd trysel [ 8];
1180 ncrcmd skip [ 8];
1181 ncrcmd skip2 [ 3];
1182 ncrcmd idle [ 2];
1183 ncrcmd select [ 18];
1184 ncrcmd prepare [ 4];
1185 ncrcmd loadpos [ 14];
1186 ncrcmd prepare2 [ 24];
1187 ncrcmd setmsg [ 5];
1188 ncrcmd clrack [ 2];
1189 ncrcmd dispatch [ 33];
1190 ncrcmd no_data [ 17];
1191 ncrcmd checkatn [ 10];
1192 ncrcmd command [ 15];
1193 ncrcmd status [ 27];
1194 ncrcmd msg_in [ 26];
1195 ncrcmd msg_bad [ 6];
1196 ncrcmd complete [ 13];
1197 ncrcmd cleanup [ 12];
1198 ncrcmd cleanup0 [ 9];
1199 ncrcmd signal [ 12];
1200 ncrcmd save_dp [ 5];
1201 ncrcmd restore_dp [ 5];
1202 ncrcmd disconnect [ 12];
1203 ncrcmd disconnect0 [ 5];
1204 ncrcmd disconnect1 [ 23];
1205 ncrcmd msg_out [ 9];
1206 ncrcmd msg_out_done [ 7];
1207 ncrcmd badgetcc [ 6];
1208 ncrcmd reselect [ 8];
1209 ncrcmd reselect1 [ 8];
1210 ncrcmd reselect2 [ 8];
1211 ncrcmd resel_tmp [ 5];
1212 ncrcmd resel_lun [ 18];
1213 ncrcmd resel_tag [ 24];
1214 ncrcmd data_in [MAX_SCATTER * 4 + 7];
1215 ncrcmd data_out [MAX_SCATTER * 4 + 7];
1216 };
1217
1218 /*
1219 ** Script fragments which stay in main memory for all chips.
1220 */
1221 struct scripth {
1222 ncrcmd tryloop [MAX_START*5+2];
1223 ncrcmd msg_parity [ 6];
1224 ncrcmd msg_reject [ 8];
1225 ncrcmd msg_ign_residue [ 32];
1226 ncrcmd msg_extended [ 18];
1227 ncrcmd msg_ext_2 [ 18];
1228 ncrcmd msg_wdtr [ 27];
1229 ncrcmd msg_ext_3 [ 18];
1230 ncrcmd msg_sdtr [ 27];
1231 ncrcmd msg_out_abort [ 10];
1232 ncrcmd getcc [ 4];
1233 ncrcmd getcc1 [ 5];
1234 #ifdef NCR_GETCC_WITHMSG
1235 ncrcmd getcc2 [ 29];
1236 #else
1237 ncrcmd getcc2 [ 14];
1238 #endif
1239 ncrcmd getcc3 [ 6];
1240 ncrcmd aborttag [ 4];
1241 ncrcmd abort [ 22];
1242 ncrcmd snooptest [ 9];
1243 ncrcmd snoopend [ 2];
1244 };
1245
1246 /*==========================================================
1247 **
1248 **
1249 ** Function headers.
1250 **
1251 **
1252 **==========================================================
1253 */
1254
1255 #ifdef _KERNEL
1256 static nccb_p ncr_alloc_nccb (ncb_p np, u_long target, u_long lun);
1257 static void ncr_complete (ncb_p np, nccb_p cp);
1258 static int ncr_delta (int * from, int * to);
1259 static void ncr_exception (ncb_p np);
1260 static void ncr_free_nccb (ncb_p np, nccb_p cp);
1261 static void ncr_freeze_devq (ncb_p np, struct cam_path *path);
1262 static void ncr_selectclock (ncb_p np, u_char scntl3);
1263 static void ncr_getclock (ncb_p np, u_char multiplier);
1264 static nccb_p ncr_get_nccb (ncb_p np, u_long t,u_long l);
1265 #if 0
1266 static u_int32_t ncr_info (int unit);
1267 #endif
1268 static void ncr_init (ncb_p np, char * msg, u_long code);
1269 static void ncr_intr (void *vnp);
1270 static void ncr_int_ma (ncb_p np, u_char dstat);
1271 static void ncr_int_sir (ncb_p np);
1272 static void ncr_int_sto (ncb_p np);
1273 #if 0
1274 static void ncr_min_phys (struct buf *bp);
1275 #endif
1276 static void ncr_poll (struct cam_sim *sim);
1277 static void ncb_profile (ncb_p np, nccb_p cp);
1278 static void ncr_script_copy_and_bind
1279 (ncb_p np, ncrcmd *src, ncrcmd *dst, int len);
1280 static void ncr_script_fill (struct script * scr, struct scripth *scrh);
1281 static int ncr_scatter (struct dsb* phys, vm_offset_t vaddr,
1282 vm_size_t datalen);
1283 static void ncr_getsync (ncb_p np, u_char sfac, u_char *fakp,
1284 u_char *scntl3p);
1285 static void ncr_setsync (ncb_p np, nccb_p cp,u_char scntl3,u_char sxfer,
1286 u_char period);
1287 static void ncr_setwide (ncb_p np, nccb_p cp, u_char wide, u_char ack);
1288 static int ncr_show_msg (u_char * msg);
1289 static int ncr_snooptest (ncb_p np);
1290 static void ncr_action (struct cam_sim *sim, union ccb *ccb);
1291 static void ncr_timeout (void *arg);
1292 static void ncr_wakeup (ncb_p np, u_long code);
1293
1294 static int ncr_probe (device_t dev);
1295 static int ncr_attach (device_t dev);
1296
1297 #endif /* _KERNEL */
1298
1299 /*==========================================================
1300 **
1301 **
1302 ** Global static data.
1303 **
1304 **
1305 **==========================================================
1306 */
1307
1308
1309 #if !defined(lint)
1310 static const char ident[] =
1311 "\n$FreeBSD$\n";
1312 #endif
1313
1314 static const u_long ncr_version = NCR_VERSION * 11
1315 + (u_long) sizeof (struct ncb) * 7
1316 + (u_long) sizeof (struct nccb) * 5
1317 + (u_long) sizeof (struct lcb) * 3
1318 + (u_long) sizeof (struct tcb) * 2;
1319
1320 #ifdef _KERNEL
1321
1322 static int ncr_debug = SCSI_NCR_DEBUG;
1323 SYSCTL_INT(_debug, OID_AUTO, ncr_debug, CTLFLAG_RW, &ncr_debug, 0, "");
1324
1325 static int ncr_cache; /* to be aligned _NOT_ static */
1326
1327 /*==========================================================
1328 **
1329 **
1330 ** Global static data: auto configure
1331 **
1332 **
1333 **==========================================================
1334 */
1335
1336 #define NCR_810_ID (0x00011000ul)
1337 #define NCR_815_ID (0x00041000ul)
1338 #define NCR_820_ID (0x00021000ul)
1339 #define NCR_825_ID (0x00031000ul)
1340 #define NCR_860_ID (0x00061000ul)
1341 #define NCR_875_ID (0x000f1000ul)
1342 #define NCR_875_ID2 (0x008f1000ul)
1343 #define NCR_885_ID (0x000d1000ul)
1344 #define NCR_895_ID (0x000c1000ul)
1345 #define NCR_896_ID (0x000b1000ul)
1346 #define NCR_895A_ID (0x00121000ul)
1347 #define NCR_1510D_ID (0x000a1000ul)
1348
1349
1350 static char *ncr_name (ncb_p np)
1351 {
1352 static char name[10];
1353 snprintf(name, sizeof(name), "ncr%d", np->unit);
1354 return (name);
1355 }
1356
1357 /*==========================================================
1358 **
1359 **
1360 ** Scripts for NCR-Processor.
1361 **
1362 ** Use ncr_script_bind for binding to physical addresses.
1363 **
1364 **
1365 **==========================================================
1366 **
1367 ** NADDR generates a reference to a field of the controller data.
1368 ** PADDR generates a reference to another part of the script.
1369 ** RADDR generates a reference to a script processor register.
1370 ** FADDR generates a reference to a script processor register
1371 ** with offset.
1372 **
1373 **----------------------------------------------------------
1374 */
1375
1376 #define RELOC_SOFTC 0x40000000
1377 #define RELOC_LABEL 0x50000000
1378 #define RELOC_REGISTER 0x60000000
1379 #define RELOC_KVAR 0x70000000
1380 #define RELOC_LABELH 0x80000000
1381 #define RELOC_MASK 0xf0000000
1382
1383 #define NADDR(label) (RELOC_SOFTC | offsetof(struct ncb, label))
1384 #define PADDR(label) (RELOC_LABEL | offsetof(struct script, label))
1385 #define PADDRH(label) (RELOC_LABELH | offsetof(struct scripth, label))
1386 #define RADDR(label) (RELOC_REGISTER | REG(label))
1387 #define FADDR(label,ofs)(RELOC_REGISTER | ((REG(label))+(ofs)))
1388 #define KVAR(which) (RELOC_KVAR | (which))
1389
1390 #define KVAR_SECOND (0)
1391 #define KVAR_TICKS (1)
1392 #define KVAR_NCR_CACHE (2)
1393
1394 #define SCRIPT_KVAR_FIRST (0)
1395 #define SCRIPT_KVAR_LAST (3)
1396
1397 /*
1398 * Kernel variables referenced in the scripts.
1399 * THESE MUST ALL BE ALIGNED TO A 4-BYTE BOUNDARY.
1400 */
1401 static void *script_kvars[] =
1402 { &time_second, &ticks, &ncr_cache };
1403
1404 static struct script script0 = {
1405 /*--------------------------< START >-----------------------*/ {
1406 /*
1407 ** Claim to be still alive ...
1408 */
1409 SCR_COPY (sizeof (((struct ncb *)0)->heartbeat)),
1410 KVAR (KVAR_SECOND),
1411 NADDR (heartbeat),
1412 /*
1413 ** Make data structure address invalid.
1414 ** clear SIGP.
1415 */
1416 SCR_LOAD_REG (dsa, 0xff),
1417 0,
1418 SCR_FROM_REG (ctest2),
1419 0,
1420 }/*-------------------------< START0 >----------------------*/,{
1421 /*
1422 ** Hook for interrupted GetConditionCode.
1423 ** Will be patched to ... IFTRUE by
1424 ** the interrupt handler.
1425 */
1426 SCR_INT ^ IFFALSE (0),
1427 SIR_SENSE_RESTART,
1428
1429 }/*-------------------------< START1 >----------------------*/,{
1430 /*
1431 ** Hook for stalled start queue.
1432 ** Will be patched to IFTRUE by the interrupt handler.
1433 */
1434 SCR_INT ^ IFFALSE (0),
1435 SIR_STALL_RESTART,
1436 /*
1437 ** Then jump to a certain point in tryloop.
1438 ** Due to the lack of indirect addressing the code
1439 ** is self modifying here.
1440 */
1441 SCR_JUMP,
1442 }/*-------------------------< STARTPOS >--------------------*/,{
1443 PADDRH(tryloop),
1444
1445 }/*-------------------------< TRYSEL >----------------------*/,{
1446 /*
1447 ** Now:
1448 ** DSA: Address of a Data Structure
1449 ** or Address of the IDLE-Label.
1450 **
1451 ** TEMP: Address of a script, which tries to
1452 ** start the NEXT entry.
1453 **
1454 ** Save the TEMP register into the SCRATCHA register.
1455 ** Then copy the DSA to TEMP and RETURN.
1456 ** This is kind of an indirect jump.
1457 ** (The script processor has NO stack, so the
1458 ** CALL is actually a jump and link, and the
1459 ** RETURN is an indirect jump.)
1460 **
1461 ** If the slot was empty, DSA contains the address
1462 ** of the IDLE part of this script. The processor
1463 ** jumps to IDLE and waits for a reselect.
1464 ** It will wake up and try the same slot again
1465 ** after the SIGP bit becomes set by the host.
1466 **
1467 ** If the slot was not empty, DSA contains
1468 ** the address of the phys-part of a nccb.
1469 ** The processor jumps to this address.
1470 ** phys starts with head,
1471 ** head starts with launch,
1472 ** so actually the processor jumps to
1473 ** the lauch part.
1474 ** If the entry is scheduled for execution,
1475 ** then launch contains a jump to SELECT.
1476 ** If it's not scheduled, it contains a jump to IDLE.
1477 */
1478 SCR_COPY (4),
1479 RADDR (temp),
1480 RADDR (scratcha),
1481 SCR_COPY (4),
1482 RADDR (dsa),
1483 RADDR (temp),
1484 SCR_RETURN,
1485 0
1486
1487 }/*-------------------------< SKIP >------------------------*/,{
1488 /*
1489 ** This entry has been canceled.
1490 ** Next time use the next slot.
1491 */
1492 SCR_COPY (4),
1493 RADDR (scratcha),
1494 PADDR (startpos),
1495 /*
1496 ** patch the launch field.
1497 ** should look like an idle process.
1498 */
1499 SCR_COPY_F (4),
1500 RADDR (dsa),
1501 PADDR (skip2),
1502 SCR_COPY (8),
1503 PADDR (idle),
1504 }/*-------------------------< SKIP2 >-----------------------*/,{
1505 0,
1506 SCR_JUMP,
1507 PADDR(start),
1508 }/*-------------------------< IDLE >------------------------*/,{
1509 /*
1510 ** Nothing to do?
1511 ** Wait for reselect.
1512 */
1513 SCR_JUMP,
1514 PADDR(reselect),
1515
1516 }/*-------------------------< SELECT >----------------------*/,{
1517 /*
1518 ** DSA contains the address of a scheduled
1519 ** data structure.
1520 **
1521 ** SCRATCHA contains the address of the script,
1522 ** which starts the next entry.
1523 **
1524 ** Set Initiator mode.
1525 **
1526 ** (Target mode is left as an exercise for the reader)
1527 */
1528
1529 SCR_CLR (SCR_TRG),
1530 0,
1531 SCR_LOAD_REG (HS_REG, 0xff),
1532 0,
1533
1534 /*
1535 ** And try to select this target.
1536 */
1537 SCR_SEL_TBL_ATN ^ offsetof (struct dsb, select),
1538 PADDR (reselect),
1539
1540 /*
1541 ** Now there are 4 possibilities:
1542 **
1543 ** (1) The ncr looses arbitration.
1544 ** This is ok, because it will try again,
1545 ** when the bus becomes idle.
1546 ** (But beware of the timeout function!)
1547 **
1548 ** (2) The ncr is reselected.
1549 ** Then the script processor takes the jump
1550 ** to the RESELECT label.
1551 **
1552 ** (3) The ncr completes the selection.
1553 ** Then it will execute the next statement.
1554 **
1555 ** (4) There is a selection timeout.
1556 ** Then the ncr should interrupt the host and stop.
1557 ** Unfortunately, it seems to continue execution
1558 ** of the script. But it will fail with an
1559 ** IID-interrupt on the next WHEN.
1560 */
1561
1562 SCR_JUMPR ^ IFTRUE (WHEN (SCR_MSG_IN)),
1563 0,
1564
1565 /*
1566 ** Send the IDENTIFY and SIMPLE_TAG messages
1567 ** (and the MSG_EXT_SDTR message)
1568 */
1569 SCR_MOVE_TBL ^ SCR_MSG_OUT,
1570 offsetof (struct dsb, smsg),
1571 #ifdef undef /* XXX better fail than try to deal with this ... */
1572 SCR_JUMPR ^ IFTRUE (WHEN (SCR_MSG_OUT)),
1573 -16,
1574 #endif
1575 SCR_CLR (SCR_ATN),
1576 0,
1577 SCR_COPY (1),
1578 RADDR (sfbr),
1579 NADDR (lastmsg),
1580 /*
1581 ** Selection complete.
1582 ** Next time use the next slot.
1583 */
1584 SCR_COPY (4),
1585 RADDR (scratcha),
1586 PADDR (startpos),
1587 }/*-------------------------< PREPARE >----------------------*/,{
1588 /*
1589 ** The ncr doesn't have an indirect load
1590 ** or store command. So we have to
1591 ** copy part of the control block to a
1592 ** fixed place, where we can access it.
1593 **
1594 ** We patch the address part of a
1595 ** COPY command with the DSA-register.
1596 */
1597 SCR_COPY_F (4),
1598 RADDR (dsa),
1599 PADDR (loadpos),
1600 /*
1601 ** then we do the actual copy.
1602 */
1603 SCR_COPY (sizeof (struct head)),
1604 /*
1605 ** continued after the next label ...
1606 */
1607
1608 }/*-------------------------< LOADPOS >---------------------*/,{
1609 0,
1610 NADDR (header),
1611 /*
1612 ** Mark this nccb as not scheduled.
1613 */
1614 SCR_COPY (8),
1615 PADDR (idle),
1616 NADDR (header.launch),
1617 /*
1618 ** Set a time stamp for this selection
1619 */
1620 SCR_COPY (sizeof (ticks)),
1621 KVAR (KVAR_TICKS),
1622 NADDR (header.stamp.select),
1623 /*
1624 ** load the savep (saved pointer) into
1625 ** the TEMP register (actual pointer)
1626 */
1627 SCR_COPY (4),
1628 NADDR (header.savep),
1629 RADDR (temp),
1630 /*
1631 ** Initialize the status registers
1632 */
1633 SCR_COPY (4),
1634 NADDR (header.status),
1635 RADDR (scr0),
1636
1637 }/*-------------------------< PREPARE2 >---------------------*/,{
1638 /*
1639 ** Load the synchronous mode register
1640 */
1641 SCR_COPY (1),
1642 NADDR (sync_st),
1643 RADDR (sxfer),
1644 /*
1645 ** Load the wide mode and timing register
1646 */
1647 SCR_COPY (1),
1648 NADDR (wide_st),
1649 RADDR (scntl3),
1650 /*
1651 ** Initialize the msgout buffer with a NOOP message.
1652 */
1653 SCR_LOAD_REG (scratcha, MSG_NOOP),
1654 0,
1655 SCR_COPY (1),
1656 RADDR (scratcha),
1657 NADDR (msgout),
1658 SCR_COPY (1),
1659 RADDR (scratcha),
1660 NADDR (msgin),
1661 /*
1662 ** Message in phase ?
1663 */
1664 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
1665 PADDR (dispatch),
1666 /*
1667 ** Extended or reject message ?
1668 */
1669 SCR_FROM_REG (sbdl),
1670 0,
1671 SCR_JUMP ^ IFTRUE (DATA (MSG_EXTENDED)),
1672 PADDR (msg_in),
1673 SCR_JUMP ^ IFTRUE (DATA (MSG_MESSAGE_REJECT)),
1674 PADDRH (msg_reject),
1675 /*
1676 ** normal processing
1677 */
1678 SCR_JUMP,
1679 PADDR (dispatch),
1680 }/*-------------------------< SETMSG >----------------------*/,{
1681 SCR_COPY (1),
1682 RADDR (scratcha),
1683 NADDR (msgout),
1684 SCR_SET (SCR_ATN),
1685 0,
1686 }/*-------------------------< CLRACK >----------------------*/,{
1687 /*
1688 ** Terminate possible pending message phase.
1689 */
1690 SCR_CLR (SCR_ACK),
1691 0,
1692
1693 }/*-----------------------< DISPATCH >----------------------*/,{
1694 SCR_FROM_REG (HS_REG),
1695 0,
1696 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)),
1697 SIR_NEGO_FAILED,
1698 /*
1699 ** remove bogus output signals
1700 */
1701 SCR_REG_REG (socl, SCR_AND, CACK|CATN),
1702 0,
1703 SCR_RETURN ^ IFTRUE (WHEN (SCR_DATA_OUT)),
1704 0,
1705 SCR_RETURN ^ IFTRUE (IF (SCR_DATA_IN)),
1706 0,
1707 SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)),
1708 PADDR (msg_out),
1709 SCR_JUMP ^ IFTRUE (IF (SCR_MSG_IN)),
1710 PADDR (msg_in),
1711 SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)),
1712 PADDR (command),
1713 SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)),
1714 PADDR (status),
1715 /*
1716 ** Discard one illegal phase byte, if required.
1717 */
1718 SCR_LOAD_REG (scratcha, XE_BAD_PHASE),
1719 0,
1720 SCR_COPY (1),
1721 RADDR (scratcha),
1722 NADDR (xerr_st),
1723 SCR_JUMPR ^ IFFALSE (IF (SCR_ILG_OUT)),
1724 8,
1725 SCR_MOVE_ABS (1) ^ SCR_ILG_OUT,
1726 NADDR (scratch),
1727 SCR_JUMPR ^ IFFALSE (IF (SCR_ILG_IN)),
1728 8,
1729 SCR_MOVE_ABS (1) ^ SCR_ILG_IN,
1730 NADDR (scratch),
1731 SCR_JUMP,
1732 PADDR (dispatch),
1733
1734 }/*-------------------------< NO_DATA >--------------------*/,{
1735 /*
1736 ** The target wants to tranfer too much data
1737 ** or in the wrong direction.
1738 ** Remember that in extended error.
1739 */
1740 SCR_LOAD_REG (scratcha, XE_EXTRA_DATA),
1741 0,
1742 SCR_COPY (1),
1743 RADDR (scratcha),
1744 NADDR (xerr_st),
1745 /*
1746 ** Discard one data byte, if required.
1747 */
1748 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)),
1749 8,
1750 SCR_MOVE_ABS (1) ^ SCR_DATA_OUT,
1751 NADDR (scratch),
1752 SCR_JUMPR ^ IFFALSE (IF (SCR_DATA_IN)),
1753 8,
1754 SCR_MOVE_ABS (1) ^ SCR_DATA_IN,
1755 NADDR (scratch),
1756 /*
1757 ** .. and repeat as required.
1758 */
1759 SCR_CALL,
1760 PADDR (dispatch),
1761 SCR_JUMP,
1762 PADDR (no_data),
1763 }/*-------------------------< CHECKATN >--------------------*/,{
1764 /*
1765 ** If AAP (bit 1 of scntl0 register) is set
1766 ** and a parity error is detected,
1767 ** the script processor asserts ATN.
1768 **
1769 ** The target should switch to a MSG_OUT phase
1770 ** to get the message.
1771 */
1772 SCR_FROM_REG (socl),
1773 0,
1774 SCR_JUMP ^ IFFALSE (MASK (CATN, CATN)),
1775 PADDR (dispatch),
1776 /*
1777 ** count it
1778 */
1779 SCR_REG_REG (PS_REG, SCR_ADD, 1),
1780 0,
1781 /*
1782 ** Prepare a MSG_INITIATOR_DET_ERR message
1783 ** (initiator detected error).
1784 ** The target should retry the transfer.
1785 */
1786 SCR_LOAD_REG (scratcha, MSG_INITIATOR_DET_ERR),
1787 0,
1788 SCR_JUMP,
1789 PADDR (setmsg),
1790
1791 }/*-------------------------< COMMAND >--------------------*/,{
1792 /*
1793 ** If this is not a GETCC transfer ...
1794 */
1795 SCR_FROM_REG (SS_REG),
1796 0,
1797 /*<<<*/ SCR_JUMPR ^ IFTRUE (DATA (SCSI_STATUS_CHECK_COND)),
1798 28,
1799 /*
1800 ** ... set a timestamp ...
1801 */
1802 SCR_COPY (sizeof (ticks)),
1803 KVAR (KVAR_TICKS),
1804 NADDR (header.stamp.command),
1805 /*
1806 ** ... and send the command
1807 */
1808 SCR_MOVE_TBL ^ SCR_COMMAND,
1809 offsetof (struct dsb, cmd),
1810 SCR_JUMP,
1811 PADDR (dispatch),
1812 /*
1813 ** Send the GETCC command
1814 */
1815 /*>>>*/ SCR_MOVE_TBL ^ SCR_COMMAND,
1816 offsetof (struct dsb, scmd),
1817 SCR_JUMP,
1818 PADDR (dispatch),
1819
1820 }/*-------------------------< STATUS >--------------------*/,{
1821 /*
1822 ** set the timestamp.
1823 */
1824 SCR_COPY (sizeof (ticks)),
1825 KVAR (KVAR_TICKS),
1826 NADDR (header.stamp.status),
1827 /*
1828 ** If this is a GETCC transfer,
1829 */
1830 SCR_FROM_REG (SS_REG),
1831 0,
1832 /*<<<*/ SCR_JUMPR ^ IFFALSE (DATA (SCSI_STATUS_CHECK_COND)),
1833 40,
1834 /*
1835 ** get the status
1836 */
1837 SCR_MOVE_ABS (1) ^ SCR_STATUS,
1838 NADDR (scratch),
1839 /*
1840 ** Save status to scsi_status.
1841 ** Mark as complete.
1842 ** And wait for disconnect.
1843 */
1844 SCR_TO_REG (SS_REG),
1845 0,
1846 SCR_REG_REG (SS_REG, SCR_OR, SCSI_STATUS_SENSE),
1847 0,
1848 SCR_LOAD_REG (HS_REG, HS_COMPLETE),
1849 0,
1850 SCR_JUMP,
1851 PADDR (checkatn),
1852 /*
1853 ** If it was no GETCC transfer,
1854 ** save the status to scsi_status.
1855 */
1856 /*>>>*/ SCR_MOVE_ABS (1) ^ SCR_STATUS,
1857 NADDR (scratch),
1858 SCR_TO_REG (SS_REG),
1859 0,
1860 /*
1861 ** if it was no check condition ...
1862 */
1863 SCR_JUMP ^ IFTRUE (DATA (SCSI_STATUS_CHECK_COND)),
1864 PADDR (checkatn),
1865 /*
1866 ** ... mark as complete.
1867 */
1868 SCR_LOAD_REG (HS_REG, HS_COMPLETE),
1869 0,
1870 SCR_JUMP,
1871 PADDR (checkatn),
1872
1873 }/*-------------------------< MSG_IN >--------------------*/,{
1874 /*
1875 ** Get the first byte of the message
1876 ** and save it to SCRATCHA.
1877 **
1878 ** The script processor doesn't negate the
1879 ** ACK signal after this transfer.
1880 */
1881 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1882 NADDR (msgin[0]),
1883 /*
1884 ** Check for message parity error.
1885 */
1886 SCR_TO_REG (scratcha),
1887 0,
1888 SCR_FROM_REG (socl),
1889 0,
1890 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)),
1891 PADDRH (msg_parity),
1892 SCR_FROM_REG (scratcha),
1893 0,
1894 /*
1895 ** Parity was ok, handle this message.
1896 */
1897 SCR_JUMP ^ IFTRUE (DATA (MSG_CMDCOMPLETE)),
1898 PADDR (complete),
1899 SCR_JUMP ^ IFTRUE (DATA (MSG_SAVEDATAPOINTER)),
1900 PADDR (save_dp),
1901 SCR_JUMP ^ IFTRUE (DATA (MSG_RESTOREPOINTERS)),
1902 PADDR (restore_dp),
1903 SCR_JUMP ^ IFTRUE (DATA (MSG_DISCONNECT)),
1904 PADDR (disconnect),
1905 SCR_JUMP ^ IFTRUE (DATA (MSG_EXTENDED)),
1906 PADDRH (msg_extended),
1907 SCR_JUMP ^ IFTRUE (DATA (MSG_NOOP)),
1908 PADDR (clrack),
1909 SCR_JUMP ^ IFTRUE (DATA (MSG_MESSAGE_REJECT)),
1910 PADDRH (msg_reject),
1911 SCR_JUMP ^ IFTRUE (DATA (MSG_IGN_WIDE_RESIDUE)),
1912 PADDRH (msg_ign_residue),
1913 /*
1914 ** Rest of the messages left as
1915 ** an exercise ...
1916 **
1917 ** Unimplemented messages:
1918 ** fall through to MSG_BAD.
1919 */
1920 }/*-------------------------< MSG_BAD >------------------*/,{
1921 /*
1922 ** unimplemented message - reject it.
1923 */
1924 SCR_INT,
1925 SIR_REJECT_SENT,
1926 SCR_LOAD_REG (scratcha, MSG_MESSAGE_REJECT),
1927 0,
1928 SCR_JUMP,
1929 PADDR (setmsg),
1930
1931 }/*-------------------------< COMPLETE >-----------------*/,{
1932 /*
1933 ** Complete message.
1934 **
1935 ** If it's not the get condition code,
1936 ** copy TEMP register to LASTP in header.
1937 */
1938 SCR_FROM_REG (SS_REG),
1939 0,
1940 /*<<<*/ SCR_JUMPR ^ IFTRUE (MASK (SCSI_STATUS_SENSE, SCSI_STATUS_SENSE)),
1941 12,
1942 SCR_COPY (4),
1943 RADDR (temp),
1944 NADDR (header.lastp),
1945 /*>>>*/ /*
1946 ** When we terminate the cycle by clearing ACK,
1947 ** the target may disconnect immediately.
1948 **
1949 ** We don't want to be told of an
1950 ** "unexpected disconnect",
1951 ** so we disable this feature.
1952 */
1953 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
1954 0,
1955 /*
1956 ** Terminate cycle ...
1957 */
1958 SCR_CLR (SCR_ACK|SCR_ATN),
1959 0,
1960 /*
1961 ** ... and wait for the disconnect.
1962 */
1963 SCR_WAIT_DISC,
1964 0,
1965 }/*-------------------------< CLEANUP >-------------------*/,{
1966 /*
1967 ** dsa: Pointer to nccb
1968 ** or xxxxxxFF (no nccb)
1969 **
1970 ** HS_REG: Host-Status (<>0!)
1971 */
1972 SCR_FROM_REG (dsa),
1973 0,
1974 SCR_JUMP ^ IFTRUE (DATA (0xff)),
1975 PADDR (signal),
1976 /*
1977 ** dsa is valid.
1978 ** save the status registers
1979 */
1980 SCR_COPY (4),
1981 RADDR (scr0),
1982 NADDR (header.status),
1983 /*
1984 ** and copy back the header to the nccb.
1985 */
1986 SCR_COPY_F (4),
1987 RADDR (dsa),
1988 PADDR (cleanup0),
1989 SCR_COPY (sizeof (struct head)),
1990 NADDR (header),
1991 }/*-------------------------< CLEANUP0 >--------------------*/,{
1992 0,
1993
1994 /*
1995 ** If command resulted in "check condition"
1996 ** status and is not yet completed,
1997 ** try to get the condition code.
1998 */
1999 SCR_FROM_REG (HS_REG),
2000 0,
2001 /*<<<*/ SCR_JUMPR ^ IFFALSE (MASK (0, HS_DONEMASK)),
2002 16,
2003 SCR_FROM_REG (SS_REG),
2004 0,
2005 SCR_JUMP ^ IFTRUE (DATA (SCSI_STATUS_CHECK_COND)),
2006 PADDRH(getcc2),
2007 }/*-------------------------< SIGNAL >----------------------*/,{
2008 /*
2009 ** if status = queue full,
2010 ** reinsert in startqueue and stall queue.
2011 */
2012 /*>>>*/ SCR_FROM_REG (SS_REG),
2013 0,
2014 SCR_INT ^ IFTRUE (DATA (SCSI_STATUS_QUEUE_FULL)),
2015 SIR_STALL_QUEUE,
2016 /*
2017 ** And make the DSA register invalid.
2018 */
2019 SCR_LOAD_REG (dsa, 0xff), /* invalid */
2020 0,
2021 /*
2022 ** if job completed ...
2023 */
2024 SCR_FROM_REG (HS_REG),
2025 0,
2026 /*
2027 ** ... signal completion to the host
2028 */
2029 SCR_INT_FLY ^ IFFALSE (MASK (0, HS_DONEMASK)),
2030 0,
2031 /*
2032 ** Auf zu neuen Schandtaten!
2033 */
2034 SCR_JUMP,
2035 PADDR(start),
2036
2037 }/*-------------------------< SAVE_DP >------------------*/,{
2038 /*
2039 ** SAVE_DP message:
2040 ** Copy TEMP register to SAVEP in header.
2041 */
2042 SCR_COPY (4),
2043 RADDR (temp),
2044 NADDR (header.savep),
2045 SCR_JUMP,
2046 PADDR (clrack),
2047 }/*-------------------------< RESTORE_DP >---------------*/,{
2048 /*
2049 ** RESTORE_DP message:
2050 ** Copy SAVEP in header to TEMP register.
2051 */
2052 SCR_COPY (4),
2053 NADDR (header.savep),
2054 RADDR (temp),
2055 SCR_JUMP,
2056 PADDR (clrack),
2057
2058 }/*-------------------------< DISCONNECT >---------------*/,{
2059 /*
2060 ** If QUIRK_AUTOSAVE is set,
2061 ** do an "save pointer" operation.
2062 */
2063 SCR_FROM_REG (QU_REG),
2064 0,
2065 /*<<<*/ SCR_JUMPR ^ IFFALSE (MASK (QUIRK_AUTOSAVE, QUIRK_AUTOSAVE)),
2066 12,
2067 /*
2068 ** like SAVE_DP message:
2069 ** Copy TEMP register to SAVEP in header.
2070 */
2071 SCR_COPY (4),
2072 RADDR (temp),
2073 NADDR (header.savep),
2074 /*>>>*/ /*
2075 ** Check if temp==savep or temp==goalp:
2076 ** if not, log a missing save pointer message.
2077 ** In fact, it's a comparison mod 256.
2078 **
2079 ** Hmmm, I hadn't thought that I would be urged to
2080 ** write this kind of ugly self modifying code.
2081 **
2082 ** It's unbelievable, but the ncr53c8xx isn't able
2083 ** to subtract one register from another.
2084 */
2085 SCR_FROM_REG (temp),
2086 0,
2087 /*
2088 ** You are not expected to understand this ..
2089 **
2090 ** CAUTION: only little endian architectures supported! XXX
2091 */
2092 SCR_COPY_F (1),
2093 NADDR (header.savep),
2094 PADDR (disconnect0),
2095 }/*-------------------------< DISCONNECT0 >--------------*/,{
2096 /*<<<*/ SCR_JUMPR ^ IFTRUE (DATA (1)),
2097 20,
2098 /*
2099 ** neither this
2100 */
2101 SCR_COPY_F (1),
2102 NADDR (header.goalp),
2103 PADDR (disconnect1),
2104 }/*-------------------------< DISCONNECT1 >--------------*/,{
2105 SCR_INT ^ IFFALSE (DATA (1)),
2106 SIR_MISSING_SAVE,
2107 /*>>>*/
2108
2109 /*
2110 ** DISCONNECTing ...
2111 **
2112 ** disable the "unexpected disconnect" feature,
2113 ** and remove the ACK signal.
2114 */
2115 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
2116 0,
2117 SCR_CLR (SCR_ACK|SCR_ATN),
2118 0,
2119 /*
2120 ** Wait for the disconnect.
2121 */
2122 SCR_WAIT_DISC,
2123 0,
2124 /*
2125 ** Profiling:
2126 ** Set a time stamp,
2127 ** and count the disconnects.
2128 */
2129 SCR_COPY (sizeof (ticks)),
2130 KVAR (KVAR_TICKS),
2131 NADDR (header.stamp.disconnect),
2132 SCR_COPY (4),
2133 NADDR (disc_phys),
2134 RADDR (temp),
2135 SCR_REG_REG (temp, SCR_ADD, 0x01),
2136 0,
2137 SCR_COPY (4),
2138 RADDR (temp),
2139 NADDR (disc_phys),
2140 /*
2141 ** Status is: DISCONNECTED.
2142 */
2143 SCR_LOAD_REG (HS_REG, HS_DISCONNECT),
2144 0,
2145 SCR_JUMP,
2146 PADDR (cleanup),
2147
2148 }/*-------------------------< MSG_OUT >-------------------*/,{
2149 /*
2150 ** The target requests a message.
2151 */
2152 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
2153 NADDR (msgout),
2154 SCR_COPY (1),
2155 RADDR (sfbr),
2156 NADDR (lastmsg),
2157 /*
2158 ** If it was no ABORT message ...
2159 */
2160 SCR_JUMP ^ IFTRUE (DATA (MSG_ABORT)),
2161 PADDRH (msg_out_abort),
2162 /*
2163 ** ... wait for the next phase
2164 ** if it's a message out, send it again, ...
2165 */
2166 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)),
2167 PADDR (msg_out),
2168 }/*-------------------------< MSG_OUT_DONE >--------------*/,{
2169 /*
2170 ** ... else clear the message ...
2171 */
2172 SCR_LOAD_REG (scratcha, MSG_NOOP),
2173 0,
2174 SCR_COPY (4),
2175 RADDR (scratcha),
2176 NADDR (msgout),
2177 /*
2178 ** ... and process the next phase
2179 */
2180 SCR_JUMP,
2181 PADDR (dispatch),
2182
2183 }/*------------------------< BADGETCC >---------------------*/,{
2184 /*
2185 ** If SIGP was set, clear it and try again.
2186 */
2187 SCR_FROM_REG (ctest2),
2188 0,
2189 SCR_JUMP ^ IFTRUE (MASK (CSIGP,CSIGP)),
2190 PADDRH (getcc2),
2191 SCR_INT,
2192 SIR_SENSE_FAILED,
2193 }/*-------------------------< RESELECT >--------------------*/,{
2194 /*
2195 ** This NOP will be patched with LED OFF
2196 ** SCR_REG_REG (gpreg, SCR_OR, 0x01)
2197 */
2198 SCR_NO_OP,
2199 0,
2200
2201 /*
2202 ** make the DSA invalid.
2203 */
2204 SCR_LOAD_REG (dsa, 0xff),
2205 0,
2206 SCR_CLR (SCR_TRG),
2207 0,
2208 /*
2209 ** Sleep waiting for a reselection.
2210 ** If SIGP is set, special treatment.
2211 **
2212 ** Zu allem bereit ..
2213 */
2214 SCR_WAIT_RESEL,
2215 PADDR(reselect2),
2216 }/*-------------------------< RESELECT1 >--------------------*/,{
2217 /*
2218 ** This NOP will be patched with LED ON
2219 ** SCR_REG_REG (gpreg, SCR_AND, 0xfe)
2220 */
2221 SCR_NO_OP,
2222 0,
2223 /*
2224 ** ... zu nichts zu gebrauchen ?
2225 **
2226 ** load the target id into the SFBR
2227 ** and jump to the control block.
2228 **
2229 ** Look at the declarations of
2230 ** - struct ncb
2231 ** - struct tcb
2232 ** - struct lcb
2233 ** - struct nccb
2234 ** to understand what's going on.
2235 */
2236 SCR_REG_SFBR (ssid, SCR_AND, 0x8F),
2237 0,
2238 SCR_TO_REG (sdid),
2239 0,
2240 SCR_JUMP,
2241 NADDR (jump_tcb),
2242 }/*-------------------------< RESELECT2 >-------------------*/,{
2243 /*
2244 ** This NOP will be patched with LED ON
2245 ** SCR_REG_REG (gpreg, SCR_AND, 0xfe)
2246 */
2247 SCR_NO_OP,
2248 0,
2249 /*
2250 ** If it's not connected :(
2251 ** -> interrupted by SIGP bit.
2252 ** Jump to start.
2253 */
2254 SCR_FROM_REG (ctest2),
2255 0,
2256 SCR_JUMP ^ IFTRUE (MASK (CSIGP,CSIGP)),
2257 PADDR (start),
2258 SCR_JUMP,
2259 PADDR (reselect),
2260
2261 }/*-------------------------< RESEL_TMP >-------------------*/,{
2262 /*
2263 ** The return address in TEMP
2264 ** is in fact the data structure address,
2265 ** so copy it to the DSA register.
2266 */
2267 SCR_COPY (4),
2268 RADDR (temp),
2269 RADDR (dsa),
2270 SCR_JUMP,
2271 PADDR (prepare),
2272
2273 }/*-------------------------< RESEL_LUN >-------------------*/,{
2274 /*
2275 ** come back to this point
2276 ** to get an IDENTIFY message
2277 ** Wait for a msg_in phase.
2278 */
2279 /*<<<*/ SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_IN)),
2280 48,
2281 /*
2282 ** message phase
2283 ** It's not a sony, it's a trick:
2284 ** read the data without acknowledging it.
2285 */
2286 SCR_FROM_REG (sbdl),
2287 0,
2288 /*<<<*/ SCR_JUMPR ^ IFFALSE (MASK (MSG_IDENTIFYFLAG, 0x98)),
2289 32,
2290 /*
2291 ** It WAS an Identify message.
2292 ** get it and ack it!
2293 */
2294 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
2295 NADDR (msgin),
2296 SCR_CLR (SCR_ACK),
2297 0,
2298 /*
2299 ** Mask out the lun.
2300 */
2301 SCR_REG_REG (sfbr, SCR_AND, 0x07),
2302 0,
2303 SCR_RETURN,
2304 0,
2305 /*
2306 ** No message phase or no IDENTIFY message:
2307 ** return 0.
2308 */
2309 /*>>>*/ SCR_LOAD_SFBR (0),
2310 0,
2311 SCR_RETURN,
2312 0,
2313
2314 }/*-------------------------< RESEL_TAG >-------------------*/,{
2315 /*
2316 ** come back to this point
2317 ** to get a SIMPLE_TAG message
2318 ** Wait for a MSG_IN phase.
2319 */
2320 /*<<<*/ SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_IN)),
2321 64,
2322 /*
2323 ** message phase
2324 ** It's a trick - read the data
2325 ** without acknowledging it.
2326 */
2327 SCR_FROM_REG (sbdl),
2328 0,
2329 /*<<<*/ SCR_JUMPR ^ IFFALSE (DATA (MSG_SIMPLE_Q_TAG)),
2330 48,
2331 /*
2332 ** It WAS a SIMPLE_TAG message.
2333 ** get it and ack it!
2334 */
2335 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
2336 NADDR (msgin),
2337 SCR_CLR (SCR_ACK),
2338 0,
2339 /*
2340 ** Wait for the second byte (the tag)
2341 */
2342 /*<<<*/ SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_IN)),
2343 24,
2344 /*
2345 ** Get it and ack it!
2346 */
2347 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
2348 NADDR (msgin),
2349 SCR_CLR (SCR_ACK|SCR_CARRY),
2350 0,
2351 SCR_RETURN,
2352 0,
2353 /*
2354 ** No message phase or no SIMPLE_TAG message
2355 ** or no second byte: return 0.
2356 */
2357 /*>>>*/ SCR_LOAD_SFBR (0),
2358 0,
2359 SCR_SET (SCR_CARRY),
2360 0,
2361 SCR_RETURN,
2362 0,
2363
2364 }/*-------------------------< DATA_IN >--------------------*/,{
2365 /*
2366 ** Because the size depends on the
2367 ** #define MAX_SCATTER parameter,
2368 ** it is filled in at runtime.
2369 **
2370 ** SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)),
2371 ** PADDR (no_data),
2372 ** SCR_COPY (sizeof (ticks)),
2373 ** KVAR (KVAR_TICKS),
2374 ** NADDR (header.stamp.data),
2375 ** SCR_MOVE_TBL ^ SCR_DATA_IN,
2376 ** offsetof (struct dsb, data[ 0]),
2377 **
2378 ** ##===========< i=1; i<MAX_SCATTER >=========
2379 ** || SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_IN)),
2380 ** || PADDR (checkatn),
2381 ** || SCR_MOVE_TBL ^ SCR_DATA_IN,
2382 ** || offsetof (struct dsb, data[ i]),
2383 ** ##==========================================
2384 **
2385 ** SCR_CALL,
2386 ** PADDR (checkatn),
2387 ** SCR_JUMP,
2388 ** PADDR (no_data),
2389 */
2390
2391 }/*-------------------------< DATA_OUT >-------------------*/,{
2392 /*
2393 ** Because the size depends on the
2394 ** #define MAX_SCATTER parameter,
2395 ** it is filled in at runtime.
2396 **
2397 ** SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_OUT)),
2398 ** PADDR (no_data),
2399 ** SCR_COPY (sizeof (ticks)),
2400 ** KVAR (KVAR_TICKS),
2401 ** NADDR (header.stamp.data),
2402 ** SCR_MOVE_TBL ^ SCR_DATA_OUT,
2403 ** offsetof (struct dsb, data[ 0]),
2404 **
2405 ** ##===========< i=1; i<MAX_SCATTER >=========
2406 ** || SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_OUT)),
2407 ** || PADDR (dispatch),
2408 ** || SCR_MOVE_TBL ^ SCR_DATA_OUT,
2409 ** || offsetof (struct dsb, data[ i]),
2410 ** ##==========================================
2411 **
2412 ** SCR_CALL,
2413 ** PADDR (dispatch),
2414 ** SCR_JUMP,
2415 ** PADDR (no_data),
2416 **
2417 **---------------------------------------------------------
2418 */
2419 (u_long)0
2420
2421 }/*--------------------------------------------------------*/
2422 };
2423
2424
2425 static struct scripth scripth0 = {
2426 /*-------------------------< TRYLOOP >---------------------*/{
2427 /*
2428 ** Load an entry of the start queue into dsa
2429 ** and try to start it by jumping to TRYSEL.
2430 **
2431 ** Because the size depends on the
2432 ** #define MAX_START parameter, it is filled
2433 ** in at runtime.
2434 **
2435 **-----------------------------------------------------------
2436 **
2437 ** ##===========< I=0; i<MAX_START >===========
2438 ** || SCR_COPY (4),
2439 ** || NADDR (squeue[i]),
2440 ** || RADDR (dsa),
2441 ** || SCR_CALL,
2442 ** || PADDR (trysel),
2443 ** ##==========================================
2444 **
2445 ** SCR_JUMP,
2446 ** PADDRH(tryloop),
2447 **
2448 **-----------------------------------------------------------
2449 */
2450
2451 }/*-------------------------< MSG_PARITY >---------------*/,{
2452 /*
2453 ** count it
2454 */
2455 SCR_REG_REG (PS_REG, SCR_ADD, 0x01),
2456 0,
2457 /*
2458 ** send a "message parity error" message.
2459 */
2460 SCR_LOAD_REG (scratcha, MSG_PARITY_ERROR),
2461 0,
2462 SCR_JUMP,
2463 PADDR (setmsg),
2464 }/*-------------------------< MSG_MESSAGE_REJECT >---------------*/,{
2465 /*
2466 ** If a negotiation was in progress,
2467 ** negotiation failed.
2468 */
2469 SCR_FROM_REG (HS_REG),
2470 0,
2471 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)),
2472 SIR_NEGO_FAILED,
2473 /*
2474 ** else make host log this message
2475 */
2476 SCR_INT ^ IFFALSE (DATA (HS_NEGOTIATE)),
2477 SIR_REJECT_RECEIVED,
2478 SCR_JUMP,
2479 PADDR (clrack),
2480
2481 }/*-------------------------< MSG_IGN_RESIDUE >----------*/,{
2482 /*
2483 ** Terminate cycle
2484 */
2485 SCR_CLR (SCR_ACK),
2486 0,
2487 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
2488 PADDR (dispatch),
2489 /*
2490 ** get residue size.
2491 */
2492 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
2493 NADDR (msgin[1]),
2494 /*
2495 ** Check for message parity error.
2496 */
2497 SCR_TO_REG (scratcha),
2498 0,
2499 SCR_FROM_REG (socl),
2500 0,
2501 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)),
2502 PADDRH (msg_parity),
2503 SCR_FROM_REG (scratcha),
2504 0,
2505 /*
2506 ** Size is 0 .. ignore message.
2507 */
2508 SCR_JUMP ^ IFTRUE (DATA (0)),
2509 PADDR (clrack),
2510 /*
2511 ** Size is not 1 .. have to interrupt.
2512 */
2513 /*<<<*/ SCR_JUMPR ^ IFFALSE (DATA (1)),
2514 40,
2515 /*
2516 ** Check for residue byte in swide register
2517 */
2518 SCR_FROM_REG (scntl2),
2519 0,
2520 /*<<<*/ SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)),
2521 16,
2522 /*
2523 ** There IS data in the swide register.
2524 ** Discard it.
2525 */
2526 SCR_REG_REG (scntl2, SCR_OR, WSR),
2527 0,
2528 SCR_JUMP,
2529 PADDR (clrack),
2530 /*
2531 ** Load again the size to the sfbr register.
2532 */
2533 /*>>>*/ SCR_FROM_REG (scratcha),
2534 0,
2535 /*>>>*/ SCR_INT,
2536 SIR_IGN_RESIDUE,
2537 SCR_JUMP,
2538 PADDR (clrack),
2539
2540 }/*-------------------------< MSG_EXTENDED >-------------*/,{
2541 /*
2542 ** Terminate cycle
2543 */
2544 SCR_CLR (SCR_ACK),
2545 0,
2546 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
2547 PADDR (dispatch),
2548 /*
2549 ** get length.
2550 */
2551 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
2552 NADDR (msgin[1]),
2553 /*
2554 ** Check for message parity error.
2555 */
2556 SCR_TO_REG (scratcha),
2557 0,
2558 SCR_FROM_REG (socl),
2559 0,
2560 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)),
2561 PADDRH (msg_parity),
2562 SCR_FROM_REG (scratcha),
2563 0,
2564 /*
2565 */
2566 SCR_JUMP ^ IFTRUE (DATA (3)),
2567 PADDRH (msg_ext_3),
2568 SCR_JUMP ^ IFFALSE (DATA (2)),
2569 PADDR (msg_bad),
2570 }/*-------------------------< MSG_EXT_2 >----------------*/,{
2571 SCR_CLR (SCR_ACK),
2572 0,
2573 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
2574 PADDR (dispatch),
2575 /*
2576 ** get extended message code.
2577 */
2578 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
2579 NADDR (msgin[2]),
2580 /*
2581 ** Check for message parity error.
2582 */
2583 SCR_TO_REG (scratcha),
2584 0,
2585 SCR_FROM_REG (socl),
2586 0,
2587 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)),
2588 PADDRH (msg_parity),
2589 SCR_FROM_REG (scratcha),
2590 0,
2591 SCR_JUMP ^ IFTRUE (DATA (MSG_EXT_WDTR)),
2592 PADDRH (msg_wdtr),
2593 /*
2594 ** unknown extended message
2595 */
2596 SCR_JUMP,
2597 PADDR (msg_bad)
2598 }/*-------------------------< MSG_WDTR >-----------------*/,{
2599 SCR_CLR (SCR_ACK),
2600 0,
2601 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
2602 PADDR (dispatch),
2603 /*
2604 ** get data bus width
2605 */
2606 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
2607 NADDR (msgin[3]),
2608 SCR_FROM_REG (socl),
2609 0,
2610 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)),
2611 PADDRH (msg_parity),
2612 /*
2613 ** let the host do the real work.
2614 */
2615 SCR_INT,
2616 SIR_NEGO_WIDE,
2617 /*
2618 ** let the target fetch our answer.
2619 */
2620 SCR_SET (SCR_ATN),
2621 0,
2622 SCR_CLR (SCR_ACK),
2623 0,
2624
2625 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)),
2626 SIR_NEGO_PROTO,
2627 /*
2628 ** Send the MSG_EXT_WDTR
2629 */
2630 SCR_MOVE_ABS (4) ^ SCR_MSG_OUT,
2631 NADDR (msgout),
2632 SCR_CLR (SCR_ATN),
2633 0,
2634 SCR_COPY (1),
2635 RADDR (sfbr),
2636 NADDR (lastmsg),
2637 SCR_JUMP,
2638 PADDR (msg_out_done),
2639
2640 }/*-------------------------< MSG_EXT_3 >----------------*/,{
2641 SCR_CLR (SCR_ACK),
2642 0,
2643 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
2644 PADDR (dispatch),
2645 /*
2646 ** get extended message code.
2647 */
2648 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
2649 NADDR (msgin[2]),
2650 /*
2651 ** Check for message parity error.
2652 */
2653 SCR_TO_REG (scratcha),
2654 0,
2655 SCR_FROM_REG (socl),
2656 0,
2657 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)),
2658 PADDRH (msg_parity),
2659 SCR_FROM_REG (scratcha),
2660 0,
2661 SCR_JUMP ^ IFTRUE (DATA (MSG_EXT_SDTR)),
2662 PADDRH (msg_sdtr),
2663 /*
2664 ** unknown extended message
2665 */
2666 SCR_JUMP,
2667 PADDR (msg_bad)
2668
2669 }/*-------------------------< MSG_SDTR >-----------------*/,{
2670 SCR_CLR (SCR_ACK),
2671 0,
2672 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
2673 PADDR (dispatch),
2674 /*
2675 ** get period and offset
2676 */
2677 SCR_MOVE_ABS (2) ^ SCR_MSG_IN,
2678 NADDR (msgin[3]),
2679 SCR_FROM_REG (socl),
2680 0,
2681 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)),
2682 PADDRH (msg_parity),
2683 /*
2684 ** let the host do the real work.
2685 */
2686 SCR_INT,
2687 SIR_NEGO_SYNC,
2688 /*
2689 ** let the target fetch our answer.
2690 */
2691 SCR_SET (SCR_ATN),
2692 0,
2693 SCR_CLR (SCR_ACK),
2694 0,
2695
2696 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)),
2697 SIR_NEGO_PROTO,
2698 /*
2699 ** Send the MSG_EXT_SDTR
2700 */
2701 SCR_MOVE_ABS (5) ^ SCR_MSG_OUT,
2702 NADDR (msgout),
2703 SCR_CLR (SCR_ATN),
2704 0,
2705 SCR_COPY (1),
2706 RADDR (sfbr),
2707 NADDR (lastmsg),
2708 SCR_JUMP,
2709 PADDR (msg_out_done),
2710
2711 }/*-------------------------< MSG_OUT_ABORT >-------------*/,{
2712 /*
2713 ** After ABORT message,
2714 **
2715 ** expect an immediate disconnect, ...
2716 */
2717 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
2718 0,
2719 SCR_CLR (SCR_ACK|SCR_ATN),
2720 0,
2721 SCR_WAIT_DISC,
2722 0,
2723 /*
2724 ** ... and set the status to "ABORTED"
2725 */
2726 SCR_LOAD_REG (HS_REG, HS_ABORTED),
2727 0,
2728 SCR_JUMP,
2729 PADDR (cleanup),
2730
2731 }/*-------------------------< GETCC >-----------------------*/,{
2732 /*
2733 ** The ncr doesn't have an indirect load
2734 ** or store command. So we have to
2735 ** copy part of the control block to a
2736 ** fixed place, where we can modify it.
2737 **
2738 ** We patch the address part of a COPY command
2739 ** with the address of the dsa register ...
2740 */
2741 SCR_COPY_F (4),
2742 RADDR (dsa),
2743 PADDRH (getcc1),
2744 /*
2745 ** ... then we do the actual copy.
2746 */
2747 SCR_COPY (sizeof (struct head)),
2748 }/*-------------------------< GETCC1 >----------------------*/,{
2749 0,
2750 NADDR (header),
2751 /*
2752 ** Initialize the status registers
2753 */
2754 SCR_COPY (4),
2755 NADDR (header.status),
2756 RADDR (scr0),
2757 }/*-------------------------< GETCC2 >----------------------*/,{
2758 /*
2759 ** Get the condition code from a target.
2760 **
2761 ** DSA points to a data structure.
2762 ** Set TEMP to the script location
2763 ** that receives the condition code.
2764 **
2765 ** Because there is no script command
2766 ** to load a longword into a register,
2767 ** we use a CALL command.
2768 */
2769 /*<<<*/ SCR_CALLR,
2770 24,
2771 /*
2772 ** Get the condition code.
2773 */
2774 SCR_MOVE_TBL ^ SCR_DATA_IN,
2775 offsetof (struct dsb, sense),
2776 /*
2777 ** No data phase may follow!
2778 */
2779 SCR_CALL,
2780 PADDR (checkatn),
2781 SCR_JUMP,
2782 PADDR (no_data),
2783 /*>>>*/
2784
2785 /*
2786 ** The CALL jumps to this point.
2787 ** Prepare for a RESTORE_POINTER message.
2788 ** Save the TEMP register into the saved pointer.
2789 */
2790 SCR_COPY (4),
2791 RADDR (temp),
2792 NADDR (header.savep),
2793 /*
2794 ** Load scratcha, because in case of a selection timeout,
2795 ** the host will expect a new value for startpos in
2796 ** the scratcha register.
2797 */
2798 SCR_COPY (4),
2799 PADDR (startpos),
2800 RADDR (scratcha),
2801 #ifdef NCR_GETCC_WITHMSG
2802 /*
2803 ** If QUIRK_NOMSG is set, select without ATN.
2804 ** and don't send a message.
2805 */
2806 SCR_FROM_REG (QU_REG),
2807 0,
2808 SCR_JUMP ^ IFTRUE (MASK (QUIRK_NOMSG, QUIRK_NOMSG)),
2809 PADDRH(getcc3),
2810 /*
2811 ** Then try to connect to the target.
2812 ** If we are reselected, special treatment
2813 ** of the current job is required before
2814 ** accepting the reselection.
2815 */
2816 SCR_SEL_TBL_ATN ^ offsetof (struct dsb, select),
2817 PADDR(badgetcc),
2818 /*
2819 ** Send the IDENTIFY message.
2820 ** In case of short transfer, remove ATN.
2821 */
2822 SCR_MOVE_TBL ^ SCR_MSG_OUT,
2823 offsetof (struct dsb, smsg2),
2824 SCR_CLR (SCR_ATN),
2825 0,
2826 /*
2827 ** save the first byte of the message.
2828 */
2829 SCR_COPY (1),
2830 RADDR (sfbr),
2831 NADDR (lastmsg),
2832 SCR_JUMP,
2833 PADDR (prepare2),
2834
2835 #endif
2836 }/*-------------------------< GETCC3 >----------------------*/,{
2837 /*
2838 ** Try to connect to the target.
2839 ** If we are reselected, special treatment
2840 ** of the current job is required before
2841 ** accepting the reselection.
2842 **
2843 ** Silly target won't accept a message.
2844 ** Select without ATN.
2845 */
2846 SCR_SEL_TBL ^ offsetof (struct dsb, select),
2847 PADDR(badgetcc),
2848 /*
2849 ** Force error if selection timeout
2850 */
2851 SCR_JUMPR ^ IFTRUE (WHEN (SCR_MSG_IN)),
2852 0,
2853 /*
2854 ** don't negotiate.
2855 */
2856 SCR_JUMP,
2857 PADDR (prepare2),
2858 }/*-------------------------< ABORTTAG >-------------------*/,{
2859 /*
2860 ** Abort a bad reselection.
2861 ** Set the message to ABORT vs. ABORT_TAG
2862 */
2863 SCR_LOAD_REG (scratcha, MSG_ABORT_TAG),
2864 0,
2865 SCR_JUMPR ^ IFFALSE (CARRYSET),
2866 8,
2867 }/*-------------------------< ABORT >----------------------*/,{
2868 SCR_LOAD_REG (scratcha, MSG_ABORT),
2869 0,
2870 SCR_COPY (1),
2871 RADDR (scratcha),
2872 NADDR (msgout),
2873 SCR_SET (SCR_ATN),
2874 0,
2875 SCR_CLR (SCR_ACK),
2876 0,
2877 /*
2878 ** and send it.
2879 ** we expect an immediate disconnect
2880 */
2881 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
2882 0,
2883 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
2884 NADDR (msgout),
2885 SCR_COPY (1),
2886 RADDR (sfbr),
2887 NADDR (lastmsg),
2888 SCR_CLR (SCR_ACK|SCR_ATN),
2889 0,
2890 SCR_WAIT_DISC,
2891 0,
2892 SCR_JUMP,
2893 PADDR (start),
2894 }/*-------------------------< SNOOPTEST >-------------------*/,{
2895 /*
2896 ** Read the variable.
2897 */
2898 SCR_COPY (4),
2899 KVAR (KVAR_NCR_CACHE),
2900 RADDR (scratcha),
2901 /*
2902 ** Write the variable.
2903 */
2904 SCR_COPY (4),
2905 RADDR (temp),
2906 KVAR (KVAR_NCR_CACHE),
2907 /*
2908 ** Read back the variable.
2909 */
2910 SCR_COPY (4),
2911 KVAR (KVAR_NCR_CACHE),
2912 RADDR (temp),
2913 }/*-------------------------< SNOOPEND >-------------------*/,{
2914 /*
2915 ** And stop.
2916 */
2917 SCR_INT,
2918 99,
2919 }/*--------------------------------------------------------*/
2920 };
2921
2922
2923 /*==========================================================
2924 **
2925 **
2926 ** Fill in #define dependent parts of the script
2927 **
2928 **
2929 **==========================================================
2930 */
2931
2932 void ncr_script_fill (struct script * scr, struct scripth * scrh)
2933 {
2934 int i;
2935 ncrcmd *p;
2936
2937 p = scrh->tryloop;
2938 for (i=0; i<MAX_START; i++) {
2939 *p++ =SCR_COPY (4);
2940 *p++ =NADDR (squeue[i]);
2941 *p++ =RADDR (dsa);
2942 *p++ =SCR_CALL;
2943 *p++ =PADDR (trysel);
2944 };
2945 *p++ =SCR_JUMP;
2946 *p++ =PADDRH(tryloop);
2947
2948 assert ((char *)p == (char *)&scrh->tryloop + sizeof (scrh->tryloop));
2949
2950 p = scr->data_in;
2951
2952 *p++ =SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN));
2953 *p++ =PADDR (no_data);
2954 *p++ =SCR_COPY (sizeof (ticks));
2955 *p++ =(ncrcmd) KVAR (KVAR_TICKS);
2956 *p++ =NADDR (header.stamp.data);
2957 *p++ =SCR_MOVE_TBL ^ SCR_DATA_IN;
2958 *p++ =offsetof (struct dsb, data[ 0]);
2959
2960 for (i=1; i<MAX_SCATTER; i++) {
2961 *p++ =SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_IN));
2962 *p++ =PADDR (checkatn);
2963 *p++ =SCR_MOVE_TBL ^ SCR_DATA_IN;
2964 *p++ =offsetof (struct dsb, data[i]);
2965 };
2966
2967 *p++ =SCR_CALL;
2968 *p++ =PADDR (checkatn);
2969 *p++ =SCR_JUMP;
2970 *p++ =PADDR (no_data);
2971
2972 assert ((char *)p == (char *)&scr->data_in + sizeof (scr->data_in));
2973
2974 p = scr->data_out;
2975
2976 *p++ =SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_OUT));
2977 *p++ =PADDR (no_data);
2978 *p++ =SCR_COPY (sizeof (ticks));
2979 *p++ =(ncrcmd) KVAR (KVAR_TICKS);
2980 *p++ =NADDR (header.stamp.data);
2981 *p++ =SCR_MOVE_TBL ^ SCR_DATA_OUT;
2982 *p++ =offsetof (struct dsb, data[ 0]);
2983
2984 for (i=1; i<MAX_SCATTER; i++) {
2985 *p++ =SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_OUT));
2986 *p++ =PADDR (dispatch);
2987 *p++ =SCR_MOVE_TBL ^ SCR_DATA_OUT;
2988 *p++ =offsetof (struct dsb, data[i]);
2989 };
2990
2991 *p++ =SCR_CALL;
2992 *p++ =PADDR (dispatch);
2993 *p++ =SCR_JUMP;
2994 *p++ =PADDR (no_data);
2995
2996 assert ((char *)p == (char *)&scr->data_out + sizeof (scr->data_out));
2997 }
2998
2999 /*==========================================================
3000 **
3001 **
3002 ** Copy and rebind a script.
3003 **
3004 **
3005 **==========================================================
3006 */
3007
3008 static void ncr_script_copy_and_bind (ncb_p np, ncrcmd *src, ncrcmd *dst, int len)
3009 {
3010 ncrcmd opcode, new, old, tmp1, tmp2;
3011 ncrcmd *start, *end;
3012 int relocs, offset;
3013
3014 start = src;
3015 end = src + len/4;
3016 offset = 0;
3017
3018 while (src < end) {
3019
3020 opcode = *src++;
3021 WRITESCRIPT_OFF(dst, offset, opcode);
3022 offset += 4;
3023
3024 /*
3025 ** If we forget to change the length
3026 ** in struct script, a field will be
3027 ** padded with 0. This is an illegal
3028 ** command.
3029 */
3030
3031 if (opcode == 0) {
3032 printf ("%s: ERROR0 IN SCRIPT at %d.\n",
3033 ncr_name(np), (int) (src-start-1));
3034 DELAY (1000000);
3035 };
3036
3037 if (DEBUG_FLAGS & DEBUG_SCRIPT)
3038 printf ("%p: <%x>\n",
3039 (src-1), (unsigned)opcode);
3040
3041 /*
3042 ** We don't have to decode ALL commands
3043 */
3044 switch (opcode >> 28) {
3045
3046 case 0xc:
3047 /*
3048 ** COPY has TWO arguments.
3049 */
3050 relocs = 2;
3051 tmp1 = src[0];
3052 if ((tmp1 & RELOC_MASK) == RELOC_KVAR)
3053 tmp1 = 0;
3054 tmp2 = src[1];
3055 if ((tmp2 & RELOC_MASK) == RELOC_KVAR)
3056 tmp2 = 0;
3057 if ((tmp1 ^ tmp2) & 3) {
3058 printf ("%s: ERROR1 IN SCRIPT at %d.\n",
3059 ncr_name(np), (int) (src-start-1));
3060 DELAY (1000000);
3061 }
3062 /*
3063 ** If PREFETCH feature not enabled, remove
3064 ** the NO FLUSH bit if present.
3065 */
3066 if ((opcode & SCR_NO_FLUSH) && !(np->features&FE_PFEN))
3067 WRITESCRIPT_OFF(dst, offset - 4,
3068 (opcode & ~SCR_NO_FLUSH));
3069 break;
3070
3071 case 0x0:
3072 /*
3073 ** MOVE (absolute address)
3074 */
3075 relocs = 1;
3076 break;
3077
3078 case 0x8:
3079 /*
3080 ** JUMP / CALL
3081 ** dont't relocate if relative :-)
3082 */
3083 if (opcode & 0x00800000)
3084 relocs = 0;
3085 else
3086 relocs = 1;
3087 break;
3088
3089 case 0x4:
3090 case 0x5:
3091 case 0x6:
3092 case 0x7:
3093 relocs = 1;
3094 break;
3095
3096 default:
3097 relocs = 0;
3098 break;
3099 };
3100
3101 if (relocs) {
3102 while (relocs--) {
3103 old = *src++;
3104
3105 switch (old & RELOC_MASK) {
3106 case RELOC_REGISTER:
3107 new = (old & ~RELOC_MASK) + rman_get_start(np->reg_res);
3108 break;
3109 case RELOC_LABEL:
3110 new = (old & ~RELOC_MASK) + np->p_script;
3111 break;
3112 case RELOC_LABELH:
3113 new = (old & ~RELOC_MASK) + np->p_scripth;
3114 break;
3115 case RELOC_SOFTC:
3116 new = (old & ~RELOC_MASK) + vtophys(np);
3117 break;
3118 case RELOC_KVAR:
3119 if (((old & ~RELOC_MASK) <
3120 SCRIPT_KVAR_FIRST) ||
3121 ((old & ~RELOC_MASK) >
3122 SCRIPT_KVAR_LAST))
3123 panic("ncr KVAR out of range");
3124 new = vtophys(script_kvars[old &
3125 ~RELOC_MASK]);
3126 break;
3127 case 0:
3128 /* Don't relocate a 0 address. */
3129 if (old == 0) {
3130 new = old;
3131 break;
3132 }
3133 /* fall through */
3134 default:
3135 panic("ncr_script_copy_and_bind: weird relocation %x @ %d\n", old, (int)(src - start));
3136 break;
3137 }
3138
3139 WRITESCRIPT_OFF(dst, offset, new);
3140 offset += 4;
3141 }
3142 } else {
3143 WRITESCRIPT_OFF(dst, offset, *src++);
3144 offset += 4;
3145 }
3146
3147 };
3148 }
3149
3150 /*==========================================================
3151 **
3152 **
3153 ** Auto configuration.
3154 **
3155 **
3156 **==========================================================
3157 */
3158
3159 #if 0
3160 /*----------------------------------------------------------
3161 **
3162 ** Reduce the transfer length to the max value
3163 ** we can transfer safely.
3164 **
3165 ** Reading a block greater then MAX_SIZE from the
3166 ** raw (character) device exercises a memory leak
3167 ** in the vm subsystem. This is common to ALL devices.
3168 ** We have submitted a description of this bug to
3169 ** <FreeBSD-bugs@freefall.cdrom.com>.
3170 ** It should be fixed in the current release.
3171 **
3172 **----------------------------------------------------------
3173 */
3174
3175 void ncr_min_phys (struct buf *bp)
3176 {
3177 if ((unsigned long)bp->b_bcount > MAX_SIZE) bp->b_bcount = MAX_SIZE;
3178 }
3179
3180 #endif
3181
3182 #if 0
3183 /*----------------------------------------------------------
3184 **
3185 ** Maximal number of outstanding requests per target.
3186 **
3187 **----------------------------------------------------------
3188 */
3189
3190 u_int32_t ncr_info (int unit)
3191 {
3192 return (1); /* may be changed later */
3193 }
3194
3195 #endif
3196
3197 /*----------------------------------------------------------
3198 **
3199 ** NCR chip devices table and chip look up function.
3200 ** Features bit are defined in ncrreg.h. Is it the
3201 ** right place?
3202 **
3203 **----------------------------------------------------------
3204 */
3205 typedef struct {
3206 unsigned long device_id;
3207 unsigned short minrevid;
3208 char *name;
3209 unsigned char maxburst;
3210 unsigned char maxoffs;
3211 unsigned char clock_divn;
3212 unsigned int features;
3213 } ncr_chip;
3214
3215 static ncr_chip ncr_chip_table[] = {
3216 {NCR_810_ID, 0x00, "ncr 53c810 fast10 scsi", 4, 8, 4,
3217 FE_ERL}
3218 ,
3219 {NCR_810_ID, 0x10, "ncr 53c810a fast10 scsi", 4, 8, 4,
3220 FE_ERL|FE_LDSTR|FE_PFEN|FE_BOF}
3221 ,
3222 {NCR_815_ID, 0x00, "ncr 53c815 fast10 scsi", 4, 8, 4,
3223 FE_ERL|FE_BOF}
3224 ,
3225 {NCR_820_ID, 0x00, "ncr 53c820 fast10 wide scsi", 4, 8, 4,
3226 FE_WIDE|FE_ERL}
3227 ,
3228 {NCR_825_ID, 0x00, "ncr 53c825 fast10 wide scsi", 4, 8, 4,
3229 FE_WIDE|FE_ERL|FE_BOF}
3230 ,
3231 {NCR_825_ID, 0x10, "ncr 53c825a fast10 wide scsi", 7, 8, 4,
3232 FE_WIDE|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}
3233 ,
3234 {NCR_860_ID, 0x00, "ncr 53c860 fast20 scsi", 4, 8, 5,
3235 FE_ULTRA|FE_CLK80|FE_CACHE_SET|FE_LDSTR|FE_PFEN}
3236 ,
3237 {NCR_875_ID, 0x00, "ncr 53c875 fast20 wide scsi", 7, 16, 5,
3238 FE_WIDE|FE_ULTRA|FE_CLK80|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}
3239 ,
3240 {NCR_875_ID, 0x02, "ncr 53c875 fast20 wide scsi", 7, 16, 5,
3241 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}
3242 ,
3243 {NCR_875_ID2, 0x00, "ncr 53c875j fast20 wide scsi", 7, 16, 5,
3244 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}
3245 ,
3246 {NCR_885_ID, 0x00, "ncr 53c885 fast20 wide scsi", 7, 16, 5,
3247 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}
3248 ,
3249 {NCR_895_ID, 0x00, "ncr 53c895 fast40 wide scsi", 7, 31, 7,
3250 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}
3251 ,
3252 {NCR_896_ID, 0x00, "ncr 53c896 fast40 wide scsi", 7, 31, 7,
3253 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}
3254 ,
3255 {NCR_895A_ID, 0x00, "ncr 53c895a fast40 wide scsi", 7, 31, 7,
3256 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}
3257 ,
3258 {NCR_1510D_ID, 0x00, "ncr 53c1510d fast40 wide scsi", 7, 31, 7,
3259 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}
3260 };
3261
3262 static int ncr_chip_lookup(u_long device_id, u_char revision_id)
3263 {
3264 int i, found;
3265
3266 found = -1;
3267 for (i = 0; i < sizeof(ncr_chip_table)/sizeof(ncr_chip_table[0]); i++) {
3268 if (device_id == ncr_chip_table[i].device_id &&
3269 ncr_chip_table[i].minrevid <= revision_id) {
3270 if (found < 0 ||
3271 ncr_chip_table[found].minrevid
3272 < ncr_chip_table[i].minrevid) {
3273 found = i;
3274 }
3275 }
3276 }
3277 return found;
3278 }
3279
3280 /*----------------------------------------------------------
3281 **
3282 ** Probe the hostadapter.
3283 **
3284 **----------------------------------------------------------
3285 */
3286
3287
3288
3289 static int ncr_probe (device_t dev)
3290 {
3291 int i;
3292
3293 i = ncr_chip_lookup(pci_get_devid(dev), pci_get_revid(dev));
3294 if (i >= 0) {
3295 device_set_desc(dev, ncr_chip_table[i].name);
3296 return (-1000); /* Allows to use both ncr and sym */
3297 }
3298
3299 return (ENXIO);
3300 }
3301
3302
3303
3304 /*==========================================================
3305 **
3306 ** NCR chip clock divisor table.
3307 ** Divisors are multiplied by 10,000,000 in order to make
3308 ** calculations more simple.
3309 **
3310 **==========================================================
3311 */
3312
3313 #define _5M 5000000
3314 static u_long div_10M[] =
3315 {2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M};
3316
3317 /*===============================================================
3318 **
3319 ** NCR chips allow burst lengths of 2, 4, 8, 16, 32, 64, 128
3320 ** transfers. 32,64,128 are only supported by 875 and 895 chips.
3321 ** We use log base 2 (burst length) as internal code, with
3322 ** value 0 meaning "burst disabled".
3323 **
3324 **===============================================================
3325 */
3326
3327 /*
3328 * Burst length from burst code.
3329 */
3330 #define burst_length(bc) (!(bc))? 0 : 1 << (bc)
3331
3332 /*
3333 * Burst code from io register bits.
3334 */
3335 #define burst_code(dmode, ctest4, ctest5) \
3336 (ctest4) & 0x80? 0 : (((dmode) & 0xc0) >> 6) + ((ctest5) & 0x04) + 1
3337
3338 /*
3339 * Set initial io register bits from burst code.
3340 */
3341 static void
3342 ncr_init_burst(ncb_p np, u_char bc)
3343 {
3344 np->rv_ctest4 &= ~0x80;
3345 np->rv_dmode &= ~(0x3 << 6);
3346 np->rv_ctest5 &= ~0x4;
3347
3348 if (!bc) {
3349 np->rv_ctest4 |= 0x80;
3350 }
3351 else {
3352 --bc;
3353 np->rv_dmode |= ((bc & 0x3) << 6);
3354 np->rv_ctest5 |= (bc & 0x4);
3355 }
3356 }
3357
3358 /*==========================================================
3359 **
3360 **
3361 ** Auto configuration: attach and init a host adapter.
3362 **
3363 **
3364 **==========================================================
3365 */
3366
3367
3368 static int
3369 ncr_attach (device_t dev)
3370 {
3371 ncb_p np = (struct ncb*) device_get_softc(dev);
3372 u_char rev = 0;
3373 u_long period;
3374 int i, rid;
3375 u_int8_t usrsync;
3376 u_int8_t usrwide;
3377 struct cam_devq *devq;
3378
3379 /*
3380 ** allocate and initialize structures.
3381 */
3382
3383 np->unit = device_get_unit(dev);
3384
3385 /*
3386 ** Try to map the controller chip to
3387 ** virtual and physical memory.
3388 */
3389
3390 np->reg_rid = 0x14;
3391 np->reg_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &np->reg_rid,
3392 0, ~0, 1, RF_ACTIVE);
3393 if (!np->reg_res) {
3394 device_printf(dev, "could not map memory\n");
3395 return ENXIO;
3396 }
3397
3398 /*
3399 ** Make the controller's registers available.
3400 ** Now the INB INW INL OUTB OUTW OUTL macros
3401 ** can be used safely.
3402 */
3403
3404 np->bst = rman_get_bustag(np->reg_res);
3405 np->bsh = rman_get_bushandle(np->reg_res);
3406
3407
3408 #ifdef NCR_IOMAPPED
3409 /*
3410 ** Try to map the controller chip into iospace.
3411 */
3412
3413 if (!pci_map_port (config_id, 0x10, &np->port))
3414 return;
3415 #endif
3416
3417
3418 /*
3419 ** Save some controller register default values
3420 */
3421
3422 np->rv_scntl3 = INB(nc_scntl3) & 0x77;
3423 np->rv_dmode = INB(nc_dmode) & 0xce;
3424 np->rv_dcntl = INB(nc_dcntl) & 0xa9;
3425 np->rv_ctest3 = INB(nc_ctest3) & 0x01;
3426 np->rv_ctest4 = INB(nc_ctest4) & 0x88;
3427 np->rv_ctest5 = INB(nc_ctest5) & 0x24;
3428 np->rv_gpcntl = INB(nc_gpcntl);
3429 np->rv_stest2 = INB(nc_stest2) & 0x20;
3430
3431 if (bootverbose >= 2) {
3432 printf ("\tBIOS values: SCNTL3:%02x DMODE:%02x DCNTL:%02x\n",
3433 np->rv_scntl3, np->rv_dmode, np->rv_dcntl);
3434 printf ("\t CTEST3:%02x CTEST4:%02x CTEST5:%02x\n",
3435 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5);
3436 }
3437
3438 np->rv_dcntl |= NOCOM;
3439
3440 /*
3441 ** Do chip dependent initialization.
3442 */
3443
3444 rev = pci_get_revid(dev);
3445
3446 /*
3447 ** Get chip features from chips table.
3448 */
3449 i = ncr_chip_lookup(pci_get_devid(dev), rev);
3450
3451 if (i >= 0) {
3452 np->maxburst = ncr_chip_table[i].maxburst;
3453 np->maxoffs = ncr_chip_table[i].maxoffs;
3454 np->clock_divn = ncr_chip_table[i].clock_divn;
3455 np->features = ncr_chip_table[i].features;
3456 } else { /* Should'nt happen if probe() is ok */
3457 np->maxburst = 4;
3458 np->maxoffs = 8;
3459 np->clock_divn = 4;
3460 np->features = FE_ERL;
3461 }
3462
3463 np->maxwide = np->features & FE_WIDE ? 1 : 0;
3464 np->clock_khz = np->features & FE_CLK80 ? 80000 : 40000;
3465 if (np->features & FE_QUAD) np->multiplier = 4;
3466 else if (np->features & FE_DBLR) np->multiplier = 2;
3467 else np->multiplier = 1;
3468
3469 /*
3470 ** Get the frequency of the chip's clock.
3471 ** Find the right value for scntl3.
3472 */
3473 if (np->features & (FE_ULTRA|FE_ULTRA2))
3474 ncr_getclock(np, np->multiplier);
3475
3476 #ifdef NCR_TEKRAM_EEPROM
3477 if (bootverbose) {
3478 printf ("%s: Tekram EEPROM read %s\n",
3479 ncr_name(np),
3480 read_tekram_eeprom (np, NULL) ?
3481 "succeeded" : "failed");
3482 }
3483 #endif /* NCR_TEKRAM_EEPROM */
3484
3485 /*
3486 * If scntl3 != 0, we assume BIOS is present.
3487 */
3488 if (np->rv_scntl3)
3489 np->features |= FE_BIOS;
3490
3491 /*
3492 * Divisor to be used for async (timer pre-scaler).
3493 */
3494 i = np->clock_divn - 1;
3495 while (i >= 0) {
3496 --i;
3497 if (10ul * SCSI_NCR_MIN_ASYNC * np->clock_khz > div_10M[i]) {
3498 ++i;
3499 break;
3500 }
3501 }
3502 np->rv_scntl3 = i+1;
3503
3504 /*
3505 * Minimum synchronous period factor supported by the chip.
3506 * Btw, 'period' is in tenths of nanoseconds.
3507 */
3508
3509 period = (4 * div_10M[0] + np->clock_khz - 1) / np->clock_khz;
3510 if (period <= 250) np->minsync = 10;
3511 else if (period <= 303) np->minsync = 11;
3512 else if (period <= 500) np->minsync = 12;
3513 else np->minsync = (period + 40 - 1) / 40;
3514
3515 /*
3516 * Check against chip SCSI standard support (SCSI-2,ULTRA,ULTRA2).
3517 */
3518
3519 if (np->minsync < 25 && !(np->features & (FE_ULTRA|FE_ULTRA2)))
3520 np->minsync = 25;
3521 else if (np->minsync < 12 && !(np->features & FE_ULTRA2))
3522 np->minsync = 12;
3523
3524 /*
3525 * Maximum synchronous period factor supported by the chip.
3526 */
3527
3528 period = (11 * div_10M[np->clock_divn - 1]) / (4 * np->clock_khz);
3529 np->maxsync = period > 2540 ? 254 : period / 10;
3530
3531 /*
3532 * Now, some features available with Symbios compatible boards.
3533 * LED support through GPIO0 and DIFF support.
3534 */
3535
3536 #ifdef SCSI_NCR_SYMBIOS_COMPAT
3537 if (!(np->rv_gpcntl & 0x01))
3538 np->features |= FE_LED0;
3539 #if 0 /* Not safe enough without NVRAM support or user settable option */
3540 if (!(INB(nc_gpreg) & 0x08))
3541 np->features |= FE_DIFF;
3542 #endif
3543 #endif /* SCSI_NCR_SYMBIOS_COMPAT */
3544
3545 /*
3546 * Prepare initial IO registers settings.
3547 * Trust BIOS only if we believe we have one and if we want to.
3548 */
3549 #ifdef SCSI_NCR_TRUST_BIOS
3550 if (!(np->features & FE_BIOS)) {
3551 #else
3552 if (1) {
3553 #endif
3554 np->rv_dmode = 0;
3555 np->rv_dcntl = NOCOM;
3556 np->rv_ctest3 = 0;
3557 np->rv_ctest4 = MPEE;
3558 np->rv_ctest5 = 0;
3559 np->rv_stest2 = 0;
3560
3561 if (np->features & FE_ERL)
3562 np->rv_dmode |= ERL; /* Enable Read Line */
3563 if (np->features & FE_BOF)
3564 np->rv_dmode |= BOF; /* Burst Opcode Fetch */
3565 if (np->features & FE_ERMP)
3566 np->rv_dmode |= ERMP; /* Enable Read Multiple */
3567 if (np->features & FE_CLSE)
3568 np->rv_dcntl |= CLSE; /* Cache Line Size Enable */
3569 if (np->features & FE_WRIE)
3570 np->rv_ctest3 |= WRIE; /* Write and Invalidate */
3571 if (np->features & FE_PFEN)
3572 np->rv_dcntl |= PFEN; /* Prefetch Enable */
3573 if (np->features & FE_DFS)
3574 np->rv_ctest5 |= DFS; /* Dma Fifo Size */
3575 if (np->features & FE_DIFF)
3576 np->rv_stest2 |= 0x20; /* Differential mode */
3577 ncr_init_burst(np, np->maxburst); /* Max dwords burst length */
3578 } else {
3579 np->maxburst =
3580 burst_code(np->rv_dmode, np->rv_ctest4, np->rv_ctest5);
3581 }
3582
3583 /*
3584 ** Get on-chip SRAM address, if supported
3585 */
3586 if ((np->features & FE_RAM) && sizeof(struct script) <= 4096) {
3587 np->sram_rid = 0x18;
3588 np->sram_res = bus_alloc_resource(dev, SYS_RES_MEMORY,
3589 &np->sram_rid,
3590 0, ~0, 1, RF_ACTIVE);
3591 }
3592
3593 /*
3594 ** Allocate structure for script relocation.
3595 */
3596 if (np->sram_res != NULL) {
3597 np->script = NULL;
3598 np->p_script = rman_get_start(np->sram_res);
3599 np->bst2 = rman_get_bustag(np->sram_res);
3600 np->bsh2 = rman_get_bushandle(np->sram_res);
3601 } else if (sizeof (struct script) > PAGE_SIZE) {
3602 np->script = (struct script*) vm_page_alloc_contig
3603 (round_page(sizeof (struct script)),
3604 0, 0xffffffff, PAGE_SIZE);
3605 } else {
3606 np->script = (struct script *)
3607 malloc (sizeof (struct script), M_DEVBUF, M_WAITOK);
3608 }
3609
3610 /* XXX JGibbs - Use contigmalloc */
3611 if (sizeof (struct scripth) > PAGE_SIZE) {
3612 np->scripth = (struct scripth*) vm_page_alloc_contig
3613 (round_page(sizeof (struct scripth)),
3614 0, 0xffffffff, PAGE_SIZE);
3615 } else
3616 {
3617 np->scripth = (struct scripth *)
3618 malloc (sizeof (struct scripth), M_DEVBUF, M_WAITOK);
3619 }
3620
3621 #ifdef SCSI_NCR_PCI_CONFIG_FIXUP
3622 /*
3623 ** If cache line size is enabled, check PCI config space and
3624 ** try to fix it up if necessary.
3625 */
3626 #ifdef PCIR_CACHELNSZ /* To be sure that new PCI stuff is present */
3627 {
3628 u_char cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3629 u_short command = pci_read_config(dev, PCIR_COMMAND, 2);
3630
3631 if (!cachelnsz) {
3632 cachelnsz = 8;
3633 printf("%s: setting PCI cache line size register to %d.\n",
3634 ncr_name(np), (int)cachelnsz);
3635 pci_write_config(dev, PCIR_CACHELNSZ, cachelnsz, 1);
3636 }
3637
3638 if (!(command & (1<<4))) {
3639 command |= (1<<4);
3640 printf("%s: setting PCI command write and invalidate.\n",
3641 ncr_name(np));
3642 pci_write_config(dev, PCIR_COMMAND, command, 2);
3643 }
3644 }
3645 #endif /* PCIR_CACHELNSZ */
3646
3647 #endif /* SCSI_NCR_PCI_CONFIG_FIXUP */
3648
3649 /* Initialize per-target user settings */
3650 usrsync = 0;
3651 if (SCSI_NCR_DFLT_SYNC) {
3652 usrsync = SCSI_NCR_DFLT_SYNC;
3653 if (usrsync > np->maxsync)
3654 usrsync = np->maxsync;
3655 if (usrsync < np->minsync)
3656 usrsync = np->minsync;
3657 };
3658
3659 usrwide = (SCSI_NCR_MAX_WIDE);
3660 if (usrwide > np->maxwide) usrwide=np->maxwide;
3661
3662 for (i=0;i<MAX_TARGET;i++) {
3663 tcb_p tp = &np->target[i];
3664
3665 tp->tinfo.user.period = usrsync;
3666 tp->tinfo.user.offset = usrsync != 0 ? np->maxoffs : 0;
3667 tp->tinfo.user.width = usrwide;
3668 tp->tinfo.disc_tag = NCR_CUR_DISCENB
3669 | NCR_CUR_TAGENB
3670 | NCR_USR_DISCENB
3671 | NCR_USR_TAGENB;
3672 }
3673
3674 /*
3675 ** Bells and whistles ;-)
3676 */
3677 if (bootverbose)
3678 printf("%s: minsync=%d, maxsync=%d, maxoffs=%d, %d dwords burst, %s dma fifo\n",
3679 ncr_name(np), np->minsync, np->maxsync, np->maxoffs,
3680 burst_length(np->maxburst),
3681 (np->rv_ctest5 & DFS) ? "large" : "normal");
3682
3683 /*
3684 ** Print some complementary information that can be helpfull.
3685 */
3686 if (bootverbose)
3687 printf("%s: %s, %s IRQ driver%s\n",
3688 ncr_name(np),
3689 np->rv_stest2 & 0x20 ? "differential" : "single-ended",
3690 np->rv_dcntl & IRQM ? "totem pole" : "open drain",
3691 np->sram_res ? ", using on-chip SRAM" : "");
3692
3693 /*
3694 ** Patch scripts to physical addresses
3695 */
3696 ncr_script_fill (&script0, &scripth0);
3697
3698 if (np->script)
3699 np->p_script = vtophys(np->script);
3700 np->p_scripth = vtophys(np->scripth);
3701
3702 ncr_script_copy_and_bind (np, (ncrcmd *) &script0,
3703 (ncrcmd *) np->script, sizeof(struct script));
3704
3705 ncr_script_copy_and_bind (np, (ncrcmd *) &scripth0,
3706 (ncrcmd *) np->scripth, sizeof(struct scripth));
3707
3708 /*
3709 ** Patch the script for LED support.
3710 */
3711
3712 if (np->features & FE_LED0) {
3713 WRITESCRIPT(reselect[0], SCR_REG_REG(gpreg, SCR_OR, 0x01));
3714 WRITESCRIPT(reselect1[0], SCR_REG_REG(gpreg, SCR_AND, 0xfe));
3715 WRITESCRIPT(reselect2[0], SCR_REG_REG(gpreg, SCR_AND, 0xfe));
3716 }
3717
3718 /*
3719 ** init data structure
3720 */
3721
3722 np->jump_tcb.l_cmd = SCR_JUMP;
3723 np->jump_tcb.l_paddr = NCB_SCRIPTH_PHYS (np, abort);
3724
3725 /*
3726 ** Get SCSI addr of host adapter (set by bios?).
3727 */
3728
3729 np->myaddr = INB(nc_scid) & 0x07;
3730 if (!np->myaddr) np->myaddr = SCSI_NCR_MYADDR;
3731
3732 #ifdef NCR_DUMP_REG
3733 /*
3734 ** Log the initial register contents
3735 */
3736 {
3737 int reg;
3738 for (reg=0; reg<256; reg+=4) {
3739 if (reg%16==0) printf ("reg[%2x]", reg);
3740 printf (" %08x", (int)pci_conf_read (config_id, reg));
3741 if (reg%16==12) printf ("\n");
3742 }
3743 }
3744 #endif /* NCR_DUMP_REG */
3745
3746 /*
3747 ** Reset chip.
3748 */
3749
3750 OUTB (nc_istat, SRST);
3751 DELAY (1000);
3752 OUTB (nc_istat, 0 );
3753
3754
3755 /*
3756 ** Now check the cache handling of the pci chipset.
3757 */
3758
3759 if (ncr_snooptest (np)) {
3760 printf ("CACHE INCORRECTLY CONFIGURED.\n");
3761 return EINVAL;
3762 };
3763
3764 /*
3765 ** Install the interrupt handler.
3766 */
3767
3768 rid = 0;
3769 np->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
3770 RF_SHAREABLE | RF_ACTIVE);
3771 if (np->irq_res == NULL) {
3772 device_printf(dev,
3773 "interruptless mode: reduced performance.\n");
3774 } else {
3775 bus_setup_intr(dev, np->irq_res, INTR_TYPE_CAM,
3776 ncr_intr, np, &np->irq_handle);
3777 }
3778
3779 /*
3780 ** Create the device queue. We only allow MAX_START-1 concurrent
3781 ** transactions so we can be sure to have one element free in our
3782 ** start queue to reset to the idle loop.
3783 */
3784 devq = cam_simq_alloc(MAX_START - 1);
3785 if (devq == NULL)
3786 return ENOMEM;
3787
3788 /*
3789 ** Now tell the generic SCSI layer
3790 ** about our bus.
3791 */
3792 np->sim = cam_sim_alloc(ncr_action, ncr_poll, "ncr", np, np->unit,
3793 1, MAX_TAGS, devq);
3794 if (np->sim == NULL) {
3795 cam_simq_free(devq);
3796 return ENOMEM;
3797 }
3798
3799
3800 if (xpt_bus_register(np->sim, 0) != CAM_SUCCESS) {
3801 cam_sim_free(np->sim, /*free_devq*/ TRUE);
3802 return ENOMEM;
3803 }
3804
3805 if (xpt_create_path(&np->path, /*periph*/NULL,
3806 cam_sim_path(np->sim), CAM_TARGET_WILDCARD,
3807 CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
3808 xpt_bus_deregister(cam_sim_path(np->sim));
3809 cam_sim_free(np->sim, /*free_devq*/TRUE);
3810 return ENOMEM;
3811 }
3812
3813 /*
3814 ** start the timeout daemon
3815 */
3816 ncr_timeout (np);
3817 np->lasttime=0;
3818
3819 return 0;
3820 }
3821
3822 /*==========================================================
3823 **
3824 **
3825 ** Process pending device interrupts.
3826 **
3827 **
3828 **==========================================================
3829 */
3830
3831 static void
3832 ncr_intr(vnp)
3833 void *vnp;
3834 {
3835 ncb_p np = vnp;
3836 int oldspl = splcam();
3837
3838 if (DEBUG_FLAGS & DEBUG_TINY) printf ("[");
3839
3840 if (INB(nc_istat) & (INTF|SIP|DIP)) {
3841 /*
3842 ** Repeat until no outstanding ints
3843 */
3844 do {
3845 ncr_exception (np);
3846 } while (INB(nc_istat) & (INTF|SIP|DIP));
3847
3848 np->ticks = 100;
3849 };
3850
3851 if (DEBUG_FLAGS & DEBUG_TINY) printf ("]\n");
3852
3853 splx (oldspl);
3854 }
3855
3856 /*==========================================================
3857 **
3858 **
3859 ** Start execution of a SCSI command.
3860 ** This is called from the generic SCSI driver.
3861 **
3862 **
3863 **==========================================================
3864 */
3865
3866 static void
3867 ncr_action (struct cam_sim *sim, union ccb *ccb)
3868 {
3869 ncb_p np;
3870
3871 np = (ncb_p) cam_sim_softc(sim);
3872
3873 switch (ccb->ccb_h.func_code) {
3874 /* Common cases first */
3875 case XPT_SCSI_IO: /* Execute the requested I/O operation */
3876 {
3877 nccb_p cp;
3878 lcb_p lp;
3879 tcb_p tp;
3880 int oldspl;
3881 struct ccb_scsiio *csio;
3882 u_int8_t *msgptr;
3883 u_int msglen;
3884 u_int msglen2;
3885 int segments;
3886 u_int8_t nego;
3887 u_int8_t idmsg;
3888 u_int8_t qidx;
3889
3890 tp = &np->target[ccb->ccb_h.target_id];
3891 csio = &ccb->csio;
3892
3893 oldspl = splcam();
3894
3895 /*
3896 * Last time we need to check if this CCB needs to
3897 * be aborted.
3898 */
3899 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) {
3900 xpt_done(ccb);
3901 splx(oldspl);
3902 return;
3903 }
3904 ccb->ccb_h.status |= CAM_SIM_QUEUED;
3905
3906 /*---------------------------------------------------
3907 **
3908 ** Assign an nccb / bind ccb
3909 **
3910 **----------------------------------------------------
3911 */
3912 cp = ncr_get_nccb (np, ccb->ccb_h.target_id,
3913 ccb->ccb_h.target_lun);
3914 if (cp == NULL) {
3915 /* XXX JGibbs - Freeze SIMQ */
3916 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
3917 xpt_done(ccb);
3918 return;
3919 };
3920
3921 cp->ccb = ccb;
3922
3923 /*---------------------------------------------------
3924 **
3925 ** timestamp
3926 **
3927 **----------------------------------------------------
3928 */
3929 /*
3930 ** XXX JGibbs - Isn't this expensive
3931 ** enough to be conditionalized??
3932 */
3933
3934 bzero (&cp->phys.header.stamp, sizeof (struct tstamp));
3935 cp->phys.header.stamp.start = ticks;
3936
3937 nego = 0;
3938 if (tp->nego_cp == NULL) {
3939
3940 if (tp->tinfo.current.width
3941 != tp->tinfo.goal.width) {
3942 tp->nego_cp = cp;
3943 nego = NS_WIDE;
3944 } else if ((tp->tinfo.current.period
3945 != tp->tinfo.goal.period)
3946 || (tp->tinfo.current.offset
3947 != tp->tinfo.goal.offset)) {
3948 tp->nego_cp = cp;
3949 nego = NS_SYNC;
3950 };
3951 };
3952
3953 /*---------------------------------------------------
3954 **
3955 ** choose a new tag ...
3956 **
3957 **----------------------------------------------------
3958 */
3959 lp = tp->lp[ccb->ccb_h.target_lun];
3960
3961 if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0
3962 && (ccb->csio.tag_action != CAM_TAG_ACTION_NONE)
3963 && (nego == 0)) {
3964 /*
3965 ** assign a tag to this nccb
3966 */
3967 while (!cp->tag) {
3968 nccb_p cp2 = lp->next_nccb;
3969 lp->lasttag = lp->lasttag % 255 + 1;
3970 while (cp2 && cp2->tag != lp->lasttag)
3971 cp2 = cp2->next_nccb;
3972 if (cp2) continue;
3973 cp->tag=lp->lasttag;
3974 if (DEBUG_FLAGS & DEBUG_TAGS) {
3975 PRINT_ADDR(ccb);
3976 printf ("using tag #%d.\n", cp->tag);
3977 };
3978 };
3979 } else {
3980 cp->tag=0;
3981 };
3982
3983 /*----------------------------------------------------
3984 **
3985 ** Build the identify / tag / sdtr message
3986 **
3987 **----------------------------------------------------
3988 */
3989 idmsg = MSG_IDENTIFYFLAG | ccb->ccb_h.target_lun;
3990 if (tp->tinfo.disc_tag & NCR_CUR_DISCENB)
3991 idmsg |= MSG_IDENTIFY_DISCFLAG;
3992
3993 msgptr = cp->scsi_smsg;
3994 msglen = 0;
3995 msgptr[msglen++] = idmsg;
3996
3997 if (cp->tag) {
3998 msgptr[msglen++] = ccb->csio.tag_action;
3999 msgptr[msglen++] = cp->tag;
4000 }
4001
4002 switch (nego) {
4003 case NS_SYNC:
4004 msgptr[msglen++] = MSG_EXTENDED;
4005 msgptr[msglen++] = MSG_EXT_SDTR_LEN;
4006 msgptr[msglen++] = MSG_EXT_SDTR;
4007 msgptr[msglen++] = tp->tinfo.goal.period;
4008 msgptr[msglen++] = tp->tinfo.goal.offset;;
4009 if (DEBUG_FLAGS & DEBUG_NEGO) {
4010 PRINT_ADDR(ccb);
4011 printf ("sync msgout: ");
4012 ncr_show_msg (&cp->scsi_smsg [msglen-5]);
4013 printf (".\n");
4014 };
4015 break;
4016 case NS_WIDE:
4017 msgptr[msglen++] = MSG_EXTENDED;
4018 msgptr[msglen++] = MSG_EXT_WDTR_LEN;
4019 msgptr[msglen++] = MSG_EXT_WDTR;
4020 msgptr[msglen++] = tp->tinfo.goal.width;
4021 if (DEBUG_FLAGS & DEBUG_NEGO) {
4022 PRINT_ADDR(ccb);
4023 printf ("wide msgout: ");
4024 ncr_show_msg (&cp->scsi_smsg [msglen-4]);
4025 printf (".\n");
4026 };
4027 break;
4028 };
4029
4030 /*----------------------------------------------------
4031 **
4032 ** Build the identify message for getcc.
4033 **
4034 **----------------------------------------------------
4035 */
4036
4037 cp->scsi_smsg2 [0] = idmsg;
4038 msglen2 = 1;
4039
4040 /*----------------------------------------------------
4041 **
4042 ** Build the data descriptors
4043 **
4044 **----------------------------------------------------
4045 */
4046
4047 /* XXX JGibbs - Handle other types of I/O */
4048 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
4049 segments = ncr_scatter(&cp->phys,
4050 (vm_offset_t)csio->data_ptr,
4051 (vm_size_t)csio->dxfer_len);
4052
4053 if (segments < 0) {
4054 ccb->ccb_h.status = CAM_REQ_TOO_BIG;
4055 ncr_free_nccb(np, cp);
4056 splx(oldspl);
4057 xpt_done(ccb);
4058 return;
4059 }
4060 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
4061 cp->phys.header.savep = NCB_SCRIPT_PHYS (np, data_in);
4062 cp->phys.header.goalp = cp->phys.header.savep +20 +segments*16;
4063 } else { /* CAM_DIR_OUT */
4064 cp->phys.header.savep = NCB_SCRIPT_PHYS (np, data_out);
4065 cp->phys.header.goalp = cp->phys.header.savep +20 +segments*16;
4066 }
4067 } else {
4068 cp->phys.header.savep = NCB_SCRIPT_PHYS (np, no_data);
4069 cp->phys.header.goalp = cp->phys.header.savep;
4070 }
4071
4072 cp->phys.header.lastp = cp->phys.header.savep;
4073
4074
4075 /*----------------------------------------------------
4076 **
4077 ** fill in nccb
4078 **
4079 **----------------------------------------------------
4080 **
4081 **
4082 ** physical -> virtual backlink
4083 ** Generic SCSI command
4084 */
4085 cp->phys.header.cp = cp;
4086 /*
4087 ** Startqueue
4088 */
4089 cp->phys.header.launch.l_paddr = NCB_SCRIPT_PHYS (np, select);
4090 cp->phys.header.launch.l_cmd = SCR_JUMP;
4091 /*
4092 ** select
4093 */
4094 cp->phys.select.sel_id = ccb->ccb_h.target_id;
4095 cp->phys.select.sel_scntl3 = tp->tinfo.wval;
4096 cp->phys.select.sel_sxfer = tp->tinfo.sval;
4097 /*
4098 ** message
4099 */
4100 cp->phys.smsg.addr = CCB_PHYS (cp, scsi_smsg);
4101 cp->phys.smsg.size = msglen;
4102
4103 cp->phys.smsg2.addr = CCB_PHYS (cp, scsi_smsg2);
4104 cp->phys.smsg2.size = msglen2;
4105 /*
4106 ** command
4107 */
4108 /* XXX JGibbs - Support other command types */
4109 cp->phys.cmd.addr = vtophys (csio->cdb_io.cdb_bytes);
4110 cp->phys.cmd.size = csio->cdb_len;
4111 /*
4112 ** sense command
4113 */
4114 cp->phys.scmd.addr = CCB_PHYS (cp, sensecmd);
4115 cp->phys.scmd.size = 6;
4116 /*
4117 ** patch requested size into sense command
4118 */
4119 cp->sensecmd[0] = 0x03;
4120 cp->sensecmd[1] = ccb->ccb_h.target_lun << 5;
4121 cp->sensecmd[4] = sizeof(struct scsi_sense_data);
4122 cp->sensecmd[4] = csio->sense_len;
4123 /*
4124 ** sense data
4125 */
4126 cp->phys.sense.addr = vtophys (&csio->sense_data);
4127 cp->phys.sense.size = csio->sense_len;
4128 /*
4129 ** status
4130 */
4131 cp->actualquirks = QUIRK_NOMSG;
4132 cp->host_status = nego ? HS_NEGOTIATE : HS_BUSY;
4133 cp->s_status = SCSI_STATUS_ILLEGAL;
4134 cp->parity_status = 0;
4135
4136 cp->xerr_status = XE_OK;
4137 cp->sync_status = tp->tinfo.sval;
4138 cp->nego_status = nego;
4139 cp->wide_status = tp->tinfo.wval;
4140
4141 /*----------------------------------------------------
4142 **
4143 ** Critical region: start this job.
4144 **
4145 **----------------------------------------------------
4146 */
4147
4148 /*
4149 ** reselect pattern and activate this job.
4150 */
4151
4152 cp->jump_nccb.l_cmd = (SCR_JUMP ^ IFFALSE (DATA (cp->tag)));
4153 cp->tlimit = time_second
4154 + ccb->ccb_h.timeout / 1000 + 2;
4155 cp->magic = CCB_MAGIC;
4156
4157 /*
4158 ** insert into start queue.
4159 */
4160
4161 qidx = np->squeueput + 1;
4162 if (qidx >= MAX_START) qidx=0;
4163 np->squeue [qidx ] = NCB_SCRIPT_PHYS (np, idle);
4164 np->squeue [np->squeueput] = CCB_PHYS (cp, phys);
4165 np->squeueput = qidx;
4166
4167 if(DEBUG_FLAGS & DEBUG_QUEUE)
4168 printf("%s: queuepos=%d tryoffset=%d.\n",
4169 ncr_name (np), np->squeueput,
4170 (unsigned)(READSCRIPT(startpos[0]) -
4171 (NCB_SCRIPTH_PHYS (np, tryloop))));
4172
4173 /*
4174 ** Script processor may be waiting for reselect.
4175 ** Wake it up.
4176 */
4177 OUTB (nc_istat, SIGP);
4178
4179 /*
4180 ** and reenable interrupts
4181 */
4182 splx (oldspl);
4183 break;
4184 }
4185 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
4186 case XPT_EN_LUN: /* Enable LUN as a target */
4187 case XPT_TARGET_IO: /* Execute target I/O request */
4188 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
4189 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/
4190 case XPT_ABORT: /* Abort the specified CCB */
4191 /* XXX Implement */
4192 ccb->ccb_h.status = CAM_REQ_INVALID;
4193 xpt_done(ccb);
4194 break;
4195 case XPT_SET_TRAN_SETTINGS:
4196 {
4197 struct ccb_trans_settings *cts;
4198 tcb_p tp;
4199 u_int update_type;
4200 int s;
4201
4202 cts = &ccb->cts;
4203 update_type = 0;
4204 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0)
4205 update_type |= NCR_TRANS_GOAL;
4206 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0)
4207 update_type |= NCR_TRANS_USER;
4208
4209 s = splcam();
4210 tp = &np->target[ccb->ccb_h.target_id];
4211 /* Tag and disc enables */
4212 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) {
4213 if (update_type & NCR_TRANS_GOAL) {
4214 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0)
4215 tp->tinfo.disc_tag |= NCR_CUR_DISCENB;
4216 else
4217 tp->tinfo.disc_tag &= ~NCR_CUR_DISCENB;
4218 }
4219
4220 if (update_type & NCR_TRANS_USER) {
4221 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0)
4222 tp->tinfo.disc_tag |= NCR_USR_DISCENB;
4223 else
4224 tp->tinfo.disc_tag &= ~NCR_USR_DISCENB;
4225 }
4226
4227 }
4228
4229 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) {
4230 if (update_type & NCR_TRANS_GOAL) {
4231 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0)
4232 tp->tinfo.disc_tag |= NCR_CUR_TAGENB;
4233 else
4234 tp->tinfo.disc_tag &= ~NCR_CUR_TAGENB;
4235 }
4236
4237 if (update_type & NCR_TRANS_USER) {
4238 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0)
4239 tp->tinfo.disc_tag |= NCR_USR_TAGENB;
4240 else
4241 tp->tinfo.disc_tag &= ~NCR_USR_TAGENB;
4242 }
4243 }
4244
4245 /* Filter bus width and sync negotiation settings */
4246 if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0) {
4247 if (cts->bus_width > np->maxwide)
4248 cts->bus_width = np->maxwide;
4249 }
4250
4251 if (((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0)
4252 || ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)) {
4253 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) {
4254 if (cts->sync_period != 0
4255 && (cts->sync_period < np->minsync))
4256 cts->sync_period = np->minsync;
4257 }
4258 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0) {
4259 if (cts->sync_offset == 0)
4260 cts->sync_period = 0;
4261 if (cts->sync_offset > np->maxoffs)
4262 cts->sync_offset = np->maxoffs;
4263 }
4264 }
4265 if ((update_type & NCR_TRANS_USER) != 0) {
4266 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0)
4267 tp->tinfo.user.period = cts->sync_period;
4268 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)
4269 tp->tinfo.user.offset = cts->sync_offset;
4270 if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0)
4271 tp->tinfo.user.width = cts->bus_width;
4272 }
4273 if ((update_type & NCR_TRANS_GOAL) != 0) {
4274 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0)
4275 tp->tinfo.goal.period = cts->sync_period;
4276
4277 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)
4278 tp->tinfo.goal.offset = cts->sync_offset;
4279
4280 if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0)
4281 tp->tinfo.goal.width = cts->bus_width;
4282 }
4283 splx(s);
4284 ccb->ccb_h.status = CAM_REQ_CMP;
4285 xpt_done(ccb);
4286 break;
4287 }
4288 case XPT_GET_TRAN_SETTINGS:
4289 /* Get default/user set transfer settings for the target */
4290 {
4291 struct ccb_trans_settings *cts;
4292 struct ncr_transinfo *tinfo;
4293 tcb_p tp;
4294 int s;
4295
4296 cts = &ccb->cts;
4297 tp = &np->target[ccb->ccb_h.target_id];
4298
4299 s = splcam();
4300 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) {
4301 tinfo = &tp->tinfo.current;
4302 if (tp->tinfo.disc_tag & NCR_CUR_DISCENB)
4303 cts->flags |= CCB_TRANS_DISC_ENB;
4304 else
4305 cts->flags &= ~CCB_TRANS_DISC_ENB;
4306
4307 if (tp->tinfo.disc_tag & NCR_CUR_TAGENB)
4308 cts->flags |= CCB_TRANS_TAG_ENB;
4309 else
4310 cts->flags &= ~CCB_TRANS_TAG_ENB;
4311 } else {
4312 tinfo = &tp->tinfo.user;
4313 if (tp->tinfo.disc_tag & NCR_USR_DISCENB)
4314 cts->flags |= CCB_TRANS_DISC_ENB;
4315 else
4316 cts->flags &= ~CCB_TRANS_DISC_ENB;
4317
4318 if (tp->tinfo.disc_tag & NCR_USR_TAGENB)
4319 cts->flags |= CCB_TRANS_TAG_ENB;
4320 else
4321 cts->flags &= ~CCB_TRANS_TAG_ENB;
4322 }
4323
4324 cts->sync_period = tinfo->period;
4325 cts->sync_offset = tinfo->offset;
4326 cts->bus_width = tinfo->width;
4327
4328 splx(s);
4329
4330 cts->valid = CCB_TRANS_SYNC_RATE_VALID
4331 | CCB_TRANS_SYNC_OFFSET_VALID
4332 | CCB_TRANS_BUS_WIDTH_VALID
4333 | CCB_TRANS_DISC_VALID
4334 | CCB_TRANS_TQ_VALID;
4335
4336 ccb->ccb_h.status = CAM_REQ_CMP;
4337 xpt_done(ccb);
4338 break;
4339 }
4340 case XPT_CALC_GEOMETRY:
4341 {
4342 struct ccb_calc_geometry *ccg;
4343 u_int32_t size_mb;
4344 u_int32_t secs_per_cylinder;
4345 int extended;
4346
4347 /* XXX JGibbs - I'm sure the NCR uses a different strategy,
4348 * but it should be able to deal with Adaptec
4349 * geometry too.
4350 */
4351 extended = 1;
4352 ccg = &ccb->ccg;
4353 size_mb = ccg->volume_size
4354 / ((1024L * 1024L) / ccg->block_size);
4355
4356 if (size_mb > 1024 && extended) {
4357 ccg->heads = 255;
4358 ccg->secs_per_track = 63;
4359 } else {
4360 ccg->heads = 64;
4361 ccg->secs_per_track = 32;
4362 }
4363 secs_per_cylinder = ccg->heads * ccg->secs_per_track;
4364 ccg->cylinders = ccg->volume_size / secs_per_cylinder;
4365 ccb->ccb_h.status = CAM_REQ_CMP;
4366 xpt_done(ccb);
4367 break;
4368 }
4369 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
4370 {
4371 OUTB (nc_scntl1, CRST);
4372 ccb->ccb_h.status = CAM_REQ_CMP;
4373 DELAY(10000); /* Wait until our interrupt handler sees it */
4374 xpt_done(ccb);
4375 break;
4376 }
4377 case XPT_TERM_IO: /* Terminate the I/O process */
4378 /* XXX Implement */
4379 ccb->ccb_h.status = CAM_REQ_INVALID;
4380 xpt_done(ccb);
4381 break;
4382 case XPT_PATH_INQ: /* Path routing inquiry */
4383 {
4384 struct ccb_pathinq *cpi = &ccb->cpi;
4385
4386 cpi->version_num = 1; /* XXX??? */
4387 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE;
4388 if ((np->features & FE_WIDE) != 0)
4389 cpi->hba_inquiry |= PI_WIDE_16;
4390 cpi->target_sprt = 0;
4391 cpi->hba_misc = 0;
4392 cpi->hba_eng_cnt = 0;
4393 cpi->max_target = (np->features & FE_WIDE) ? 15 : 7;
4394 cpi->max_lun = MAX_LUN - 1;
4395 cpi->initiator_id = np->myaddr;
4396 cpi->bus_id = cam_sim_bus(sim);
4397 cpi->base_transfer_speed = 3300;
4398 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
4399 strncpy(cpi->hba_vid, "Symbios", HBA_IDLEN);
4400 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
4401 cpi->unit_number = cam_sim_unit(sim);
4402 cpi->ccb_h.status = CAM_REQ_CMP;
4403 xpt_done(ccb);
4404 break;
4405 }
4406 default:
4407 ccb->ccb_h.status = CAM_REQ_INVALID;
4408 xpt_done(ccb);
4409 break;
4410 }
4411 }
4412
4413 /*==========================================================
4414 **
4415 **
4416 ** Complete execution of a SCSI command.
4417 ** Signal completion to the generic SCSI driver.
4418 **
4419 **
4420 **==========================================================
4421 */
4422
4423 void
4424 ncr_complete (ncb_p np, nccb_p cp)
4425 {
4426 union ccb *ccb;
4427 tcb_p tp;
4428 lcb_p lp;
4429
4430 /*
4431 ** Sanity check
4432 */
4433
4434 if (!cp || (cp->magic!=CCB_MAGIC) || !cp->ccb) return;
4435 cp->magic = 1;
4436 cp->tlimit= 0;
4437
4438 /*
4439 ** No Reselect anymore.
4440 */
4441 cp->jump_nccb.l_cmd = (SCR_JUMP);
4442
4443 /*
4444 ** No starting.
4445 */
4446 cp->phys.header.launch.l_paddr= NCB_SCRIPT_PHYS (np, idle);
4447
4448 /*
4449 ** timestamp
4450 */
4451 ncb_profile (np, cp);
4452
4453 if (DEBUG_FLAGS & DEBUG_TINY)
4454 printf ("CCB=%x STAT=%x/%x\n", (int)(intptr_t)cp & 0xfff,
4455 cp->host_status,cp->s_status);
4456
4457 ccb = cp->ccb;
4458 cp->ccb = NULL;
4459 tp = &np->target[ccb->ccb_h.target_id];
4460 lp = tp->lp[ccb->ccb_h.target_lun];
4461
4462 /*
4463 ** We do not queue more than 1 nccb per target
4464 ** with negotiation at any time. If this nccb was
4465 ** used for negotiation, clear this info in the tcb.
4466 */
4467
4468 if (cp == tp->nego_cp)
4469 tp->nego_cp = NULL;
4470
4471 /*
4472 ** Check for parity errors.
4473 */
4474 /* XXX JGibbs - What about reporting them??? */
4475
4476 if (cp->parity_status) {
4477 PRINT_ADDR(ccb);
4478 printf ("%d parity error(s), fallback.\n", cp->parity_status);
4479 /*
4480 ** fallback to asynch transfer.
4481 */
4482 tp->tinfo.goal.period = 0;
4483 tp->tinfo.goal.offset = 0;
4484 };
4485
4486 /*
4487 ** Check for extended errors.
4488 */
4489
4490 if (cp->xerr_status != XE_OK) {
4491 PRINT_ADDR(ccb);
4492 switch (cp->xerr_status) {
4493 case XE_EXTRA_DATA:
4494 printf ("extraneous data discarded.\n");
4495 break;
4496 case XE_BAD_PHASE:
4497 printf ("illegal scsi phase (4/5).\n");
4498 break;
4499 default:
4500 printf ("extended error %d.\n", cp->xerr_status);
4501 break;
4502 };
4503 if (cp->host_status==HS_COMPLETE)
4504 cp->host_status = HS_FAIL;
4505 };
4506
4507 /*
4508 ** Check the status.
4509 */
4510 if (cp->host_status == HS_COMPLETE) {
4511
4512 if (cp->s_status == SCSI_STATUS_OK) {
4513
4514 /*
4515 ** All went well.
4516 */
4517 /* XXX JGibbs - Properly calculate residual */
4518
4519 tp->bytes += ccb->csio.dxfer_len;
4520 tp->transfers ++;
4521
4522 ccb->ccb_h.status = CAM_REQ_CMP;
4523 } else if ((cp->s_status & SCSI_STATUS_SENSE) != 0) {
4524
4525 /*
4526 * XXX Could be TERMIO too. Should record
4527 * original status.
4528 */
4529 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
4530 cp->s_status &= ~SCSI_STATUS_SENSE;
4531 if (cp->s_status == SCSI_STATUS_OK) {
4532 ccb->ccb_h.status =
4533 CAM_AUTOSNS_VALID|CAM_SCSI_STATUS_ERROR;
4534 } else {
4535 ccb->ccb_h.status = CAM_AUTOSENSE_FAIL;
4536 }
4537 } else {
4538 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
4539 ccb->csio.scsi_status = cp->s_status;
4540 }
4541
4542
4543 } else if (cp->host_status == HS_SEL_TIMEOUT) {
4544
4545 /*
4546 ** Device failed selection
4547 */
4548 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
4549
4550 } else if (cp->host_status == HS_TIMEOUT) {
4551
4552 /*
4553 ** No response
4554 */
4555 ccb->ccb_h.status = CAM_CMD_TIMEOUT;
4556 } else if (cp->host_status == HS_STALL) {
4557 ccb->ccb_h.status = CAM_REQUEUE_REQ;
4558 } else {
4559
4560 /*
4561 ** Other protocol messes
4562 */
4563 PRINT_ADDR(ccb);
4564 printf ("COMMAND FAILED (%x %x) @%p.\n",
4565 cp->host_status, cp->s_status, cp);
4566
4567 ccb->ccb_h.status = CAM_CMD_TIMEOUT;
4568 }
4569
4570 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) {
4571 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
4572 ccb->ccb_h.status |= CAM_DEV_QFRZN;
4573 }
4574
4575 /*
4576 ** Free this nccb
4577 */
4578 ncr_free_nccb (np, cp);
4579
4580 /*
4581 ** signal completion to generic driver.
4582 */
4583 xpt_done (ccb);
4584 }
4585
4586 /*==========================================================
4587 **
4588 **
4589 ** Signal all (or one) control block done.
4590 **
4591 **
4592 **==========================================================
4593 */
4594
4595 void
4596 ncr_wakeup (ncb_p np, u_long code)
4597 {
4598 /*
4599 ** Starting at the default nccb and following
4600 ** the links, complete all jobs with a
4601 ** host_status greater than "disconnect".
4602 **
4603 ** If the "code" parameter is not zero,
4604 ** complete all jobs that are not IDLE.
4605 */
4606
4607 nccb_p cp = np->link_nccb;
4608 while (cp) {
4609 switch (cp->host_status) {
4610
4611 case HS_IDLE:
4612 break;
4613
4614 case HS_DISCONNECT:
4615 if(DEBUG_FLAGS & DEBUG_TINY) printf ("D");
4616 /* fall through */
4617
4618 case HS_BUSY:
4619 case HS_NEGOTIATE:
4620 if (!code) break;
4621 cp->host_status = code;
4622
4623 /* fall through */
4624
4625 default:
4626 ncr_complete (np, cp);
4627 break;
4628 };
4629 cp = cp -> link_nccb;
4630 };
4631 }
4632
4633 static void
4634 ncr_freeze_devq (ncb_p np, struct cam_path *path)
4635 {
4636 nccb_p cp;
4637 int i;
4638 int count;
4639 int firstskip;
4640 /*
4641 ** Starting at the first nccb and following
4642 ** the links, complete all jobs that match
4643 ** the passed in path and are in the start queue.
4644 */
4645
4646 cp = np->link_nccb;
4647 count = 0;
4648 firstskip = 0;
4649 while (cp) {
4650 switch (cp->host_status) {
4651
4652 case HS_BUSY:
4653 case HS_NEGOTIATE:
4654 if ((cp->phys.header.launch.l_paddr
4655 == NCB_SCRIPT_PHYS (np, select))
4656 && (xpt_path_comp(path, cp->ccb->ccb_h.path) >= 0)) {
4657
4658 /* Mark for removal from the start queue */
4659 for (i = 1; i < MAX_START; i++) {
4660 int idx;
4661
4662 idx = np->squeueput - i;
4663
4664 if (idx < 0)
4665 idx = MAX_START + idx;
4666 if (np->squeue[idx]
4667 == CCB_PHYS(cp, phys)) {
4668 np->squeue[idx] =
4669 NCB_SCRIPT_PHYS (np, skip);
4670 if (i > firstskip)
4671 firstskip = i;
4672 break;
4673 }
4674 }
4675 cp->host_status=HS_STALL;
4676 ncr_complete (np, cp);
4677 count++;
4678 }
4679 break;
4680 default:
4681 break;
4682 }
4683 cp = cp->link_nccb;
4684 }
4685
4686 if (count > 0) {
4687 int j;
4688 int bidx;
4689
4690 /* Compress the start queue */
4691 j = 0;
4692 bidx = np->squeueput;
4693 i = np->squeueput - firstskip;
4694 if (i < 0)
4695 i = MAX_START + i;
4696 for (;;) {
4697
4698 bidx = i - j;
4699 if (bidx < 0)
4700 bidx = MAX_START + bidx;
4701
4702 if (np->squeue[i] == NCB_SCRIPT_PHYS (np, skip)) {
4703 j++;
4704 } else if (j != 0) {
4705 np->squeue[bidx] = np->squeue[i];
4706 if (np->squeue[bidx]
4707 == NCB_SCRIPT_PHYS(np, idle))
4708 break;
4709 }
4710 i = (i + 1) % MAX_START;
4711 }
4712 np->squeueput = bidx;
4713 }
4714 }
4715
4716 /*==========================================================
4717 **
4718 **
4719 ** Start NCR chip.
4720 **
4721 **
4722 **==========================================================
4723 */
4724
4725 void
4726 ncr_init(ncb_p np, char * msg, u_long code)
4727 {
4728 int i;
4729
4730 /*
4731 ** Reset chip.
4732 */
4733
4734 OUTB (nc_istat, SRST);
4735 DELAY (1000);
4736 OUTB (nc_istat, 0);
4737
4738 /*
4739 ** Message.
4740 */
4741
4742 if (msg) printf ("%s: restart (%s).\n", ncr_name (np), msg);
4743
4744 /*
4745 ** Clear Start Queue
4746 */
4747
4748 for (i=0;i<MAX_START;i++)
4749 np -> squeue [i] = NCB_SCRIPT_PHYS (np, idle);
4750
4751 /*
4752 ** Start at first entry.
4753 */
4754
4755 np->squeueput = 0;
4756 WRITESCRIPT(startpos[0], NCB_SCRIPTH_PHYS (np, tryloop));
4757 WRITESCRIPT(start0 [0], SCR_INT ^ IFFALSE (0));
4758
4759 /*
4760 ** Wakeup all pending jobs.
4761 */
4762
4763 ncr_wakeup (np, code);
4764
4765 /*
4766 ** Init chip.
4767 */
4768
4769 OUTB (nc_istat, 0x00 ); /* Remove Reset, abort ... */
4770 OUTB (nc_scntl0, 0xca ); /* full arb., ena parity, par->ATN */
4771 OUTB (nc_scntl1, 0x00 ); /* odd parity, and remove CRST!! */
4772 ncr_selectclock(np, np->rv_scntl3); /* Select SCSI clock */
4773 OUTB (nc_scid , RRE|np->myaddr);/* host adapter SCSI address */
4774 OUTW (nc_respid, 1ul<<np->myaddr);/* id to respond to */
4775 OUTB (nc_istat , SIGP ); /* Signal Process */
4776 OUTB (nc_dmode , np->rv_dmode); /* XXX modify burstlen ??? */
4777 OUTB (nc_dcntl , np->rv_dcntl);
4778 OUTB (nc_ctest3, np->rv_ctest3);
4779 OUTB (nc_ctest5, np->rv_ctest5);
4780 OUTB (nc_ctest4, np->rv_ctest4);/* enable master parity checking */
4781 OUTB (nc_stest2, np->rv_stest2|EXT); /* Extended Sreq/Sack filtering */
4782 OUTB (nc_stest3, TE ); /* TolerANT enable */
4783 OUTB (nc_stime0, 0x0b ); /* HTH = disabled, STO = 0.1 sec. */
4784
4785 if (bootverbose >= 2) {
4786 printf ("\tACTUAL values:SCNTL3:%02x DMODE:%02x DCNTL:%02x\n",
4787 np->rv_scntl3, np->rv_dmode, np->rv_dcntl);
4788 printf ("\t CTEST3:%02x CTEST4:%02x CTEST5:%02x\n",
4789 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5);
4790 }
4791
4792 /*
4793 ** Enable GPIO0 pin for writing if LED support.
4794 */
4795
4796 if (np->features & FE_LED0) {
4797 OUTOFFB (nc_gpcntl, 0x01);
4798 }
4799
4800 /*
4801 ** Fill in target structure.
4802 */
4803 for (i=0;i<MAX_TARGET;i++) {
4804 tcb_p tp = &np->target[i];
4805
4806 tp->tinfo.sval = 0;
4807 tp->tinfo.wval = np->rv_scntl3;
4808
4809 tp->tinfo.current.period = 0;
4810 tp->tinfo.current.offset = 0;
4811 tp->tinfo.current.width = MSG_EXT_WDTR_BUS_8_BIT;
4812 }
4813
4814 /*
4815 ** enable ints
4816 */
4817
4818 OUTW (nc_sien , STO|HTH|MA|SGE|UDC|RST);
4819 OUTB (nc_dien , MDPE|BF|ABRT|SSI|SIR|IID);
4820
4821 /*
4822 ** Start script processor.
4823 */
4824
4825 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, start));
4826
4827 /*
4828 * Notify the XPT of the event
4829 */
4830 if (code == HS_RESET)
4831 xpt_async(AC_BUS_RESET, np->path, NULL);
4832 }
4833
4834 static void
4835 ncr_poll(struct cam_sim *sim)
4836 {
4837 ncr_intr(cam_sim_softc(sim));
4838 }
4839
4840
4841 /*==========================================================
4842 **
4843 ** Get clock factor and sync divisor for a given
4844 ** synchronous factor period.
4845 ** Returns the clock factor (in sxfer) and scntl3
4846 ** synchronous divisor field.
4847 **
4848 **==========================================================
4849 */
4850
4851 static void ncr_getsync(ncb_p np, u_char sfac, u_char *fakp, u_char *scntl3p)
4852 {
4853 u_long clk = np->clock_khz; /* SCSI clock frequency in kHz */
4854 int div = np->clock_divn; /* Number of divisors supported */
4855 u_long fak; /* Sync factor in sxfer */
4856 u_long per; /* Period in tenths of ns */
4857 u_long kpc; /* (per * clk) */
4858
4859 /*
4860 ** Compute the synchronous period in tenths of nano-seconds
4861 */
4862 if (sfac <= 10) per = 250;
4863 else if (sfac == 11) per = 303;
4864 else if (sfac == 12) per = 500;
4865 else per = 40 * sfac;
4866
4867 /*
4868 ** Look for the greatest clock divisor that allows an
4869 ** input speed faster than the period.
4870 */
4871 kpc = per * clk;
4872 while (--div >= 0)
4873 if (kpc >= (div_10M[div] * 4)) break;
4874
4875 /*
4876 ** Calculate the lowest clock factor that allows an output
4877 ** speed not faster than the period.
4878 */
4879 fak = (kpc - 1) / div_10M[div] + 1;
4880
4881 #if 0 /* You can #if 1 if you think this optimization is usefull */
4882
4883 per = (fak * div_10M[div]) / clk;
4884
4885 /*
4886 ** Why not to try the immediate lower divisor and to choose
4887 ** the one that allows the fastest output speed ?
4888 ** We dont want input speed too much greater than output speed.
4889 */
4890 if (div >= 1 && fak < 6) {
4891 u_long fak2, per2;
4892 fak2 = (kpc - 1) / div_10M[div-1] + 1;
4893 per2 = (fak2 * div_10M[div-1]) / clk;
4894 if (per2 < per && fak2 <= 6) {
4895 fak = fak2;
4896 per = per2;
4897 --div;
4898 }
4899 }
4900 #endif
4901
4902 if (fak < 4) fak = 4; /* Should never happen, too bad ... */
4903
4904 /*
4905 ** Compute and return sync parameters for the ncr
4906 */
4907 *fakp = fak - 4;
4908 *scntl3p = ((div+1) << 4) + (sfac < 25 ? 0x80 : 0);
4909 }
4910
4911 /*==========================================================
4912 **
4913 ** Switch sync mode for current job and its target
4914 **
4915 **==========================================================
4916 */
4917
4918 static void
4919 ncr_setsync(ncb_p np, nccb_p cp, u_char scntl3, u_char sxfer, u_char period)
4920 {
4921 union ccb *ccb;
4922 struct ccb_trans_settings neg;
4923 tcb_p tp;
4924 int div;
4925 u_int target = INB (nc_sdid) & 0x0f;
4926 u_int period_10ns;
4927
4928 assert (cp);
4929 if (!cp) return;
4930
4931 ccb = cp->ccb;
4932 assert (ccb);
4933 if (!ccb) return;
4934 assert (target == ccb->ccb_h.target_id);
4935
4936 tp = &np->target[target];
4937
4938 if (!scntl3 || !(sxfer & 0x1f))
4939 scntl3 = np->rv_scntl3;
4940 scntl3 = (scntl3 & 0xf0) | (tp->tinfo.wval & EWS)
4941 | (np->rv_scntl3 & 0x07);
4942
4943 /*
4944 ** Deduce the value of controller sync period from scntl3.
4945 ** period is in tenths of nano-seconds.
4946 */
4947
4948 div = ((scntl3 >> 4) & 0x7);
4949 if ((sxfer & 0x1f) && div)
4950 period_10ns =
4951 (((sxfer>>5)+4)*div_10M[div-1])/np->clock_khz;
4952 else
4953 period_10ns = 0;
4954
4955 tp->tinfo.goal.period = period;
4956 tp->tinfo.goal.offset = sxfer & 0x1f;
4957 tp->tinfo.current.period = period;
4958 tp->tinfo.current.offset = sxfer & 0x1f;
4959
4960 /*
4961 ** Stop there if sync parameters are unchanged
4962 */
4963 if (tp->tinfo.sval == sxfer && tp->tinfo.wval == scntl3) return;
4964 tp->tinfo.sval = sxfer;
4965 tp->tinfo.wval = scntl3;
4966
4967 if (sxfer & 0x1f) {
4968 /*
4969 ** Disable extended Sreq/Sack filtering
4970 */
4971 if (period_10ns <= 2000) OUTOFFB (nc_stest2, EXT);
4972 }
4973
4974 /*
4975 ** Tell the SCSI layer about the
4976 ** new transfer parameters.
4977 */
4978 neg.sync_period = period;
4979 neg.sync_offset = sxfer & 0x1f;
4980 neg.valid = CCB_TRANS_SYNC_RATE_VALID
4981 | CCB_TRANS_SYNC_OFFSET_VALID;
4982 xpt_setup_ccb(&neg.ccb_h, ccb->ccb_h.path,
4983 /*priority*/1);
4984 xpt_async(AC_TRANSFER_NEG, ccb->ccb_h.path, &neg);
4985
4986 /*
4987 ** set actual value and sync_status
4988 */
4989 OUTB (nc_sxfer, sxfer);
4990 np->sync_st = sxfer;
4991 OUTB (nc_scntl3, scntl3);
4992 np->wide_st = scntl3;
4993
4994 /*
4995 ** patch ALL nccbs of this target.
4996 */
4997 for (cp = np->link_nccb; cp; cp = cp->link_nccb) {
4998 if (!cp->ccb) continue;
4999 if (cp->ccb->ccb_h.target_id != target) continue;
5000 cp->sync_status = sxfer;
5001 cp->wide_status = scntl3;
5002 };
5003 }
5004
5005 /*==========================================================
5006 **
5007 ** Switch wide mode for current job and its target
5008 ** SCSI specs say: a SCSI device that accepts a WDTR
5009 ** message shall reset the synchronous agreement to
5010 ** asynchronous mode.
5011 **
5012 **==========================================================
5013 */
5014
5015 static void ncr_setwide (ncb_p np, nccb_p cp, u_char wide, u_char ack)
5016 {
5017 union ccb *ccb;
5018 struct ccb_trans_settings neg;
5019 u_int target = INB (nc_sdid) & 0x0f;
5020 tcb_p tp;
5021 u_char scntl3;
5022 u_char sxfer;
5023
5024 assert (cp);
5025 if (!cp) return;
5026
5027 ccb = cp->ccb;
5028 assert (ccb);
5029 if (!ccb) return;
5030 assert (target == ccb->ccb_h.target_id);
5031
5032 tp = &np->target[target];
5033 tp->tinfo.current.width = wide;
5034 tp->tinfo.goal.width = wide;
5035 tp->tinfo.current.period = 0;
5036 tp->tinfo.current.offset = 0;
5037
5038 scntl3 = (tp->tinfo.wval & (~EWS)) | (wide ? EWS : 0);
5039
5040 sxfer = ack ? 0 : tp->tinfo.sval;
5041
5042 /*
5043 ** Stop there if sync/wide parameters are unchanged
5044 */
5045 if (tp->tinfo.sval == sxfer && tp->tinfo.wval == scntl3) return;
5046 tp->tinfo.sval = sxfer;
5047 tp->tinfo.wval = scntl3;
5048
5049 /* Tell the SCSI layer about the new transfer params */
5050 neg.bus_width = (scntl3 & EWS) ? MSG_EXT_WDTR_BUS_16_BIT
5051 : MSG_EXT_WDTR_BUS_8_BIT;
5052 neg.sync_period = 0;
5053 neg.sync_offset = 0;
5054 neg.valid = CCB_TRANS_BUS_WIDTH_VALID
5055 | CCB_TRANS_SYNC_RATE_VALID
5056 | CCB_TRANS_SYNC_OFFSET_VALID;
5057 xpt_setup_ccb(&neg.ccb_h, ccb->ccb_h.path,
5058 /*priority*/1);
5059 xpt_async(AC_TRANSFER_NEG, ccb->ccb_h.path, &neg);
5060
5061 /*
5062 ** set actual value and sync_status
5063 */
5064 OUTB (nc_sxfer, sxfer);
5065 np->sync_st = sxfer;
5066 OUTB (nc_scntl3, scntl3);
5067 np->wide_st = scntl3;
5068
5069 /*
5070 ** patch ALL nccbs of this target.
5071 */
5072 for (cp = np->link_nccb; cp; cp = cp->link_nccb) {
5073 if (!cp->ccb) continue;
5074 if (cp->ccb->ccb_h.target_id != target) continue;
5075 cp->sync_status = sxfer;
5076 cp->wide_status = scntl3;
5077 };
5078 }
5079
5080 /*==========================================================
5081 **
5082 **
5083 ** ncr timeout handler.
5084 **
5085 **
5086 **==========================================================
5087 **
5088 ** Misused to keep the driver running when
5089 ** interrupts are not configured correctly.
5090 **
5091 **----------------------------------------------------------
5092 */
5093
5094 static void
5095 ncr_timeout (void *arg)
5096 {
5097 ncb_p np = arg;
5098 time_t thistime = time_second;
5099 ticks_t step = np->ticks;
5100 u_long count = 0;
5101 long signed t;
5102 nccb_p cp;
5103
5104 if (np->lasttime != thistime) {
5105 /*
5106 ** block ncr interrupts
5107 */
5108 int oldspl = splcam();
5109 np->lasttime = thistime;
5110
5111 /*----------------------------------------------------
5112 **
5113 ** handle ncr chip timeouts
5114 **
5115 ** Assumption:
5116 ** We have a chance to arbitrate for the
5117 ** SCSI bus at least every 10 seconds.
5118 **
5119 **----------------------------------------------------
5120 */
5121
5122 t = thistime - np->heartbeat;
5123
5124 if (t<2) np->latetime=0; else np->latetime++;
5125
5126 if (np->latetime>2) {
5127 /*
5128 ** If there are no requests, the script
5129 ** processor will sleep on SEL_WAIT_RESEL.
5130 ** But we have to check whether it died.
5131 ** Let's try to wake it up.
5132 */
5133 OUTB (nc_istat, SIGP);
5134 };
5135
5136 /*----------------------------------------------------
5137 **
5138 ** handle nccb timeouts
5139 **
5140 **----------------------------------------------------
5141 */
5142
5143 for (cp=np->link_nccb; cp; cp=cp->link_nccb) {
5144 /*
5145 ** look for timed out nccbs.
5146 */
5147 if (!cp->host_status) continue;
5148 count++;
5149 if (cp->tlimit > thistime) continue;
5150
5151 /*
5152 ** Disable reselect.
5153 ** Remove it from startqueue.
5154 */
5155 cp->jump_nccb.l_cmd = (SCR_JUMP);
5156 if (cp->phys.header.launch.l_paddr ==
5157 NCB_SCRIPT_PHYS (np, select)) {
5158 printf ("%s: timeout nccb=%p (skip)\n",
5159 ncr_name (np), cp);
5160 cp->phys.header.launch.l_paddr
5161 = NCB_SCRIPT_PHYS (np, skip);
5162 };
5163
5164 switch (cp->host_status) {
5165
5166 case HS_BUSY:
5167 case HS_NEGOTIATE:
5168 /* fall through */
5169 case HS_DISCONNECT:
5170 cp->host_status=HS_TIMEOUT;
5171 };
5172 cp->tag = 0;
5173
5174 /*
5175 ** wakeup this nccb.
5176 */
5177 ncr_complete (np, cp);
5178 };
5179 splx (oldspl);
5180 }
5181
5182 np->timeout_ch =
5183 timeout (ncr_timeout, (caddr_t) np, step ? step : 1);
5184
5185 if (INB(nc_istat) & (INTF|SIP|DIP)) {
5186
5187 /*
5188 ** Process pending interrupts.
5189 */
5190
5191 int oldspl = splcam();
5192 if (DEBUG_FLAGS & DEBUG_TINY) printf ("{");
5193 ncr_exception (np);
5194 if (DEBUG_FLAGS & DEBUG_TINY) printf ("}");
5195 splx (oldspl);
5196 };
5197 }
5198
5199 /*==========================================================
5200 **
5201 ** log message for real hard errors
5202 **
5203 ** "ncr0 targ 0?: ERROR (ds:si) (so-si-sd) (sxfer/scntl3) @ name (dsp:dbc)."
5204 ** " reg: r0 r1 r2 r3 r4 r5 r6 ..... rf."
5205 **
5206 ** exception register:
5207 ** ds: dstat
5208 ** si: sist
5209 **
5210 ** SCSI bus lines:
5211 ** so: control lines as driver by NCR.
5212 ** si: control lines as seen by NCR.
5213 ** sd: scsi data lines as seen by NCR.
5214 **
5215 ** wide/fastmode:
5216 ** sxfer: (see the manual)
5217 ** scntl3: (see the manual)
5218 **
5219 ** current script command:
5220 ** dsp: script adress (relative to start of script).
5221 ** dbc: first word of script command.
5222 **
5223 ** First 16 register of the chip:
5224 ** r0..rf
5225 **
5226 **==========================================================
5227 */
5228
5229 static void ncr_log_hard_error(ncb_p np, u_short sist, u_char dstat)
5230 {
5231 u_int32_t dsp;
5232 int script_ofs;
5233 int script_size;
5234 char *script_name;
5235 u_char *script_base;
5236 int i;
5237
5238 dsp = INL (nc_dsp);
5239
5240 if (np->p_script < dsp &&
5241 dsp <= np->p_script + sizeof(struct script)) {
5242 script_ofs = dsp - np->p_script;
5243 script_size = sizeof(struct script);
5244 script_base = (u_char *) np->script;
5245 script_name = "script";
5246 }
5247 else if (np->p_scripth < dsp &&
5248 dsp <= np->p_scripth + sizeof(struct scripth)) {
5249 script_ofs = dsp - np->p_scripth;
5250 script_size = sizeof(struct scripth);
5251 script_base = (u_char *) np->scripth;
5252 script_name = "scripth";
5253 } else {
5254 script_ofs = dsp;
5255 script_size = 0;
5256 script_base = 0;
5257 script_name = "mem";
5258 }
5259
5260 printf ("%s:%d: ERROR (%x:%x) (%x-%x-%x) (%x/%x) @ (%s %x:%08x).\n",
5261 ncr_name (np), (unsigned)INB (nc_sdid)&0x0f, dstat, sist,
5262 (unsigned)INB (nc_socl), (unsigned)INB (nc_sbcl), (unsigned)INB (nc_sbdl),
5263 (unsigned)INB (nc_sxfer),(unsigned)INB (nc_scntl3), script_name, script_ofs,
5264 (unsigned)INL (nc_dbc));
5265
5266 if (((script_ofs & 3) == 0) &&
5267 (unsigned)script_ofs < script_size) {
5268 printf ("%s: script cmd = %08x\n", ncr_name(np),
5269 (int)READSCRIPT_OFF(script_base, script_ofs));
5270 }
5271
5272 printf ("%s: regdump:", ncr_name(np));
5273 for (i=0; i<16;i++)
5274 printf (" %02x", (unsigned)INB_OFF(i));
5275 printf (".\n");
5276 }
5277
5278 /*==========================================================
5279 **
5280 **
5281 ** ncr chip exception handler.
5282 **
5283 **
5284 **==========================================================
5285 */
5286
5287 void ncr_exception (ncb_p np)
5288 {
5289 u_char istat, dstat;
5290 u_short sist;
5291
5292 /*
5293 ** interrupt on the fly ?
5294 */
5295 while ((istat = INB (nc_istat)) & INTF) {
5296 if (DEBUG_FLAGS & DEBUG_TINY) printf ("F ");
5297 OUTB (nc_istat, INTF);
5298 np->profile.num_fly++;
5299 ncr_wakeup (np, 0);
5300 };
5301 if (!(istat & (SIP|DIP))) {
5302 return;
5303 }
5304
5305 /*
5306 ** Steinbach's Guideline for Systems Programming:
5307 ** Never test for an error condition you don't know how to handle.
5308 */
5309
5310 sist = (istat & SIP) ? INW (nc_sist) : 0;
5311 dstat = (istat & DIP) ? INB (nc_dstat) : 0;
5312 np->profile.num_int++;
5313
5314 if (DEBUG_FLAGS & DEBUG_TINY)
5315 printf ("<%d|%x:%x|%x:%x>",
5316 INB(nc_scr0),
5317 dstat,sist,
5318 (unsigned)INL(nc_dsp),
5319 (unsigned)INL(nc_dbc));
5320 if ((dstat==DFE) && (sist==PAR)) return;
5321
5322 /*==========================================================
5323 **
5324 ** First the normal cases.
5325 **
5326 **==========================================================
5327 */
5328 /*-------------------------------------------
5329 ** SCSI reset
5330 **-------------------------------------------
5331 */
5332
5333 if (sist & RST) {
5334 ncr_init (np, bootverbose ? "scsi reset" : NULL, HS_RESET);
5335 return;
5336 };
5337
5338 /*-------------------------------------------
5339 ** selection timeout
5340 **
5341 ** IID excluded from dstat mask!
5342 ** (chip bug)
5343 **-------------------------------------------
5344 */
5345
5346 if ((sist & STO) &&
5347 !(sist & (GEN|HTH|MA|SGE|UDC|RST|PAR)) &&
5348 !(dstat & (MDPE|BF|ABRT|SIR))) {
5349 ncr_int_sto (np);
5350 return;
5351 };
5352
5353 /*-------------------------------------------
5354 ** Phase mismatch.
5355 **-------------------------------------------
5356 */
5357
5358 if ((sist & MA) &&
5359 !(sist & (STO|GEN|HTH|SGE|UDC|RST|PAR)) &&
5360 !(dstat & (MDPE|BF|ABRT|SIR|IID))) {
5361 ncr_int_ma (np, dstat);
5362 return;
5363 };
5364
5365 /*----------------------------------------
5366 ** move command with length 0
5367 **----------------------------------------
5368 */
5369
5370 if ((dstat & IID) &&
5371 !(sist & (STO|GEN|HTH|MA|SGE|UDC|RST|PAR)) &&
5372 !(dstat & (MDPE|BF|ABRT|SIR)) &&
5373 ((INL(nc_dbc) & 0xf8000000) == SCR_MOVE_TBL)) {
5374 /*
5375 ** Target wants more data than available.
5376 ** The "no_data" script will do it.
5377 */
5378 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, no_data));
5379 return;
5380 };
5381
5382 /*-------------------------------------------
5383 ** Programmed interrupt
5384 **-------------------------------------------
5385 */
5386
5387 if ((dstat & SIR) &&
5388 !(sist & (STO|GEN|HTH|MA|SGE|UDC|RST|PAR)) &&
5389 !(dstat & (MDPE|BF|ABRT|IID)) &&
5390 (INB(nc_dsps) <= SIR_MAX)) {
5391 ncr_int_sir (np);
5392 return;
5393 };
5394
5395 /*========================================
5396 ** log message for real hard errors
5397 **========================================
5398 */
5399
5400 ncr_log_hard_error(np, sist, dstat);
5401
5402 /*========================================
5403 ** do the register dump
5404 **========================================
5405 */
5406
5407 if (time_second - np->regtime > 10) {
5408 int i;
5409 np->regtime = time_second;
5410 for (i=0; i<sizeof(np->regdump); i++)
5411 ((volatile char*)&np->regdump)[i] = INB_OFF(i);
5412 np->regdump.nc_dstat = dstat;
5413 np->regdump.nc_sist = sist;
5414 };
5415
5416
5417 /*----------------------------------------
5418 ** clean up the dma fifo
5419 **----------------------------------------
5420 */
5421
5422 if ( (INB(nc_sstat0) & (ILF|ORF|OLF) ) ||
5423 (INB(nc_sstat1) & (FF3210) ) ||
5424 (INB(nc_sstat2) & (ILF1|ORF1|OLF1)) || /* wide .. */
5425 !(dstat & DFE)) {
5426 printf ("%s: have to clear fifos.\n", ncr_name (np));
5427 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */
5428 OUTB (nc_ctest3, np->rv_ctest3 | CLF);
5429 /* clear dma fifo */
5430 }
5431
5432 /*----------------------------------------
5433 ** handshake timeout
5434 **----------------------------------------
5435 */
5436
5437 if (sist & HTH) {
5438 printf ("%s: handshake timeout\n", ncr_name(np));
5439 OUTB (nc_scntl1, CRST);
5440 DELAY (1000);
5441 OUTB (nc_scntl1, 0x00);
5442 OUTB (nc_scr0, HS_FAIL);
5443 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, cleanup));
5444 return;
5445 }
5446
5447 /*----------------------------------------
5448 ** unexpected disconnect
5449 **----------------------------------------
5450 */
5451
5452 if ((sist & UDC) &&
5453 !(sist & (STO|GEN|HTH|MA|SGE|RST|PAR)) &&
5454 !(dstat & (MDPE|BF|ABRT|SIR|IID))) {
5455 OUTB (nc_scr0, HS_UNEXPECTED);
5456 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, cleanup));
5457 return;
5458 };
5459
5460 /*----------------------------------------
5461 ** cannot disconnect
5462 **----------------------------------------
5463 */
5464
5465 if ((dstat & IID) &&
5466 !(sist & (STO|GEN|HTH|MA|SGE|UDC|RST|PAR)) &&
5467 !(dstat & (MDPE|BF|ABRT|SIR)) &&
5468 ((INL(nc_dbc) & 0xf8000000) == SCR_WAIT_DISC)) {
5469 /*
5470 ** Unexpected data cycle while waiting for disconnect.
5471 */
5472 if (INB(nc_sstat2) & LDSC) {
5473 /*
5474 ** It's an early reconnect.
5475 ** Let's continue ...
5476 */
5477 OUTB (nc_dcntl, np->rv_dcntl | STD);
5478 /*
5479 ** info message
5480 */
5481 printf ("%s: INFO: LDSC while IID.\n",
5482 ncr_name (np));
5483 return;
5484 };
5485 printf ("%s: target %d doesn't release the bus.\n",
5486 ncr_name (np), INB (nc_sdid)&0x0f);
5487 /*
5488 ** return without restarting the NCR.
5489 ** timeout will do the real work.
5490 */
5491 return;
5492 };
5493
5494 /*----------------------------------------
5495 ** single step
5496 **----------------------------------------
5497 */
5498
5499 if ((dstat & SSI) &&
5500 !(sist & (STO|GEN|HTH|MA|SGE|UDC|RST|PAR)) &&
5501 !(dstat & (MDPE|BF|ABRT|SIR|IID))) {
5502 OUTB (nc_dcntl, np->rv_dcntl | STD);
5503 return;
5504 };
5505
5506 /*
5507 ** @RECOVER@ HTH, SGE, ABRT.
5508 **
5509 ** We should try to recover from these interrupts.
5510 ** They may occur if there are problems with synch transfers, or
5511 ** if targets are switched on or off while the driver is running.
5512 */
5513
5514 if (sist & SGE) {
5515 /* clear scsi offsets */
5516 OUTB (nc_ctest3, np->rv_ctest3 | CLF);
5517 }
5518
5519 /*
5520 ** Freeze controller to be able to read the messages.
5521 */
5522
5523 if (DEBUG_FLAGS & DEBUG_FREEZE) {
5524 int i;
5525 unsigned char val;
5526 for (i=0; i<0x60; i++) {
5527 switch (i%16) {
5528
5529 case 0:
5530 printf ("%s: reg[%d0]: ",
5531 ncr_name(np),i/16);
5532 break;
5533 case 4:
5534 case 8:
5535 case 12:
5536 printf (" ");
5537 break;
5538 };
5539 val = bus_space_read_1(np->bst, np->bsh, i);
5540 printf (" %x%x", val/16, val%16);
5541 if (i%16==15) printf (".\n");
5542 };
5543
5544 untimeout (ncr_timeout, (caddr_t) np, np->timeout_ch);
5545
5546 printf ("%s: halted!\n", ncr_name(np));
5547 /*
5548 ** don't restart controller ...
5549 */
5550 OUTB (nc_istat, SRST);
5551 return;
5552 };
5553
5554 #ifdef NCR_FREEZE
5555 /*
5556 ** Freeze system to be able to read the messages.
5557 */
5558 printf ("ncr: fatal error: system halted - press reset to reboot ...");
5559 (void) splhigh();
5560 for (;;);
5561 #endif
5562
5563 /*
5564 ** sorry, have to kill ALL jobs ...
5565 */
5566
5567 ncr_init (np, "fatal error", HS_FAIL);
5568 }
5569
5570 /*==========================================================
5571 **
5572 ** ncr chip exception handler for selection timeout
5573 **
5574 **==========================================================
5575 **
5576 ** There seems to be a bug in the 53c810.
5577 ** Although a STO-Interrupt is pending,
5578 ** it continues executing script commands.
5579 ** But it will fail and interrupt (IID) on
5580 ** the next instruction where it's looking
5581 ** for a valid phase.
5582 **
5583 **----------------------------------------------------------
5584 */
5585
5586 void ncr_int_sto (ncb_p np)
5587 {
5588 u_long dsa, scratcha, diff;
5589 nccb_p cp;
5590 if (DEBUG_FLAGS & DEBUG_TINY) printf ("T");
5591
5592 /*
5593 ** look for nccb and set the status.
5594 */
5595
5596 dsa = INL (nc_dsa);
5597 cp = np->link_nccb;
5598 while (cp && (CCB_PHYS (cp, phys) != dsa))
5599 cp = cp->link_nccb;
5600
5601 if (cp) {
5602 cp-> host_status = HS_SEL_TIMEOUT;
5603 ncr_complete (np, cp);
5604 };
5605
5606 /*
5607 ** repair start queue
5608 */
5609
5610 scratcha = INL (nc_scratcha);
5611 diff = scratcha - NCB_SCRIPTH_PHYS (np, tryloop);
5612
5613 /* assert ((diff <= MAX_START * 20) && !(diff % 20));*/
5614
5615 if ((diff <= MAX_START * 20) && !(diff % 20)) {
5616 WRITESCRIPT(startpos[0], scratcha);
5617 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, start));
5618 return;
5619 };
5620 ncr_init (np, "selection timeout", HS_FAIL);
5621 }
5622
5623 /*==========================================================
5624 **
5625 **
5626 ** ncr chip exception handler for phase errors.
5627 **
5628 **
5629 **==========================================================
5630 **
5631 ** We have to construct a new transfer descriptor,
5632 ** to transfer the rest of the current block.
5633 **
5634 **----------------------------------------------------------
5635 */
5636
5637 static void ncr_int_ma (ncb_p np, u_char dstat)
5638 {
5639 u_int32_t dbc;
5640 u_int32_t rest;
5641 u_int32_t dsa;
5642 u_int32_t dsp;
5643 u_int32_t nxtdsp;
5644 volatile void *vdsp_base;
5645 size_t vdsp_off;
5646 u_int32_t oadr, olen;
5647 u_int32_t *tblp, *newcmd;
5648 u_char cmd, sbcl, ss0, ss2, ctest5;
5649 u_short delta;
5650 nccb_p cp;
5651
5652 dsp = INL (nc_dsp);
5653 dsa = INL (nc_dsa);
5654 dbc = INL (nc_dbc);
5655 ss0 = INB (nc_sstat0);
5656 ss2 = INB (nc_sstat2);
5657 sbcl= INB (nc_sbcl);
5658
5659 cmd = dbc >> 24;
5660 rest= dbc & 0xffffff;
5661
5662 ctest5 = (np->rv_ctest5 & DFS) ? INB (nc_ctest5) : 0;
5663 if (ctest5 & DFS)
5664 delta=(((ctest5<<8) | (INB (nc_dfifo) & 0xff)) - rest) & 0x3ff;
5665 else
5666 delta=(INB (nc_dfifo) - rest) & 0x7f;
5667
5668
5669 /*
5670 ** The data in the dma fifo has not been transfered to
5671 ** the target -> add the amount to the rest
5672 ** and clear the data.
5673 ** Check the sstat2 register in case of wide transfer.
5674 */
5675
5676 if (!(dstat & DFE)) rest += delta;
5677 if (ss0 & OLF) rest++;
5678 if (ss0 & ORF) rest++;
5679 if (INB(nc_scntl3) & EWS) {
5680 if (ss2 & OLF1) rest++;
5681 if (ss2 & ORF1) rest++;
5682 };
5683 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */
5684 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */
5685
5686 /*
5687 ** locate matching cp
5688 */
5689 cp = np->link_nccb;
5690 while (cp && (CCB_PHYS (cp, phys) != dsa))
5691 cp = cp->link_nccb;
5692
5693 if (!cp) {
5694 printf ("%s: SCSI phase error fixup: CCB already dequeued (%p)\n",
5695 ncr_name (np), (void *) np->header.cp);
5696 return;
5697 }
5698 if (cp != np->header.cp) {
5699 printf ("%s: SCSI phase error fixup: CCB address mismatch "
5700 "(%p != %p) np->nccb = %p\n",
5701 ncr_name (np), (void *)cp, (void *)np->header.cp,
5702 (void *)np->link_nccb);
5703 /* return;*/
5704 }
5705
5706 /*
5707 ** find the interrupted script command,
5708 ** and the address at which to continue.
5709 */
5710
5711 if (dsp == vtophys (&cp->patch[2])) {
5712 vdsp_base = cp;
5713 vdsp_off = offsetof(struct nccb, patch[0]);
5714 nxtdsp = READSCRIPT_OFF(vdsp_base, vdsp_off + 3*4);
5715 } else if (dsp == vtophys (&cp->patch[6])) {
5716 vdsp_base = cp;
5717 vdsp_off = offsetof(struct nccb, patch[4]);
5718 nxtdsp = READSCRIPT_OFF(vdsp_base, vdsp_off + 3*4);
5719 } else if (dsp > np->p_script &&
5720 dsp <= np->p_script + sizeof(struct script)) {
5721 vdsp_base = np->script;
5722 vdsp_off = dsp - np->p_script - 8;
5723 nxtdsp = dsp;
5724 } else {
5725 vdsp_base = np->scripth;
5726 vdsp_off = dsp - np->p_scripth - 8;
5727 nxtdsp = dsp;
5728 };
5729
5730 /*
5731 ** log the information
5732 */
5733 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_PHASE)) {
5734 printf ("P%x%x ",cmd&7, sbcl&7);
5735 printf ("RL=%d D=%d SS0=%x ",
5736 (unsigned) rest, (unsigned) delta, ss0);
5737 };
5738 if (DEBUG_FLAGS & DEBUG_PHASE) {
5739 printf ("\nCP=%p CP2=%p DSP=%x NXT=%x VDSP=%p CMD=%x ",
5740 cp, np->header.cp,
5741 dsp,
5742 nxtdsp, (volatile char*)vdsp_base+vdsp_off, cmd);
5743 };
5744
5745 /*
5746 ** get old startaddress and old length.
5747 */
5748
5749 oadr = READSCRIPT_OFF(vdsp_base, vdsp_off + 1*4);
5750
5751 if (cmd & 0x10) { /* Table indirect */
5752 tblp = (u_int32_t *) ((char*) &cp->phys + oadr);
5753 olen = tblp[0];
5754 oadr = tblp[1];
5755 } else {
5756 tblp = (u_int32_t *) 0;
5757 olen = READSCRIPT_OFF(vdsp_base, vdsp_off) & 0xffffff;
5758 };
5759
5760 if (DEBUG_FLAGS & DEBUG_PHASE) {
5761 printf ("OCMD=%x\nTBLP=%p OLEN=%lx OADR=%lx\n",
5762 (unsigned) (READSCRIPT_OFF(vdsp_base, vdsp_off) >> 24),
5763 (void *) tblp,
5764 (u_long) olen,
5765 (u_long) oadr);
5766 };
5767
5768 /*
5769 ** if old phase not dataphase, leave here.
5770 */
5771
5772 if (cmd != (READSCRIPT_OFF(vdsp_base, vdsp_off) >> 24)) {
5773 PRINT_ADDR(cp->ccb);
5774 printf ("internal error: cmd=%02x != %02x=(vdsp[0] >> 24)\n",
5775 (unsigned)cmd,
5776 (unsigned)READSCRIPT_OFF(vdsp_base, vdsp_off) >> 24);
5777
5778 return;
5779 }
5780 if (cmd & 0x06) {
5781 PRINT_ADDR(cp->ccb);
5782 printf ("phase change %x-%x %d@%08x resid=%d.\n",
5783 cmd&7, sbcl&7, (unsigned)olen,
5784 (unsigned)oadr, (unsigned)rest);
5785
5786 OUTB (nc_dcntl, np->rv_dcntl | STD);
5787 return;
5788 };
5789
5790 /*
5791 ** choose the correct patch area.
5792 ** if savep points to one, choose the other.
5793 */
5794
5795 newcmd = cp->patch;
5796 if (cp->phys.header.savep == vtophys (newcmd)) newcmd+=4;
5797
5798 /*
5799 ** fillin the commands
5800 */
5801
5802 newcmd[0] = ((cmd & 0x0f) << 24) | rest;
5803 newcmd[1] = oadr + olen - rest;
5804 newcmd[2] = SCR_JUMP;
5805 newcmd[3] = nxtdsp;
5806
5807 if (DEBUG_FLAGS & DEBUG_PHASE) {
5808 PRINT_ADDR(cp->ccb);
5809 printf ("newcmd[%d] %x %x %x %x.\n",
5810 (int)(newcmd - cp->patch),
5811 (unsigned)newcmd[0],
5812 (unsigned)newcmd[1],
5813 (unsigned)newcmd[2],
5814 (unsigned)newcmd[3]);
5815 }
5816 /*
5817 ** fake the return address (to the patch).
5818 ** and restart script processor at dispatcher.
5819 */
5820 np->profile.num_break++;
5821 OUTL (nc_temp, vtophys (newcmd));
5822 if ((cmd & 7) == 0)
5823 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, dispatch));
5824 else
5825 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, checkatn));
5826 }
5827
5828 /*==========================================================
5829 **
5830 **
5831 ** ncr chip exception handler for programmed interrupts.
5832 **
5833 **
5834 **==========================================================
5835 */
5836
5837 static int ncr_show_msg (u_char * msg)
5838 {
5839 u_char i;
5840 printf ("%x",*msg);
5841 if (*msg==MSG_EXTENDED) {
5842 for (i=1;i<8;i++) {
5843 if (i-1>msg[1]) break;
5844 printf ("-%x",msg[i]);
5845 };
5846 return (i+1);
5847 } else if ((*msg & 0xf0) == 0x20) {
5848 printf ("-%x",msg[1]);
5849 return (2);
5850 };
5851 return (1);
5852 }
5853
5854 void ncr_int_sir (ncb_p np)
5855 {
5856 u_char scntl3;
5857 u_char chg, ofs, per, fak, wide;
5858 u_char num = INB (nc_dsps);
5859 nccb_p cp=0;
5860 u_long dsa;
5861 u_int target = INB (nc_sdid) & 0x0f;
5862 tcb_p tp = &np->target[target];
5863 int i;
5864 if (DEBUG_FLAGS & DEBUG_TINY) printf ("I#%d", num);
5865
5866 switch (num) {
5867 case SIR_SENSE_RESTART:
5868 case SIR_STALL_RESTART:
5869 break;
5870
5871 default:
5872 /*
5873 ** lookup the nccb
5874 */
5875 dsa = INL (nc_dsa);
5876 cp = np->link_nccb;
5877 while (cp && (CCB_PHYS (cp, phys) != dsa))
5878 cp = cp->link_nccb;
5879
5880 assert (cp);
5881 if (!cp)
5882 goto out;
5883 assert (cp == np->header.cp);
5884 if (cp != np->header.cp)
5885 goto out;
5886 }
5887
5888 switch (num) {
5889
5890 /*--------------------------------------------------------------------
5891 **
5892 ** Processing of interrupted getcc selects
5893 **
5894 **--------------------------------------------------------------------
5895 */
5896
5897 case SIR_SENSE_RESTART:
5898 /*------------------------------------------
5899 ** Script processor is idle.
5900 ** Look for interrupted "check cond"
5901 **------------------------------------------
5902 */
5903
5904 if (DEBUG_FLAGS & DEBUG_RESTART)
5905 printf ("%s: int#%d",ncr_name (np),num);
5906 cp = (nccb_p) 0;
5907 for (i=0; i<MAX_TARGET; i++) {
5908 if (DEBUG_FLAGS & DEBUG_RESTART) printf (" t%d", i);
5909 tp = &np->target[i];
5910 if (DEBUG_FLAGS & DEBUG_RESTART) printf ("+");
5911 cp = tp->hold_cp;
5912 if (!cp) continue;
5913 if (DEBUG_FLAGS & DEBUG_RESTART) printf ("+");
5914 if ((cp->host_status==HS_BUSY) &&
5915 (cp->s_status==SCSI_STATUS_CHECK_COND))
5916 break;
5917 if (DEBUG_FLAGS & DEBUG_RESTART) printf ("- (remove)");
5918 tp->hold_cp = cp = (nccb_p) 0;
5919 };
5920
5921 if (cp) {
5922 if (DEBUG_FLAGS & DEBUG_RESTART)
5923 printf ("+ restart job ..\n");
5924 OUTL (nc_dsa, CCB_PHYS (cp, phys));
5925 OUTL (nc_dsp, NCB_SCRIPTH_PHYS (np, getcc));
5926 return;
5927 };
5928
5929 /*
5930 ** no job, resume normal processing
5931 */
5932 if (DEBUG_FLAGS & DEBUG_RESTART) printf (" -- remove trap\n");
5933 WRITESCRIPT(start0[0], SCR_INT ^ IFFALSE (0));
5934 break;
5935
5936 case SIR_SENSE_FAILED:
5937 /*-------------------------------------------
5938 ** While trying to select for
5939 ** getting the condition code,
5940 ** a target reselected us.
5941 **-------------------------------------------
5942 */
5943 if (DEBUG_FLAGS & DEBUG_RESTART) {
5944 PRINT_ADDR(cp->ccb);
5945 printf ("in getcc reselect by t%d.\n",
5946 INB(nc_ssid) & 0x0f);
5947 }
5948
5949 /*
5950 ** Mark this job
5951 */
5952 cp->host_status = HS_BUSY;
5953 cp->s_status = SCSI_STATUS_CHECK_COND;
5954 np->target[cp->ccb->ccb_h.target_id].hold_cp = cp;
5955
5956 /*
5957 ** And patch code to restart it.
5958 */
5959 WRITESCRIPT(start0[0], SCR_INT);
5960 break;
5961
5962 /*-----------------------------------------------------------------------------
5963 **
5964 ** Was Sie schon immer ueber transfermode negotiation wissen wollten ...
5965 **
5966 ** We try to negotiate sync and wide transfer only after
5967 ** a successfull inquire command. We look at byte 7 of the
5968 ** inquire data to determine the capabilities if the target.
5969 **
5970 ** When we try to negotiate, we append the negotiation message
5971 ** to the identify and (maybe) simple tag message.
5972 ** The host status field is set to HS_NEGOTIATE to mark this
5973 ** situation.
5974 **
5975 ** If the target doesn't answer this message immidiately
5976 ** (as required by the standard), the SIR_NEGO_FAIL interrupt
5977 ** will be raised eventually.
5978 ** The handler removes the HS_NEGOTIATE status, and sets the
5979 ** negotiated value to the default (async / nowide).
5980 **
5981 ** If we receive a matching answer immediately, we check it
5982 ** for validity, and set the values.
5983 **
5984 ** If we receive a Reject message immediately, we assume the
5985 ** negotiation has failed, and fall back to standard values.
5986 **
5987 ** If we receive a negotiation message while not in HS_NEGOTIATE
5988 ** state, it's a target initiated negotiation. We prepare a
5989 ** (hopefully) valid answer, set our parameters, and send back
5990 ** this answer to the target.
5991 **
5992 ** If the target doesn't fetch the answer (no message out phase),
5993 ** we assume the negotiation has failed, and fall back to default
5994 ** settings.
5995 **
5996 ** When we set the values, we adjust them in all nccbs belonging
5997 ** to this target, in the controller's register, and in the "phys"
5998 ** field of the controller's struct ncb.
5999 **
6000 ** Possible cases: hs sir msg_in value send goto
6001 ** We try try to negotiate:
6002 ** -> target doesnt't msgin NEG FAIL noop defa. - dispatch
6003 ** -> target rejected our msg NEG FAIL reject defa. - dispatch
6004 ** -> target answered (ok) NEG SYNC sdtr set - clrack
6005 ** -> target answered (!ok) NEG SYNC sdtr defa. REJ--->msg_bad
6006 ** -> target answered (ok) NEG WIDE wdtr set - clrack
6007 ** -> target answered (!ok) NEG WIDE wdtr defa. REJ--->msg_bad
6008 ** -> any other msgin NEG FAIL noop defa. - dispatch
6009 **
6010 ** Target tries to negotiate:
6011 ** -> incoming message --- SYNC sdtr set SDTR -
6012 ** -> incoming message --- WIDE wdtr set WDTR -
6013 ** We sent our answer:
6014 ** -> target doesn't msgout --- PROTO ? defa. - dispatch
6015 **
6016 **-----------------------------------------------------------------------------
6017 */
6018
6019 case SIR_NEGO_FAILED:
6020 /*-------------------------------------------------------
6021 **
6022 ** Negotiation failed.
6023 ** Target doesn't send an answer message,
6024 ** or target rejected our message.
6025 **
6026 ** Remove negotiation request.
6027 **
6028 **-------------------------------------------------------
6029 */
6030 OUTB (HS_PRT, HS_BUSY);
6031
6032 /* fall through */
6033
6034 case SIR_NEGO_PROTO:
6035 /*-------------------------------------------------------
6036 **
6037 ** Negotiation failed.
6038 ** Target doesn't fetch the answer message.
6039 **
6040 **-------------------------------------------------------
6041 */
6042
6043 if (DEBUG_FLAGS & DEBUG_NEGO) {
6044 PRINT_ADDR(cp->ccb);
6045 printf ("negotiation failed sir=%x status=%x.\n",
6046 num, cp->nego_status);
6047 };
6048
6049 /*
6050 ** any error in negotiation:
6051 ** fall back to default mode.
6052 */
6053 switch (cp->nego_status) {
6054
6055 case NS_SYNC:
6056 ncr_setsync (np, cp, 0, 0xe0, 0);
6057 break;
6058
6059 case NS_WIDE:
6060 ncr_setwide (np, cp, 0, 0);
6061 break;
6062
6063 };
6064 np->msgin [0] = MSG_NOOP;
6065 np->msgout[0] = MSG_NOOP;
6066 cp->nego_status = 0;
6067 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, dispatch));
6068 break;
6069
6070 case SIR_NEGO_SYNC:
6071 /*
6072 ** Synchronous request message received.
6073 */
6074
6075 if (DEBUG_FLAGS & DEBUG_NEGO) {
6076 PRINT_ADDR(cp->ccb);
6077 printf ("sync msgin: ");
6078 (void) ncr_show_msg (np->msgin);
6079 printf (".\n");
6080 };
6081
6082 /*
6083 ** get requested values.
6084 */
6085
6086 chg = 0;
6087 per = np->msgin[3];
6088 ofs = np->msgin[4];
6089 if (ofs==0) per=255;
6090
6091 /*
6092 ** check values against driver limits.
6093 */
6094 if (per < np->minsync)
6095 {chg = 1; per = np->minsync;}
6096 if (per < tp->tinfo.user.period)
6097 {chg = 1; per = tp->tinfo.user.period;}
6098 if (ofs > tp->tinfo.user.offset)
6099 {chg = 1; ofs = tp->tinfo.user.offset;}
6100
6101 /*
6102 ** Check against controller limits.
6103 */
6104
6105 fak = 7;
6106 scntl3 = 0;
6107 if (ofs != 0) {
6108 ncr_getsync(np, per, &fak, &scntl3);
6109 if (fak > 7) {
6110 chg = 1;
6111 ofs = 0;
6112 }
6113 }
6114 if (ofs == 0) {
6115 fak = 7;
6116 per = 0;
6117 scntl3 = 0;
6118 }
6119
6120 if (DEBUG_FLAGS & DEBUG_NEGO) {
6121 PRINT_ADDR(cp->ccb);
6122 printf ("sync: per=%d scntl3=0x%x ofs=%d fak=%d chg=%d.\n",
6123 per, scntl3, ofs, fak, chg);
6124 }
6125
6126 if (INB (HS_PRT) == HS_NEGOTIATE) {
6127 OUTB (HS_PRT, HS_BUSY);
6128 switch (cp->nego_status) {
6129
6130 case NS_SYNC:
6131 /*
6132 ** This was an answer message
6133 */
6134 if (chg) {
6135 /*
6136 ** Answer wasn't acceptable.
6137 */
6138 ncr_setsync (np, cp, 0, 0xe0, 0);
6139 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, msg_bad));
6140 } else {
6141 /*
6142 ** Answer is ok.
6143 */
6144 ncr_setsync (np,cp,scntl3,(fak<<5)|ofs, per);
6145 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, clrack));
6146 };
6147 return;
6148
6149 case NS_WIDE:
6150 ncr_setwide (np, cp, 0, 0);
6151 break;
6152 };
6153 };
6154
6155 /*
6156 ** It was a request. Set value and
6157 ** prepare an answer message
6158 */
6159
6160 ncr_setsync (np, cp, scntl3, (fak<<5)|ofs, per);
6161
6162 np->msgout[0] = MSG_EXTENDED;
6163 np->msgout[1] = 3;
6164 np->msgout[2] = MSG_EXT_SDTR;
6165 np->msgout[3] = per;
6166 np->msgout[4] = ofs;
6167
6168 cp->nego_status = NS_SYNC;
6169
6170 if (DEBUG_FLAGS & DEBUG_NEGO) {
6171 PRINT_ADDR(cp->ccb);
6172 printf ("sync msgout: ");
6173 (void) ncr_show_msg (np->msgout);
6174 printf (".\n");
6175 }
6176
6177 if (!ofs) {
6178 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, msg_bad));
6179 return;
6180 }
6181 np->msgin [0] = MSG_NOOP;
6182
6183 break;
6184
6185 case SIR_NEGO_WIDE:
6186 /*
6187 ** Wide request message received.
6188 */
6189 if (DEBUG_FLAGS & DEBUG_NEGO) {
6190 PRINT_ADDR(cp->ccb);
6191 printf ("wide msgin: ");
6192 (void) ncr_show_msg (np->msgin);
6193 printf (".\n");
6194 };
6195
6196 /*
6197 ** get requested values.
6198 */
6199
6200 chg = 0;
6201 wide = np->msgin[3];
6202
6203 /*
6204 ** check values against driver limits.
6205 */
6206
6207 if (wide > tp->tinfo.user.width)
6208 {chg = 1; wide = tp->tinfo.user.width;}
6209
6210 if (DEBUG_FLAGS & DEBUG_NEGO) {
6211 PRINT_ADDR(cp->ccb);
6212 printf ("wide: wide=%d chg=%d.\n", wide, chg);
6213 }
6214
6215 if (INB (HS_PRT) == HS_NEGOTIATE) {
6216 OUTB (HS_PRT, HS_BUSY);
6217 switch (cp->nego_status) {
6218
6219 case NS_WIDE:
6220 /*
6221 ** This was an answer message
6222 */
6223 if (chg) {
6224 /*
6225 ** Answer wasn't acceptable.
6226 */
6227 ncr_setwide (np, cp, 0, 1);
6228 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, msg_bad));
6229 } else {
6230 /*
6231 ** Answer is ok.
6232 */
6233 ncr_setwide (np, cp, wide, 1);
6234 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, clrack));
6235 };
6236 return;
6237
6238 case NS_SYNC:
6239 ncr_setsync (np, cp, 0, 0xe0, 0);
6240 break;
6241 };
6242 };
6243
6244 /*
6245 ** It was a request, set value and
6246 ** prepare an answer message
6247 */
6248
6249 ncr_setwide (np, cp, wide, 1);
6250
6251 np->msgout[0] = MSG_EXTENDED;
6252 np->msgout[1] = 2;
6253 np->msgout[2] = MSG_EXT_WDTR;
6254 np->msgout[3] = wide;
6255
6256 np->msgin [0] = MSG_NOOP;
6257
6258 cp->nego_status = NS_WIDE;
6259
6260 if (DEBUG_FLAGS & DEBUG_NEGO) {
6261 PRINT_ADDR(cp->ccb);
6262 printf ("wide msgout: ");
6263 (void) ncr_show_msg (np->msgout);
6264 printf (".\n");
6265 }
6266 break;
6267
6268 /*--------------------------------------------------------------------
6269 **
6270 ** Processing of special messages
6271 **
6272 **--------------------------------------------------------------------
6273 */
6274
6275 case SIR_REJECT_RECEIVED:
6276 /*-----------------------------------------------
6277 **
6278 ** We received a MSG_MESSAGE_REJECT message.
6279 **
6280 **-----------------------------------------------
6281 */
6282
6283 PRINT_ADDR(cp->ccb);
6284 printf ("MSG_MESSAGE_REJECT received (%x:%x).\n",
6285 (unsigned)np->lastmsg, np->msgout[0]);
6286 break;
6287
6288 case SIR_REJECT_SENT:
6289 /*-----------------------------------------------
6290 **
6291 ** We received an unknown message
6292 **
6293 **-----------------------------------------------
6294 */
6295
6296 PRINT_ADDR(cp->ccb);
6297 printf ("MSG_MESSAGE_REJECT sent for ");
6298 (void) ncr_show_msg (np->msgin);
6299 printf (".\n");
6300 break;
6301
6302 /*--------------------------------------------------------------------
6303 **
6304 ** Processing of special messages
6305 **
6306 **--------------------------------------------------------------------
6307 */
6308
6309 case SIR_IGN_RESIDUE:
6310 /*-----------------------------------------------
6311 **
6312 ** We received an IGNORE RESIDUE message,
6313 ** which couldn't be handled by the script.
6314 **
6315 **-----------------------------------------------
6316 */
6317
6318 PRINT_ADDR(cp->ccb);
6319 printf ("MSG_IGN_WIDE_RESIDUE received, but not yet implemented.\n");
6320 break;
6321
6322 case SIR_MISSING_SAVE:
6323 /*-----------------------------------------------
6324 **
6325 ** We received an DISCONNECT message,
6326 ** but the datapointer wasn't saved before.
6327 **
6328 **-----------------------------------------------
6329 */
6330
6331 PRINT_ADDR(cp->ccb);
6332 printf ("MSG_DISCONNECT received, but datapointer not saved:\n"
6333 "\tdata=%x save=%x goal=%x.\n",
6334 (unsigned) INL (nc_temp),
6335 (unsigned) np->header.savep,
6336 (unsigned) np->header.goalp);
6337 break;
6338
6339 /*--------------------------------------------------------------------
6340 **
6341 ** Processing of a "SCSI_STATUS_QUEUE_FULL" status.
6342 **
6343 ** XXX JGibbs - We should do the same thing for BUSY status.
6344 **
6345 ** The current command has been rejected,
6346 ** because there are too many in the command queue.
6347 ** We have started too many commands for that target.
6348 **
6349 **--------------------------------------------------------------------
6350 */
6351 case SIR_STALL_QUEUE:
6352 cp->xerr_status = XE_OK;
6353 cp->host_status = HS_COMPLETE;
6354 cp->s_status = SCSI_STATUS_QUEUE_FULL;
6355 ncr_freeze_devq(np, cp->ccb->ccb_h.path);
6356 ncr_complete(np, cp);
6357
6358 /* FALL THROUGH */
6359
6360 case SIR_STALL_RESTART:
6361 /*-----------------------------------------------
6362 **
6363 ** Enable selecting again,
6364 ** if NO disconnected jobs.
6365 **
6366 **-----------------------------------------------
6367 */
6368 /*
6369 ** Look for a disconnected job.
6370 */
6371 cp = np->link_nccb;
6372 while (cp && cp->host_status != HS_DISCONNECT)
6373 cp = cp->link_nccb;
6374
6375 /*
6376 ** if there is one, ...
6377 */
6378 if (cp) {
6379 /*
6380 ** wait for reselection
6381 */
6382 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, reselect));
6383 return;
6384 };
6385
6386 /*
6387 ** else remove the interrupt.
6388 */
6389
6390 printf ("%s: queue empty.\n", ncr_name (np));
6391 WRITESCRIPT(start1[0], SCR_INT ^ IFFALSE (0));
6392 break;
6393 };
6394
6395 out:
6396 OUTB (nc_dcntl, np->rv_dcntl | STD);
6397 }
6398
6399 /*==========================================================
6400 **
6401 **
6402 ** Aquire a control block
6403 **
6404 **
6405 **==========================================================
6406 */
6407
6408 static nccb_p ncr_get_nccb
6409 (ncb_p np, u_long target, u_long lun)
6410 {
6411 lcb_p lp;
6412 int s;
6413 nccb_p cp = NULL;
6414
6415 /* Keep our timeout handler out */
6416 s = splsoftclock();
6417
6418 /*
6419 ** Lun structure available ?
6420 */
6421
6422 lp = np->target[target].lp[lun];
6423 if (lp) {
6424 cp = lp->next_nccb;
6425
6426 /*
6427 ** Look for free CCB
6428 */
6429
6430 while (cp && cp->magic) {
6431 cp = cp->next_nccb;
6432 }
6433 }
6434
6435 /*
6436 ** if nothing available, create one.
6437 */
6438
6439 if (cp == NULL)
6440 cp = ncr_alloc_nccb(np, target, lun);
6441
6442 if (cp != NULL) {
6443 if (cp->magic) {
6444 printf("%s: Bogus free cp found\n", ncr_name(np));
6445 splx(s);
6446 return (NULL);
6447 }
6448 cp->magic = 1;
6449 }
6450 splx(s);
6451 return (cp);
6452 }
6453
6454 /*==========================================================
6455 **
6456 **
6457 ** Release one control block
6458 **
6459 **
6460 **==========================================================
6461 */
6462
6463 void ncr_free_nccb (ncb_p np, nccb_p cp)
6464 {
6465 /*
6466 ** sanity
6467 */
6468
6469 assert (cp != NULL);
6470
6471 cp -> host_status = HS_IDLE;
6472 cp -> magic = 0;
6473 }
6474
6475 /*==========================================================
6476 **
6477 **
6478 ** Allocation of resources for Targets/Luns/Tags.
6479 **
6480 **
6481 **==========================================================
6482 */
6483
6484 static nccb_p
6485 ncr_alloc_nccb (ncb_p np, u_long target, u_long lun)
6486 {
6487 tcb_p tp;
6488 lcb_p lp;
6489 nccb_p cp;
6490
6491 assert (np != NULL);
6492
6493 if (target>=MAX_TARGET) return(NULL);
6494 if (lun >=MAX_LUN ) return(NULL);
6495
6496 tp=&np->target[target];
6497
6498 if (!tp->jump_tcb.l_cmd) {
6499
6500 /*
6501 ** initialize it.
6502 */
6503 tp->jump_tcb.l_cmd = (SCR_JUMP^IFFALSE (DATA (0x80 + target)));
6504 tp->jump_tcb.l_paddr = np->jump_tcb.l_paddr;
6505
6506 tp->getscr[0] =
6507 (np->features & FE_PFEN)? SCR_COPY(1) : SCR_COPY_F(1);
6508 tp->getscr[1] = vtophys (&tp->tinfo.sval);
6509 tp->getscr[2] = rman_get_start(np->reg_res) + offsetof (struct ncr_reg, nc_sxfer);
6510 tp->getscr[3] =
6511 (np->features & FE_PFEN)? SCR_COPY(1) : SCR_COPY_F(1);
6512 tp->getscr[4] = vtophys (&tp->tinfo.wval);
6513 tp->getscr[5] = rman_get_start(np->reg_res) + offsetof (struct ncr_reg, nc_scntl3);
6514
6515 assert (((offsetof(struct ncr_reg, nc_sxfer) ^
6516 (offsetof(struct tcb ,tinfo)
6517 + offsetof(struct ncr_target_tinfo, sval))) & 3) == 0);
6518 assert (((offsetof(struct ncr_reg, nc_scntl3) ^
6519 (offsetof(struct tcb, tinfo)
6520 + offsetof(struct ncr_target_tinfo, wval))) &3) == 0);
6521
6522 tp->call_lun.l_cmd = (SCR_CALL);
6523 tp->call_lun.l_paddr = NCB_SCRIPT_PHYS (np, resel_lun);
6524
6525 tp->jump_lcb.l_cmd = (SCR_JUMP);
6526 tp->jump_lcb.l_paddr = NCB_SCRIPTH_PHYS (np, abort);
6527 np->jump_tcb.l_paddr = vtophys (&tp->jump_tcb);
6528 }
6529
6530 /*
6531 ** Logic unit control block
6532 */
6533 lp = tp->lp[lun];
6534 if (!lp) {
6535 /*
6536 ** Allocate a lcb
6537 */
6538 lp = (lcb_p) malloc (sizeof (struct lcb), M_DEVBUF, M_NOWAIT);
6539 if (!lp) return(NULL);
6540
6541 /*
6542 ** Initialize it
6543 */
6544 bzero (lp, sizeof (*lp));
6545 lp->jump_lcb.l_cmd = (SCR_JUMP ^ IFFALSE (DATA (lun)));
6546 lp->jump_lcb.l_paddr = tp->jump_lcb.l_paddr;
6547
6548 lp->call_tag.l_cmd = (SCR_CALL);
6549 lp->call_tag.l_paddr = NCB_SCRIPT_PHYS (np, resel_tag);
6550
6551 lp->jump_nccb.l_cmd = (SCR_JUMP);
6552 lp->jump_nccb.l_paddr = NCB_SCRIPTH_PHYS (np, aborttag);
6553
6554 lp->actlink = 1;
6555
6556 /*
6557 ** Chain into LUN list
6558 */
6559 tp->jump_lcb.l_paddr = vtophys (&lp->jump_lcb);
6560 tp->lp[lun] = lp;
6561
6562 }
6563
6564 /*
6565 ** Allocate a nccb
6566 */
6567 cp = (nccb_p) malloc (sizeof (struct nccb), M_DEVBUF, M_NOWAIT);
6568
6569 if (!cp)
6570 return (NULL);
6571
6572 if (DEBUG_FLAGS & DEBUG_ALLOC) {
6573 printf ("new nccb @%p.\n", cp);
6574 }
6575
6576 /*
6577 ** Initialize it
6578 */
6579 bzero (cp, sizeof (*cp));
6580
6581 /*
6582 ** Fill in physical addresses
6583 */
6584
6585 cp->p_nccb = vtophys (cp);
6586
6587 /*
6588 ** Chain into reselect list
6589 */
6590 cp->jump_nccb.l_cmd = SCR_JUMP;
6591 cp->jump_nccb.l_paddr = lp->jump_nccb.l_paddr;
6592 lp->jump_nccb.l_paddr = CCB_PHYS (cp, jump_nccb);
6593 cp->call_tmp.l_cmd = SCR_CALL;
6594 cp->call_tmp.l_paddr = NCB_SCRIPT_PHYS (np, resel_tmp);
6595
6596 /*
6597 ** Chain into wakeup list
6598 */
6599 cp->link_nccb = np->link_nccb;
6600 np->link_nccb = cp;
6601
6602 /*
6603 ** Chain into CCB list
6604 */
6605 cp->next_nccb = lp->next_nccb;
6606 lp->next_nccb = cp;
6607
6608 return (cp);
6609 }
6610
6611 /*==========================================================
6612 **
6613 **
6614 ** Build Scatter Gather Block
6615 **
6616 **
6617 **==========================================================
6618 **
6619 ** The transfer area may be scattered among
6620 ** several non adjacent physical pages.
6621 **
6622 ** We may use MAX_SCATTER blocks.
6623 **
6624 **----------------------------------------------------------
6625 */
6626
6627 static int ncr_scatter
6628 (struct dsb* phys, vm_offset_t vaddr, vm_size_t datalen)
6629 {
6630 u_long paddr, pnext;
6631
6632 u_short segment = 0;
6633 u_long segsize, segaddr;
6634 u_long size, csize = 0;
6635 u_long chunk = MAX_SIZE;
6636 int free;
6637
6638 bzero (&phys->data, sizeof (phys->data));
6639 if (!datalen) return (0);
6640
6641 paddr = vtophys (vaddr);
6642
6643 /*
6644 ** insert extra break points at a distance of chunk.
6645 ** We try to reduce the number of interrupts caused
6646 ** by unexpected phase changes due to disconnects.
6647 ** A typical harddisk may disconnect before ANY block.
6648 ** If we wanted to avoid unexpected phase changes at all
6649 ** we had to use a break point every 512 bytes.
6650 ** Of course the number of scatter/gather blocks is
6651 ** limited.
6652 */
6653
6654 free = MAX_SCATTER - 1;
6655
6656 if (vaddr & PAGE_MASK) free -= datalen / PAGE_SIZE;
6657
6658 if (free>1)
6659 while ((chunk * free >= 2 * datalen) && (chunk>=1024))
6660 chunk /= 2;
6661
6662 if(DEBUG_FLAGS & DEBUG_SCATTER)
6663 printf("ncr?:\tscattering virtual=%p size=%d chunk=%d.\n",
6664 (void *) vaddr, (unsigned) datalen, (unsigned) chunk);
6665
6666 /*
6667 ** Build data descriptors.
6668 */
6669 while (datalen && (segment < MAX_SCATTER)) {
6670
6671 /*
6672 ** this segment is empty
6673 */
6674 segsize = 0;
6675 segaddr = paddr;
6676 pnext = paddr;
6677
6678 if (!csize) csize = chunk;
6679
6680 while ((datalen) && (paddr == pnext) && (csize)) {
6681
6682 /*
6683 ** continue this segment
6684 */
6685 pnext = (paddr & (~PAGE_MASK)) + PAGE_SIZE;
6686
6687 /*
6688 ** Compute max size
6689 */
6690
6691 size = pnext - paddr; /* page size */
6692 if (size > datalen) size = datalen; /* data size */
6693 if (size > csize ) size = csize ; /* chunksize */
6694
6695 segsize += size;
6696 vaddr += size;
6697 csize -= size;
6698 datalen -= size;
6699 paddr = vtophys (vaddr);
6700 };
6701
6702 if(DEBUG_FLAGS & DEBUG_SCATTER)
6703 printf ("\tseg #%d addr=%x size=%d (rest=%d).\n",
6704 segment,
6705 (unsigned) segaddr,
6706 (unsigned) segsize,
6707 (unsigned) datalen);
6708
6709 phys->data[segment].addr = segaddr;
6710 phys->data[segment].size = segsize;
6711 segment++;
6712 }
6713
6714 if (datalen) {
6715 printf("ncr?: scatter/gather failed (residue=%d).\n",
6716 (unsigned) datalen);
6717 return (-1);
6718 };
6719
6720 return (segment);
6721 }
6722
6723 /*==========================================================
6724 **
6725 **
6726 ** Test the pci bus snoop logic :-(
6727 **
6728 ** Has to be called with interrupts disabled.
6729 **
6730 **
6731 **==========================================================
6732 */
6733
6734 #ifndef NCR_IOMAPPED
6735 static int ncr_regtest (struct ncb* np)
6736 {
6737 register volatile u_int32_t data;
6738 /*
6739 ** ncr registers may NOT be cached.
6740 ** write 0xffffffff to a read only register area,
6741 ** and try to read it back.
6742 */
6743 data = 0xffffffff;
6744 OUTL_OFF(offsetof(struct ncr_reg, nc_dstat), data);
6745 data = INL_OFF(offsetof(struct ncr_reg, nc_dstat));
6746 #if 1
6747 if (data == 0xffffffff) {
6748 #else
6749 if ((data & 0xe2f0fffd) != 0x02000080) {
6750 #endif
6751 printf ("CACHE TEST FAILED: reg dstat-sstat2 readback %x.\n",
6752 (unsigned) data);
6753 return (0x10);
6754 };
6755 return (0);
6756 }
6757 #endif
6758
6759 static int ncr_snooptest (struct ncb* np)
6760 {
6761 u_int32_t ncr_rd, ncr_wr, ncr_bk, host_rd, host_wr, pc;
6762 int i, err=0;
6763 #ifndef NCR_IOMAPPED
6764 err |= ncr_regtest (np);
6765 if (err) return (err);
6766 #endif
6767 /*
6768 ** init
6769 */
6770 pc = NCB_SCRIPTH_PHYS (np, snooptest);
6771 host_wr = 1;
6772 ncr_wr = 2;
6773 /*
6774 ** Set memory and register.
6775 */
6776 ncr_cache = host_wr;
6777 OUTL (nc_temp, ncr_wr);
6778 /*
6779 ** Start script (exchange values)
6780 */
6781 OUTL (nc_dsp, pc);
6782 /*
6783 ** Wait 'til done (with timeout)
6784 */
6785 for (i=0; i<NCR_SNOOP_TIMEOUT; i++)
6786 if (INB(nc_istat) & (INTF|SIP|DIP))
6787 break;
6788 /*
6789 ** Save termination position.
6790 */
6791 pc = INL (nc_dsp);
6792 /*
6793 ** Read memory and register.
6794 */
6795 host_rd = ncr_cache;
6796 ncr_rd = INL (nc_scratcha);
6797 ncr_bk = INL (nc_temp);
6798 /*
6799 ** Reset ncr chip
6800 */
6801 OUTB (nc_istat, SRST);
6802 DELAY (1000);
6803 OUTB (nc_istat, 0 );
6804 /*
6805 ** check for timeout
6806 */
6807 if (i>=NCR_SNOOP_TIMEOUT) {
6808 printf ("CACHE TEST FAILED: timeout.\n");
6809 return (0x20);
6810 };
6811 /*
6812 ** Check termination position.
6813 */
6814 if (pc != NCB_SCRIPTH_PHYS (np, snoopend)+8) {
6815 printf ("CACHE TEST FAILED: script execution failed.\n");
6816 printf ("start=%08lx, pc=%08lx, end=%08lx\n",
6817 (u_long) NCB_SCRIPTH_PHYS (np, snooptest), (u_long) pc,
6818 (u_long) NCB_SCRIPTH_PHYS (np, snoopend) +8);
6819 return (0x40);
6820 };
6821 /*
6822 ** Show results.
6823 */
6824 if (host_wr != ncr_rd) {
6825 printf ("CACHE TEST FAILED: host wrote %d, ncr read %d.\n",
6826 (int) host_wr, (int) ncr_rd);
6827 err |= 1;
6828 };
6829 if (host_rd != ncr_wr) {
6830 printf ("CACHE TEST FAILED: ncr wrote %d, host read %d.\n",
6831 (int) ncr_wr, (int) host_rd);
6832 err |= 2;
6833 };
6834 if (ncr_bk != ncr_wr) {
6835 printf ("CACHE TEST FAILED: ncr wrote %d, read back %d.\n",
6836 (int) ncr_wr, (int) ncr_bk);
6837 err |= 4;
6838 };
6839 return (err);
6840 }
6841
6842 /*==========================================================
6843 **
6844 **
6845 ** Profiling the drivers and targets performance.
6846 **
6847 **
6848 **==========================================================
6849 */
6850
6851 /*
6852 ** Compute the difference in milliseconds.
6853 **/
6854
6855 static int ncr_delta (int *from, int *to)
6856 {
6857 if (!from) return (-1);
6858 if (!to) return (-2);
6859 return ((to - from) * 1000 / hz);
6860 }
6861
6862 #define PROFILE cp->phys.header.stamp
6863 static void ncb_profile (ncb_p np, nccb_p cp)
6864 {
6865 int co, da, st, en, di, se, post,work,disc;
6866 u_long diff;
6867
6868 PROFILE.end = ticks;
6869
6870 st = ncr_delta (&PROFILE.start,&PROFILE.status);
6871 if (st<0) return; /* status not reached */
6872
6873 da = ncr_delta (&PROFILE.start,&PROFILE.data);
6874 if (da<0) return; /* No data transfer phase */
6875
6876 co = ncr_delta (&PROFILE.start,&PROFILE.command);
6877 if (co<0) return; /* command not executed */
6878
6879 en = ncr_delta (&PROFILE.start,&PROFILE.end),
6880 di = ncr_delta (&PROFILE.start,&PROFILE.disconnect),
6881 se = ncr_delta (&PROFILE.start,&PROFILE.select);
6882 post = en - st;
6883
6884 /*
6885 ** @PROFILE@ Disconnect time invalid if multiple disconnects
6886 */
6887
6888 if (di>=0) disc = se-di; else disc = 0;
6889
6890 work = (st - co) - disc;
6891
6892 diff = (np->disc_phys - np->disc_ref) & 0xff;
6893 np->disc_ref += diff;
6894
6895 np->profile.num_trans += 1;
6896 if (cp->ccb)
6897 np->profile.num_bytes += cp->ccb->csio.dxfer_len;
6898 np->profile.num_disc += diff;
6899 np->profile.ms_setup += co;
6900 np->profile.ms_data += work;
6901 np->profile.ms_disc += disc;
6902 np->profile.ms_post += post;
6903 }
6904 #undef PROFILE
6905
6906 /*==========================================================
6907 **
6908 ** Determine the ncr's clock frequency.
6909 ** This is essential for the negotiation
6910 ** of the synchronous transfer rate.
6911 **
6912 **==========================================================
6913 **
6914 ** Note: we have to return the correct value.
6915 ** THERE IS NO SAVE DEFAULT VALUE.
6916 **
6917 ** Most NCR/SYMBIOS boards are delivered with a 40 Mhz clock.
6918 ** 53C860 and 53C875 rev. 1 support fast20 transfers but
6919 ** do not have a clock doubler and so are provided with a
6920 ** 80 MHz clock. All other fast20 boards incorporate a doubler
6921 ** and so should be delivered with a 40 MHz clock.
6922 ** The future fast40 chips (895/895) use a 40 Mhz base clock
6923 ** and provide a clock quadrupler (160 Mhz). The code below
6924 ** tries to deal as cleverly as possible with all this stuff.
6925 **
6926 **----------------------------------------------------------
6927 */
6928
6929 /*
6930 * Select NCR SCSI clock frequency
6931 */
6932 static void ncr_selectclock(ncb_p np, u_char scntl3)
6933 {
6934 if (np->multiplier < 2) {
6935 OUTB(nc_scntl3, scntl3);
6936 return;
6937 }
6938
6939 if (bootverbose >= 2)
6940 printf ("%s: enabling clock multiplier\n", ncr_name(np));
6941
6942 OUTB(nc_stest1, DBLEN); /* Enable clock multiplier */
6943 if (np->multiplier > 2) { /* Poll bit 5 of stest4 for quadrupler */
6944 int i = 20;
6945 while (!(INB(nc_stest4) & LCKFRQ) && --i > 0)
6946 DELAY(20);
6947 if (!i)
6948 printf("%s: the chip cannot lock the frequency\n", ncr_name(np));
6949 } else /* Wait 20 micro-seconds for doubler */
6950 DELAY(20);
6951 OUTB(nc_stest3, HSC); /* Halt the scsi clock */
6952 OUTB(nc_scntl3, scntl3);
6953 OUTB(nc_stest1, (DBLEN|DBLSEL));/* Select clock multiplier */
6954 OUTB(nc_stest3, 0x00); /* Restart scsi clock */
6955 }
6956
6957 /*
6958 * calculate NCR SCSI clock frequency (in KHz)
6959 */
6960 static unsigned
6961 ncrgetfreq (ncb_p np, int gen)
6962 {
6963 int ms = 0;
6964 /*
6965 * Measure GEN timer delay in order
6966 * to calculate SCSI clock frequency
6967 *
6968 * This code will never execute too
6969 * many loop iterations (if DELAY is
6970 * reasonably correct). It could get
6971 * too low a delay (too high a freq.)
6972 * if the CPU is slow executing the
6973 * loop for some reason (an NMI, for
6974 * example). For this reason we will
6975 * if multiple measurements are to be
6976 * performed trust the higher delay
6977 * (lower frequency returned).
6978 */
6979 OUTB (nc_stest1, 0); /* make sure clock doubler is OFF */
6980 OUTW (nc_sien , 0); /* mask all scsi interrupts */
6981 (void) INW (nc_sist); /* clear pending scsi interrupt */
6982 OUTB (nc_dien , 0); /* mask all dma interrupts */
6983 (void) INW (nc_sist); /* another one, just to be sure :) */
6984 OUTB (nc_scntl3, 4); /* set pre-scaler to divide by 3 */
6985 OUTB (nc_stime1, 0); /* disable general purpose timer */
6986 OUTB (nc_stime1, gen); /* set to nominal delay of (1<<gen) * 125us */
6987 while (!(INW(nc_sist) & GEN) && ms++ < 1000)
6988 DELAY(1000); /* count ms */
6989 OUTB (nc_stime1, 0); /* disable general purpose timer */
6990 OUTB (nc_scntl3, 0);
6991 /*
6992 * Set prescaler to divide by whatever "" means.
6993 * "" ought to choose divide by 2, but appears
6994 * to set divide by 3.5 mode in my 53c810 ...
6995 */
6996 OUTB (nc_scntl3, 0);
6997
6998 if (bootverbose >= 2)
6999 printf ("\tDelay (GEN=%d): %u msec\n", gen, ms);
7000 /*
7001 * adjust for prescaler, and convert into KHz
7002 */
7003 return ms ? ((1 << gen) * 4440) / ms : 0;
7004 }
7005
7006 static void ncr_getclock (ncb_p np, u_char multiplier)
7007 {
7008 unsigned char scntl3;
7009 unsigned char stest1;
7010 scntl3 = INB(nc_scntl3);
7011 stest1 = INB(nc_stest1);
7012
7013 np->multiplier = 1;
7014
7015 if (multiplier > 1) {
7016 np->multiplier = multiplier;
7017 np->clock_khz = 40000 * multiplier;
7018 } else {
7019 if ((scntl3 & 7) == 0) {
7020 unsigned f1, f2;
7021 /* throw away first result */
7022 (void) ncrgetfreq (np, 11);
7023 f1 = ncrgetfreq (np, 11);
7024 f2 = ncrgetfreq (np, 11);
7025
7026 if (bootverbose >= 2)
7027 printf ("\tNCR clock is %uKHz, %uKHz\n", f1, f2);
7028 if (f1 > f2) f1 = f2; /* trust lower result */
7029 if (f1 > 45000) {
7030 scntl3 = 5; /* >45Mhz: assume 80MHz */
7031 } else {
7032 scntl3 = 3; /* <45Mhz: assume 40MHz */
7033 }
7034 }
7035 else if ((scntl3 & 7) == 5)
7036 np->clock_khz = 80000; /* Probably a 875 rev. 1 ? */
7037 }
7038 }
7039
7040 /*=========================================================================*/
7041
7042 #ifdef NCR_TEKRAM_EEPROM
7043
7044 struct tekram_eeprom_dev {
7045 u_char devmode;
7046 #define TKR_PARCHK 0x01
7047 #define TKR_TRYSYNC 0x02
7048 #define TKR_ENDISC 0x04
7049 #define TKR_STARTUNIT 0x08
7050 #define TKR_USETAGS 0x10
7051 #define TKR_TRYWIDE 0x20
7052 u_char syncparam; /* max. sync transfer rate (table ?) */
7053 u_char filler1;
7054 u_char filler2;
7055 };
7056
7057
7058 struct tekram_eeprom {
7059 struct tekram_eeprom_dev
7060 dev[16];
7061 u_char adaptid;
7062 u_char adaptmode;
7063 #define TKR_ADPT_GT2DRV 0x01
7064 #define TKR_ADPT_GT1GB 0x02
7065 #define TKR_ADPT_RSTBUS 0x04
7066 #define TKR_ADPT_ACTNEG 0x08
7067 #define TKR_ADPT_NOSEEK 0x10
7068 #define TKR_ADPT_MORLUN 0x20
7069 u_char delay; /* unit ? ( table ??? ) */
7070 u_char tags; /* use 4 times as many ... */
7071 u_char filler[60];
7072 };
7073
7074 static void
7075 tekram_write_bit (ncb_p np, int bit)
7076 {
7077 u_char val = 0x10 + ((bit & 1) << 1);
7078
7079 DELAY(10);
7080 OUTB (nc_gpreg, val);
7081 DELAY(10);
7082 OUTB (nc_gpreg, val | 0x04);
7083 DELAY(10);
7084 OUTB (nc_gpreg, val);
7085 DELAY(10);
7086 }
7087
7088 static int
7089 tekram_read_bit (ncb_p np)
7090 {
7091 OUTB (nc_gpreg, 0x10);
7092 DELAY(10);
7093 OUTB (nc_gpreg, 0x14);
7094 DELAY(10);
7095 return INB (nc_gpreg) & 1;
7096 }
7097
7098 static u_short
7099 read_tekram_eeprom_reg (ncb_p np, int reg)
7100 {
7101 int bit;
7102 u_short result = 0;
7103 int cmd = 0x80 | reg;
7104
7105 OUTB (nc_gpreg, 0x10);
7106
7107 tekram_write_bit (np, 1);
7108 for (bit = 7; bit >= 0; bit--)
7109 {
7110 tekram_write_bit (np, cmd >> bit);
7111 }
7112
7113 for (bit = 0; bit < 16; bit++)
7114 {
7115 result <<= 1;
7116 result |= tekram_read_bit (np);
7117 }
7118
7119 OUTB (nc_gpreg, 0x00);
7120 return result;
7121 }
7122
7123 static int
7124 read_tekram_eeprom(ncb_p np, struct tekram_eeprom *buffer)
7125 {
7126 u_short *p = (u_short *) buffer;
7127 u_short sum = 0;
7128 int i;
7129
7130 if (INB (nc_gpcntl) != 0x09)
7131 {
7132 return 0;
7133 }
7134 for (i = 0; i < 64; i++)
7135 {
7136 u_short val;
7137 if((i&0x0f) == 0) printf ("%02x:", i*2);
7138 val = read_tekram_eeprom_reg (np, i);
7139 if (p)
7140 *p++ = val;
7141 sum += val;
7142 if((i&0x01) == 0x00) printf (" ");
7143 printf ("%02x%02x", val & 0xff, (val >> 8) & 0xff);
7144 if((i&0x0f) == 0x0f) printf ("\n");
7145 }
7146 printf ("Sum = %04x\n", sum);
7147 return sum == 0x1234;
7148 }
7149 #endif /* NCR_TEKRAM_EEPROM */
7150
7151 static device_method_t ncr_methods[] = {
7152 /* Device interface */
7153 DEVMETHOD(device_probe, ncr_probe),
7154 DEVMETHOD(device_attach, ncr_attach),
7155
7156 { 0, 0 }
7157 };
7158
7159 static driver_t ncr_driver = {
7160 "ncr",
7161 ncr_methods,
7162 sizeof(struct ncb),
7163 };
7164
7165 static devclass_t ncr_devclass;
7166
7167 DRIVER_MODULE(if_ncr, pci, ncr_driver, ncr_devclass, 0, 0);
7168
7169 /*=========================================================================*/
7170 #endif /* _KERNEL */
Cache object: afd189be8420fe2be75a34d2e8b02ba1
|