FreeBSD/Linux Kernel Cross Reference
sys/pci/ncrreg.h
1 /**************************************************************************
2 **
3 ** $FreeBSD: releng/5.3/sys/pci/ncrreg.h 50477 1999-08-28 01:08:13Z peter $
4 **
5 ** Device driver for the NCR 53C810 PCI-SCSI-Controller.
6 **
7 ** 386bsd / FreeBSD / NetBSD
8 **
9 **-------------------------------------------------------------------------
10 **
11 ** Written for 386bsd and FreeBSD by
12 ** wolf@cologne.de Wolfgang Stanglmeier
13 ** se@mi.Uni-Koeln.de Stefan Esser
14 **
15 ** Ported to NetBSD by
16 ** mycroft@gnu.ai.mit.edu
17 **
18 **-------------------------------------------------------------------------
19 **
20 ** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved.
21 **
22 ** Redistribution and use in source and binary forms, with or without
23 ** modification, are permitted provided that the following conditions
24 ** are met:
25 ** 1. Redistributions of source code must retain the above copyright
26 ** notice, this list of conditions and the following disclaimer.
27 ** 2. Redistributions in binary form must reproduce the above copyright
28 ** notice, this list of conditions and the following disclaimer in the
29 ** documentation and/or other materials provided with the distribution.
30 ** 3. The name of the author may not be used to endorse or promote products
31 ** derived from this software without specific prior written permission.
32 **
33 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
34 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
35 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
36 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
37 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
38 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
39 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
40 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
42 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 **
44 ***************************************************************************
45 */
46
47 #ifndef __NCR_REG_H__
48 #define __NCR_REG_H__
49
50 /*-----------------------------------------------------------------
51 **
52 ** The ncr 53c810 register structure.
53 **
54 **-----------------------------------------------------------------
55 */
56
57 struct ncr_reg {
58 /*00*/ u_char nc_scntl0; /* full arb., ena parity, par->ATN */
59
60 /*01*/ u_char nc_scntl1; /* no reset */
61 #define ISCON 0x10 /* connected to scsi */
62 #define CRST 0x08 /* force reset */
63
64 /*02*/ u_char nc_scntl2; /* no disconnect expected */
65 #define SDU 0x80 /* cmd: disconnect will raise error */
66 #define CHM 0x40 /* sta: chained mode */
67 #define WSS 0x08 /* sta: wide scsi send [W]*/
68 #define WSR 0x01 /* sta: wide scsi received [W]*/
69
70 /*03*/ u_char nc_scntl3; /* cnf system clock dependent */
71 #define EWS 0x08 /* cmd: enable wide scsi [W]*/
72
73 /*04*/ u_char nc_scid; /* cnf host adapter scsi address */
74 #define RRE 0x40 /* r/w:e enable response to resel. */
75 #define SRE 0x20 /* r/w:e enable response to select */
76
77 /*05*/ u_char nc_sxfer; /* ### Sync speed and count */
78
79 /*06*/ u_char nc_sdid; /* ### Destination-ID */
80
81 /*07*/ u_char nc_gpreg; /* ??? IO-Pins */
82
83 /*08*/ u_char nc_sfbr; /* ### First byte in phase */
84
85 /*09*/ u_char nc_socl;
86 #define CREQ 0x80 /* r/w: SCSI-REQ */
87 #define CACK 0x40 /* r/w: SCSI-ACK */
88 #define CBSY 0x20 /* r/w: SCSI-BSY */
89 #define CSEL 0x10 /* r/w: SCSI-SEL */
90 #define CATN 0x08 /* r/w: SCSI-ATN */
91 #define CMSG 0x04 /* r/w: SCSI-MSG */
92 #define CC_D 0x02 /* r/w: SCSI-C_D */
93 #define CI_O 0x01 /* r/w: SCSI-I_O */
94
95 /*0a*/ u_char nc_ssid;
96
97 /*0b*/ u_char nc_sbcl;
98
99 /*0c*/ u_char nc_dstat;
100 #define DFE 0x80 /* sta: dma fifo empty */
101 #define MDPE 0x40 /* int: master data parity error */
102 #define BF 0x20 /* int: script: bus fault */
103 #define ABRT 0x10 /* int: script: command aborted */
104 #define SSI 0x08 /* int: script: single step */
105 #define SIR 0x04 /* int: script: interrupt instruct. */
106 #define IID 0x01 /* int: script: illegal instruct. */
107
108 /*0d*/ u_char nc_sstat0;
109 #define ILF 0x80 /* sta: data in SIDL register lsb */
110 #define ORF 0x40 /* sta: data in SODR register lsb */
111 #define OLF 0x20 /* sta: data in SODL register lsb */
112 #define AIP 0x10 /* sta: arbitration in progress */
113 #define LOA 0x08 /* sta: arbitration lost */
114 #define WOA 0x04 /* sta: arbitration won */
115 #define IRST 0x02 /* sta: scsi reset signal */
116 #define SDP 0x01 /* sta: scsi parity signal */
117
118 /*0e*/ u_char nc_sstat1;
119 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
120
121 /*0f*/ u_char nc_sstat2;
122 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
123 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
124 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
125 #define LDSC 0x02 /* sta: disconnect & reconnect */
126
127 /*10*/ u_int32_t nc_dsa; /* --> Base page */
128
129 /*14*/ u_char nc_istat; /* --> Main Command and status */
130 #define CABRT 0x80 /* cmd: abort current operation */
131 #define SRST 0x40 /* mod: reset chip */
132 #define SIGP 0x20 /* r/w: message from host to ncr */
133 #define SEM 0x10 /* r/w: message between host + ncr */
134 #define CON 0x08 /* sta: connected to scsi */
135 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
136 #define SIP 0x02 /* sta: scsi-interrupt */
137 #define DIP 0x01 /* sta: host/script interrupt */
138
139 /*15*/ u_char nc_15_;
140 /*16*/ u_char nc_16_;
141 /*17*/ u_char nc_17_;
142
143 /*18*/ u_char nc_ctest0;
144 /*19*/ u_char nc_ctest1;
145
146 /*1a*/ u_char nc_ctest2;
147 #define CSIGP 0x40
148
149 /*1b*/ u_char nc_ctest3;
150 #define FLF 0x08 /* cmd: flush dma fifo */
151 #define CLF 0x04 /* cmd: clear dma fifo */
152 #define FM 0x02 /* mod: fetch pin mode */
153 #define WRIE 0x01 /* mod: write and invalidate enable */
154
155 /*1c*/ u_int32_t nc_temp; /* ### Temporary stack */
156
157 /*20*/ u_char nc_dfifo;
158 /*21*/ u_char nc_ctest4;
159 #define BDIS 0x80 /* mod: burst disable */
160 #define MPEE 0x08 /* mod: master parity error enable */
161
162 /*22*/ u_char nc_ctest5;
163 #define DFS 0x20 /* mod: dma fifo size */
164 /*23*/ u_char nc_ctest6;
165
166 /*24*/ u_int32_t nc_dbc; /* ### Byte count and command */
167 /*28*/ u_int32_t nc_dnad; /* ### Next command register */
168 /*2c*/ u_int32_t nc_dsp; /* --> Script Pointer */
169 /*30*/ u_int32_t nc_dsps; /* --> Script pointer save/opcode#2 */
170 /*34*/ u_int32_t nc_scratcha; /* ??? Temporary register a */
171
172 /*38*/ u_char nc_dmode;
173 #define BL_2 0x80 /* mod: burst length shift value +2 */
174 #define BL_1 0x40 /* mod: burst length shift value +1 */
175 #define ERL 0x08 /* mod: enable read line */
176 #define ERMP 0x04 /* mod: enable read multiple */
177 #define BOF 0x02 /* mod: burst op code fetch */
178
179 /*39*/ u_char nc_dien;
180 /*3a*/ u_char nc_dwt;
181
182 /*3b*/ u_char nc_dcntl; /* --> Script execution control */
183 #define CLSE 0x80 /* mod: cache line size enable */
184 #define PFF 0x40 /* cmd: pre-fetch flush */
185 #define PFEN 0x20 /* mod: pre-fetch enable */
186 #define SSM 0x10 /* mod: single step mode */
187 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
188 #define STD 0x04 /* cmd: start dma mode */
189 #define IRQD 0x02 /* mod: irq disable */
190 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
191
192 /*3c*/ u_int32_t nc_adder;
193
194 /*40*/ u_short nc_sien; /* -->: interrupt enable */
195 /*42*/ u_short nc_sist; /* <--: interrupt status */
196 #define STO 0x0400/* sta: timeout (select) */
197 #define GEN 0x0200/* sta: timeout (general) */
198 #define HTH 0x0100/* sta: timeout (handshake) */
199 #define MA 0x80 /* sta: phase mismatch */
200 #define CMP 0x40 /* sta: arbitration complete */
201 #define SEL 0x20 /* sta: selected by another device */
202 #define RSL 0x10 /* sta: reselected by another device*/
203 #define SGE 0x08 /* sta: gross error (over/underflow)*/
204 #define UDC 0x04 /* sta: unexpected disconnect */
205 #define RST 0x02 /* sta: scsi bus reset detected */
206 #define PAR 0x01 /* sta: scsi parity error */
207
208 /*44*/ u_char nc_slpar;
209 /*45*/ u_char nc_swide;
210 /*46*/ u_char nc_macntl;
211 /*47*/ u_char nc_gpcntl;
212 /*48*/ u_char nc_stime0; /* cmd: timeout for select&handshake*/
213 /*49*/ u_char nc_stime1; /* cmd: timeout user defined */
214 /*4a*/ u_short nc_respid; /* sta: Reselect-IDs */
215
216 /*4c*/ u_char nc_stest0;
217
218 /*4d*/ u_char nc_stest1;
219 #define DBLEN 0x08 /* clock doubler running */
220 #define DBLSEL 0x04 /* clock doubler selected */
221
222 /*4e*/ u_char nc_stest2;
223 #define ROF 0x40 /* reset scsi offset (after gross error!) */
224 #define EXT 0x02 /* extended filtering */
225
226 /*4f*/ u_char nc_stest3;
227 #define TE 0x80 /* c: tolerAnt enable */
228 #define HSC 0x20 /* c: Halt SCSI Clock */
229 #define CSF 0x02 /* c: clear scsi fifo */
230
231 /*50*/ u_short nc_sidl; /* Lowlevel: latched from scsi data */
232 /*52*/ u_char nc_stest4;
233 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
234 #define SMODE_HVD 0x40 /* High Voltage Differential */
235 #define SMODE_SE 0x80 /* Single Ended */
236 #define SMODE_LVD 0xc0 /* Low Voltage Differential */
237 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
238
239 /*53*/ u_char nc_53_;
240 /*54*/ u_short nc_sodl; /* Lowlevel: data out to scsi data */
241 /*56*/ u_short nc_56_;
242 /*58*/ u_short nc_sbdl; /* Lowlevel: data from scsi data */
243 /*5a*/ u_short nc_5a_;
244 /*5c*/ u_char nc_scr0; /* Working register B */
245 /*5d*/ u_char nc_scr1; /* */
246 /*5e*/ u_char nc_scr2; /* */
247 /*5f*/ u_char nc_scr3; /* */
248 /*60*/
249 };
250
251 /*-----------------------------------------------------------
252 **
253 ** Utility macros for the script.
254 **
255 **-----------------------------------------------------------
256 */
257
258 #define REGJ(p,r) (offsetof(struct ncr_reg, p ## r))
259 #define REG(r) REGJ (nc_, r)
260
261 #ifndef TARGET_MODE
262 #define TARGET_MODE 0
263 #endif
264
265 typedef u_int32_t ncrcmd;
266
267 /*-----------------------------------------------------------
268 **
269 ** SCSI phases
270 **
271 **-----------------------------------------------------------
272 */
273
274 #define SCR_DATA_OUT 0x00000000
275 #define SCR_DATA_IN 0x01000000
276 #define SCR_COMMAND 0x02000000
277 #define SCR_STATUS 0x03000000
278 #define SCR_ILG_OUT 0x04000000
279 #define SCR_ILG_IN 0x05000000
280 #define SCR_MSG_OUT 0x06000000
281 #define SCR_MSG_IN 0x07000000
282
283 /*-----------------------------------------------------------
284 **
285 ** Data transfer via SCSI.
286 **
287 **-----------------------------------------------------------
288 **
289 ** MOVE_ABS (LEN)
290 ** <<start address>>
291 **
292 ** MOVE_IND (LEN)
293 ** <<dnad_offset>>
294 **
295 ** MOVE_TBL
296 ** <<dnad_offset>>
297 **
298 **-----------------------------------------------------------
299 */
300
301 #define SCR_MOVE_ABS(l) ((0x08000000 ^ (TARGET_MODE << 1ul)) | (l))
302 #define SCR_MOVE_IND(l) ((0x28000000 ^ (TARGET_MODE << 1ul)) | (l))
303 #define SCR_MOVE_TBL (0x18000000 ^ (TARGET_MODE << 1ul))
304
305 struct scr_tblmove {
306 u_int32_t size;
307 u_int32_t addr;
308 };
309
310 /*-----------------------------------------------------------
311 **
312 ** Selection
313 **
314 **-----------------------------------------------------------
315 **
316 ** SEL_ABS | SCR_ID (0..7) [ | REL_JMP]
317 ** <<alternate_address>>
318 **
319 ** SEL_TBL | << dnad_offset>> [ | REL_JMP]
320 ** <<alternate_address>>
321 **
322 **-----------------------------------------------------------
323 */
324
325 #define SCR_SEL_ABS 0x40000000
326 #define SCR_SEL_ABS_ATN 0x41000000
327 #define SCR_SEL_TBL 0x42000000
328 #define SCR_SEL_TBL_ATN 0x43000000
329
330 struct scr_tblsel {
331 u_char sel_0;
332 u_char sel_sxfer;
333 u_char sel_id;
334 u_char sel_scntl3;
335 };
336
337 #define SCR_JMP_REL 0x04000000
338 #define SCR_ID(id) (((u_int32_t)(id)) << 16)
339
340 /*-----------------------------------------------------------
341 **
342 ** Waiting for Disconnect or Reselect
343 **
344 **-----------------------------------------------------------
345 **
346 ** WAIT_DISC
347 ** dummy: <<alternate_address>>
348 **
349 ** WAIT_RESEL
350 ** <<alternate_address>>
351 **
352 **-----------------------------------------------------------
353 */
354
355 #define SCR_WAIT_DISC 0x48000000
356 #define SCR_WAIT_RESEL 0x50000000
357
358 /*-----------------------------------------------------------
359 **
360 ** Bit Set / Reset
361 **
362 **-----------------------------------------------------------
363 **
364 ** SET (flags {|.. })
365 **
366 ** CLR (flags {|.. })
367 **
368 **-----------------------------------------------------------
369 */
370
371 #define SCR_SET(f) (0x58000000 | (f))
372 #define SCR_CLR(f) (0x60000000 | (f))
373
374 #define SCR_CARRY 0x00000400
375 #define SCR_TRG 0x00000200
376 #define SCR_ACK 0x00000040
377 #define SCR_ATN 0x00000008
378
379
380 /*-----------------------------------------------------------
381 **
382 ** Memory to memory move
383 **
384 **-----------------------------------------------------------
385 **
386 ** COPY (bytecount)
387 ** << source_address >>
388 ** << destination_address >>
389 **
390 ** SCR_COPY sets the NO FLUSH option by default.
391 ** SCR_COPY_F does not set this option.
392 **
393 ** For chips which do not support this option,
394 ** ncr_copy_and_bind() will remove this bit.
395 **-----------------------------------------------------------
396 */
397
398 #define SCR_NO_FLUSH 0x01000000
399
400 #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
401 #define SCR_COPY_F(n) (0xc0000000 | (n))
402
403
404 /*-----------------------------------------------------------
405 **
406 ** Register move and binary operations
407 **
408 **-----------------------------------------------------------
409 **
410 ** SFBR_REG (reg, op, data) reg = SFBR op data
411 ** << 0 >>
412 **
413 ** REG_SFBR (reg, op, data) SFBR = reg op data
414 ** << 0 >>
415 **
416 ** REG_REG (reg, op, data) reg = reg op data
417 ** << 0 >>
418 **
419 **-----------------------------------------------------------
420 */
421
422 #define SCR_REG_OFS(ofs) ((ofs) << 16ul)
423
424 #define SCR_SFBR_REG(reg,op,data) \
425 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul))
426
427 #define SCR_REG_SFBR(reg,op,data) \
428 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul))
429
430 #define SCR_REG_REG(reg,op,data) \
431 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul))
432
433
434 #define SCR_LOAD 0x00000000
435 #define SCR_SHL 0x01000000
436 #define SCR_OR 0x02000000
437 #define SCR_XOR 0x03000000
438 #define SCR_AND 0x04000000
439 #define SCR_SHR 0x05000000
440 #define SCR_ADD 0x06000000
441 #define SCR_ADDC 0x07000000
442
443 /*-----------------------------------------------------------
444 **
445 ** FROM_REG (reg) reg = SFBR
446 ** << 0 >>
447 **
448 ** TO_REG (reg) SFBR = reg
449 ** << 0 >>
450 **
451 ** LOAD_REG (reg, data) reg = <data>
452 ** << 0 >>
453 **
454 ** LOAD_SFBR(data) SFBR = <data>
455 ** << 0 >>
456 **
457 **-----------------------------------------------------------
458 */
459
460 #define SCR_FROM_REG(reg) \
461 SCR_REG_SFBR(reg,SCR_OR,0)
462
463 #define SCR_TO_REG(reg) \
464 SCR_SFBR_REG(reg,SCR_OR,0)
465
466 #define SCR_LOAD_REG(reg,data) \
467 SCR_REG_REG(reg,SCR_LOAD,data)
468
469 #define SCR_LOAD_SFBR(data) \
470 (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
471
472 /*-----------------------------------------------------------
473 **
474 ** Waiting for Disconnect or Reselect
475 **
476 **-----------------------------------------------------------
477 **
478 ** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
479 ** <<address>>
480 **
481 ** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
482 ** <<distance>>
483 **
484 ** CALL [ | IFTRUE/IFFALSE ( ... ) ]
485 ** <<address>>
486 **
487 ** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
488 ** <<distance>>
489 **
490 ** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
491 ** <<dummy>>
492 **
493 ** INT [ | IFTRUE/IFFALSE ( ... ) ]
494 ** <<ident>>
495 **
496 ** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
497 ** <<ident>>
498 **
499 ** Conditions:
500 ** WHEN (phase)
501 ** IF (phase)
502 ** CARRY
503 ** DATA (data, mask)
504 **
505 **-----------------------------------------------------------
506 */
507
508 #define SCR_NO_OP 0x80000000
509 #define SCR_JUMP 0x80080000
510 #define SCR_JUMPR 0x80880000
511 #define SCR_CALL 0x88080000
512 #define SCR_CALLR 0x88880000
513 #define SCR_RETURN 0x90080000
514 #define SCR_INT 0x98080000
515 #define SCR_INT_FLY 0x98180000
516
517 #define IFFALSE(arg) (0x00080000 | (arg))
518 #define IFTRUE(arg) (0x00000000 | (arg))
519
520 #define WHEN(phase) (0x00030000 | (phase))
521 #define IF(phase) (0x00020000 | (phase))
522
523 #define DATA(D) (0x00040000 | ((D) & 0xff))
524 #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
525
526 #define CARRYSET (0x00200000)
527
528 /*-----------------------------------------------------------
529 **
530 ** SCSI constants.
531 **
532 **-----------------------------------------------------------
533 */
534
535 /*
536 ** Messages
537 */
538 #define M_X_MODIFY_DP (0x00)
539
540 /*
541 ** Status
542 */
543 #define SCSI_STATUS_ILLEGAL (0xff)
544 #define SCSI_STATUS_SENSE (0x80)
545
546 /*
547 ** Bits defining chip features.
548 ** For now only some of them are used, since we explicitely
549 ** deal with PCI device id and revision id.
550 */
551 #define FE_LED0 (1<<0)
552 #define FE_WIDE (1<<1)
553 #define FE_ULTRA (1<<2)
554 #define FE_ULTRA2 (1<<3)
555 #define FE_DBLR (1<<4)
556 #define FE_QUAD (1<<5)
557 #define FE_ERL (1<<6)
558 #define FE_CLSE (1<<7)
559 #define FE_WRIE (1<<8)
560 #define FE_ERMP (1<<9)
561 #define FE_BOF (1<<10)
562 #define FE_DFS (1<<11)
563 #define FE_PFEN (1<<12)
564 #define FE_LDSTR (1<<13)
565 #define FE_RAM (1<<14)
566 #define FE_CLK80 (1<<15)
567 #define FE_DIFF (1<<16)
568 #define FE_BIOS (1<<17)
569 #define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
570 #define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_ULTRA2|FE_DBLR|FE_QUAD|F_CLK80)
571 #define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM)
572
573 #endif /*__NCR_REG_H__*/
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