Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/pci.c
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1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #include "pci.h" 31 #if NPCI > 0 32 33 #include "opt_devfs.h" 34 #include "opt_simos.h" 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/types.h> 44 #include <sys/buf.h> 45 #ifdef DEVFS 46 #include <sys/devfsext.h> 47 #endif /* DEVFS */ 48 49 #include <vm/vm.h> 50 #include <vm/pmap.h> 51 #include <vm/vm_extern.h> 52 53 #include <pci/pcireg.h> 54 #include <pci/pcivar.h> 55 #include <pci/pci_ioctl.h> 56 57 #ifdef APIC_IO 58 #include <machine/smp.h> 59 #endif /* APIC_IO */ 60 61 STAILQ_HEAD(devlist, pci_devinfo) pci_devq; 62 u_int32_t pci_numdevs = 0; 63 u_int32_t pci_generation = 0; 64 65 /* return highest PCI bus number known to be used, or -1 if none */ 66 67 static int 68 pci_bushigh(void) 69 { 70 if (pci_cfgopen() == 0) 71 return (-1); 72 return (0); 73 } 74 75 /* return base address of memory or port map */ 76 77 static int 78 pci_mapbase(unsigned mapreg) 79 { 80 int mask = 0x03; 81 if ((mapreg & 0x01) == 0) 82 mask = 0x0f; 83 return (mapreg & ~mask); 84 } 85 86 /* return map type of memory or port map */ 87 88 static int 89 pci_maptype(unsigned mapreg) 90 { 91 static u_int8_t maptype[0x10] = { 92 PCI_MAPMEM, PCI_MAPPORT, 93 PCI_MAPMEM, 0, 94 PCI_MAPMEM, PCI_MAPPORT, 95 0, 0, 96 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 97 PCI_MAPMEM|PCI_MAPMEMP, 0, 98 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 99 0, 0, 100 }; 101 102 return maptype[mapreg & 0x0f]; 103 } 104 105 /* return log2 of map size decoded for memory or port map */ 106 107 static int 108 pci_mapsize(unsigned testval) 109 { 110 int ln2size; 111 112 testval = pci_mapbase(testval); 113 ln2size = 0; 114 if (testval != 0) { 115 while ((testval & 1) == 0) 116 { 117 ln2size++; 118 testval >>= 1; 119 } 120 } 121 return (ln2size); 122 } 123 124 /* return log2 of address range supported by map register */ 125 126 static int 127 pci_maprange(unsigned mapreg) 128 { 129 int ln2range = 0; 130 switch (mapreg & 0x07) { 131 case 0x00: 132 case 0x01: 133 case 0x05: 134 ln2range = 32; 135 break; 136 case 0x02: 137 ln2range = 20; 138 break; 139 case 0x04: 140 ln2range = 64; 141 break; 142 } 143 return (ln2range); 144 } 145 146 /* extract map parameters into newly allocated array of pcimap structures */ 147 148 static pcimap * 149 pci_readmaps(pcicfgregs *cfg, int maxmaps) 150 { 151 int i, j = 0; 152 pcimap *map; 153 int map64 = 0; 154 int reg = PCIR_MAPS; 155 156 for (i = 0; i < maxmaps; i++) { 157 int reg = PCIR_MAPS + i*4; 158 u_int32_t base; 159 u_int32_t ln2range; 160 161 base = pci_cfgread(cfg, reg, 4); 162 ln2range = pci_maprange(base); 163 164 if (base == 0 || ln2range == 0 || base == 0xffffffff) 165 continue; /* skip invalid entry */ 166 else { 167 j++; 168 if (ln2range > 32) { 169 i++; 170 j++; 171 } 172 } 173 } 174 175 map = malloc(j * sizeof (pcimap), M_DEVBUF, M_WAITOK); 176 if (map != NULL) { 177 bzero(map, sizeof(pcimap) * j); 178 cfg->nummaps = j; 179 180 for (i = 0, j = 0; i < maxmaps; i++, reg += 4) { 181 u_int32_t base; 182 u_int32_t testval; 183 184 base = pci_cfgread(cfg, reg, 4); 185 186 if (map64 == 0) { 187 if (base == 0 || base == 0xffffffff) 188 continue; /* skip invalid entry */ 189 pci_cfgwrite(cfg, reg, 0xffffffff, 4); 190 testval = pci_cfgread(cfg, reg, 4); 191 pci_cfgwrite(cfg, reg, base, 4); 192 193 map[j].reg = reg; 194 map[j].base = pci_mapbase(base); 195 map[j].type = pci_maptype(base); 196 map[j].ln2size = pci_mapsize(testval); 197 map[j].ln2range = pci_maprange(testval); 198 map64 = map[j].ln2range == 64; 199 } else { 200 /* only fill in base, other fields are 0 */ 201 map[j].base = base; 202 map64 = 0; 203 } 204 j++; 205 } 206 } 207 return (map); 208 } 209 210 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 211 212 static void 213 pci_fixancient(pcicfgregs *cfg) 214 { 215 if (cfg->hdrtype != 0) 216 return; 217 218 /* PCI to PCI bridges use header type 1 */ 219 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 220 cfg->hdrtype = 1; 221 } 222 223 /* read config data specific to header type 1 device (PCI to PCI bridge) */ 224 225 static void * 226 pci_readppb(pcicfgregs *cfg) 227 { 228 pcih1cfgregs *p; 229 230 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK); 231 if (p == NULL) 232 return (NULL); 233 234 bzero(p, sizeof *p); 235 236 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_1, 2); 237 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_1, 2); 238 239 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_1, 1); 240 241 p->iobase = PCI_PPBIOBASE (pci_cfgread(cfg, PCIR_IOBASEH_1, 2), 242 pci_cfgread(cfg, PCIR_IOBASEL_1, 1)); 243 p->iolimit = PCI_PPBIOLIMIT (pci_cfgread(cfg, PCIR_IOLIMITH_1, 2), 244 pci_cfgread(cfg, PCIR_IOLIMITL_1, 1)); 245 246 p->membase = PCI_PPBMEMBASE (0, 247 pci_cfgread(cfg, PCIR_MEMBASE_1, 2)); 248 p->memlimit = PCI_PPBMEMLIMIT (0, 249 pci_cfgread(cfg, PCIR_MEMLIMIT_1, 2)); 250 251 p->pmembase = PCI_PPBMEMBASE ( 252 (pci_addr_t)pci_cfgread(cfg, PCIR_PMBASEH_1, 4), 253 pci_cfgread(cfg, PCIR_PMBASEL_1, 2)); 254 255 p->pmemlimit = PCI_PPBMEMLIMIT ( 256 (pci_addr_t)pci_cfgread(cfg, PCIR_PMLIMITH_1, 4), 257 pci_cfgread(cfg, PCIR_PMLIMITL_1, 2)); 258 return (p); 259 } 260 261 /* read config data specific to header type 2 device (PCI to CardBus bridge) */ 262 263 static void * 264 pci_readpcb(pcicfgregs *cfg) 265 { 266 pcih2cfgregs *p; 267 268 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK); 269 if (p == NULL) 270 return (NULL); 271 272 bzero(p, sizeof *p); 273 274 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_2, 2); 275 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_2, 2); 276 277 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_2, 1); 278 279 p->membase0 = pci_cfgread(cfg, PCIR_MEMBASE0_2, 4); 280 p->memlimit0 = pci_cfgread(cfg, PCIR_MEMLIMIT0_2, 4); 281 p->membase1 = pci_cfgread(cfg, PCIR_MEMBASE1_2, 4); 282 p->memlimit1 = pci_cfgread(cfg, PCIR_MEMLIMIT1_2, 4); 283 284 p->iobase0 = pci_cfgread(cfg, PCIR_IOBASE0_2, 4); 285 p->iolimit0 = pci_cfgread(cfg, PCIR_IOLIMIT0_2, 4); 286 p->iobase1 = pci_cfgread(cfg, PCIR_IOBASE1_2, 4); 287 p->iolimit1 = pci_cfgread(cfg, PCIR_IOLIMIT1_2, 4); 288 289 p->pccardif = pci_cfgread(cfg, PCIR_PCCARDIF_2, 4); 290 return p; 291 } 292 293 /* extract header type specific config data */ 294 295 static void 296 pci_hdrtypedata(pcicfgregs *cfg) 297 { 298 switch (cfg->hdrtype) { 299 case 0: 300 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_0, 2); 301 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_0, 2); 302 cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_0); 303 break; 304 case 1: 305 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_1, 2); 306 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_1, 2); 307 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_1, 1); 308 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_1, 1); 309 cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_1); 310 cfg->hdrspec = pci_readppb(cfg); 311 break; 312 case 2: 313 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_2, 2); 314 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_2, 2); 315 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_2, 1); 316 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_2, 1); 317 cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_2); 318 cfg->hdrspec = pci_readpcb(cfg); 319 break; 320 } 321 } 322 323 /* read configuration header into pcicfgrect structure */ 324 325 static struct pci_devinfo * 326 pci_readcfg(pcicfgregs *probe) 327 { 328 pcicfgregs *cfg = NULL; 329 struct pci_devinfo *devlist_entry; 330 struct devlist *devlist_head; 331 332 devlist_head = &pci_devq; 333 334 devlist_entry = NULL; 335 336 if (pci_cfgread(probe, PCIR_DEVVENDOR, 4) != -1) { 337 devlist_entry = malloc(sizeof(struct pci_devinfo), 338 M_DEVBUF, M_WAITOK); 339 if (devlist_entry == NULL) 340 return (NULL); 341 342 bzero(devlist_entry, sizeof(*devlist_entry)); 343 344 cfg = &devlist_entry->cfg; 345 346 cfg->bus = probe->bus; 347 cfg->slot = probe->slot; 348 cfg->func = probe->func; 349 cfg->vendor = pci_cfgread(cfg, PCIR_VENDOR, 2); 350 cfg->device = pci_cfgread(cfg, PCIR_DEVICE, 2); 351 cfg->cmdreg = pci_cfgread(cfg, PCIR_COMMAND, 2); 352 cfg->statreg = pci_cfgread(cfg, PCIR_STATUS, 2); 353 cfg->baseclass = pci_cfgread(cfg, PCIR_CLASS, 1); 354 cfg->subclass = pci_cfgread(cfg, PCIR_SUBCLASS, 1); 355 cfg->progif = pci_cfgread(cfg, PCIR_PROGIF, 1); 356 cfg->revid = pci_cfgread(cfg, PCIR_REVID, 1); 357 cfg->hdrtype = pci_cfgread(cfg, PCIR_HEADERTYPE, 1); 358 cfg->cachelnsz = pci_cfgread(cfg, PCIR_CACHELNSZ, 1); 359 cfg->lattimer = pci_cfgread(cfg, PCIR_LATTIMER, 1); 360 cfg->intpin = pci_cfgread(cfg, PCIR_INTPIN, 1); 361 cfg->intline = pci_cfgread(cfg, PCIR_INTLINE, 1); 362 #ifdef __alpha__ 363 alpha_platform_assign_pciintr(cfg); 364 #endif 365 366 #ifdef APIC_IO 367 if (cfg->intpin != 0) { 368 int airq; 369 370 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin); 371 if (airq >= 0) { 372 /* PCI specific entry found in MP table */ 373 if (airq != cfg->intline) { 374 undirect_pci_irq(cfg->intline); 375 cfg->intline = airq; 376 } 377 } else { 378 /* 379 * PCI interrupts might be redirected to the 380 * ISA bus according to some MP tables. Use the 381 * same methods as used by the ISA devices 382 * devices to find the proper IOAPIC int pin. 383 */ 384 airq = isa_apic_irq(cfg->intline); 385 if ((airq >= 0) && (airq != cfg->intline)) { 386 /* XXX: undirect_pci_irq() ? */ 387 undirect_isa_irq(cfg->intline); 388 cfg->intline = airq; 389 } 390 } 391 } 392 #endif /* APIC_IO */ 393 394 cfg->mingnt = pci_cfgread(cfg, PCIR_MINGNT, 1); 395 cfg->maxlat = pci_cfgread(cfg, PCIR_MAXLAT, 1); 396 397 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 398 cfg->hdrtype &= ~PCIM_MFDEV; 399 400 pci_fixancient(cfg); 401 pci_hdrtypedata(cfg); 402 403 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 404 405 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 406 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 407 devlist_entry->conf.pc_sel.pc_func = cfg->func; 408 devlist_entry->conf.pc_hdr = cfg->hdrtype; 409 410 devlist_entry->conf.pc_subvendor = cfg->subvendor; 411 devlist_entry->conf.pc_subdevice = cfg->subdevice; 412 devlist_entry->conf.pc_vendor = cfg->vendor; 413 devlist_entry->conf.pc_device = cfg->device; 414 415 devlist_entry->conf.pc_class = cfg->baseclass; 416 devlist_entry->conf.pc_subclass = cfg->subclass; 417 devlist_entry->conf.pc_progif = cfg->progif; 418 devlist_entry->conf.pc_revid = cfg->revid; 419 420 pci_numdevs++; 421 pci_generation++; 422 } 423 return (devlist_entry); 424 } 425 426 #if 0 427 /* free pcicfgregs structure and all depending data structures */ 428 429 static int 430 pci_freecfg(struct pci_devinfo *dinfo) 431 { 432 struct devlist *devlist_head; 433 434 devlist_head = &pci_devq; 435 436 if (dinfo->cfg.hdrspec != NULL) 437 free(dinfo->cfg.hdrspec, M_DEVBUF); 438 if (dinfo->cfg.map != NULL) 439 free(dinfo->cfg.map, M_DEVBUF); 440 /* XXX this hasn't been tested */ 441 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 442 free(dinfo, M_DEVBUF); 443 444 /* increment the generation count */ 445 pci_generation++; 446 447 /* we're losing one device */ 448 pci_numdevs--; 449 return (0); 450 } 451 #endif 452 453 static void 454 pci_addcfg(struct pci_devinfo *dinfo) 455 { 456 if (bootverbose) { 457 int i; 458 pcicfgregs *cfg = &dinfo->cfg; 459 460 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 461 cfg->vendor, cfg->device, cfg->revid); 462 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 463 cfg->baseclass, cfg->subclass, cfg->progif, 464 cfg->hdrtype, cfg->mfdev); 465 printf("\tsubordinatebus=%x \tsecondarybus=%x\n", 466 cfg->subordinatebus, cfg->secondarybus); 467 #ifdef PCI_DEBUG 468 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 469 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 470 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 471 cfg->lattimer, cfg->lattimer * 30, 472 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 473 #endif /* PCI_DEBUG */ 474 if (cfg->intpin > 0) 475 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 476 477 for (i = 0; i < cfg->nummaps; i++) { 478 pcimap *m = &cfg->map[i]; 479 printf("\tmap[%d]: type %x, range %2d, base %08x, size %2d\n", 480 i, m->type, m->ln2range, m->base, m->ln2size); 481 } 482 } 483 pci_drvattach(dinfo); /* XXX currently defined in pci_compat.c */ 484 } 485 486 /* scan one PCI bus for devices */ 487 488 static int 489 pci_probebus(int bus) 490 { 491 pcicfgregs probe; 492 int bushigh = bus; 493 494 #ifdef SIMOS 495 #undef PCI_SLOTMAX 496 #define PCI_SLOTMAX 0 497 #endif 498 499 bzero(&probe, sizeof probe); 500 /* XXX KDM */ 501 /* probe.parent = pci_bridgeto(bus); */ 502 probe.bus = bus; 503 for (probe.slot = 0; probe.slot <= PCI_SLOTMAX; probe.slot++) { 504 int pcifunchigh = 0; 505 for (probe.func = 0; probe.func <= pcifunchigh; probe.func++) { 506 struct pci_devinfo *dinfo = pci_readcfg(&probe); 507 if (dinfo != NULL) { 508 if (dinfo->cfg.mfdev) 509 pcifunchigh = 7; 510 /* 511 * XXX: Temporarily move pci_addcfg() up before 512 * the use of cfg->subordinatebus. This is 513 * necessary, since pci_addcfg() calls the 514 * device's probe(), which may read the bus# 515 * from some device dependent register of 516 * some host to PCI bridges. The probe will 517 * eventually be moved to pci_readcfg(), and 518 * pci_addcfg() will then be moved back down 519 * below the conditional statement ... 520 */ 521 pci_addcfg(dinfo); 522 523 if (bushigh < dinfo->cfg.subordinatebus) 524 bushigh = dinfo->cfg.subordinatebus; 525 if (bushigh < dinfo->cfg.secondarybus) 526 bushigh = dinfo->cfg.secondarybus; 527 528 /* XXX KDM */ 529 /* cfg = NULL; we don't own this anymore ... */ 530 } 531 } 532 } 533 return (bushigh); 534 } 535 536 /* scan a PCI bus tree reached through one PCI attachment point */ 537 538 int 539 pci_probe(pciattach *parent) 540 { 541 int bushigh; 542 int bus = 0; 543 544 STAILQ_INIT(&pci_devq); 545 546 bushigh = pci_bushigh(); 547 while (bus <= bushigh) { 548 int newbushigh; 549 550 printf("Probing for devices on PCI bus %d:\n", bus); 551 newbushigh = pci_probebus(bus); 552 553 if (bushigh < newbushigh) 554 bushigh = newbushigh; 555 bus++; 556 } 557 return (bushigh); 558 } 559 560 /* 561 * This is the user interface to PCI configuration space. 562 */ 563 564 static int 565 pci_open(dev_t dev, int oflags, int devtype, struct proc *p) 566 { 567 if ((oflags & FWRITE) && securelevel > 0) { 568 return EPERM; 569 } 570 return 0; 571 } 572 573 static int 574 pci_close(dev_t dev, int flag, int devtype, struct proc *p) 575 { 576 return 0; 577 } 578 579 /* 580 * Match a single pci_conf structure against an array of pci_match_conf 581 * structures. The first argument, 'matches', is an array of num_matches 582 * pci_match_conf structures. match_buf is a pointer to the pci_conf 583 * structure that will be compared to every entry in the matches array. 584 * This function returns 1 on failure, 0 on success. 585 */ 586 static int 587 pci_conf_match(struct pci_match_conf *matches, int num_matches, 588 struct pci_conf *match_buf) 589 { 590 int i; 591 592 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0)) 593 return(1); 594 595 for (i = 0; i < num_matches; i++) { 596 /* 597 * I'm not sure why someone would do this...but... 598 */ 599 if (matches[i].flags == PCI_GETCONF_NO_MATCH) 600 continue; 601 602 /* 603 * Look at each of the match flags. If it's set, do the 604 * comparison. If the comparison fails, we don't have a 605 * match, go on to the next item if there is one. 606 */ 607 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0) 608 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus)) 609 continue; 610 611 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0) 612 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev)) 613 continue; 614 615 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0) 616 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func)) 617 continue; 618 619 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0) 620 && (match_buf->pc_vendor != matches[i].pc_vendor)) 621 continue; 622 623 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0) 624 && (match_buf->pc_device != matches[i].pc_device)) 625 continue; 626 627 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0) 628 && (match_buf->pc_class != matches[i].pc_class)) 629 continue; 630 631 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0) 632 && (match_buf->pd_unit != matches[i].pd_unit)) 633 continue; 634 635 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0) 636 && (strncmp(matches[i].pd_name, match_buf->pd_name, 637 sizeof(match_buf->pd_name)) != 0)) 638 continue; 639 640 return(0); 641 } 642 643 return(1); 644 } 645 646 /* 647 * Locate the parent of a PCI device by scanning the PCI devlist 648 * and return the entry for the parent. 649 * For devices on PCI Bus 0 (the host bus), this is the PCI Host. 650 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge. 651 */ 652 653 pcicfgregs * 654 pci_devlist_get_parent(pcicfgregs *cfg) 655 { 656 struct devlist *devlist_head; 657 struct pci_devinfo *dinfo; 658 pcicfgregs *bridge_cfg; 659 int i; 660 661 dinfo = STAILQ_FIRST(devlist_head = &pci_devq); 662 663 /* If the device is on PCI bus 0, look for the host */ 664 if (cfg->bus == 0) { 665 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 666 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 667 bridge_cfg = &dinfo->cfg; 668 if (bridge_cfg->baseclass == PCIC_BRIDGE 669 && bridge_cfg->subclass == PCIS_BRIDGE_HOST 670 && bridge_cfg->bus == cfg->bus) { 671 return bridge_cfg; 672 } 673 } 674 } 675 676 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */ 677 if (cfg->bus > 0) { 678 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 679 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 680 bridge_cfg = &dinfo->cfg; 681 if (bridge_cfg->baseclass == PCIC_BRIDGE 682 && bridge_cfg->subclass == PCIS_BRIDGE_PCI 683 && bridge_cfg->secondarybus == cfg->bus) { 684 return bridge_cfg; 685 } 686 } 687 } 688 689 return NULL; 690 } 691 692 static int 693 pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 694 { 695 struct pci_io *io; 696 int error; 697 698 if (!(flag & FWRITE)) 699 return EPERM; 700 701 702 switch(cmd) { 703 case PCIOCGETCONF: 704 { 705 struct pci_devinfo *dinfo; 706 struct pci_conf_io *cio; 707 struct devlist *devlist_head; 708 struct pci_match_conf *pattern_buf; 709 int num_patterns; 710 size_t iolen; 711 int ionum, i; 712 713 cio = (struct pci_conf_io *)data; 714 715 num_patterns = 0; 716 dinfo = NULL; 717 718 /* 719 * Hopefully the user won't pass in a null pointer, but it 720 * can't hurt to check. 721 */ 722 if (cio == NULL) { 723 error = EINVAL; 724 break; 725 } 726 727 /* 728 * If the user specified an offset into the device list, 729 * but the list has changed since they last called this 730 * ioctl, tell them that the list has changed. They will 731 * have to get the list from the beginning. 732 */ 733 if ((cio->offset != 0) 734 && (cio->generation != pci_generation)){ 735 cio->num_matches = 0; 736 cio->status = PCI_GETCONF_LIST_CHANGED; 737 error = 0; 738 break; 739 } 740 741 /* 742 * Check to see whether the user has asked for an offset 743 * past the end of our list. 744 */ 745 if (cio->offset >= pci_numdevs) { 746 cio->num_matches = 0; 747 cio->status = PCI_GETCONF_LAST_DEVICE; 748 error = 0; 749 break; 750 } 751 752 /* get the head of the device queue */ 753 devlist_head = &pci_devq; 754 755 /* 756 * Determine how much room we have for pci_conf structures. 757 * Round the user's buffer size down to the nearest 758 * multiple of sizeof(struct pci_conf) in case the user 759 * didn't specify a multiple of that size. 760 */ 761 iolen = min(cio->match_buf_len - 762 (cio->match_buf_len % sizeof(struct pci_conf)), 763 pci_numdevs * sizeof(struct pci_conf)); 764 765 /* 766 * Since we know that iolen is a multiple of the size of 767 * the pciconf union, it's okay to do this. 768 */ 769 ionum = iolen / sizeof(struct pci_conf); 770 771 /* 772 * If this test is true, the user wants the pci_conf 773 * structures returned to match the supplied entries. 774 */ 775 if ((cio->num_patterns > 0) 776 && (cio->pat_buf_len > 0)) { 777 /* 778 * pat_buf_len needs to be: 779 * num_patterns * sizeof(struct pci_match_conf) 780 * While it is certainly possible the user just 781 * allocated a large buffer, but set the number of 782 * matches correctly, it is far more likely that 783 * their kernel doesn't match the userland utility 784 * they're using. It's also possible that the user 785 * forgot to initialize some variables. Yes, this 786 * may be overly picky, but I hazard to guess that 787 * it's far more likely to just catch folks that 788 * updated their kernel but not their userland. 789 */ 790 if ((cio->num_patterns * 791 sizeof(struct pci_match_conf)) != cio->pat_buf_len){ 792 /* The user made a mistake, return an error*/ 793 cio->status = PCI_GETCONF_ERROR; 794 printf("pci_ioctl: pat_buf_len %d != " 795 "num_patterns (%d) * sizeof(struct " 796 "pci_match_conf) (%d)\npci_ioctl: " 797 "pat_buf_len should be = %d\n", 798 cio->pat_buf_len, cio->num_patterns, 799 sizeof(struct pci_match_conf), 800 sizeof(struct pci_match_conf) * 801 cio->num_patterns); 802 printf("pci_ioctl: do your headers match your " 803 "kernel?\n"); 804 cio->num_matches = 0; 805 error = EINVAL; 806 break; 807 } 808 809 /* 810 * Check the user's buffer to make sure it's readable. 811 */ 812 if ((error = useracc((caddr_t)cio->patterns, 813 cio->pat_buf_len, B_READ)) != 1){ 814 printf("pci_ioctl: pattern buffer %p, " 815 "length %u isn't user accessible for" 816 " READ\n", cio->patterns, 817 cio->pat_buf_len); 818 error = EACCES; 819 break; 820 } 821 /* 822 * Allocate a buffer to hold the patterns. 823 */ 824 pattern_buf = malloc(cio->pat_buf_len, M_TEMP, 825 M_WAITOK); 826 error = copyin(cio->patterns, pattern_buf, 827 cio->pat_buf_len); 828 if (error != 0) 829 break; 830 num_patterns = cio->num_patterns; 831 832 } else if ((cio->num_patterns > 0) 833 || (cio->pat_buf_len > 0)) { 834 /* 835 * The user made a mistake, spit out an error. 836 */ 837 cio->status = PCI_GETCONF_ERROR; 838 cio->num_matches = 0; 839 printf("pci_ioctl: invalid GETCONF arguments\n"); 840 error = EINVAL; 841 break; 842 } else 843 pattern_buf = NULL; 844 845 /* 846 * Make sure we can write to the match buffer. 847 */ 848 if ((error = useracc((caddr_t)cio->matches, cio->match_buf_len, 849 B_WRITE)) != 1) { 850 printf("pci_ioctl: match buffer %p, length %u " 851 "isn't user accessible for WRITE\n", 852 cio->matches, cio->match_buf_len); 853 error = EACCES; 854 break; 855 } 856 857 /* 858 * Go through the list of devices and copy out the devices 859 * that match the user's criteria. 860 */ 861 for (cio->num_matches = 0, error = 0, i = 0, 862 dinfo = STAILQ_FIRST(devlist_head); 863 (dinfo != NULL) && (cio->num_matches < ionum) 864 && (error == 0) && (i < pci_numdevs); 865 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 866 867 if (i < cio->offset) 868 continue; 869 870 if ((pattern_buf == NULL) || 871 (pci_conf_match(pattern_buf, num_patterns, 872 &dinfo->conf) == 0)) { 873 874 /* 875 * If we've filled up the user's buffer, 876 * break out at this point. Since we've 877 * got a match here, we'll pick right back 878 * up at the matching entry. We can also 879 * tell the user that there are more matches 880 * left. 881 */ 882 if (cio->num_matches >= ionum) 883 break; 884 885 error = copyout(&dinfo->conf, 886 &cio->matches[cio->num_matches], 887 sizeof(struct pci_conf)); 888 cio->num_matches++; 889 } 890 } 891 892 /* 893 * Set the pointer into the list, so if the user is getting 894 * n records at a time, where n < pci_numdevs, 895 */ 896 cio->offset = i; 897 898 /* 899 * Set the generation, the user will need this if they make 900 * another ioctl call with offset != 0. 901 */ 902 cio->generation = pci_generation; 903 904 /* 905 * If this is the last device, inform the user so he won't 906 * bother asking for more devices. If dinfo isn't NULL, we 907 * know that there are more matches in the list because of 908 * the way the traversal is done. 909 */ 910 if (dinfo == NULL) 911 cio->status = PCI_GETCONF_LAST_DEVICE; 912 else 913 cio->status = PCI_GETCONF_MORE_DEVS; 914 915 if (pattern_buf != NULL) 916 free(pattern_buf, M_TEMP); 917 918 break; 919 } 920 case PCIOCREAD: 921 io = (struct pci_io *)data; 922 switch(io->pi_width) { 923 pcicfgregs probe; 924 case 4: 925 case 2: 926 case 1: 927 probe.bus = io->pi_sel.pc_bus; 928 probe.slot = io->pi_sel.pc_dev; 929 probe.func = io->pi_sel.pc_func; 930 io->pi_data = pci_cfgread(&probe, 931 io->pi_reg, io->pi_width); 932 error = 0; 933 break; 934 default: 935 error = ENODEV; 936 break; 937 } 938 break; 939 940 case PCIOCWRITE: 941 io = (struct pci_io *)data; 942 switch(io->pi_width) { 943 pcicfgregs probe; 944 case 4: 945 case 2: 946 case 1: 947 probe.bus = io->pi_sel.pc_bus; 948 probe.slot = io->pi_sel.pc_dev; 949 probe.func = io->pi_sel.pc_func; 950 pci_cfgwrite(&probe, 951 io->pi_reg, io->pi_data, io->pi_width); 952 error = 0; 953 break; 954 default: 955 error = ENODEV; 956 break; 957 } 958 break; 959 960 default: 961 error = ENOTTY; 962 break; 963 } 964 965 return (error); 966 } 967 968 #define PCI_CDEV 78 969 970 static struct cdevsw pcicdev = { 971 pci_open, pci_close, noread, nowrite, pci_ioctl, nostop, noreset, 972 nodevtotty, seltrue, nommap, nostrategy, "pci", 0, PCI_CDEV 973 }; 974 975 #ifdef DEVFS 976 static void *pci_devfs_token; 977 #endif 978 979 static void 980 pci_cdevinit(void *dummy) 981 { 982 dev_t dev; 983 984 dev = makedev(PCI_CDEV, 0); 985 cdevsw_add(&dev, &pcicdev, NULL); 986 #ifdef DEVFS 987 pci_devfs_token = devfs_add_devswf(&pcicdev, 0, DV_CHR, 988 UID_ROOT, GID_WHEEL, 0644, "pci"); 989 #endif 990 } 991 992 SYSINIT(pcidev, SI_SUB_DRIVERS, SI_ORDER_MIDDLE+PCI_CDEV, pci_cdevinit, NULL); 993 994 #endif /* NPCI > 0 */
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