Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/pcireg.h
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
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1 #ifndef PCI_COMPAT 2 #define PCI_COMPAT 3 #endif 4 /* 5 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 /* 34 * PCIM_xxx: mask to locate subfield in register 35 * PCIR_xxx: config register offset 36 * PCIC_xxx: device class 37 * PCIS_xxx: device subclass 38 * PCIP_xxx: device programming interface 39 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 40 * PCID_xxx: device ID 41 */ 42 43 /* some PCI bus constants */ 44 45 #define PCI_BUSMAX 255 46 #define PCI_SLOTMAX 31 47 #define PCI_FUNCMAX 7 48 #define PCI_REGMAX 255 49 50 /* PCI config header registers for all devices */ 51 52 #define PCIR_DEVVENDOR 0x00 53 #define PCIR_VENDOR 0x00 54 #define PCIR_DEVICE 0x02 55 #define PCIR_COMMAND 0x04 56 #define PCIM_CMD_PORTEN 0x0001 57 #define PCIM_CMD_MEMEN 0x0002 58 #define PCIM_CMD_BUSMASTEREN 0x0004 59 #define PCIM_CMD_MWRICEN 0x0010 60 #define PCIM_CMD_PERRESPEN 0x0040 61 #define PCIM_CMD_SERRESPEN 0x0100 62 #define PCIR_STATUS 0x06 63 #define PCIM_STATUS_CAPPRESENT 0x0010 64 #define PCIM_STATUS_66CAPABLE 0x0020 65 #define PCIM_STATUS_BACKTOBACK 0x0080 66 #define PCIM_STATUS_PERRREPORT 0x0100 67 #define PCIM_STATUS_SEL_FAST 0x0000 68 #define PCIM_STATUS_SEL_MEDIMUM 0x0200 69 #define PCIM_STATUS_SEL_SLOW 0x0400 70 #define PCIM_STATUS_SEL_MASK 0x0600 71 #define PCIM_STATUS_STABORT 0x0800 72 #define PCIM_STATUS_RTABORT 0x1000 73 #define PCIM_STATUS_RMABORT 0x2000 74 #define PCIM_STATUS_SERR 0x4000 75 #define PCIM_STATUS_PERR 0x8000 76 #define PCIR_REVID 0x08 77 #define PCIR_PROGIF 0x09 78 #define PCIR_SUBCLASS 0x0a 79 #define PCIR_CLASS 0x0b 80 #define PCIR_CACHELNSZ 0x0c 81 #define PCIR_LATTIMER 0x0d 82 #define PCIR_HEADERTYPE 0x0e 83 #define PCIM_MFDEV 0x80 84 #define PCIR_BIST 0x0f 85 86 /* config registers for header type 0 devices */ 87 88 #define PCIR_MAPS 0x10 89 #define PCIR_BARS PCIR_MAPS 90 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 91 #define PCIR_CARDBUSCIS 0x28 92 #define PCIR_SUBVEND_0 0x2c 93 #define PCIR_SUBDEV_0 0x2e 94 #define PCIR_BIOS 0x30 95 #define PCIM_BIOS_ENABLE 0x01 96 #define PCIR_CAP_PTR 0x34 97 #define PCIR_INTLINE 0x3c 98 #define PCIR_INTPIN 0x3d 99 #define PCIR_MINGNT 0x3e 100 #define PCIR_MAXLAT 0x3f 101 102 /* config registers for header type 1 devices */ 103 104 #define PCIR_SECSTAT_1 0 /**/ 105 106 #define PCIR_PRIBUS_1 0x18 107 #define PCIR_SECBUS_1 0x19 108 #define PCIR_SUBBUS_1 0x1a 109 #define PCIR_SECLAT_1 0x1b 110 111 #define PCIR_IOBASEL_1 0x1c 112 #define PCIR_IOLIMITL_1 0x1d 113 #define PCIR_IOBASEH_1 0 /**/ 114 #define PCIR_IOLIMITH_1 0 /**/ 115 116 #define PCIR_MEMBASE_1 0x20 117 #define PCIR_MEMLIMIT_1 0x22 118 119 #define PCIR_PMBASEL_1 0x24 120 #define PCIR_PMLIMITL_1 0x26 121 #define PCIR_PMBASEH_1 0 /**/ 122 #define PCIR_PMLIMITH_1 0 /**/ 123 124 #define PCIR_BRIDGECTL_1 0 /**/ 125 126 #define PCIR_SUBVEND_1 0x34 127 #define PCIR_SUBDEV_1 0x36 128 129 /* config registers for header type 2 devices */ 130 131 #define PCIR_SECSTAT_2 0x16 132 133 #define PCIR_PRIBUS_2 0x18 134 #define PCIR_SECBUS_2 0x19 135 #define PCIR_SUBBUS_2 0x1a 136 #define PCIR_SECLAT_2 0x1b 137 138 #define PCIR_MEMBASE0_2 0x1c 139 #define PCIR_MEMLIMIT0_2 0x20 140 #define PCIR_MEMBASE1_2 0x24 141 #define PCIR_MEMLIMIT1_2 0x28 142 #define PCIR_IOBASE0_2 0x2c 143 #define PCIR_IOLIMIT0_2 0x30 144 #define PCIR_IOBASE1_2 0x34 145 #define PCIR_IOLIMIT1_2 0x38 146 147 #define PCIR_BRIDGECTL_2 0x3e 148 149 #define PCIR_SUBVEND_2 0x40 150 #define PCIR_SUBDEV_2 0x42 151 152 #define PCIR_PCCARDIF_2 0x44 153 154 /* PCI device class, subclass and programming interface definitions */ 155 156 #define PCIC_OLD 0x00 157 #define PCIS_OLD_NONVGA 0x00 158 #define PCIS_OLD_VGA 0x01 159 160 #define PCIC_STORAGE 0x01 161 #define PCIS_STORAGE_SCSI 0x00 162 #define PCIS_STORAGE_IDE 0x01 163 #define PCIP_STORAGE_IDE_MODEPRIM 0x01 164 #define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 165 #define PCIP_STORAGE_IDE_MODESEC 0x04 166 #define PCIP_STORAGE_IDE_PROGINDSEC 0x08 167 #define PCIP_STORAGE_IDE_MASTERDEV 0x80 168 #define PCIS_STORAGE_FLOPPY 0x02 169 #define PCIS_STORAGE_IPI 0x03 170 #define PCIS_STORAGE_RAID 0x04 171 #define PCIS_STORAGE_OTHER 0x80 172 173 #define PCIC_NETWORK 0x02 174 #define PCIS_NETWORK_ETHERNET 0x00 175 #define PCIS_NETWORK_TOKENRING 0x01 176 #define PCIS_NETWORK_FDDI 0x02 177 #define PCIS_NETWORK_ATM 0x03 178 #define PCIS_NETWORK_OTHER 0x80 179 180 #define PCIC_DISPLAY 0x03 181 #define PCIS_DISPLAY_VGA 0x00 182 #define PCIS_DISPLAY_XGA 0x01 183 #define PCIS_DISPLAY_OTHER 0x80 184 185 #define PCIC_MULTIMEDIA 0x04 186 #define PCIS_MULTIMEDIA_VIDEO 0x00 187 #define PCIS_MULTIMEDIA_AUDIO 0x01 188 #define PCIS_MULTIMEDIA_OTHER 0x80 189 190 #define PCIC_MEMORY 0x05 191 #define PCIS_MEMORY_RAM 0x00 192 #define PCIS_MEMORY_FLASH 0x01 193 #define PCIS_MEMORY_OTHER 0x80 194 195 #define PCIC_BRIDGE 0x06 196 #define PCIS_BRIDGE_HOST 0x00 197 #define PCIS_BRIDGE_ISA 0x01 198 #define PCIS_BRIDGE_EISA 0x02 199 #define PCIS_BRIDGE_MCA 0x03 200 #define PCIS_BRIDGE_PCI 0x04 201 #define PCIS_BRIDGE_PCMCIA 0x05 202 #define PCIS_BRIDGE_NUBUS 0x06 203 #define PCIS_BRIDGE_CARDBUS 0x07 204 #define PCIS_BRIDGE_OTHER 0x80 205 206 #define PCIC_SIMPLECOMM 0x07 207 #define PCIS_SIMPLECOMM_UART 0x00 208 #define PCIP_SIMPLECOMM_UART_16550A 0x02 209 #define PCIS_SIMPLECOMM_PAR 0x01 210 #define PCIS_SIMPLECOMM_OTHER 0x80 211 212 #define PCIC_BASEPERIPH 0x08 213 #define PCIS_BASEPERIPH_PIC 0x00 214 #define PCIS_BASEPERIPH_DMA 0x01 215 #define PCIS_BASEPERIPH_TIMER 0x02 216 #define PCIS_BASEPERIPH_RTC 0x03 217 #define PCIS_BASEPERIPH_OTHER 0x80 218 219 #define PCIC_INPUTDEV 0x09 220 #define PCIS_INPUTDEV_KEYBOARD 0x00 221 #define PCIS_INPUTDEV_DIGITIZER 0x01 222 #define PCIS_INPUTDEV_MOUSE 0x02 223 #define PCIS_INPUTDEV_OTHER 0x80 224 225 #define PCIC_DOCKING 0x0a 226 #define PCIS_DOCKING_GENERIC 0x00 227 #define PCIS_DOCKING_OTHER 0x80 228 229 #define PCIC_PROCESSOR 0x0b 230 #define PCIS_PROCESSOR_386 0x00 231 #define PCIS_PROCESSOR_486 0x01 232 #define PCIS_PROCESSOR_PENTIUM 0x02 233 #define PCIS_PROCESSOR_ALPHA 0x10 234 #define PCIS_PROCESSOR_POWERPC 0x20 235 #define PCIS_PROCESSOR_COPROC 0x40 236 237 #define PCIC_SERIALBUS 0x0c 238 #define PCIS_SERIALBUS_FW 0x00 239 #define PCIS_SERIALBUS_ACCESS 0x01 240 #define PCIS_SERIALBUS_SSA 0x02 241 #define PCIS_SERIALBUS_USB 0x03 242 #define PCIS_SERIALBUS_FC 0x04 243 #define PCIS_SERIALBUS_SMBUS 0x05 244 245 #define PCIC_OTHER 0xff 246 247 /* PCI power manangement */ 248 249 #define PCIR_POWER_CAP 0x2 250 #define PCIM_PCAP_SPEC 0x0007 251 #define PCIM_PCAP_PMEREQCLK 0x0008 252 #define PCIM_PCAP_PMEREQPWR 0x0010 253 #define PCIM_PCAP_DEVSPECINIT 0x0020 254 #define PCIM_PCAP_DYNCLOCK 0x0040 255 #define PCIM_PCAP_SECCLOCK 0x00c0 256 #define PCIM_PCAP_CLOCKMASK 0x00c0 257 #define PCIM_PCAP_REQFULLCLOCK 0x0100 258 #define PCIM_PCAP_D1SUPP 0x0200 259 #define PCIM_PCAP_D2SUPP 0x0400 260 #define PCIM_PCAP_D0PME 0x1000 261 #define PCIM_PCAP_D1PME 0x2000 262 #define PCIM_PCAP_D2PME 0x4000 263 264 #define PCIR_POWER_STATUS 0x4 265 #define PCIM_PSTAT_D0 0x0000 266 #define PCIM_PSTAT_D1 0x0001 267 #define PCIM_PSTAT_D2 0x0002 268 #define PCIM_PSTAT_D3 0x0003 269 #define PCIM_PSTAT_DMASK 0x0003 270 #define PCIM_PSTAT_REPENABLE 0x0010 271 #define PCIM_PSTAT_PMEENABLE 0x0100 272 #define PCIM_PSTAT_D0POWER 0x0000 273 #define PCIM_PSTAT_D1POWER 0x0200 274 #define PCIM_PSTAT_D2POWER 0x0400 275 #define PCIM_PSTAT_D3POWER 0x0600 276 #define PCIM_PSTAT_D0HEAT 0x0800 277 #define PCIM_PSTAT_D1HEAT 0x1000 278 #define PCIM_PSTAT_D2HEAT 0x1200 279 #define PCIM_PSTAT_D3HEAT 0x1400 280 #define PCIM_PSTAT_DATAUNKN 0x0000 281 #define PCIM_PSTAT_DATADIV10 0x2000 282 #define PCIM_PSTAT_DATADIV100 0x4000 283 #define PCIM_PSTAT_DATADIV1000 0x6000 284 #define PCIM_PSTAT_DATADIVMASK 0x6000 285 #define PCIM_PSTAT_PME 0x8000 286 287 #define PCIR_POWER_PMCSR 0x6 288 #define PCIM_PMCSR_DCLOCK 0x10 289 #define PCIM_PMCSR_B2SUPP 0x20 290 #define PCIM_BMCSR_B3SUPP 0x40 291 #define PCIM_BMCSR_BPCE 0x80 292 293 #define PCIR_POWER_DATA 0x7 294 295 /* PCI-X definitions */ 296 #define PCIXR_COMMAND 0x96 297 #define PCIXR_DEVADDR 0x98 298 #define PCIXM_DEVADDR_FNUM 0x0003 /* Function Number */ 299 #define PCIXM_DEVADDR_DNUM 0x00F8 /* Device Number */ 300 #define PCIXM_DEVADDR_BNUM 0xFF00 /* Bus Number */ 301 #define PCIXR_STATUS 0x9A 302 #define PCIXM_STATUS_64BIT 0x0001 /* Active 64bit connection to device. */ 303 #define PCIXM_STATUS_133CAP 0x0002 /* Device is 133MHz capable */ 304 #define PCIXM_STATUS_SCDISC 0x0004 /* Split Completion Discarded */ 305 #define PCIXM_STATUS_UNEXPSC 0x0008 /* Unexpected Split Completion */ 306 #define PCIXM_STATUS_CMPLEXDEV 0x0010 /* Device Complexity (set == bridge) */ 307 #define PCIXM_STATUS_MAXMRDBC 0x0060 /* Maximum Burst Read Count */ 308 #define PCIXM_STATUS_MAXSPLITS 0x0380 /* Maximum Split Transactions */ 309 #define PCIXM_STATUS_MAXCRDS 0x1C00 /* Maximum Cumulative Read Size */ 310 #define PCIXM_STATUS_RCVDSCEM 0x2000 /* Received a Split Comp w/Error msg */ 311 312 /* some PCI vendor definitions (only used to identify ancient devices !!! */ 313 314 #define PCIV_INTEL 0x8086 315 316 #define PCID_INTEL_SATURN 0x0483 317 #define PCID_INTEL_ORION 0x84c4 318 319 /* for compatibility to FreeBSD-2.2 version of PCI code */ 320 321 #ifdef PCI_COMPAT 322 323 #define PCI_ID_REG 0x00 324 #define PCI_COMMAND_STATUS_REG 0x04 325 #define PCI_COMMAND_IO_ENABLE 0x00000001 326 #define PCI_COMMAND_MEM_ENABLE 0x00000002 327 #define PCI_CLASS_REG 0x08 328 #define PCI_CLASS_MASK 0xff000000 329 #define PCI_SUBCLASS_MASK 0x00ff0000 330 #define PCI_REVISION_MASK 0x000000ff 331 #define PCI_CLASS_PREHISTORIC 0x00000000 332 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x00010000 333 #define PCI_CLASS_MASS_STORAGE 0x01000000 334 #define PCI_CLASS_DISPLAY 0x03000000 335 #define PCI_SUBCLASS_DISPLAY_VGA 0x00000000 336 #define PCI_CLASS_BRIDGE 0x06000000 337 #define PCI_MAP_REG_START 0x10 338 #define PCI_MAP_REG_END 0x28 339 #define PCI_MAP_IO 0x00000001 340 #define PCI_INTERRUPT_REG 0x3c 341 342 #endif /* PCI_COMPAT */
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