The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/pci/pcisupport.c

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    1 /**************************************************************************
    2 **
    3 ** $FreeBSD$
    4 **
    5 **  Device driver for DEC/INTEL PCI chipsets.
    6 **
    7 **  FreeBSD
    8 **
    9 **-------------------------------------------------------------------------
   10 **
   11 **  Written for FreeBSD by
   12 **      wolf@cologne.de         Wolfgang Stanglmeier
   13 **      se@mi.Uni-Koeln.de      Stefan Esser
   14 **
   15 **-------------------------------------------------------------------------
   16 **
   17 ** Copyright (c) 1994,1995 Stefan Esser.  All rights reserved.
   18 **
   19 ** Redistribution and use in source and binary forms, with or without
   20 ** modification, are permitted provided that the following conditions
   21 ** are met:
   22 ** 1. Redistributions of source code must retain the above copyright
   23 **    notice, this list of conditions and the following disclaimer.
   24 ** 2. Redistributions in binary form must reproduce the above copyright
   25 **    notice, this list of conditions and the following disclaimer in the
   26 **    documentation and/or other materials provided with the distribution.
   27 ** 3. The name of the author may not be used to endorse or promote products
   28 **    derived from this software without specific prior written permission.
   29 **
   30 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   31 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   32 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   33 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   34 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   35 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   36 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   37 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   38 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   39 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   40 **
   41 ***************************************************************************
   42 */
   43 
   44 #include "opt_bus.h"
   45 #include "opt_pci.h"
   46 
   47 #include <sys/param.h>
   48 #include <sys/systm.h>
   49 #include <sys/malloc.h>
   50 #include <sys/kernel.h>
   51 #include <sys/bus.h>
   52 
   53 #include <pci/pcivar.h>
   54 #include <pci/pcireg.h>
   55 
   56 #include <vm/vm.h>
   57 #include <vm/vm_object.h>
   58 #include <vm/pmap.h>
   59 
   60 /*---------------------------------------------------------
   61 **
   62 **      Intel chipsets for 486 / Pentium processor
   63 **
   64 **---------------------------------------------------------
   65 */
   66 
   67 static  void    chipset_attach(device_t dev, int unit);
   68 
   69 struct condmsg {
   70     unsigned char       port;
   71     unsigned char       mask;
   72     unsigned char       value;
   73     char                flags;
   74     const char          *text;
   75 };
   76 
   77 
   78 static void
   79 fixbushigh_i1225(device_t dev)
   80 {
   81         int sublementarybus;
   82 
   83         sublementarybus = pci_read_config(dev, 0x41, 1);
   84         if (sublementarybus != 0xff) {
   85                 pci_set_secondarybus(dev, sublementarybus + 1);
   86                 pci_set_subordinatebus(dev, sublementarybus + 1);
   87         }
   88 }
   89 
   90 static void
   91 fixwsc_natoma(device_t dev)
   92 {
   93         int pmccfg;
   94 
   95         pmccfg = pci_read_config(dev, 0x50, 2);
   96 #if defined(SMP)
   97         if (pmccfg & 0x8000) {
   98                 printf("Correcting Natoma config for SMP\n");
   99                 pmccfg &= ~0x8000;
  100                 pci_write_config(dev, 0x50, pmccfg, 2);
  101         }
  102 #else
  103         if ((pmccfg & 0x8000) == 0) {
  104                 printf("Correcting Natoma config for non-SMP\n");
  105                 pmccfg |= 0x8000;
  106                 pci_write_config(dev, 0x50, pmccfg, 2);
  107         }
  108 #endif
  109 }
  110                 
  111 #ifndef PCI_QUIET
  112 
  113 #define M_XX 0  /* end of list */
  114 #define M_EQ 1  /* mask and return true if equal */
  115 #define M_NE 2  /* mask and return true if not equal */
  116 #define M_TR 3  /* don't read config, always true */
  117 #define M_EN 4  /* mask and print "enabled" if true, "disabled" if false */
  118 #define M_NN 5  /* opposite sense of M_EN */
  119 
  120 static const struct condmsg conf82425ex[] =
  121 {
  122     { 0x00, 0x00, 0x00, M_TR, "\tClock " },
  123     { 0x50, 0x06, 0x00, M_EQ, "25" },
  124     { 0x50, 0x06, 0x02, M_EQ, "33" },
  125     { 0x50, 0x04, 0x04, M_EQ, "??", },
  126     { 0x00, 0x00, 0x00, M_TR, "MHz, L1 Cache " },
  127     { 0x50, 0x01, 0x00, M_EQ, "Disabled\n" },
  128     { 0x50, 0x09, 0x01, M_EQ, "Write-through\n" },
  129     { 0x50, 0x09, 0x09, M_EQ, "Write-back\n" },
  130 
  131     { 0x00, 0x00, 0x00, M_TR, "\tL2 Cache " },
  132     { 0x52, 0x07, 0x00, M_EQ, "Disabled" },
  133     { 0x52, 0x0f, 0x01, M_EQ, "64KB Write-through" },
  134     { 0x52, 0x0f, 0x02, M_EQ, "128KB Write-through" },
  135     { 0x52, 0x0f, 0x03, M_EQ, "256KB Write-through" },
  136     { 0x52, 0x0f, 0x04, M_EQ, "512KB Write-through" },
  137     { 0x52, 0x0f, 0x01, M_EQ, "64KB Write-back" },
  138     { 0x52, 0x0f, 0x02, M_EQ, "128KB Write-back" },
  139     { 0x52, 0x0f, 0x03, M_EQ, "256KB Write-back" },
  140     { 0x52, 0x0f, 0x04, M_EQ, "512KB Write-back" },
  141     { 0x53, 0x01, 0x00, M_EQ, ", 3-" },
  142     { 0x53, 0x01, 0x01, M_EQ, ", 2-" },
  143     { 0x53, 0x06, 0x00, M_EQ, "3-3-3" },
  144     { 0x53, 0x06, 0x02, M_EQ, "2-2-2" },
  145     { 0x53, 0x06, 0x04, M_EQ, "1-1-1" },
  146     { 0x53, 0x06, 0x06, M_EQ, "?-?-?" },
  147     { 0x53, 0x18, 0x00, M_EQ, "/4-2-2-2\n" },
  148     { 0x53, 0x18, 0x08, M_EQ, "/3-2-2-2\n" },
  149     { 0x53, 0x18, 0x10, M_EQ, "/?-?-?-?\n" },
  150     { 0x53, 0x18, 0x18, M_EQ, "/2-1-1-1\n" },
  151 
  152     { 0x56, 0x00, 0x00, M_TR, "\tDRAM: " },
  153     { 0x56, 0x02, 0x02, M_EQ, "Fast Code Read, " },
  154     { 0x56, 0x04, 0x04, M_EQ, "Fast Data Read, " },
  155     { 0x56, 0x08, 0x08, M_EQ, "Fast Write, " },
  156     { 0x57, 0x20, 0x20, M_EQ, "Pipelined CAS" },
  157     { 0x57, 0x2e, 0x00, M_NE, "\n\t" },
  158     { 0x57, 0x00, 0x00, M_TR, "Timing: RAS: " },
  159     { 0x57, 0x07, 0x00, M_EQ, "4" },
  160     { 0x57, 0x07, 0x01, M_EQ, "3" },
  161     { 0x57, 0x07, 0x02, M_EQ, "2" },
  162     { 0x57, 0x07, 0x04, M_EQ, "1.5" },
  163     { 0x57, 0x07, 0x05, M_EQ, "1" },
  164     { 0x57, 0x00, 0x00, M_TR, " Clocks, CAS Read: " },
  165     { 0x57, 0x18, 0x00, M_EQ, "3/1", },
  166     { 0x57, 0x18, 0x00, M_EQ, "2/1", },
  167     { 0x57, 0x18, 0x00, M_EQ, "1.5/0.5", },
  168     { 0x57, 0x18, 0x00, M_EQ, "1/1", },
  169     { 0x57, 0x00, 0x00, M_TR, ", CAS Write: " },
  170     { 0x57, 0x20, 0x00, M_EQ, "2/1", },
  171     { 0x57, 0x20, 0x20, M_EQ, "1/1", },
  172     { 0x57, 0x00, 0x00, M_TR, "\n" },
  173 
  174     { 0x40, 0x01, 0x01, M_EQ, "\tCPU-to-PCI Byte Merging\n" },
  175     { 0x40, 0x02, 0x02, M_EQ, "\tCPU-to-PCI Bursting\n" },
  176     { 0x40, 0x04, 0x04, M_EQ, "\tPCI Posted Writes\n" },
  177     { 0x40, 0x20, 0x00, M_EQ, "\tDRAM Parity Disabled\n" },
  178 
  179     { 0x48, 0x03, 0x01, M_EQ, "\tPCI IDE controller: Primary (1F0h-1F7h,3F6h,3F7h)" },
  180     { 0x48, 0x03, 0x02, M_EQ, "\tPCI IDE controller: Secondary (170h-177h,376h,377h)" },
  181     { 0x4d, 0x01, 0x01, M_EQ, "\tRTC (70-77h)\n" },
  182     { 0x4d, 0x02, 0x02, M_EQ, "\tKeyboard (60,62,64,66h)\n" },
  183     { 0x4d, 0x08, 0x08, M_EQ, "\tIRQ12/M Mouse Function\n" },
  184 
  185 /* end marker */
  186     { 0 }
  187 };
  188 
  189 static const struct condmsg conf82424zx[] =
  190 {
  191     { 0x00, 0x00, 0x00, M_TR, "\tCPU: " },
  192     { 0x50, 0xe0, 0x00, M_EQ, "486DX" },
  193     { 0x50, 0xe0, 0x20, M_EQ, "486SX" },
  194     { 0x50, 0xe0, 0x40, M_EQ, "486DX2 or 486DX4" },
  195     { 0x50, 0xe0, 0x80, M_EQ, "Overdrive (writeback)" },
  196 
  197     { 0x00, 0x00, 0x00, M_TR, ", bus=" },
  198     { 0x50, 0x03, 0x00, M_EQ, "25MHz" },
  199     { 0x50, 0x03, 0x01, M_EQ, "33MHz" },
  200     { 0x53, 0x01, 0x01, M_TR, ", CPU->Memory posting "},
  201     { 0x53, 0x01, 0x00, M_EQ, "OFF" },
  202     { 0x53, 0x01, 0x01, M_EQ, "ON" },
  203 
  204     { 0x56, 0x30, 0x00, M_NE, "\n\tWarning:" },
  205     { 0x56, 0x20, 0x00, M_NE, " NO cache parity!" },
  206     { 0x56, 0x10, 0x00, M_NE, " NO DRAM parity!" },
  207     { 0x55, 0x04, 0x04, M_EQ, "\n\tWarning: refresh OFF! " },
  208 
  209     { 0x00, 0x00, 0x00, M_TR, "\n\tCache: " },
  210     { 0x52, 0x01, 0x00, M_EQ, "None" },
  211     { 0x52, 0xc1, 0x01, M_EQ, "64KB" },
  212     { 0x52, 0xc1, 0x41, M_EQ, "128KB" },
  213     { 0x52, 0xc1, 0x81, M_EQ, "256KB" },
  214     { 0x52, 0xc1, 0xc1, M_EQ, "512KB" },
  215     { 0x52, 0x03, 0x01, M_EQ, " writethrough" },
  216     { 0x52, 0x03, 0x03, M_EQ, " writeback" },
  217 
  218     { 0x52, 0x01, 0x01, M_EQ, ", cache clocks=" },
  219     { 0x52, 0x05, 0x01, M_EQ, "3-1-1-1" },
  220     { 0x52, 0x05, 0x05, M_EQ, "2-1-1-1" },
  221 
  222     { 0x00, 0x00, 0x00, M_TR, "\n\tDRAM:" },
  223     { 0x55, 0x43, 0x00, M_NE, " page mode" },
  224     { 0x55, 0x02, 0x02, M_EQ, " code fetch" },
  225     { 0x55, 0x43, 0x43, M_EQ, "," },
  226     { 0x55, 0x43, 0x42, M_EQ, " and" },
  227     { 0x55, 0x40, 0x40, M_EQ, " read" },
  228     { 0x55, 0x03, 0x03, M_EQ, " and" },
  229     { 0x55, 0x43, 0x41, M_EQ, " and" },
  230     { 0x55, 0x01, 0x01, M_EQ, " write" },
  231     { 0x55, 0x43, 0x00, M_NE, "," },
  232 
  233     { 0x00, 0x00, 0x00, M_TR, " memory clocks=" },
  234     { 0x55, 0x20, 0x00, M_EQ, "X-2-2-2" },
  235     { 0x55, 0x20, 0x20, M_EQ, "X-1-2-1" },
  236 
  237     { 0x00, 0x00, 0x00, M_TR, "\n\tCPU->PCI: posting " },
  238     { 0x53, 0x02, 0x00, M_NE, "ON" },
  239     { 0x53, 0x02, 0x00, M_EQ, "OFF" },
  240     { 0x00, 0x00, 0x00, M_TR, ", burst mode " },
  241     { 0x54, 0x02, 0x00, M_NE, "ON" },
  242     { 0x54, 0x02, 0x00, M_EQ, "OFF" },
  243     { 0x00, 0x00, 0x00, M_TR, "\n\tPCI->Memory: posting " },
  244     { 0x54, 0x01, 0x00, M_NE, "ON" },
  245     { 0x54, 0x01, 0x00, M_EQ, "OFF" },
  246 
  247     { 0x00, 0x00, 0x00, M_TR, "\n" },
  248 
  249 /* end marker */
  250     { 0 }
  251 };
  252 
  253 static const struct condmsg conf82434lx[] =
  254 {
  255     { 0x00, 0x00, 0x00, M_TR, "\tCPU: " },
  256     { 0x50, 0xe3, 0x82, M_EQ, "Pentium, 60MHz" },
  257     { 0x50, 0xe3, 0x83, M_EQ, "Pentium, 66MHz" },
  258     { 0x50, 0xe3, 0xa2, M_EQ, "Pentium, 90MHz" },
  259     { 0x50, 0xe3, 0xa3, M_EQ, "Pentium, 100MHz" },
  260     { 0x50, 0xc2, 0x82, M_NE, "(unknown)" },
  261     { 0x50, 0x04, 0x00, M_EQ, " (primary cache OFF)" },
  262 
  263     { 0x53, 0x01, 0x01, M_TR, ", CPU->Memory posting "},
  264     { 0x53, 0x01, 0x01, M_NE, "OFF" },
  265     { 0x53, 0x01, 0x01, M_EQ, "ON" },
  266 
  267     { 0x53, 0x08, 0x00, M_NE, ", read around write"},
  268 
  269     { 0x70, 0x04, 0x00, M_EQ, "\n\tWarning: Cache parity disabled!" },
  270     { 0x57, 0x20, 0x00, M_NE, "\n\tWarning: DRAM parity mask!" },
  271     { 0x57, 0x01, 0x00, M_EQ, "\n\tWarning: refresh OFF! " },
  272 
  273     { 0x00, 0x00, 0x00, M_TR, "\n\tCache: " },
  274     { 0x52, 0x01, 0x00, M_EQ, "None" },
  275     { 0x52, 0x81, 0x01, M_EQ, "" },
  276     { 0x52, 0xc1, 0x81, M_EQ, "256KB" },
  277     { 0x52, 0xc1, 0xc1, M_EQ, "512KB" },
  278     { 0x52, 0x03, 0x01, M_EQ, " writethrough" },
  279     { 0x52, 0x03, 0x03, M_EQ, " writeback" },
  280 
  281     { 0x52, 0x01, 0x01, M_EQ, ", cache clocks=" },
  282     { 0x52, 0x21, 0x01, M_EQ, "3-2-2-2/4-2-2-2" },
  283     { 0x52, 0x21, 0x21, M_EQ, "3-1-1-1" },
  284 
  285     { 0x52, 0x01, 0x01, M_EQ, "\n\tCache flags: " },
  286     { 0x52, 0x11, 0x11, M_EQ, " cache-all" },
  287     { 0x52, 0x09, 0x09, M_EQ, " byte-control" },
  288     { 0x52, 0x05, 0x05, M_EQ, " powersaver" },
  289 
  290     { 0x00, 0x00, 0x00, M_TR, "\n\tDRAM:" },
  291     { 0x57, 0x10, 0x00, M_EQ, " page mode" },
  292 
  293     { 0x00, 0x00, 0x00, M_TR, " memory clocks=" },
  294     { 0x57, 0xc0, 0x00, M_EQ, "X-4-4-4 (70ns)" },
  295     { 0x57, 0xc0, 0x40, M_EQ, "X-4-4-4/X-3-3-3 (60ns)" },
  296     { 0x57, 0xc0, 0x80, M_EQ, "???" },
  297     { 0x57, 0xc0, 0xc0, M_EQ, "X-3-3-3 (50ns)" },
  298     { 0x58, 0x02, 0x02, M_EQ, ", RAS-wait" },
  299     { 0x58, 0x01, 0x01, M_EQ, ", CAS-wait" },
  300 
  301     { 0x00, 0x00, 0x00, M_TR, "\n\tCPU->PCI: posting " },
  302     { 0x53, 0x02, 0x02, M_EQ, "ON" },
  303     { 0x53, 0x02, 0x00, M_EQ, "OFF" },
  304     { 0x00, 0x00, 0x00, M_TR, ", burst mode " },
  305     { 0x54, 0x02, 0x00, M_NE, "ON" },
  306     { 0x54, 0x02, 0x00, M_EQ, "OFF" },
  307     { 0x54, 0x04, 0x00, M_TR, ", PCI clocks=" },
  308     { 0x54, 0x04, 0x00, M_EQ, "2-2-2-2" },
  309     { 0x54, 0x04, 0x00, M_NE, "2-1-1-1" },
  310     { 0x00, 0x00, 0x00, M_TR, "\n\tPCI->Memory: posting " },
  311     { 0x54, 0x01, 0x00, M_NE, "ON" },
  312     { 0x54, 0x01, 0x00, M_EQ, "OFF" },
  313 
  314     { 0x57, 0x01, 0x01, M_EQ, "\n\tRefresh:" },
  315     { 0x57, 0x03, 0x03, M_EQ, " CAS#/RAS#(Hidden)" },
  316     { 0x57, 0x03, 0x01, M_EQ, " RAS#Only" },
  317     { 0x57, 0x05, 0x05, M_EQ, " BurstOf4" },
  318 
  319     { 0x00, 0x00, 0x00, M_TR, "\n" },
  320 
  321 /* end marker */
  322     { 0 }
  323 };
  324 
  325 static const struct condmsg conf82378[] =
  326 {
  327     { 0x00, 0x00, 0x00, M_TR, "\tBus Modes:" },
  328     { 0x41, 0x04, 0x04, M_EQ, " Bus Park," },
  329     { 0x41, 0x02, 0x02, M_EQ, " Bus Lock," },
  330     { 0x41, 0x02, 0x00, M_EQ, " Resource Lock," },
  331     { 0x41, 0x01, 0x01, M_EQ, " GAT" },
  332     { 0x4d, 0x20, 0x20, M_EQ, "\n\tCoprocessor errors enabled" },
  333     { 0x4d, 0x10, 0x10, M_EQ, "\n\tMouse function enabled" },
  334 
  335     { 0x4e, 0x30, 0x10, M_EQ, "\n\tIDE controller: Primary (1F0h-1F7h,3F6h,3F7h)" },
  336     { 0x4e, 0x30, 0x30, M_EQ, "\n\tIDE controller: Secondary (170h-177h,376h,377h)" },
  337     { 0x4e, 0x28, 0x08, M_EQ, "\n\tFloppy controller: 3F0h,3F1h " },
  338     { 0x4e, 0x24, 0x04, M_EQ, "\n\tFloppy controller: 3F2h-3F7h " },
  339     { 0x4e, 0x28, 0x28, M_EQ, "\n\tFloppy controller: 370h,371h " },
  340     { 0x4e, 0x24, 0x24, M_EQ, "\n\tFloppy controller: 372h-377h " },
  341     { 0x4e, 0x02, 0x02, M_EQ, "\n\tKeyboard controller: 60h,62h,64h,66h" },
  342     { 0x4e, 0x01, 0x01, M_EQ, "\n\tRTC: 70h-77h" },
  343 
  344     { 0x4f, 0x80, 0x80, M_EQ, "\n\tConfiguration RAM: 0C00h,0800h-08FFh" },
  345     { 0x4f, 0x40, 0x40, M_EQ, "\n\tPort 92: enabled" },
  346     { 0x4f, 0x03, 0x00, M_EQ, "\n\tSerial Port A: COM1 (3F8h-3FFh)" },
  347     { 0x4f, 0x03, 0x01, M_EQ, "\n\tSerial Port A: COM2 (2F8h-2FFh)" },
  348     { 0x4f, 0x0c, 0x00, M_EQ, "\n\tSerial Port B: COM1 (3F8h-3FFh)" },
  349     { 0x4f, 0x0c, 0x04, M_EQ, "\n\tSerial Port B: COM2 (2F8h-2FFh)" },
  350     { 0x4f, 0x30, 0x00, M_EQ, "\n\tParallel Port: LPT1 (3BCh-3BFh)" },
  351     { 0x4f, 0x30, 0x04, M_EQ, "\n\tParallel Port: LPT2 (378h-37Fh)" },
  352     { 0x4f, 0x30, 0x20, M_EQ, "\n\tParallel Port: LPT3 (278h-27Fh)" },
  353     { 0x00, 0x00, 0x00, M_TR, "\n" },
  354 
  355 /* end marker */
  356     { 0 }
  357 };
  358 
  359 static const struct condmsg conf82437fx[] = 
  360 {
  361     /* PCON -- PCI Control Register */
  362     { 0x00, 0x00, 0x00, M_TR, "\tCPU Inactivity timer: " },
  363     { 0x50, 0xe0, 0xe0, M_EQ, "8" },
  364     { 0x50, 0xe0, 0xd0, M_EQ, "7" },
  365     { 0x50, 0xe0, 0xc0, M_EQ, "6" },
  366     { 0x50, 0xe0, 0xb0, M_EQ, "5" },
  367     { 0x50, 0xe0, 0xa0, M_EQ, "4" },
  368     { 0x50, 0xe0, 0x90, M_EQ, "3" },
  369     { 0x50, 0xe0, 0x80, M_EQ, "2" },
  370     { 0x50, 0xe0, 0x00, M_EQ, "1" },
  371     { 0x00, 0x00, 0x00, M_TR, " clocks\n\tPeer Concurrency: " },
  372     { 0x50, 0x08, 0x08, M_EN, 0 },
  373     { 0x00, 0x00, 0x00, M_TR, "\n\tCPU-to-PCI Write Bursting: " },
  374     { 0x50, 0x04, 0x00, M_NN, 0 },
  375     { 0x00, 0x00, 0x00, M_TR, "\n\tPCI Streaming: " },
  376     { 0x50, 0x02, 0x00, M_NN, 0 },
  377     { 0x00, 0x00, 0x00, M_TR, "\n\tBus Concurrency: " },
  378     { 0x50, 0x01, 0x00, M_NN, 0 },
  379 
  380     /* CC -- Cache Control Regsiter */
  381     { 0x00, 0x00, 0x00, M_TR, "\n\tCache:" },
  382     { 0x52, 0xc0, 0x80, M_EQ, " 512K" },
  383     { 0x52, 0xc0, 0x40, M_EQ, " 256K" },
  384     { 0x52, 0xc0, 0x00, M_EQ, " NO" },
  385     { 0x52, 0x30, 0x00, M_EQ, " pipelined-burst" },
  386     { 0x52, 0x30, 0x10, M_EQ, " burst" },
  387     { 0x52, 0x30, 0x20, M_EQ, " asynchronous" },
  388     { 0x52, 0x30, 0x30, M_EQ, " dual-bank pipelined-burst" },
  389     { 0x00, 0x00, 0x00, M_TR, " secondary; L1 " },
  390     { 0x52, 0x01, 0x00, M_EN, 0 },
  391     { 0x00, 0x00, 0x00, M_TR, "\n" },
  392 
  393     /* DRAMC -- DRAM Control Register */
  394     { 0x57, 0x07, 0x00, M_EQ, "Warning: refresh OFF!\n" },
  395     { 0x00, 0x00, 0x00, M_TR, "\tDRAM:" },
  396     { 0x57, 0xc0, 0x00, M_EQ, " no memory hole" },
  397     { 0x57, 0xc0, 0x40, M_EQ, " 512K-640K memory hole" },
  398     { 0x57, 0xc0, 0x80, M_EQ, " 15M-16M memory hole" },
  399     { 0x57, 0x07, 0x01, M_EQ, ", 50 MHz refresh" },
  400     { 0x57, 0x07, 0x02, M_EQ, ", 60 MHz refresh" },
  401     { 0x57, 0x07, 0x03, M_EQ, ", 66 MHz refresh" },
  402 
  403     /* DRAMT = DRAM Timing Register */
  404     { 0x00, 0x00, 0x00, M_TR, "\n\tRead burst timing: " },
  405     { 0x58, 0x60, 0x00, M_EQ, "x-4-4-4/x-4-4-4" },
  406     { 0x58, 0x60, 0x20, M_EQ, "x-3-3-3/x-4-4-4" },
  407     { 0x58, 0x60, 0x40, M_EQ, "x-2-2-2/x-3-3-3" },
  408     { 0x58, 0x60, 0x60, M_EQ, "???" },
  409     { 0x00, 0x00, 0x00, M_TR, "\n\tWrite burst timing: " },
  410     { 0x58, 0x18, 0x00, M_EQ, "x-4-4-4" },
  411     { 0x58, 0x18, 0x08, M_EQ, "x-3-3-3" },
  412     { 0x58, 0x18, 0x10, M_EQ, "x-2-2-2" },
  413     { 0x58, 0x18, 0x18, M_EQ, "???" },
  414     { 0x00, 0x00, 0x00, M_TR, "\n\tRAS-CAS delay: " },
  415     { 0x58, 0x04, 0x00, M_EQ, "3" },
  416     { 0x58, 0x04, 0x04, M_EQ, "2" },
  417     { 0x00, 0x00, 0x00, M_TR, " clocks\n" },
  418 
  419     /* end marker */
  420     { 0 }
  421 };
  422 
  423 static const struct condmsg conf82437vx[] = 
  424 {
  425     /* PCON -- PCI Control Register */
  426     { 0x00, 0x00, 0x00, M_TR, "\n\tPCI Concurrency: " },
  427     { 0x50, 0x08, 0x08, M_EN, 0 },
  428 
  429     /* CC -- Cache Control Regsiter */
  430     { 0x00, 0x00, 0x00, M_TR, "\n\tCache:" },
  431     { 0x52, 0xc0, 0x80, M_EQ, " 512K" },
  432     { 0x52, 0xc0, 0x40, M_EQ, " 256K" },
  433     { 0x52, 0xc0, 0x00, M_EQ, " NO" },
  434     { 0x52, 0x30, 0x00, M_EQ, " pipelined-burst" },
  435     { 0x52, 0x30, 0x10, M_EQ, " burst" },
  436     { 0x52, 0x30, 0x20, M_EQ, " asynchronous" },
  437     { 0x52, 0x30, 0x30, M_EQ, " dual-bank pipelined-burst" },
  438     { 0x00, 0x00, 0x00, M_TR, " secondary; L1 " },
  439     { 0x52, 0x01, 0x00, M_EN, 0 },
  440     { 0x00, 0x00, 0x00, M_TR, "\n" },
  441 
  442     /* DRAMC -- DRAM Control Register */
  443     { 0x57, 0x07, 0x00, M_EQ, "Warning: refresh OFF!\n" },
  444     { 0x00, 0x00, 0x00, M_TR, "\tDRAM:" },
  445     { 0x57, 0xc0, 0x00, M_EQ, " no memory hole" },
  446     { 0x57, 0xc0, 0x40, M_EQ, " 512K-640K memory hole" },
  447     { 0x57, 0xc0, 0x80, M_EQ, " 15M-16M memory hole" },
  448     { 0x57, 0x07, 0x01, M_EQ, ", 50 MHz refresh" },
  449     { 0x57, 0x07, 0x02, M_EQ, ", 60 MHz refresh" },
  450     { 0x57, 0x07, 0x03, M_EQ, ", 66 MHz refresh" },
  451 
  452     /* DRAMT = DRAM Timing Register */
  453     { 0x00, 0x00, 0x00, M_TR, "\n\tRead burst timing: " },
  454     { 0x58, 0x60, 0x00, M_EQ, "x-4-4-4/x-4-4-4" },
  455     { 0x58, 0x60, 0x20, M_EQ, "x-3-3-3/x-4-4-4" },
  456     { 0x58, 0x60, 0x40, M_EQ, "x-2-2-2/x-3-3-3" },
  457     { 0x58, 0x60, 0x60, M_EQ, "???" },
  458     { 0x00, 0x00, 0x00, M_TR, "\n\tWrite burst timing: " },
  459     { 0x58, 0x18, 0x00, M_EQ, "x-4-4-4" },
  460     { 0x58, 0x18, 0x08, M_EQ, "x-3-3-3" },
  461     { 0x58, 0x18, 0x10, M_EQ, "x-2-2-2" },
  462     { 0x58, 0x18, 0x18, M_EQ, "???" },
  463     { 0x00, 0x00, 0x00, M_TR, "\n\tRAS-CAS delay: " },
  464     { 0x58, 0x04, 0x00, M_EQ, "3" },
  465     { 0x58, 0x04, 0x04, M_EQ, "2" },
  466     { 0x00, 0x00, 0x00, M_TR, " clocks\n" },
  467 
  468     /* end marker */
  469     { 0 }
  470 };
  471 
  472 static const struct condmsg conf82371fb[] =
  473 {
  474     /* IORT -- ISA I/O Recovery Timer Register */
  475     { 0x00, 0x00, 0x00, M_TR, "\tI/O Recovery Timing: 8-bit " },
  476     { 0x4c, 0x40, 0x00, M_EQ, "3.5" },
  477     { 0x4c, 0x78, 0x48, M_EQ, "1" },
  478     { 0x4c, 0x78, 0x50, M_EQ, "2" },
  479     { 0x4c, 0x78, 0x58, M_EQ, "3" },
  480     { 0x4c, 0x78, 0x60, M_EQ, "4" },
  481     { 0x4c, 0x78, 0x68, M_EQ, "5" },
  482     { 0x4c, 0x78, 0x70, M_EQ, "6" },
  483     { 0x4c, 0x78, 0x78, M_EQ, "7" },
  484     { 0x4c, 0x78, 0x40, M_EQ, "8" },
  485     { 0x00, 0x00, 0x00, M_TR, " clocks, 16-bit " },
  486     { 0x4c, 0x04, 0x00, M_EQ, "3.5" },
  487     { 0x4c, 0x07, 0x05, M_EQ, "1" },
  488     { 0x4c, 0x07, 0x06, M_EQ, "2" },
  489     { 0x4c, 0x07, 0x07, M_EQ, "3" },
  490     { 0x4c, 0x07, 0x04, M_EQ, "4" },
  491     { 0x00, 0x00, 0x00, M_TR, " clocks\n" },
  492 
  493     /* XBCS -- X-Bus Chip Select Register */
  494     { 0x00, 0x00, 0x00, M_TR, "\tExtended BIOS: " },
  495     { 0x4e, 0x80, 0x80, M_EN, 0 },
  496     { 0x00, 0x00, 0x00, M_TR, "\n\tLower BIOS: " },
  497     { 0x4e, 0x40, 0x40, M_EN, 0 },
  498     { 0x00, 0x00, 0x00, M_TR, "\n\tCoprocessor IRQ13: " },
  499     { 0x4e, 0x20, 0x20, M_EN, 0 },
  500     { 0x00, 0x00, 0x00, M_TR, "\n\tMouse IRQ12: " },
  501     { 0x4e, 0x10, 0x10, M_EN, 0 },
  502     { 0x00, 0x00, 0x00, M_TR, "\n" },
  503 
  504     { 0x00, 0x00, 0x00, M_TR, "\tInterrupt Routing: " },
  505 #define PIRQ(x, n) \
  506     { 0x00, 0x00, 0x00, M_TR, n ": " }, \
  507     { x, 0x80, 0x80, M_EQ, "disabled" }, \
  508     { x, 0xc0, 0x40, M_EQ, "[shared] " }, \
  509     { x, 0x8f, 0x03, M_EQ, "IRQ3" }, \
  510     { x, 0x8f, 0x04, M_EQ, "IRQ4" }, \
  511     { x, 0x8f, 0x05, M_EQ, "IRQ5" }, \
  512     { x, 0x8f, 0x06, M_EQ, "IRQ6" }, \
  513     { x, 0x8f, 0x07, M_EQ, "IRQ7" }, \
  514     { x, 0x8f, 0x09, M_EQ, "IRQ9" }, \
  515     { x, 0x8f, 0x0a, M_EQ, "IRQ10" }, \
  516     { x, 0x8f, 0x0b, M_EQ, "IRQ11" }, \
  517     { x, 0x8f, 0x0c, M_EQ, "IRQ12" }, \
  518     { x, 0x8f, 0x0e, M_EQ, "IRQ14" }, \
  519     { x, 0x8f, 0x0f, M_EQ, "IRQ15" }
  520 
  521     /* Interrupt routing */
  522     PIRQ(0x60, "A"),
  523     PIRQ(0x61, ", B"),
  524     PIRQ(0x62, ", C"),
  525     PIRQ(0x63, ", D"),
  526     PIRQ(0x70, "\n\t\tMB0"),
  527     PIRQ(0x71, ", MB1"),
  528 
  529     { 0x00, 0x00, 0x00, M_TR, "\n" },
  530 
  531 #undef PIRQ
  532 
  533     /* XXX - do DMA routing, too? */
  534     { 0 }
  535 };
  536 
  537 static const struct condmsg conf82371fb2[] =
  538 {
  539     /* IDETM -- IDE Timing Register */
  540     { 0x00, 0x00, 0x00, M_TR, "\tPrimary IDE: " },
  541     { 0x41, 0x80, 0x80, M_EN, 0 },
  542     { 0x00, 0x00, 0x00, M_TR, "\n\tSecondary IDE: " },
  543     { 0x43, 0x80, 0x80, M_EN, 0 },
  544     { 0x00, 0x00, 0x00, M_TR, "\n" },
  545 
  546     /* end of list */
  547     { 0 }
  548 };
  549 
  550 static void
  551 writeconfig (device_t dev, const struct condmsg *tbl)
  552 {
  553     while (tbl->flags != M_XX) {
  554         const char *text = 0;
  555 
  556         if (tbl->flags == M_TR) {
  557             text = tbl->text;
  558         } else {
  559             unsigned char v = pci_read_config(dev, tbl->port, 1);
  560             switch (tbl->flags) {
  561     case M_EQ:
  562                 if ((v & tbl->mask) == tbl->value) text = tbl->text;
  563                 break;
  564     case M_NE:
  565                 if ((v & tbl->mask) != tbl->value) text = tbl->text;
  566                 break;
  567     case M_EN:
  568                 text = (v & tbl->mask) ? "enabled" : "disabled";
  569                 break;
  570     case M_NN:
  571                 text = (v & tbl->mask) ? "disabled" : "enabled";
  572             }
  573         }
  574         if (text) printf ("%s", text);
  575         tbl++;
  576     }
  577 }
  578 
  579 #ifdef DUMPCONFIGSPACE
  580 static void
  581 dumpconfigspace (device_t dev)
  582 {
  583     int reg;
  584     printf ("configuration space registers:");
  585     for (reg = 0; reg < 0x100; reg+=4) {
  586         if ((reg & 0x0f) == 0) 
  587             printf ("\n%02x:\t", reg);
  588         printf ("%08x ", pci_read_config(dev, reg, 4));
  589     }
  590     printf ("\n");
  591 }
  592 #endif /* DUMPCONFIGSPACE */
  593 
  594 #endif /* PCI_QUIET */
  595 
  596 
  597 static void
  598 chipset_attach (device_t dev, int unit)
  599 {
  600 #ifndef PCI_QUIET
  601         if (!bootverbose)
  602                 return;
  603 
  604         switch (pci_get_devid(dev)) {
  605         case 0x04868086:
  606                 writeconfig (dev, conf82425ex);
  607                 break;
  608         case 0x04838086:
  609                 writeconfig (dev, conf82424zx);
  610                 break;
  611         case 0x04a38086:
  612                 writeconfig (dev, conf82434lx);
  613                 break;
  614         case 0x04848086:
  615                 writeconfig (dev, conf82378);
  616                 break;
  617         case 0x122d8086:
  618                 writeconfig (dev, conf82437fx);
  619                 break;
  620         case 0x70308086:
  621                 writeconfig (dev, conf82437vx);
  622                 break;
  623         case 0x70008086:
  624         case 0x122e8086:
  625                 writeconfig (dev, conf82371fb);
  626                 break;
  627         case 0x70108086:
  628         case 0x12308086:
  629                 writeconfig (dev, conf82371fb2);
  630                 break;
  631 #if 0
  632         case 0x00011011: /* DEC 21050 */
  633         case 0x00221014: /* IBM xxx */
  634                 writeconfig (dev, conf_pci2pci);
  635                 break;
  636 #endif
  637         };
  638 #endif /* PCI_QUIET */
  639 }
  640 
  641 static const char *
  642 pci_bridge_type(device_t dev)
  643 {
  644     char *descr, tmpbuf[120];
  645 
  646     if (pci_get_class(dev) != PCIC_BRIDGE)
  647             return NULL;
  648 
  649     switch (pci_get_subclass(dev)) {
  650     case PCIS_BRIDGE_HOST:      strcpy(tmpbuf, "Host to PCI"); break;
  651     case PCIS_BRIDGE_ISA:       strcpy(tmpbuf, "PCI to ISA"); break;
  652     case PCIS_BRIDGE_EISA:      strcpy(tmpbuf, "PCI to EISA"); break;
  653     case PCIS_BRIDGE_MCA:       strcpy(tmpbuf, "PCI to MCA"); break;
  654     case PCIS_BRIDGE_PCI:       strcpy(tmpbuf, "PCI to PCI"); break;
  655     case PCIS_BRIDGE_PCMCIA:    strcpy(tmpbuf, "PCI to PCMCIA"); break;
  656     case PCIS_BRIDGE_NUBUS:     strcpy(tmpbuf, "PCI to NUBUS"); break;
  657     case PCIS_BRIDGE_CARDBUS:   strcpy(tmpbuf, "PCI to CardBus"); break;
  658     case PCIS_BRIDGE_OTHER:     strcpy(tmpbuf, "PCI to Other"); break;
  659     default: 
  660             snprintf(tmpbuf, sizeof(tmpbuf),
  661                      "PCI to 0x%x", pci_get_subclass(dev)); 
  662             break;
  663     }
  664     snprintf(tmpbuf+strlen(tmpbuf), sizeof(tmpbuf)-strlen(tmpbuf),
  665              " bridge (vendor=%04x device=%04x)",
  666              pci_get_vendor(dev), pci_get_device(dev));
  667     descr = malloc (strlen(tmpbuf) +1, M_DEVBUF, M_WAITOK);
  668     strcpy(descr, tmpbuf);
  669     return descr;
  670 }
  671 
  672 static const char*
  673 pcib_match(device_t dev)
  674 {
  675         switch (pci_get_devid(dev)) {
  676         /* Intel -- vendor 0x8086 */
  677         case 0x71818086:
  678                 return ("Intel 82443LX (440 LX) PCI-PCI (AGP) bridge");
  679         case 0x71918086:
  680                 return ("Intel 82443BX (440 BX) PCI-PCI (AGP) bridge");
  681         case 0x71A18086:
  682                 return ("Intel 82443GX (440 GX) PCI-PCI (AGP) bridge");
  683         case 0x84cb8086:
  684                 return ("Intel 82454NX PCI Expander Bridge");
  685         case 0x11318086:
  686                 return ("Intel 82801BA/BAM (ICH2) PCI-PCI (AGP) bridge");
  687         case 0x124b8086:
  688                 return ("Intel 82380FB mobile PCI to PCI bridge");
  689         case 0x24188086:
  690                 return ("Intel 82801AA (ICH) Hub to PCI bridge");
  691         case 0x24288086:
  692                 return ("Intel 82801AB (ICH0) Hub to PCI bridge");
  693         case 0x244e8086:
  694                 return ("Intel 82801BA/BAM (ICH2) Hub to PCI bridge");
  695         case 0x1a318086:
  696                 return ("Intel 82845 PCI-PCI (AGP) bridge");
  697         
  698         /* VLSI -- vendor 0x1004 */
  699         case 0x01021004:
  700                 return ("VLSI 82C534 Eagle II PCI Bus bridge");
  701         case 0x01031004:
  702                 return ("VLSI 82C538 Eagle II PCI Docking bridge");
  703 
  704         /* VIA Technologies -- vendor 0x1106 */
  705         case 0x83051106:
  706                 return ("VIA 8363 (Apollo KT133) PCI-PCI (AGP) bridge");
  707         case 0x85981106:
  708                 return ("VIA 82C598MVP (Apollo MVP3) PCI-PCI (AGP) bridge");
  709         /* Exclude the ACPI function of VT82Cxxx series */
  710         case 0x30401106:
  711         case 0x30501106:
  712         case 0x30571106:
  713                 return NULL;
  714 
  715         /* AcerLabs -- vendor 0x10b9 */
  716         /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
  717         /* id is '10b9" but the register always shows "10b9". -Foxfair  */
  718         case 0x524710b9:
  719                 return ("AcerLabs M5247 PCI-PCI(AGP Supported) bridge");
  720         case 0x524310b9:/* 5243 seems like 5247, need more info to divide*/
  721                 return ("AcerLabs M5243 PCI-PCI bridge");
  722 
  723         /* AMD -- vendor 0x1022 */
  724         case 0x70071022:
  725                 return ("AMD-751 PCI-PCI (1x/2x AGP) bridge");
  726         case 0x700f1022:
  727                 return ("AMD-761 PCI-PCI (4x AGP) bridge");
  728 
  729         /* DEC -- vendor 0x1011 */
  730         case 0x00011011:
  731                 return ("DEC 21050 PCI-PCI bridge");
  732         case 0x00211011:
  733                 return ("DEC 21052 PCI-PCI bridge");
  734         case 0x00221011:
  735                 return ("DEC 21150 PCI-PCI bridge");
  736         case 0x00241011:
  737                 return ("DEC 21152 PCI-PCI bridge");
  738         case 0x00251011:
  739                 return ("DEC 21153 PCI-PCI bridge");
  740         case 0x00261011:
  741                 return ("DEC 21154 PCI-PCI bridge");
  742 
  743         /* Others */
  744         case 0x00221014:
  745                 return ("IBM 82351 PCI-PCI bridge");
  746         /* UMC United Microelectronics 0x1060 */
  747         case 0x88811060:
  748                 return ("UMC UM8881 HB4 486 PCI Chipset");
  749         };
  750 
  751         if (pci_get_class(dev) == PCIC_BRIDGE
  752             && pci_get_subclass(dev) == PCIS_BRIDGE_PCI)
  753                 return pci_bridge_type(dev);
  754 
  755         return NULL;
  756 }
  757 
  758 static int pcib_probe(device_t dev)
  759 {
  760         const char *desc;
  761 
  762         desc = pcib_match(dev);
  763         if (desc) {
  764                 device_set_desc_copy(dev, desc);
  765                 return 0;
  766         }
  767 
  768         return ENXIO;
  769 }
  770 
  771 static int pcib_attach(device_t dev)
  772 {
  773         u_int8_t secondary;
  774 
  775         chipset_attach(dev, device_get_unit(dev));
  776 
  777         secondary = pci_get_secondarybus(dev);
  778         if (secondary) {
  779                 device_add_child(dev, "pci", secondary);
  780                 return bus_generic_attach(dev);
  781         } else
  782                 return 0;
  783 }
  784 
  785 static int
  786 pcib_read_ivar(device_t dev, device_t child, int which, u_long *result)
  787 {
  788         if (which == PCIB_IVAR_HOSE) {
  789                 /*
  790                  * Pass up to parent bus.
  791                  */
  792                 *result = pci_get_hose(dev);
  793                 return(0);
  794         }
  795         return ENOENT;
  796 }
  797 
  798 /*
  799  * Route an interrupt across a PCI bridge.
  800  */
  801 static int
  802 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
  803 {
  804         device_t        bus;
  805         int             parent_intpin;
  806         int             intnum;
  807 
  808         device_printf(pcib, "Hi!\n");
  809 
  810         /*      
  811          *
  812          * The PCI standard defines a swizzle of the child-side device/intpin
  813          * to the parent-side intpin as follows.
  814          *
  815          * device = device on child bus
  816          * child_intpin = intpin on child bus slot (0-3)
  817          * parent_intpin = intpin on parent bus slot (0-3)
  818          *
  819          * parent_intpin = (device + child_intpin) % 4
  820          */
  821         parent_intpin = (pci_get_slot(pcib) + (pin - 1)) % 4;
  822 
  823         /*
  824          * Our parent is a PCI bus.  Its parent must export the pci interface
  825          * which includes the ability to route interrupts.
  826          */
  827         bus = device_get_parent(pcib);
  828         intnum = PCI_ROUTE_INTERRUPT(device_get_parent(bus), pcib,
  829             parent_intpin + 1);
  830         device_printf(pcib, "routed slot %d INT%c to irq %d\n",
  831             pci_get_slot(dev), 'A' + pin - 1, intnum);
  832         return(intnum);
  833 }
  834 
  835 static device_method_t pcib_methods[] = {
  836         /* Device interface */
  837         DEVMETHOD(device_probe,         pcib_probe),
  838         DEVMETHOD(device_attach,        pcib_attach),
  839         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  840         DEVMETHOD(device_suspend,       bus_generic_suspend),
  841         DEVMETHOD(device_resume,        bus_generic_resume),
  842 
  843         /* Bus interface */
  844         DEVMETHOD(bus_print_child,      bus_generic_print_child),
  845         DEVMETHOD(bus_read_ivar,        pcib_read_ivar),
  846         DEVMETHOD(bus_alloc_resource,   bus_generic_alloc_resource),
  847         DEVMETHOD(bus_release_resource, bus_generic_release_resource),
  848         DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
  849         DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
  850         DEVMETHOD(bus_setup_intr,       bus_generic_setup_intr),
  851         DEVMETHOD(bus_teardown_intr,    bus_generic_teardown_intr),
  852 
  853         /* pci interface */
  854         DEVMETHOD(pci_route_interrupt,  pcib_route_interrupt),
  855         { 0, 0 }
  856 };
  857 
  858 static driver_t pcib_driver = {
  859         "pcib",
  860         pcib_methods,
  861         1,
  862 };
  863 
  864 static devclass_t pcib_devclass;
  865 
  866 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
  867 
  868 static const char *
  869 eisab_match(device_t dev)
  870 {
  871         switch (pci_get_devid(dev)) {
  872         case 0x04828086:
  873                 /* Recognize this specifically, it has PCI-HOST class (!) */
  874                 return ("Intel 82375EB PCI-EISA bridge");
  875         }
  876         if (pci_get_class(dev) == PCIC_BRIDGE
  877             && pci_get_subclass(dev) == PCIS_BRIDGE_EISA)
  878                 return pci_bridge_type(dev);
  879 
  880         return NULL;
  881 }
  882 
  883 static const char *
  884 isab_match(device_t dev)
  885 {
  886         unsigned        rev;
  887 
  888         switch (pci_get_devid(dev)) {
  889         case 0x04848086:
  890                 rev = pci_get_revid(dev);
  891                 if (rev == 3)
  892                     return ("Intel 82378ZB PCI to ISA bridge");
  893                 return ("Intel 82378IB PCI to ISA bridge");
  894         case 0x122e8086:
  895                 return ("Intel 82371FB PCI to ISA bridge");
  896         case 0x70008086:
  897                 return ("Intel 82371SB PCI to ISA bridge");
  898         case 0x71108086:
  899                 return ("Intel 82371AB PCI to ISA bridge");
  900         case 0x71988086:
  901                 return ("Intel 82443MX PCI to ISA bridge");
  902         case 0x24108086:
  903                 return ("Intel 82801AA (ICH) PCI to LPC bridge");
  904         case 0x24208086:
  905                 return ("Intel 82801AB (ICH0) PCI to LPC bridge");
  906         case 0x24408086:
  907                 return ("Intel 82801BA/BAM (ICH2) PCI to LPC bridge");
  908         
  909         /* VLSI -- vendor 0x1004 */
  910         case 0x00061004:
  911                 return ("VLSI 82C593 PCI to ISA bridge");
  912 
  913         /* VIA Technologies -- vendor 0x1106 */
  914         case 0x05861106: /* south bridge section */
  915                 return ("VIA 82C586 PCI-ISA bridge");
  916         case 0x05961106:
  917                 return ("VIA 82C596B PCI-ISA bridge");
  918         case 0x06861106:
  919                 return ("VIA 82C686 PCI-ISA bridge");
  920 
  921         /* AcerLabs -- vendor 0x10b9 */
  922         /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
  923         /* id is '10b9" but the register always shows "10b9". -Foxfair  */
  924         case 0x153310b9:
  925                 return ("AcerLabs M1533 portable PCI-ISA bridge");
  926         case 0x154310b9:
  927                 return ("AcerLabs M1543 desktop PCI-ISA bridge");
  928 
  929         /* SiS -- vendor 0x1039 */
  930         case 0x00081039:
  931                 return ("SiS 85c503 PCI-ISA bridge");
  932 
  933         /* Cyrix -- vendor 0x1078 */
  934         case 0x00001078:
  935                 return ("Cyrix Cx5510 PCI-ISA bridge");
  936         case 0x01001078:
  937                 return ("Cyrix Cx5530 PCI-ISA bridge");
  938 
  939         /* NEC -- vendor 0x1033 */
  940         /* The "C-bus" is 16-bits bus on PC98. */
  941         case 0x00011033:
  942                 return ("NEC 0001 PCI to PC-98 C-bus bridge");
  943         case 0x002c1033:
  944                 return ("NEC 002C PCI to PC-98 C-bus bridge");
  945         case 0x003b1033:
  946                 return ("NEC 003B PCI to PC-98 C-bus bridge");
  947         /* UMC United Microelectronics 0x1060 */
  948         case 0x886a1060:
  949                 return ("UMC UM8886 ISA Bridge with EIDE");
  950 
  951         /* Cypress -- vendor 0x1080 */
  952         case 0xc6931080:
  953                 if (pci_get_class(dev) == PCIC_BRIDGE
  954                     && pci_get_subclass(dev) == PCIS_BRIDGE_ISA)
  955                         return ("Cypress 82C693 PCI-ISA bridge");
  956                 break;
  957 
  958         /* ServerWorks -- vendor 0x1166 */
  959         case 0x02001166:
  960                 return ("ServerWorks IB6566 PCI to ISA bridge");
  961         }
  962 
  963         if (pci_get_class(dev) == PCIC_BRIDGE
  964             && pci_get_subclass(dev) == PCIS_BRIDGE_ISA)
  965                 return pci_bridge_type(dev);
  966 
  967         return NULL;
  968 }
  969 
  970 static int
  971 isab_probe(device_t dev)
  972 {
  973         const char *desc;
  974         int     is_eisa;
  975 
  976         is_eisa = 0;
  977         desc = eisab_match(dev);
  978         if (desc)
  979                 is_eisa = 1;
  980         else
  981                 desc = isab_match(dev);
  982         if (desc) {
  983                 /*
  984                  * For a PCI-EISA bridge, add both eisa and isa.
  985                  * Only add one instance of eisa or isa for now.
  986                  */
  987                 device_set_desc_copy(dev, desc);
  988                 if (is_eisa && !devclass_get_device(devclass_find("eisa"), 0))
  989                         device_add_child(dev, "eisa", -1);
  990 
  991                 if (!devclass_get_device(devclass_find("isa"), 0))
  992                         device_add_child(dev, "isa", -1);
  993                 return -1000;
  994         }
  995         return ENXIO;
  996 }
  997 
  998 static int
  999 isab_attach(device_t dev)
 1000 {
 1001         chipset_attach(dev, device_get_unit(dev));
 1002         return bus_generic_attach(dev);
 1003 }
 1004 
 1005 static device_method_t isab_methods[] = {
 1006         /* Device interface */
 1007         DEVMETHOD(device_probe,         isab_probe),
 1008         DEVMETHOD(device_attach,        isab_attach),
 1009         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 1010         DEVMETHOD(device_suspend,       bus_generic_suspend),
 1011         DEVMETHOD(device_resume,        bus_generic_resume),
 1012 
 1013         /* Bus interface */
 1014         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 1015         DEVMETHOD(bus_alloc_resource,   bus_generic_alloc_resource),
 1016         DEVMETHOD(bus_release_resource, bus_generic_release_resource),
 1017         DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
 1018         DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
 1019         DEVMETHOD(bus_setup_intr,       bus_generic_setup_intr),
 1020         DEVMETHOD(bus_teardown_intr,    bus_generic_teardown_intr),
 1021 
 1022         { 0, 0 }
 1023 };
 1024 
 1025 static driver_t isab_driver = {
 1026         "isab",
 1027         isab_methods,
 1028         1,
 1029 };
 1030 
 1031 static devclass_t isab_devclass;
 1032 
 1033 DRIVER_MODULE(isab, pci, isab_driver, isab_devclass, 0, 0);
 1034 
 1035 const char *
 1036 pci_usb_match(device_t dev)
 1037 {
 1038         switch (pci_get_devid(dev)) {
 1039 
 1040         /* Intel -- vendor 0x8086 */
 1041         case 0x70208086:
 1042                 return ("Intel 82371SB (PIIX3) USB controller");
 1043         case 0x71128086:
 1044                 return ("Intel 82371AB/EB (PIIX4) USB controller");
 1045         case 0x24128086:
 1046                 return ("Intel 82801AA (ICH) USB controller");
 1047         case 0x24228086:
 1048                 return ("Intel 82801AB (ICH0) USB controller");
 1049         case 0x24428086:
 1050                 return ("Intel 82801BA/BAM (ICH2) USB controller USB-A");
 1051         case 0x24448086:
 1052                 return ("Intel 82801BA/BAM (ICH2) USB controller USB-B");
 1053 
 1054         /* VIA Technologies -- vendor 0x1106 (0x1107 on the Apollo Master) */
 1055         case 0x30381106:
 1056                 return ("VIA 83C572 USB controller");
 1057 
 1058         /* AcerLabs -- vendor 0x10b9 */
 1059         case 0x523710b9:
 1060                 return ("AcerLabs M5237 (Aladdin-V) USB controller");
 1061 
 1062         /* OPTi -- vendor 0x1045 */
 1063         case 0xc8611045:
 1064                 return ("OPTi 82C861 (FireLink) USB controller");
 1065 
 1066         /* NEC -- vendor 0x1033 */
 1067         case 0x00351033:
 1068                 return ("NEC uPD 9210 USB controller");
 1069 
 1070         /* CMD Tech -- vendor 0x1095 */
 1071         case 0x06701095:
 1072                 return ("CMD Tech 670 (USB0670) USB controller");
 1073         case 0x06731095:
 1074                 return ("CMD Tech 673 (USB0673) USB controller");
 1075         }
 1076 
 1077         if (pci_get_class(dev) == PCIC_SERIALBUS
 1078             && pci_get_subclass(dev) == PCIS_SERIALBUS_USB) {
 1079                 if (pci_get_progif(dev) == 0x00 /* UHCI */ ) {
 1080                         return ("UHCI USB controller");
 1081                 } else if (pci_get_progif(dev) == 0x10 /* OHCI */ ) {
 1082                         return ("OHCI USB controller");
 1083                 } else {
 1084                         return ("USB controller");
 1085                 }
 1086         }
 1087         return NULL;
 1088 }
 1089 
 1090 const char *
 1091 pci_ata_match(device_t dev)
 1092 {
 1093 
 1094         switch (pci_get_devid(dev)) {
 1095 
 1096         /* Intel -- vendor 0x8086 */
 1097         case 0x12308086:
 1098                 return ("Intel PIIX ATA controller");
 1099         case 0x70108086:
 1100                 return ("Intel PIIX3 ATA controller");
 1101         case 0x71118086:
 1102                 return ("Intel PIIX4 ATA controller");
 1103         case 0x12348086:
 1104                 return ("Intel 82371MX mobile PCI ATA accelerator (MPIIX)");
 1105 
 1106         /* Promise -- vendor 0x105a */
 1107         case 0x4d33105a:
 1108                 return ("Promise Ultra/33 ATA controller");
 1109         case 0x4d38105a:
 1110                 return ("Promise Ultra/66 ATA controller");
 1111 
 1112         /* AcerLabs -- vendor 0x10b9 */
 1113         case 0x522910b9:
 1114                 return ("AcerLabs Aladdin ATA controller");
 1115 
 1116         /* VIA Technologies -- vendor 0x1106 (0x1107 on the Apollo Master) */
 1117         case 0x05711106:
 1118                 switch (pci_read_config(dev, 0x08, 1)) {
 1119                 case 1:
 1120                         return ("VIA 85C586 ATA controller");
 1121                 case 6:
 1122                         return ("VIA 85C586 ATA controller");
 1123                 }
 1124                 /* FALL THROUGH */
 1125         case 0x15711106:
 1126                 return ("VIA Apollo ATA controller");
 1127 
 1128         /* CMD Tech -- vendor 0x1095 */
 1129         case 0x06401095:
 1130                 return ("CMD 640 ATA controller");
 1131         case 0x06461095:
 1132                 return ("CMD 646 ATA controller");
 1133 
 1134         /* Cypress -- vendor 0x1080 */
 1135         case 0xc6931080:
 1136                 return ("Cypress 82C693 ATA controller");
 1137 
 1138         /* Cyrix -- vendor 0x1078 */
 1139         case 0x01021078:
 1140                 return ("Cyrix 5530 ATA controller");
 1141 
 1142         /* SiS -- vendor 0x1039 */
 1143         case 0x55131039:
 1144                 return ("SiS 5591 ATA controller");
 1145 
 1146         /* Highpoint tech -- vendor 0x1103 */
 1147         case 0x00041103:
 1148                 return ("HighPoint HPT366 ATA controller");
 1149         }
 1150 
 1151         if (pci_get_class(dev) == PCIC_STORAGE &&
 1152             pci_get_subclass(dev) == PCIS_STORAGE_IDE)
 1153                 return ("Unknown PCI ATA controller");
 1154 
 1155         return NULL;
 1156 }
 1157 
 1158 
 1159 static const char*
 1160 chip_match(device_t dev)
 1161 {
 1162         unsigned        rev;
 1163 
 1164         switch (pci_get_devid(dev)) {
 1165         /* Intel -- vendor 0x8086 */
 1166         case 0x00088086:
 1167                 /* Silently ignore this one! What is it, anyway ??? */
 1168                 return ("");
 1169         case 0x71108086:
 1170                 /*
 1171                  * On my laptop (Tecra 8000DVD), this device has a
 1172                  * bogus subclass 0x80 so make sure that it doesn't
 1173                  * match the generic 'chip' driver by accident.
 1174                  */
 1175                 return NULL;
 1176         case 0x12258086:
 1177                 fixbushigh_i1225(dev);
 1178                 return ("Intel 824?? host to PCI bridge");
 1179         case 0x71808086:
 1180                 return ("Intel 82443LX (440 LX) host to PCI bridge");
 1181         case 0x71908086:
 1182                 return ("Intel 82443BX (440 BX) host to PCI bridge");
 1183         case 0x71928086:
 1184                 return ("Intel 82443BX host to PCI bridge (AGP disabled)");
 1185         case 0x71a08086:
 1186                 return ("Intel 82443GX host to PCI bridge");
 1187         case 0x71a18086:
 1188                 return ("Intel 82443GX host to AGP bridge");
 1189         case 0x71a28086:
 1190                 return ("Intel 82443GX host to PCI bridge (AGP disabled)");
 1191         case 0x84c48086:
 1192                 return ("Intel 82454KX/GX (Orion) host to PCI bridge");
 1193         case 0x84ca8086:
 1194                 return ("Intel 82451NX Memory and I/O controller");
 1195         case 0x04868086:
 1196                 return ("Intel 82425EX PCI system controller");
 1197         case 0x04838086:
 1198                 return ("Intel 82424ZX (Saturn) cache DRAM controller");
 1199         case 0x04a38086:
 1200                 rev = pci_get_revid(dev);
 1201                 if (rev == 16 || rev == 17)
 1202                     return ("Intel 82434NX (Neptune) PCI cache memory controller");
 1203                 return ("Intel 82434LX (Mercury) PCI cache memory controller");
 1204         case 0x122d8086:
 1205                 return ("Intel 82437FX PCI cache memory controller");
 1206         case 0x12358086:
 1207                 return ("Intel 82437MX mobile PCI cache memory controller");
 1208         case 0x12508086:
 1209                 return ("Intel 82439HX PCI cache memory controller");
 1210         case 0x70308086:
 1211                 return ("Intel 82437VX PCI cache memory controller");
 1212         case 0x71008086:
 1213                 return ("Intel 82439TX System controller (MTXC)");
 1214         case 0x71138086:
 1215                 return ("Intel 82371AB Power management controller");
 1216         case 0x719b8086:
 1217                 return ("Intel 82443MX Power management controller");
 1218         case 0x12378086:
 1219                 fixwsc_natoma(dev);
 1220                 return ("Intel 82440FX (Natoma) PCI and memory controller");
 1221         case 0x84c58086:
 1222                 return ("Intel 82453KX/GX (Orion) PCI memory controller");
 1223         case 0x71208086:
 1224                 return ("Intel 82810 (i810 GMCH) Host To Hub bridge");
 1225         case 0x71228086:
 1226         return ("Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge");
 1227         case 0x71248086:
 1228         return ("Intel 82810E (i810E GMCH) Host To Hub bridge");
 1229         case 0x24158086:
 1230                 return ("Intel 82801AA (ICH) AC'97 Audio Controller");
 1231         case 0x24258086:
 1232                 return ("Intel 82801AB (ICH0) AC'97 Audio Controller");
 1233 
 1234         /* Sony -- vendor 0x104d */
 1235         case 0x8009104d:
 1236                 return ("Sony CXD1947A FireWire Host Controller");
 1237 
 1238         /* SiS -- vendor 0x1039 */
 1239         case 0x04961039:
 1240                 return ("SiS 85c496 PCI/VL Bridge");
 1241         case 0x04061039:
 1242                 return ("SiS 85c501");
 1243         case 0x06011039:
 1244                 return ("SiS 85c601");
 1245         case 0x55911039:
 1246                 return ("SiS 5591 host to PCI bridge");
 1247         case 0x00011039:
 1248                 return ("SiS 5591 host to AGP bridge");
 1249         
 1250         /* VLSI -- vendor 0x1004 */
 1251         case 0x00051004:
 1252                 return ("VLSI 82C592 Host to PCI bridge");
 1253         case 0x01011004:
 1254                 return ("VLSI 82C532 Eagle II Peripheral controller");
 1255         case 0x01041004:
 1256                 return ("VLSI 82C535 Eagle II System controller");
 1257         case 0x01051004:
 1258                 return ("VLSI 82C147 IrDA controller");
 1259 
 1260         /* VIA Technologies -- vendor 0x1106 (0x1107 on the Apollo Master) */
 1261         case 0x15761107:
 1262                 return ("VIA 82C570 (Apollo Master) system controller");
 1263         case 0x05851106:
 1264                 return ("VIA 82C585 (Apollo VP1/VPX) system controller");
 1265         case 0x05951106:
 1266         case 0x15951106:
 1267                 return ("VIA 82C595 (Apollo VP2) system controller");
 1268         case 0x05971106:
 1269                 return ("VIA 82C597 (Apollo VP3) system controller");
 1270         /* XXX Here is MVP3, I got the datasheet but NO M/B to test it  */
 1271         /* totally. Please let me know if anything wrong.            -F */
 1272         /* XXX need info on the MVP3 -- any takers? */
 1273         case 0x05981106:
 1274                 return ("VIA 82C598MVP (Apollo MVP3) host bridge");
 1275         case 0x30401106:
 1276         case 0x30501106:
 1277         case 0x30571106:
 1278                 return NULL;
 1279         case 0x30581106:
 1280                 return ("VIA 82C686 AC97 Audio");
 1281         case 0x30681106:
 1282                 return ("VIA 82C686 AC97 Modem");
 1283 
 1284         /* AMD -- vendor 0x1022 */
 1285         case 0x70061022:
 1286                 return ("AMD-751 host to PCI bridge");
 1287         case 0x700e1022:
 1288                 return ("AMD-761 host to PCI bridge");
 1289 
 1290         /* NEC -- vendor 0x1033 */
 1291         case 0x00021033:
 1292                 return ("NEC 0002 PCI to PC-98 local bus bridge");
 1293         case 0x00161033:
 1294                 return ("NEC 0016 PCI to PC-98 local bus bridge");
 1295 
 1296         /* AcerLabs -- vendor 0x10b9 */
 1297         /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
 1298         /* id is '10b9" but the register always shows "10b9". -Foxfair  */
 1299         case 0x154110b9:
 1300                 return ("AcerLabs M1541 (Aladdin-V) PCI host bridge");
 1301         case 0x710110b9:
 1302                 return ("AcerLabs M15x3 Power Management Unit");
 1303 
 1304         /* OPTi -- vendor 0x1045 */
 1305         case 0xc5571045:
 1306                 return ("Opti 82C557 (Viper-M) host to PCI bridge");
 1307         case 0xc5581045:
 1308                 return ("Opti 82C558 (Viper-M) ISA+IDE");
 1309         case 0xc8221045:
 1310                 return ("OPTi 82C822 host to PCI Bridge");
 1311 
 1312         /* Texas Instruments -- vendor 0x104c */
 1313         case 0xac1c104c:
 1314                 return ("Texas Instruments PCI1225 CardBus controller");
 1315         case 0xac50104c:
 1316                 return ("Texas Instruments PCI1410 CardBus controller");
 1317         case 0xac51104c:
 1318                 return ("Texas Instruments PCI1420 CardBus controller");
 1319         case 0xac1b104c:
 1320                 return ("Texas Instruments PCI1450 CardBus controller");
 1321         case 0xac52104c:
 1322                 return ("Texas Instruments PCI1451 CardBus controller");
 1323 
 1324         /* NeoMagic -- vendor 0x10c8 */
 1325         case 0x800510c8:
 1326                 return ("NeoMagic MagicMedia 256AX Audio controller");
 1327         case 0x800610c8:
 1328                 return ("NeoMagic MagicMedia 256ZX Audio controller");
 1329 
 1330         /* ESS Technology Inc -- vendor 0x125d */
 1331         case 0x1978125d:
 1332                 return ("ESS Technology Maestro 2E Audio controller");
 1333 
 1334         /* Toshiba -- vendor 0x1179 */
 1335         case 0x07011179:
 1336                 return ("Toshiba Fast Infra Red controller");
 1337 
 1338         /* NEC -- vendor 0x1033 */
 1339 
 1340         /* PCI to C-bus bridge */
 1341         /* The following chipsets are PCI to PC98 C-bus bridge.
 1342          * The C-bus is the 16-bits bus on PC98 and it should be probed as
 1343          * PCI to ISA bridge.  Because class of the C-bus is not defined,
 1344          * C-bus bridges are recognized as "other bridge."  To make C-bus
 1345          * bridge be recognized as ISA bridge, this function returns NULL.
 1346          */
 1347         case 0x00011033:
 1348         case 0x002c1033:
 1349         case 0x003b1033:
 1350                 return NULL;
 1351         };
 1352 
 1353         if (pci_get_class(dev) == PCIC_BRIDGE
 1354             && pci_get_subclass(dev) != PCIS_BRIDGE_PCI
 1355             && pci_get_subclass(dev) != PCIS_BRIDGE_ISA
 1356             && pci_get_subclass(dev) != PCIS_BRIDGE_EISA)
 1357                 return pci_bridge_type(dev);
 1358 
 1359         return NULL;
 1360 }
 1361 
 1362 static int chip_probe(device_t dev)
 1363 {
 1364         const char *desc;
 1365 
 1366         desc = chip_match(dev);
 1367         if (desc) {
 1368                 if (pci_get_class(dev) == PCIC_BRIDGE
 1369                     && pci_get_subclass(dev) == PCIS_BRIDGE_HOST) {
 1370                         /*
 1371                          * Suppress printing this device since the nexus
 1372                          * has already described it.
 1373                          */
 1374                         device_quiet(dev);
 1375                 }
 1376 
 1377                 device_set_desc_copy(dev, desc);
 1378                 return -10000;  /* Low match priority */
 1379         }
 1380 
 1381         return ENXIO;
 1382 }
 1383 
 1384 static int chip_attach(device_t dev)
 1385 {
 1386         chipset_attach(dev, device_get_unit(dev));
 1387 
 1388         return 0;
 1389 }
 1390 
 1391 static device_method_t chip_methods[] = {
 1392         /* Device interface */
 1393         DEVMETHOD(device_probe,         chip_probe),
 1394         DEVMETHOD(device_attach,        chip_attach),
 1395 
 1396         { 0, 0 }
 1397 };
 1398 
 1399 static driver_t chip_driver = {
 1400         "chip",
 1401         chip_methods,
 1402         1,
 1403 };
 1404 
 1405 static devclass_t chip_devclass;
 1406 
 1407 DRIVER_MODULE(chip, pci, chip_driver, chip_devclass, 0, 0);
 1408 
 1409 /*---------------------------------------------------------
 1410 **
 1411 **      Catchall driver for VGA devices
 1412 **
 1413 **      By Garrett Wollman
 1414 **      <wollman@halloran-eldar.lcs.mit.edu>
 1415 **
 1416 **---------------------------------------------------------
 1417 */
 1418 
 1419 const char* pci_vga_match(device_t dev)
 1420 {
 1421         u_int id = pci_get_devid(dev);
 1422         const char *vendor, *chip, *type;
 1423 
 1424         vendor = chip = type = 0;
 1425         switch (id & 0xffff) {
 1426         case 0x003d:
 1427                 vendor = "Real 3D";
 1428                 switch (id >> 16) {
 1429                 case 0x00d1:
 1430                         chip = "i740"; break;
 1431                 }
 1432                 break;
 1433         case 0x10c8:
 1434                 vendor = "NeoMagic";
 1435                 switch (id >> 16) {
 1436                 case 0x0003:
 1437                         chip = "MagicGraph 128ZV"; break;
 1438                 case 0x0004:
 1439                         chip = "MagicGraph 128XD"; break;
 1440                 case 0x0005:
 1441                         chip = "MagicMedia 256AV"; break;
 1442                 case 0x0006:
 1443                         chip = "MagicMedia 256ZX"; break;
 1444                 }
 1445                 break;
 1446         case 0x121a:
 1447                 vendor = "3Dfx";
 1448                 type = "graphics accelerator";
 1449                 switch (id >> 16) {
 1450                 case 0x0001:
 1451                         chip = "Voodoo"; break;
 1452                 case 0x0002:
 1453                         chip = "Voodoo 2"; break;
 1454                 case 0x0003:
 1455                         chip = "Voodoo Banshee"; break;
 1456                 case 0x0005:
 1457                         chip = "Voodoo 3"; break;
 1458                 }
 1459                 break;
 1460         case 0x102b:
 1461                 vendor = "Matrox";
 1462                 type = "graphics accelerator";
 1463                 switch (id >> 16) {
 1464                 case 0x0518:
 1465                         chip = "MGA 2085PX"; break;
 1466                 case 0x0519:
 1467                         chip = "MGA Millennium 2064W"; break;
 1468                 case 0x051a:
 1469                         chip = "MGA 1024SG/1064SG/1164SG"; break;
 1470                 case 0x051b:
 1471                         chip = "MGA Millennium II 2164W"; break;
 1472                 case 0x051f:
 1473                         chip = "MGA Millennium II 2164WA-B AG"; break;
 1474                 case 0x0520:
 1475                         chip = "MGA G200"; break;
 1476                 case 0x0521:
 1477                         chip = "MGA G200 AGP"; break;
 1478                 case 0x0525:
 1479                         chip = "MGA G400 AGP"; break;
 1480                 case 0x0d10:
 1481                         chip = "MGA Impression"; break;
 1482                 case 0x1000:
 1483                         chip = "MGA G100"; break;
 1484                 case 0x1001:
 1485                         chip = "MGA G100 AGP"; break;
 1486                 case 0x2527:
 1487                         chip = "MGA G550 AGP"; break;
 1488 
 1489                 }
 1490                 break;
 1491         case 0x1002:
 1492                 vendor = "ATI";
 1493                 type = "graphics accelerator";
 1494                 switch (id >> 16) {
 1495                 case 0x4158:
 1496                         chip = "Mach32"; break;
 1497                 case 0x4354:
 1498                         chip = "Mach64-CT"; break;
 1499                 case 0x4358:
 1500                         chip = "Mach64-CX"; break;
 1501                 case 0x4554:
 1502                         chip = "Mach64-ET"; break;
 1503                 case 0x4654:
 1504                 case 0x5654:
 1505                         chip = "Mach64-VT"; break;
 1506                 case 0x4742:
 1507                         chip = "Mach64-GB"; break;
 1508                 case 0x4744:
 1509                         chip = "Mach64-GD"; break;
 1510                 case 0x4749:
 1511                         chip = "Mach64-GI"; break;
 1512                 case 0x474d:
 1513                         chip = "Mach64-GM"; break;
 1514                 case 0x474e:
 1515                         chip = "Mach64-GN"; break;
 1516                 case 0x474f:
 1517                         chip = "Mach64-GO"; break;
 1518                 case 0x4750:
 1519                         chip = "Mach64-GP"; break;
 1520                 case 0x4751:
 1521                         chip = "Mach64-GQ"; break;
 1522                 case 0x4752:
 1523                         chip = "Mach64-GR"; break;
 1524                 case 0x4753:
 1525                         chip = "Mach64-GS"; break;
 1526                 case 0x4754:
 1527                         chip = "Mach64-GT"; break;
 1528                 case 0x4755:
 1529                         chip = "Mach64-GU"; break;
 1530                 case 0x4756:
 1531                         chip = "Mach64-GV"; break;
 1532                 case 0x4757:
 1533                         chip = "Mach64-GW"; break;
 1534                 case 0x4758:
 1535                         chip = "Mach64-GX"; break;
 1536                 case 0x4c4d:
 1537                         chip = "Mobility-1"; break;
 1538                 case 0x4c52:
 1539                         chip = "RageMobility-P/M"; break;
 1540                 case 0x475a:
 1541                         chip = "Mach64-GZ"; break;
 1542                 case 0x5245:
 1543                         chip = "Rage128-RE"; break;
 1544                 case 0x5246:
 1545                         chip = "Rage128-RF"; break;
 1546                 case 0x524b:
 1547                         chip = "Rage128-RK"; break;
 1548                 case 0x524c:
 1549                         chip = "Rage128-RL"; break;
 1550                 }
 1551                 break;
 1552         case 0x1005:
 1553                 vendor = "Avance Logic";
 1554                 switch (id >> 16) {
 1555                 case 0x2301:
 1556                         chip = "ALG2301"; break;
 1557                 case 0x2302:
 1558                         chip = "ALG2302"; break;
 1559                 }
 1560                 break;
 1561         case 0x100c:
 1562                 vendor = "Tseng Labs";
 1563                 type = "graphics accelerator";
 1564                 switch (id >> 16) {
 1565                 case 0x3202:
 1566                 case 0x3205:
 1567                 case 0x3206:
 1568                 case 0x3207:
 1569                         chip = "ET4000 W32P"; break;
 1570                 case 0x3208:
 1571                         chip = "ET6000/ET6100"; break;
 1572                 case 0x4702:
 1573                         chip = "ET6300"; break;
 1574                 }
 1575                 break;
 1576         case 0x100e:
 1577                 vendor = "Weitek";
 1578                 type = "graphics accelerator";
 1579                 switch (id >> 16) {
 1580                 case 0x9001:
 1581                         chip = "P9000"; break;
 1582                 case 0x9100:
 1583                         chip = "P9100"; break;
 1584                 }
 1585                 break;
 1586         case 0x1013:
 1587                 vendor = "Cirrus Logic";
 1588                 switch (id >> 16) {
 1589                 case 0x0038:
 1590                         chip = "GD7548"; break;
 1591                 case 0x0040:
 1592                         chip = "GD7555"; break;
 1593                 case 0x004c:
 1594                         chip = "GD7556"; break;
 1595                 case 0x00a0:
 1596                         chip = "GD5430"; break;
 1597                 case 0x00a4:
 1598                 case 0x00a8:
 1599                         chip = "GD5434"; break;
 1600                 case 0x00ac:
 1601                         chip = "GD5436"; break;
 1602                 case 0x00b8:
 1603                         chip = "GD5446"; break;
 1604                 case 0x00bc:
 1605                         chip = "GD5480"; break;
 1606                 case 0x00d0:
 1607                         chip = "GD5462"; break;
 1608                 case 0x00d4:
 1609                 case 0x00d5:
 1610                         chip = "GD5464"; break;
 1611                 case 0x00d6:
 1612                         chip = "GD5465"; break;
 1613                 case 0x1200:
 1614                         chip = "GD7542"; break;
 1615                 case 0x1202:
 1616                         chip = "GD7543"; break;
 1617                 case 0x1204:
 1618                         chip = "GD7541"; break;
 1619                 }
 1620                 break;
 1621         case 0x1023:
 1622                 vendor = "Trident";
 1623                 break;          /* let default deal with it */
 1624         case 0x102c:
 1625                 vendor = "Chips & Technologies";
 1626                 switch (id >> 16) {
 1627                 case 0x00b8:
 1628                         chip = "64310"; break;
 1629                 case 0x00d8:
 1630                         chip = "65545"; break;
 1631                 case 0x00dc:
 1632                         chip = "65548"; break;
 1633                 case 0x00c0:
 1634                         chip = "69000"; break;
 1635                 case 0x00e0:
 1636                         chip = "65550"; break;
 1637                 case 0x00e4:
 1638                         chip = "65554"; break;
 1639                 case 0x00e5:
 1640                         chip = "65555"; break;
 1641                 case 0x00f4:
 1642                         chip = "68554"; break;
 1643                 }
 1644                 break;
 1645         case 0x1033:
 1646                 vendor = "NEC";
 1647                 switch (id >> 16) {
 1648                 case 0x0009:
 1649                         type = "PCI to PC-98 Core Graph bridge";
 1650                         break;
 1651                 }
 1652                 break;
 1653         case 0x1039:
 1654                 vendor = "SiS";
 1655                 switch (id >> 16) {
 1656                 case 0x0001:
 1657                         chip = "86c201"; break;
 1658                 case 0x0002:
 1659                         chip = "86c202"; break;
 1660                 case 0x0205:
 1661                         chip = "86c205"; break;
 1662                 case 0x0215:
 1663                         chip = "86c215"; break;
 1664                 case 0x0225:
 1665                         chip = "86c225"; break;
 1666                 case 0x0200:
 1667                         chip = "5597/98"; break;
 1668                 case 0x6326:
 1669                         chip = "6326"; break;
 1670                 case 0x6306:
 1671                         chip = "530/620"; break;
 1672                 }
 1673                 break;
 1674         case 0x105d:
 1675                 vendor = "Number Nine";
 1676                 type = "graphics accelerator";
 1677                 switch (id >> 16) {
 1678                 case 0x2309:
 1679                         chip = "Imagine 128"; break;
 1680                 case 0x2339:
 1681                         chip = "Imagine 128 II"; break;
 1682                 }
 1683                 break;
 1684         case 0x1142:
 1685                 vendor = "Alliance";
 1686                 switch (id >> 16) {
 1687                 case 0x3210:
 1688                         chip = "PM6410"; break;
 1689                 case 0x6422:
 1690                         chip = "PM6422"; break;
 1691                 case 0x6424:
 1692                         chip = "PMAT24"; break;
 1693                 }
 1694                 break;
 1695         case 0x1163:
 1696                 vendor = "Rendition Verite";
 1697                 switch (id >> 16) {
 1698                 case 0x0001:
 1699                         chip = "V1000"; break;
 1700                 case 0x2000:
 1701                         chip = "V2000"; break;
 1702                 }
 1703                 break;
 1704         case 0x1236:
 1705                 vendor = "Sigma Designs";
 1706                 if ((id >> 16) == 0x6401)
 1707                         chip = "REALmagic64/GX";
 1708                 break;
 1709         case 0x5333:
 1710                 vendor = "S3";
 1711                 type = "graphics accelerator";
 1712                 switch (id >> 16) {
 1713                 case 0x8811:
 1714                         chip = "Trio"; break;
 1715                 case 0x8812:
 1716                         chip = "Aurora 64"; break;
 1717                 case 0x8814:
 1718                         chip = "Trio 64UV+"; break;
 1719                 case 0x8901:
 1720                         chip = "Trio 64V2/DX/GX"; break;
 1721                 case 0x8902:
 1722                         chip = "Plato"; break;
 1723                 case 0x8904:
 1724                         chip = "Trio3D"; break;
 1725                 case 0x8880:
 1726                         chip = "868"; break;
 1727                 case 0x88b0:
 1728                         chip = "928"; break;
 1729                 case 0x88c0:
 1730                 case 0x88c1:
 1731                         chip = "864"; break;
 1732                 case 0x88d0:
 1733                 case 0x88d1:
 1734                         chip = "964"; break;
 1735                 case 0x88f0:
 1736                         chip = "968"; break;
 1737                 case 0x5631:
 1738                         chip = "ViRGE"; break;
 1739                 case 0x883d:
 1740                         chip = "ViRGE VX"; break;
 1741                 case 0x8a01:
 1742                         chip = "ViRGE DX/GX"; break;
 1743                 case 0x8a10:
 1744                         chip = "ViRGE GX2"; break;
 1745                 case 0x8a13:
 1746                         chip = "Trio3D/2X"; break;
 1747                 case 0x8a20:
 1748                 case 0x8a21:
 1749                         chip = "Savage3D"; break;
 1750                 case 0x8a22:
 1751                         chip = "Savage 4"; break;
 1752                 case 0x8c01:
 1753                         chip = "ViRGE MX"; break;
 1754                 case 0x8c03:
 1755                         chip = "ViRGE MX+"; break;
 1756                 }
 1757                 break;
 1758         case 0xedd8:
 1759                 vendor = "ARK Logic";
 1760                 switch (id >> 16) {
 1761                 case 0xa091:
 1762                         chip = "1000PV"; break;
 1763                 case 0xa099:
 1764                         chip = "2000PV"; break;
 1765                 case 0xa0a1:
 1766                         chip = "2000MT"; break;
 1767                 case 0xa0a9:
 1768                         chip = "2000MI"; break;
 1769                 }
 1770                 break;
 1771         case 0x3d3d:
 1772                 vendor = "3D Labs";
 1773                 type = "graphics accelerator";
 1774                 switch (id >> 16) {
 1775                 case 0x0001:
 1776                         chip = "300SX"; break;
 1777                 case 0x0002:
 1778                         chip = "500TX"; break;
 1779                 case 0x0003:
 1780                         chip = "Delta"; break;
 1781                 case 0x0004:
 1782                         chip = "PerMedia"; break;
 1783                 }
 1784                 break;
 1785         case 0x10de:
 1786                 vendor = "NVidia";
 1787                 type = "graphics accelerator";
 1788                 switch (id >> 16) {
 1789                 case 0x0008:
 1790                         chip = "NV1"; break;
 1791                 case 0x0020:
 1792                         chip = "Riva TNT"; break;       
 1793                 case 0x0028:
 1794                         chip = "Riva TNT2"; break;
 1795                 case 0x0029:
 1796                         chip = "Riva Ultra TNT2"; break;
 1797                 case 0x002c:
 1798                         chip = "Riva Vanta TNT2"; break;
 1799                 case 0x002d:
 1800                         chip = "Riva Ultra Vanta TNT2"; break;
 1801                 case 0x00a0:
 1802                         chip = "Riva Integrated TNT2"; break;
 1803                 case 0x0100:
 1804                         chip = "GeForce 256"; break;
 1805                 case 0x0101:
 1806                         chip = "GeForce DDR"; break;
 1807                 case 0x0103:
 1808                         chip = "Quadro"; break;
 1809                 case 0x0150:
 1810                 case 0x0151:
 1811                 case 0x0152:
 1812                         chip = "GeForce2 GTS"; break;
 1813                 case 0x0153:
 1814                         chip = "Quadro2"; break;
 1815                 }
 1816                 break;
 1817         case 0x12d2:
 1818                 vendor = "NVidia/SGS-Thomson";
 1819                 type = "graphics accelerator";
 1820                 switch (id >> 16) {
 1821                 case 0x0018:
 1822                         chip = "Riva128"; break;        
 1823                 }
 1824                 break;
 1825         case 0x104a:
 1826                 vendor = "SGS-Thomson";
 1827                 switch (id >> 16) {
 1828                 case 0x0008:
 1829                         chip = "STG2000"; break;
 1830                 }
 1831                 break;
 1832         case 0x8086:
 1833                 vendor = "Intel";
 1834                 switch (id >> 16) {
 1835                 case 0x7121:
 1836                         chip = "82810 (i810 GMCH)"; break;
 1837                 case 0x7123:
 1838                         chip = "82810-DC100 (i810-DC100 GMCH)"; break;
 1839                 case 0x7125:
 1840                         chip = "82810E (i810E GMCH)"; break;
 1841                 case 0x7800:
 1842                         chip = "i740 AGP"; break;
 1843                 }
 1844                 break;
 1845         case 0x10ea:
 1846                 vendor = "Intergraphics";
 1847                 switch (id >> 16) {
 1848                 case 0x1680:
 1849                         chip = "IGA-1680"; break;
 1850                 case 0x1682:
 1851                         chip = "IGA-1682"; break;
 1852                 }
 1853                 break;
 1854         }
 1855 
 1856         if (vendor && chip) {
 1857                 char *buf;
 1858                 int len;
 1859 
 1860                 if (type == 0)
 1861                         type = "SVGA controller";
 1862 
 1863                 len = strlen(vendor) + strlen(chip) + strlen(type) + 4;
 1864                 MALLOC(buf, char *, len, M_TEMP, M_NOWAIT);
 1865                 if (buf)
 1866                         sprintf(buf, "%s %s %s", vendor, chip, type);
 1867                 return buf;
 1868         }
 1869 
 1870         switch (pci_get_class(dev)) {
 1871 
 1872         case PCIC_OLD:
 1873                 if (pci_get_subclass(dev) != PCIS_OLD_VGA)
 1874                         return 0;
 1875                 if (type == 0)
 1876                         type = "VGA-compatible display device";
 1877                 break;
 1878 
 1879         case PCIC_DISPLAY:
 1880                 if (type == 0) {
 1881                         if (pci_get_subclass(dev) == PCIS_DISPLAY_VGA)
 1882                                 type = "VGA-compatible display device";
 1883                         else {
 1884                                 /*
 1885                                  * If it isn't a vga display device,
 1886                                  * don't pretend we found one.
 1887                                  */
 1888                                 return 0;
 1889                         }
 1890                 }
 1891                 break;
 1892 
 1893         default:
 1894                 return 0;
 1895         };
 1896         /*
 1897          * If we got here, we know for sure it's some sort of display
 1898          * device, but we weren't able to identify it specifically.
 1899          * At a minimum we can return the type, but we'd like to
 1900          * identify the vendor and chip ID if at all possible.
 1901          * (Some of the checks above intentionally don't bother for
 1902          * vendors where we know the chip ID is the same as the
 1903          * model number.)
 1904          */
 1905         if (vendor) {
 1906                 char *buf;
 1907                 int len;
 1908 
 1909                 len = strlen(vendor) + strlen(type) + 2 + 6 + 4 + 1;
 1910                 MALLOC(buf, char *, len, M_TEMP, M_NOWAIT);
 1911                 if (buf)
 1912                         sprintf(buf, "%s model %04x %s", vendor, id >> 16, type);
 1913                 return buf;
 1914         }
 1915         return type;
 1916 }
 1917 
 1918 /*---------------------------------------------------------
 1919 **
 1920 **      Devices to ignore
 1921 **
 1922 **---------------------------------------------------------
 1923 */
 1924 
 1925 static int
 1926 ign_probe (device_t dev)
 1927 {
 1928         switch (pci_get_devid(dev)) {
 1929 
 1930         case 0x10001042ul:      /* wd */
 1931                 return 0;
 1932 /*              return ("SMC FDC 37c665");*/
 1933         };
 1934         return ENXIO;
 1935 }
 1936 
 1937 static int
 1938 ign_attach (device_t dev)
 1939 {
 1940         return 0;
 1941 }
 1942 
 1943 static device_method_t ign_methods[] = {
 1944         /* Device interface */
 1945         DEVMETHOD(device_probe,         ign_probe),
 1946         DEVMETHOD(device_attach,        ign_attach),
 1947 
 1948         { 0, 0 }
 1949 };
 1950 
 1951 static driver_t ign_driver = {
 1952         "ign",
 1953         ign_methods,
 1954         1,
 1955 };
 1956 
 1957 static devclass_t ign_devclass;
 1958 
 1959 DRIVER_MODULE(ign, pci, ign_driver, ign_devclass, 0, 0);

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