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sys/pci/pcisupport.c
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1 /************************************************************************** 2 ** 3 ** $FreeBSD: src/sys/pci/pcisupport.c,v 1.40.2.10 1999/09/05 08:21:26 peter Exp $ 4 ** 5 ** Device driver for DEC/INTEL PCI chipsets. 6 ** 7 ** FreeBSD 8 ** 9 **------------------------------------------------------------------------- 10 ** 11 ** Written for FreeBSD by 12 ** wolf@cologne.de Wolfgang Stanglmeier 13 ** se@mi.Uni-Koeln.de Stefan Esser 14 ** 15 **------------------------------------------------------------------------- 16 ** 17 ** Copyright (c) 1994,1995 Stefan Esser. All rights reserved. 18 ** 19 ** Redistribution and use in source and binary forms, with or without 20 ** modification, are permitted provided that the following conditions 21 ** are met: 22 ** 1. Redistributions of source code must retain the above copyright 23 ** notice, this list of conditions and the following disclaimer. 24 ** 2. Redistributions in binary form must reproduce the above copyright 25 ** notice, this list of conditions and the following disclaimer in the 26 ** documentation and/or other materials provided with the distribution. 27 ** 3. The name of the author may not be used to endorse or promote products 28 ** derived from this software without specific prior written permission. 29 ** 30 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 31 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 32 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 33 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 34 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 35 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 39 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 ** 41 *************************************************************************** 42 */ 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 50 #include <pci/pcivar.h> 51 #include <pci/pcireg.h> 52 53 static void config_orion (pcici_t tag); 54 static void config_i1225 (pcici_t tag); 55 static void config_Ross (pcici_t tag); 56 57 /*--------------------------------------------------------- 58 ** 59 ** Intel chipsets for 486 / Pentium processor 60 ** 61 **--------------------------------------------------------- 62 */ 63 64 static char* chipset_probe (pcici_t tag, pcidi_t type); 65 static void chipset_attach(pcici_t tag, int unit); 66 static u_long chipset_count; 67 68 static struct pci_device chipset_device = { 69 "chip", 70 chipset_probe, 71 chipset_attach, 72 &chipset_count, 73 NULL 74 }; 75 76 DATA_SET (pcidevice_set, chipset_device); 77 78 struct condmsg { 79 unsigned char port; 80 unsigned char mask; 81 unsigned char value; 82 char flags; 83 const char *text; 84 }; 85 86 /* make sure formats expand to at least as many chars !!! */ 87 #define PPB_DESCR "generic PCI bridge (vendor=%04x device=%04x subclass=%1.2d)" 88 89 static char* 90 generic_pci_bridge (pcici_t tag) 91 { 92 char *descr; 93 unsigned classreg = pci_conf_read (tag, PCI_CLASS_REG); 94 95 if ((classreg & PCI_CLASS_MASK) == PCI_CLASS_BRIDGE) { 96 97 unsigned id = pci_conf_read (tag, PCI_ID_REG); 98 99 descr = malloc (sizeof PPB_DESCR +1, M_DEVBUF, M_WAITOK); 100 if (descr) { 101 sprintf (descr, PPB_DESCR, id & 0xffff, (id >> 16) & 0xffff, 102 (classreg >> 16) & 0xff); 103 } 104 return descr; 105 } 106 return 0; 107 } 108 109 110 static char* 111 chipset_probe (pcici_t tag, pcidi_t type) 112 { 113 unsigned rev; 114 char *descr; 115 116 switch (type) { 117 case 0x04868086: 118 return ("Intel 82425EX PCI system controller"); 119 case 0x04848086: 120 rev = (unsigned) pci_conf_read (tag, PCI_CLASS_REG) & 0xff; 121 if (rev == 3) 122 return ("Intel 82378ZB PCI-ISA bridge"); 123 return ("Intel 82378IB PCI-ISA bridge"); 124 case 0x04838086: 125 return ("Intel 82424ZX (Saturn) cache DRAM controller"); 126 case 0x04828086: 127 return ("Intel 82375EB PCI-EISA bridge"); 128 case 0x04961039: 129 return ("SiS 85c496"); 130 case 0x04a38086: 131 rev = (unsigned) pci_conf_read (tag, PCI_CLASS_REG) & 0xff; 132 if (rev == 16 || rev == 17) 133 return ("Intel 82434NX (Neptune) PCI cache memory controller"); 134 return ("Intel 82434LX (Mercury) PCI cache memory controller"); 135 case 0x122d8086: 136 return ("Intel 82437FX PCI cache memory controller"); 137 case 0x122e8086: 138 return ("Intel 82371FB PCI-ISA bridge"); 139 case 0x12308086: 140 return ("Intel 82371FB IDE interface"); 141 case 0x12348086: 142 return ("Intel 82371MX mobile PCI I/O IDE accelerator (MPIIX)"); 143 case 0x12358086: 144 return ("Intel 82437MX mobile PCI cache memory controller"); 145 case 0x12508086: 146 return ("Intel 82439"); 147 case 0x04061039: 148 return ("SiS 85c501"); 149 case 0x00081039: 150 return ("SiS 85c503"); 151 case 0x06011039: 152 return ("SiS 85c601"); 153 case 0x70008086: 154 return ("Intel 82371SB PCI-ISA bridge"); 155 case 0x70108086: 156 return ("Intel 82371SB IDE interface"); 157 case 0x70308086: 158 return ("Intel 82437VX PCI cache memory controller"); 159 case 0x71008086: 160 return ("Intel 82439TX PCI cache memory controller"); 161 case 0x71108086: 162 return ("Intel 82371AB PCI-ISA bridge"); 163 case 0x71118086: 164 return ("Intel 82371AB IDE interface"); 165 case 0x71128086: 166 return ("Intel 82371AB USB interface"); 167 case 0x71138086: 168 return ("Intel 82371AB Power management controller"); 169 case 0x12378086: 170 return ("Intel 82440FX (Natoma) PCI and memory controller"); 171 case 0x84c48086: 172 return ("Intel 82450KX (Orion) PCI memory controller"); 173 case 0x84c58086: 174 return ("Intel 82454GX (Orion) host to PCI bridge"); 175 case 0x84ca8086: 176 return ("Intel 82451NX Memory and I/O Controller"); 177 case 0x84cb8086: 178 return ("Intel 82454NX PCI Expander Bridge"); 179 case 0x00051166: 180 return ("Ross (?) host to PCI bridge"); 181 case 0x00221014: 182 return ("IBM 82351 PCI-PCI bridge"); 183 case 0x00011011: 184 return ("DEC 21050 PCI-PCI bridge"); 185 186 /* NEC -- vendor 0x1033 */ 187 case 0x00011033: 188 return ("NEC 0001 PCI to PC-98 C-bus bridge"); 189 case 0x00021033: 190 return ("NEC 0002 PCI to PC-98 local bus bridge"); 191 case 0x00161033: 192 return ("NEC 0016 PCI to PC-98 local bus bridge"); 193 case 0x002c1033: 194 return ("NEC 002C PCI to PC-98 C-bus bridge"); 195 case 0x003b1033: 196 return ("NEC 003B PCI to PC-98 C-bus bridge"); 197 }; 198 199 if (descr = generic_pci_bridge(tag)) 200 return descr; 201 202 return NULL; 203 } 204 205 #ifndef PCI_QUIET 206 207 #define M_XX 0 /* end of list */ 208 #define M_EQ 1 /* mask and return true if equal */ 209 #define M_NE 2 /* mask and return true if not equal */ 210 #define M_TR 3 /* don't read config, always true */ 211 #define M_EN 4 /* mask and print "enabled" if true, "disabled" if false */ 212 #define M_NN 5 /* opposite sense of M_EN */ 213 214 static const struct condmsg conf82425ex[] = 215 { 216 { 0x00, 0x00, 0x00, M_TR, "\tClock " }, 217 { 0x50, 0x06, 0x00, M_EQ, "25" }, 218 { 0x50, 0x06, 0x02, M_EQ, "33" }, 219 { 0x50, 0x04, 0x04, M_EQ, "??", }, 220 { 0x00, 0x00, 0x00, M_TR, "MHz, L1 Cache " }, 221 { 0x50, 0x01, 0x00, M_EQ, "Disabled\n" }, 222 { 0x50, 0x09, 0x01, M_EQ, "Write-through\n" }, 223 { 0x50, 0x09, 0x09, M_EQ, "Write-back\n" }, 224 225 { 0x00, 0x00, 0x00, M_TR, "\tL2 Cache " }, 226 { 0x52, 0x07, 0x00, M_EQ, "Disabled" }, 227 { 0x52, 0x0f, 0x01, M_EQ, "64KB Write-through" }, 228 { 0x52, 0x0f, 0x02, M_EQ, "128KB Write-through" }, 229 { 0x52, 0x0f, 0x03, M_EQ, "256KB Write-through" }, 230 { 0x52, 0x0f, 0x04, M_EQ, "512KB Write-through" }, 231 { 0x52, 0x0f, 0x01, M_EQ, "64KB Write-back" }, 232 { 0x52, 0x0f, 0x02, M_EQ, "128KB Write-back" }, 233 { 0x52, 0x0f, 0x03, M_EQ, "256KB Write-back" }, 234 { 0x52, 0x0f, 0x04, M_EQ, "512KB Write-back" }, 235 { 0x53, 0x01, 0x00, M_EQ, ", 3-" }, 236 { 0x53, 0x01, 0x01, M_EQ, ", 2-" }, 237 { 0x53, 0x06, 0x00, M_EQ, "3-3-3" }, 238 { 0x53, 0x06, 0x02, M_EQ, "2-2-2" }, 239 { 0x53, 0x06, 0x04, M_EQ, "1-1-1" }, 240 { 0x53, 0x06, 0x06, M_EQ, "?-?-?" }, 241 { 0x53, 0x18, 0x00, M_EQ, "/4-2-2-2\n" }, 242 { 0x53, 0x18, 0x08, M_EQ, "/3-2-2-2\n" }, 243 { 0x53, 0x18, 0x10, M_EQ, "/?-?-?-?\n" }, 244 { 0x53, 0x18, 0x18, M_EQ, "/2-1-1-1\n" }, 245 246 { 0x56, 0x00, 0x00, M_TR, "\tDRAM: " }, 247 { 0x56, 0x02, 0x02, M_EQ, "Fast Code Read, " }, 248 { 0x56, 0x04, 0x04, M_EQ, "Fast Data Read, " }, 249 { 0x56, 0x08, 0x08, M_EQ, "Fast Write, " }, 250 { 0x57, 0x20, 0x20, M_EQ, "Pipelined CAS" }, 251 { 0x57, 0x2e, 0x00, M_NE, "\n\t" }, 252 { 0x57, 0x00, 0x00, M_TR, "Timing: RAS: " }, 253 { 0x57, 0x07, 0x00, M_EQ, "4" }, 254 { 0x57, 0x07, 0x01, M_EQ, "3" }, 255 { 0x57, 0x07, 0x02, M_EQ, "2" }, 256 { 0x57, 0x07, 0x04, M_EQ, "1.5" }, 257 { 0x57, 0x07, 0x05, M_EQ, "1" }, 258 { 0x57, 0x00, 0x00, M_TR, " Clocks, CAS Read: " }, 259 { 0x57, 0x18, 0x00, M_EQ, "3/1", }, 260 { 0x57, 0x18, 0x00, M_EQ, "2/1", }, 261 { 0x57, 0x18, 0x00, M_EQ, "1.5/0.5", }, 262 { 0x57, 0x18, 0x00, M_EQ, "1/1", }, 263 { 0x57, 0x00, 0x00, M_TR, ", CAS Write: " }, 264 { 0x57, 0x20, 0x00, M_EQ, "2/1", }, 265 { 0x57, 0x20, 0x20, M_EQ, "1/1", }, 266 { 0x57, 0x00, 0x00, M_TR, "\n" }, 267 268 { 0x40, 0x01, 0x01, M_EQ, "\tCPU-to-PCI Byte Merging\n" }, 269 { 0x40, 0x02, 0x02, M_EQ, "\tCPU-to-PCI Bursting\n" }, 270 { 0x40, 0x04, 0x04, M_EQ, "\tPCI Posted Writes\n" }, 271 { 0x40, 0x20, 0x00, M_EQ, "\tDRAM Parity Disabled\n" }, 272 273 { 0x48, 0x03, 0x01, M_EQ, "\tPCI IDE controller: Primary (1F0h-1F7h,3F6h,3F7h)" }, 274 { 0x48, 0x03, 0x02, M_EQ, "\tPCI IDE controller: Secondary (170h-177h,376h,377h)" }, 275 { 0x4d, 0x01, 0x01, M_EQ, "\tRTC (70-77h)\n" }, 276 { 0x4d, 0x02, 0x02, M_EQ, "\tKeyboard (60,62,64,66h)\n" }, 277 { 0x4d, 0x08, 0x08, M_EQ, "\tIRQ12/M Mouse Function\n" }, 278 279 /* end marker */ 280 { 0 } 281 }; 282 283 static const struct condmsg conf82424zx[] = 284 { 285 { 0x00, 0x00, 0x00, M_TR, "\tCPU: " }, 286 { 0x50, 0xe0, 0x00, M_EQ, "486DX" }, 287 { 0x50, 0xe0, 0x20, M_EQ, "486SX" }, 288 { 0x50, 0xe0, 0x40, M_EQ, "486DX2 or 486DX4" }, 289 { 0x50, 0xe0, 0x80, M_EQ, "Overdrive (writeback)" }, 290 291 { 0x00, 0x00, 0x00, M_TR, ", bus=" }, 292 { 0x50, 0x03, 0x00, M_EQ, "25MHz" }, 293 { 0x50, 0x03, 0x01, M_EQ, "33MHz" }, 294 { 0x53, 0x01, 0x01, M_TR, ", CPU->Memory posting "}, 295 { 0x53, 0x01, 0x00, M_EQ, "OFF" }, 296 { 0x53, 0x01, 0x01, M_EQ, "ON" }, 297 298 { 0x56, 0x30, 0x00, M_NE, "\n\tWarning:" }, 299 { 0x56, 0x20, 0x00, M_NE, " NO cache parity!" }, 300 { 0x56, 0x10, 0x00, M_NE, " NO DRAM parity!" }, 301 { 0x55, 0x04, 0x04, M_EQ, "\n\tWarning: refresh OFF! " }, 302 303 { 0x00, 0x00, 0x00, M_TR, "\n\tCache: " }, 304 { 0x52, 0x01, 0x00, M_EQ, "None" }, 305 { 0x52, 0xc1, 0x01, M_EQ, "64KB" }, 306 { 0x52, 0xc1, 0x41, M_EQ, "128KB" }, 307 { 0x52, 0xc1, 0x81, M_EQ, "256KB" }, 308 { 0x52, 0xc1, 0xc1, M_EQ, "512KB" }, 309 { 0x52, 0x03, 0x01, M_EQ, " writethrough" }, 310 { 0x52, 0x03, 0x03, M_EQ, " writeback" }, 311 312 { 0x52, 0x01, 0x01, M_EQ, ", cache clocks=" }, 313 { 0x52, 0x05, 0x01, M_EQ, "3-1-1-1" }, 314 { 0x52, 0x05, 0x05, M_EQ, "2-1-1-1" }, 315 316 { 0x00, 0x00, 0x00, M_TR, "\n\tDRAM:" }, 317 { 0x55, 0x43, 0x00, M_NE, " page mode" }, 318 { 0x55, 0x02, 0x02, M_EQ, " code fetch" }, 319 { 0x55, 0x43, 0x43, M_EQ, "," }, 320 { 0x55, 0x43, 0x42, M_EQ, " and" }, 321 { 0x55, 0x40, 0x40, M_EQ, " read" }, 322 { 0x55, 0x03, 0x03, M_EQ, " and" }, 323 { 0x55, 0x43, 0x41, M_EQ, " and" }, 324 { 0x55, 0x01, 0x01, M_EQ, " write" }, 325 { 0x55, 0x43, 0x00, M_NE, "," }, 326 327 { 0x00, 0x00, 0x00, M_TR, " memory clocks=" }, 328 { 0x55, 0x20, 0x00, M_EQ, "X-2-2-2" }, 329 { 0x55, 0x20, 0x20, M_EQ, "X-1-2-1" }, 330 331 { 0x00, 0x00, 0x00, M_TR, "\n\tCPU->PCI: posting " }, 332 { 0x53, 0x02, 0x00, M_NE, "ON" }, 333 { 0x53, 0x02, 0x00, M_EQ, "OFF" }, 334 { 0x00, 0x00, 0x00, M_TR, ", burst mode " }, 335 { 0x54, 0x02, 0x00, M_NE, "ON" }, 336 { 0x54, 0x02, 0x00, M_EQ, "OFF" }, 337 { 0x00, 0x00, 0x00, M_TR, "\n\tPCI->Memory: posting " }, 338 { 0x54, 0x01, 0x00, M_NE, "ON" }, 339 { 0x54, 0x01, 0x00, M_EQ, "OFF" }, 340 341 { 0x00, 0x00, 0x00, M_TR, "\n" }, 342 343 /* end marker */ 344 { 0 } 345 }; 346 347 static const struct condmsg conf82434lx[] = 348 { 349 { 0x00, 0x00, 0x00, M_TR, "\tCPU: " }, 350 { 0x50, 0xe3, 0x82, M_EQ, "Pentium, 60MHz" }, 351 { 0x50, 0xe3, 0x83, M_EQ, "Pentium, 66MHz" }, 352 { 0x50, 0xe3, 0xa2, M_EQ, "Pentium, 90MHz" }, 353 { 0x50, 0xe3, 0xa3, M_EQ, "Pentium, 100MHz" }, 354 { 0x50, 0xc2, 0x82, M_NE, "(unknown)" }, 355 { 0x50, 0x04, 0x00, M_EQ, " (primary cache OFF)" }, 356 357 { 0x53, 0x01, 0x01, M_TR, ", CPU->Memory posting "}, 358 { 0x53, 0x01, 0x01, M_NE, "OFF" }, 359 { 0x53, 0x01, 0x01, M_EQ, "ON" }, 360 361 { 0x53, 0x08, 0x00, M_NE, ", read around write"}, 362 363 { 0x70, 0x04, 0x00, M_EQ, "\n\tWarning: Cache parity disabled!" }, 364 { 0x57, 0x20, 0x00, M_NE, "\n\tWarning: DRAM parity mask!" }, 365 { 0x57, 0x01, 0x00, M_EQ, "\n\tWarning: refresh OFF! " }, 366 367 { 0x00, 0x00, 0x00, M_TR, "\n\tCache: " }, 368 { 0x52, 0x01, 0x00, M_EQ, "None" }, 369 { 0x52, 0x81, 0x01, M_EQ, "" }, 370 { 0x52, 0xc1, 0x81, M_EQ, "256KB" }, 371 { 0x52, 0xc1, 0xc1, M_EQ, "512KB" }, 372 { 0x52, 0x03, 0x01, M_EQ, " writethrough" }, 373 { 0x52, 0x03, 0x03, M_EQ, " writeback" }, 374 375 { 0x52, 0x01, 0x01, M_EQ, ", cache clocks=" }, 376 { 0x52, 0x21, 0x01, M_EQ, "3-2-2-2/4-2-2-2" }, 377 { 0x52, 0x21, 0x21, M_EQ, "3-1-1-1" }, 378 379 { 0x52, 0x01, 0x01, M_EQ, "\n\tCache flags: " }, 380 { 0x52, 0x11, 0x11, M_EQ, " cache-all" }, 381 { 0x52, 0x09, 0x09, M_EQ, " byte-control" }, 382 { 0x52, 0x05, 0x05, M_EQ, " powersaver" }, 383 384 { 0x00, 0x00, 0x00, M_TR, "\n\tDRAM:" }, 385 { 0x57, 0x10, 0x00, M_EQ, " page mode" }, 386 387 { 0x00, 0x00, 0x00, M_TR, " memory clocks=" }, 388 { 0x57, 0xc0, 0x00, M_EQ, "X-4-4-4 (70ns)" }, 389 { 0x57, 0xc0, 0x40, M_EQ, "X-4-4-4/X-3-3-3 (60ns)" }, 390 { 0x57, 0xc0, 0x80, M_EQ, "???" }, 391 { 0x57, 0xc0, 0xc0, M_EQ, "X-3-3-3 (50ns)" }, 392 { 0x58, 0x02, 0x02, M_EQ, ", RAS-wait" }, 393 { 0x58, 0x01, 0x01, M_EQ, ", CAS-wait" }, 394 395 { 0x00, 0x00, 0x00, M_TR, "\n\tCPU->PCI: posting " }, 396 { 0x53, 0x02, 0x02, M_EQ, "ON" }, 397 { 0x53, 0x02, 0x00, M_EQ, "OFF" }, 398 { 0x00, 0x00, 0x00, M_TR, ", burst mode " }, 399 { 0x54, 0x02, 0x00, M_NE, "ON" }, 400 { 0x54, 0x02, 0x00, M_EQ, "OFF" }, 401 { 0x54, 0x04, 0x00, M_TR, ", PCI clocks=" }, 402 { 0x54, 0x04, 0x00, M_EQ, "2-2-2-2" }, 403 { 0x54, 0x04, 0x00, M_NE, "2-1-1-1" }, 404 { 0x00, 0x00, 0x00, M_TR, "\n\tPCI->Memory: posting " }, 405 { 0x54, 0x01, 0x00, M_NE, "ON" }, 406 { 0x54, 0x01, 0x00, M_EQ, "OFF" }, 407 408 { 0x57, 0x01, 0x01, M_EQ, "\n\tRefresh:" }, 409 { 0x57, 0x03, 0x03, M_EQ, " CAS#/RAS#(Hidden)" }, 410 { 0x57, 0x03, 0x01, M_EQ, " RAS#Only" }, 411 { 0x57, 0x05, 0x05, M_EQ, " BurstOf4" }, 412 413 { 0x00, 0x00, 0x00, M_TR, "\n" }, 414 415 /* end marker */ 416 { 0 } 417 }; 418 419 static const struct condmsg conf82378[] = 420 { 421 { 0x00, 0x00, 0x00, M_TR, "\tBus Modes:" }, 422 { 0x41, 0x04, 0x04, M_EQ, " Bus Park," }, 423 { 0x41, 0x02, 0x02, M_EQ, " Bus Lock," }, 424 { 0x41, 0x02, 0x00, M_EQ, " Resource Lock," }, 425 { 0x41, 0x01, 0x01, M_EQ, " GAT" }, 426 { 0x4d, 0x20, 0x20, M_EQ, "\n\tCoprocessor errors enabled" }, 427 { 0x4d, 0x10, 0x10, M_EQ, "\n\tMouse function enabled" }, 428 429 { 0x4e, 0x30, 0x10, M_EQ, "\n\tIDE controller: Primary (1F0h-1F7h,3F6h,3F7h)" }, 430 { 0x4e, 0x30, 0x30, M_EQ, "\n\tIDE controller: Secondary (170h-177h,376h,377h)" }, 431 { 0x4e, 0x28, 0x08, M_EQ, "\n\tFloppy controller: 3F0h,3F1h " }, 432 { 0x4e, 0x24, 0x04, M_EQ, "\n\tFloppy controller: 3F2h-3F7h " }, 433 { 0x4e, 0x28, 0x28, M_EQ, "\n\tFloppy controller: 370h,371h " }, 434 { 0x4e, 0x24, 0x24, M_EQ, "\n\tFloppy controller: 372h-377h " }, 435 { 0x4e, 0x02, 0x02, M_EQ, "\n\tKeyboard controller: 60h,62h,64h,66h" }, 436 { 0x4e, 0x01, 0x01, M_EQ, "\n\tRTC: 70h-77h" }, 437 438 { 0x4f, 0x80, 0x80, M_EQ, "\n\tConfiguration RAM: 0C00h,0800h-08FFh" }, 439 { 0x4f, 0x40, 0x40, M_EQ, "\n\tPort 92: enabled" }, 440 { 0x4f, 0x03, 0x00, M_EQ, "\n\tSerial Port A: COM1 (3F8h-3FFh)" }, 441 { 0x4f, 0x03, 0x01, M_EQ, "\n\tSerial Port A: COM2 (2F8h-2FFh)" }, 442 { 0x4f, 0x0c, 0x00, M_EQ, "\n\tSerial Port B: COM1 (3F8h-3FFh)" }, 443 { 0x4f, 0x0c, 0x04, M_EQ, "\n\tSerial Port B: COM2 (2F8h-2FFh)" }, 444 { 0x4f, 0x30, 0x00, M_EQ, "\n\tParallel Port: LPT1 (3BCh-3BFh)" }, 445 { 0x4f, 0x30, 0x04, M_EQ, "\n\tParallel Port: LPT2 (378h-37Fh)" }, 446 { 0x4f, 0x30, 0x20, M_EQ, "\n\tParallel Port: LPT3 (278h-27Fh)" }, 447 { 0x00, 0x00, 0x00, M_TR, "\n" }, 448 449 /* end marker */ 450 { 0 } 451 }; 452 453 static const struct condmsg conf82437fx[] = 454 { 455 /* PCON -- PCI Control Register */ 456 { 0x00, 0x00, 0x00, M_TR, "\tCPU Inactivity timer: " }, 457 { 0x50, 0xe0, 0xe0, M_EQ, "8" }, 458 { 0x50, 0xe0, 0xd0, M_EQ, "7" }, 459 { 0x50, 0xe0, 0xc0, M_EQ, "6" }, 460 { 0x50, 0xe0, 0xb0, M_EQ, "5" }, 461 { 0x50, 0xe0, 0xa0, M_EQ, "4" }, 462 { 0x50, 0xe0, 0x90, M_EQ, "3" }, 463 { 0x50, 0xe0, 0x80, M_EQ, "2" }, 464 { 0x50, 0xe0, 0x00, M_EQ, "1" }, 465 { 0x00, 0x00, 0x00, M_TR, " clocks\n\tPeer Concurrency: " }, 466 { 0x50, 0x08, 0x08, M_EN, 0 }, 467 { 0x00, 0x00, 0x00, M_TR, "\n\tCPU-to-PCI Write Bursting: " }, 468 { 0x50, 0x04, 0x00, M_NN, 0 }, 469 { 0x00, 0x00, 0x00, M_TR, "\n\tPCI Streaming: " }, 470 { 0x50, 0x02, 0x00, M_NN, 0 }, 471 { 0x00, 0x00, 0x00, M_TR, "\n\tBus Concurrency: " }, 472 { 0x50, 0x01, 0x00, M_NN, 0 }, 473 474 /* CC -- Cache Control Regsiter */ 475 { 0x00, 0x00, 0x00, M_TR, "\n\tCache:" }, 476 { 0x52, 0xc0, 0x80, M_EQ, " 512K" }, 477 { 0x52, 0xc0, 0x40, M_EQ, " 256K" }, 478 { 0x52, 0xc0, 0x00, M_EQ, " NO" }, 479 { 0x52, 0x30, 0x00, M_EQ, " pipelined-burst" }, 480 { 0x52, 0x30, 0x10, M_EQ, " burst" }, 481 { 0x52, 0x30, 0x20, M_EQ, " asynchronous" }, 482 { 0x52, 0x30, 0x30, M_EQ, " dual-bank pipelined-burst" }, 483 { 0x00, 0x00, 0x00, M_TR, " secondary; L1 " }, 484 { 0x52, 0x01, 0x00, M_EN, 0 }, 485 { 0x00, 0x00, 0x00, M_TR, "\n" }, 486 487 /* DRAMC -- DRAM Control Register */ 488 { 0x57, 0x07, 0x00, M_EQ, "Warning: refresh OFF!\n" }, 489 { 0x00, 0x00, 0x00, M_TR, "\tDRAM:" }, 490 { 0x57, 0xc0, 0x00, M_EQ, " no memory hole" }, 491 { 0x57, 0xc0, 0x40, M_EQ, " 512K-640K memory hole" }, 492 { 0x57, 0xc0, 0x80, M_EQ, " 15M-16M memory hole" }, 493 { 0x57, 0x07, 0x01, M_EQ, ", 50 MHz refresh" }, 494 { 0x57, 0x07, 0x02, M_EQ, ", 60 MHz refresh" }, 495 { 0x57, 0x07, 0x03, M_EQ, ", 66 MHz refresh" }, 496 497 /* DRAMT = DRAM Timing Register */ 498 { 0x00, 0x00, 0x00, M_TR, "\n\tRead burst timing: " }, 499 { 0x58, 0x60, 0x00, M_EQ, "x-4-4-4/x-4-4-4" }, 500 { 0x58, 0x60, 0x20, M_EQ, "x-3-3-3/x-4-4-4" }, 501 { 0x58, 0x60, 0x40, M_EQ, "x-2-2-2/x-3-3-3" }, 502 { 0x58, 0x60, 0x60, M_EQ, "???" }, 503 { 0x00, 0x00, 0x00, M_TR, "\n\tWrite burst timing: " }, 504 { 0x58, 0x18, 0x00, M_EQ, "x-4-4-4" }, 505 { 0x58, 0x18, 0x08, M_EQ, "x-3-3-3" }, 506 { 0x58, 0x18, 0x10, M_EQ, "x-2-2-2" }, 507 { 0x58, 0x18, 0x18, M_EQ, "???" }, 508 { 0x00, 0x00, 0x00, M_TR, "\n\tRAS-CAS delay: " }, 509 { 0x58, 0x04, 0x00, M_EQ, "3" }, 510 { 0x58, 0x04, 0x04, M_EQ, "2" }, 511 { 0x00, 0x00, 0x00, M_TR, " clocks\n" }, 512 513 /* end marker */ 514 { 0 } 515 }; 516 517 static const struct condmsg conf82437vx[] = 518 { 519 /* PCON -- PCI Control Register */ 520 { 0x00, 0x00, 0x00, M_TR, "\n\tPCI Concurrency: " }, 521 { 0x50, 0x08, 0x08, M_EN, 0 }, 522 523 /* CC -- Cache Control Regsiter */ 524 { 0x00, 0x00, 0x00, M_TR, "\n\tCache:" }, 525 { 0x52, 0xc0, 0x80, M_EQ, " 512K" }, 526 { 0x52, 0xc0, 0x40, M_EQ, " 256K" }, 527 { 0x52, 0xc0, 0x00, M_EQ, " NO" }, 528 { 0x52, 0x30, 0x00, M_EQ, " pipelined-burst" }, 529 { 0x52, 0x30, 0x10, M_EQ, " burst" }, 530 { 0x52, 0x30, 0x20, M_EQ, " asynchronous" }, 531 { 0x52, 0x30, 0x30, M_EQ, " dual-bank pipelined-burst" }, 532 { 0x00, 0x00, 0x00, M_TR, " secondary; L1 " }, 533 { 0x52, 0x01, 0x00, M_EN, 0 }, 534 { 0x00, 0x00, 0x00, M_TR, "\n" }, 535 536 /* DRAMC -- DRAM Control Register */ 537 { 0x57, 0x07, 0x00, M_EQ, "Warning: refresh OFF!\n" }, 538 { 0x00, 0x00, 0x00, M_TR, "\tDRAM:" }, 539 { 0x57, 0xc0, 0x00, M_EQ, " no memory hole" }, 540 { 0x57, 0xc0, 0x40, M_EQ, " 512K-640K memory hole" }, 541 { 0x57, 0xc0, 0x80, M_EQ, " 15M-16M memory hole" }, 542 { 0x57, 0x07, 0x01, M_EQ, ", 50 MHz refresh" }, 543 { 0x57, 0x07, 0x02, M_EQ, ", 60 MHz refresh" }, 544 { 0x57, 0x07, 0x03, M_EQ, ", 66 MHz refresh" }, 545 546 /* DRAMT = DRAM Timing Register */ 547 { 0x00, 0x00, 0x00, M_TR, "\n\tRead burst timing: " }, 548 { 0x58, 0x60, 0x00, M_EQ, "x-4-4-4/x-4-4-4" }, 549 { 0x58, 0x60, 0x20, M_EQ, "x-3-3-3/x-4-4-4" }, 550 { 0x58, 0x60, 0x40, M_EQ, "x-2-2-2/x-3-3-3" }, 551 { 0x58, 0x60, 0x60, M_EQ, "???" }, 552 { 0x00, 0x00, 0x00, M_TR, "\n\tWrite burst timing: " }, 553 { 0x58, 0x18, 0x00, M_EQ, "x-4-4-4" }, 554 { 0x58, 0x18, 0x08, M_EQ, "x-3-3-3" }, 555 { 0x58, 0x18, 0x10, M_EQ, "x-2-2-2" }, 556 { 0x58, 0x18, 0x18, M_EQ, "???" }, 557 { 0x00, 0x00, 0x00, M_TR, "\n\tRAS-CAS delay: " }, 558 { 0x58, 0x04, 0x00, M_EQ, "3" }, 559 { 0x58, 0x04, 0x04, M_EQ, "2" }, 560 { 0x00, 0x00, 0x00, M_TR, " clocks\n" }, 561 562 /* end marker */ 563 { 0 } 564 }; 565 566 static const struct condmsg conf82371fb[] = 567 { 568 /* IORT -- ISA I/O Recovery Timer Register */ 569 { 0x00, 0x00, 0x00, M_TR, "\tI/O Recovery Timing: 8-bit " }, 570 { 0x4c, 0x40, 0x00, M_EQ, "3.5" }, 571 { 0x4c, 0x78, 0x48, M_EQ, "1" }, 572 { 0x4c, 0x78, 0x50, M_EQ, "2" }, 573 { 0x4c, 0x78, 0x58, M_EQ, "3" }, 574 { 0x4c, 0x78, 0x60, M_EQ, "4" }, 575 { 0x4c, 0x78, 0x68, M_EQ, "5" }, 576 { 0x4c, 0x78, 0x70, M_EQ, "6" }, 577 { 0x4c, 0x78, 0x78, M_EQ, "7" }, 578 { 0x4c, 0x78, 0x40, M_EQ, "8" }, 579 { 0x00, 0x00, 0x00, M_TR, " clocks, 16-bit " }, 580 { 0x4c, 0x04, 0x00, M_EQ, "3.5" }, 581 { 0x4c, 0x07, 0x05, M_EQ, "1" }, 582 { 0x4c, 0x07, 0x06, M_EQ, "2" }, 583 { 0x4c, 0x07, 0x07, M_EQ, "3" }, 584 { 0x4c, 0x07, 0x04, M_EQ, "4" }, 585 { 0x00, 0x00, 0x00, M_TR, " clocks\n" }, 586 587 /* XBCS -- X-Bus Chip Select Register */ 588 { 0x00, 0x00, 0x00, M_TR, "\tExtended BIOS: " }, 589 { 0x4e, 0x80, 0x80, M_EN, 0 }, 590 { 0x00, 0x00, 0x00, M_TR, "\n\tLower BIOS: " }, 591 { 0x4e, 0x40, 0x40, M_EN, 0 }, 592 { 0x00, 0x00, 0x00, M_TR, "\n\tCoprocessor IRQ13: " }, 593 { 0x4e, 0x20, 0x20, M_EN, 0 }, 594 { 0x00, 0x00, 0x00, M_TR, "\n\tMouse IRQ12: " }, 595 { 0x4e, 0x10, 0x10, M_EN, 0 }, 596 { 0x00, 0x00, 0x00, M_TR, "\n" }, 597 598 { 0x00, 0x00, 0x00, M_TR, "\tInterrupt Routing: " }, 599 #define PIRQ(x, n) \ 600 { 0x00, 0x00, 0x00, M_TR, n ": " }, \ 601 { x, 0x80, 0x80, M_EQ, "disabled" }, \ 602 { x, 0xc0, 0x40, M_EQ, "[shared] " }, \ 603 { x, 0x8f, 0x03, M_EQ, "IRQ3" }, \ 604 { x, 0x8f, 0x04, M_EQ, "IRQ4" }, \ 605 { x, 0x8f, 0x05, M_EQ, "IRQ5" }, \ 606 { x, 0x8f, 0x06, M_EQ, "IRQ6" }, \ 607 { x, 0x8f, 0x07, M_EQ, "IRQ7" }, \ 608 { x, 0x8f, 0x09, M_EQ, "IRQ9" }, \ 609 { x, 0x8f, 0x0a, M_EQ, "IRQ10" }, \ 610 { x, 0x8f, 0x0b, M_EQ, "IRQ11" }, \ 611 { x, 0x8f, 0x0c, M_EQ, "IRQ12" }, \ 612 { x, 0x8f, 0x0e, M_EQ, "IRQ14" }, \ 613 { x, 0x8f, 0x0f, M_EQ, "IRQ15" } 614 615 /* Interrupt routing */ 616 PIRQ(0x60, "A"), 617 PIRQ(0x61, ", B"), 618 PIRQ(0x62, ", C"), 619 PIRQ(0x63, ", D"), 620 PIRQ(0x70, "\n\t\tMB0"), 621 PIRQ(0x71, ", MB1"), 622 623 { 0x00, 0x00, 0x00, M_TR, "\n" }, 624 625 #undef PIRQ 626 627 /* XXX - do DMA routing, too? */ 628 { 0 } 629 }; 630 631 static const struct condmsg conf82371fb2[] = 632 { 633 /* IDETM -- IDE Timing Register */ 634 { 0x00, 0x00, 0x00, M_TR, "\tPrimary IDE: " }, 635 { 0x41, 0x80, 0x80, M_EN, 0 }, 636 { 0x00, 0x00, 0x00, M_TR, "\n\tSecondary IDE: " }, 637 { 0x43, 0x80, 0x80, M_EN, 0 }, 638 { 0x00, 0x00, 0x00, M_TR, "\n" }, 639 640 /* end of list */ 641 { 0 } 642 }; 643 644 static char confread (pcici_t config_id, int port) 645 { 646 unsigned long portw = port & ~3; 647 unsigned long ports = (port - portw) << 3; 648 649 unsigned long l = pci_conf_read (config_id, portw); 650 return (l >> ports); 651 } 652 653 static void 654 writeconfig (pcici_t config_id, const struct condmsg *tbl) 655 { 656 while (tbl->flags != M_XX) { 657 const char *text = 0; 658 659 if (tbl->flags == M_TR) { 660 text = tbl->text; 661 } else { 662 unsigned char v = (unsigned char) confread(config_id, tbl->port); 663 switch (tbl->flags) { 664 case M_EQ: 665 if ((v & tbl->mask) == tbl->value) text = tbl->text; 666 break; 667 case M_NE: 668 if ((v & tbl->mask) != tbl->value) text = tbl->text; 669 break; 670 case M_EN: 671 text = (v & tbl->mask) ? "enabled" : "disabled"; 672 break; 673 case M_NN: 674 text = (v & tbl->mask) ? "disabled" : "enabled"; 675 } 676 } 677 if (text) printf ("%s", text); 678 tbl++; 679 } 680 } 681 682 #ifdef DUMPCONFIGSPACE 683 static void 684 dumpconfigspace (pcici_t tag) 685 { 686 int reg; 687 printf ("configuration space registers:"); 688 for (reg = 0; reg < 0x100; reg+=4) { 689 if ((reg & 0x0f) == 0) 690 printf ("\n%02x:\t", reg); 691 printf ("%08x ", pci_conf_read (tag, reg)); 692 } 693 printf ("\n"); 694 } 695 #endif /* DUMPCONFIGSPACE */ 696 697 #endif /* PCI_QUIET */ 698 699 extern unsigned pciroots; 700 701 static void 702 config_orion (pcici_t tag) 703 { 704 unsigned busno = (pci_conf_read (tag, 0x48) >> 16) & 0xff; 705 706 if (busno > 0) { 707 pciroots++; 708 } 709 } 710 711 static void 712 config_i1225(pcici_t tag) 713 { 714 int sublementarybus; 715 716 sublementarybus = (pci_conf_read(tag, 0x40) >> 8) & 0xff; 717 if (sublementarybus != 0xff) 718 pciroots++; 719 } 720 721 static void 722 config_Ross(pcici_t tag) 723 { 724 int secondarybus; 725 726 /* just guessing the secondary bus register number ... */ 727 secondarybus = (pci_conf_read(tag, 0x44) >> 8) & 0xff; 728 if (secondarybus != 0) 729 pciroots++; 730 } 731 732 static void 733 config_450nx(pcici_t tag) 734 { 735 unsigned long devmap; 736 int i; 737 738 /* Read the MIOC devmap to determine which PCI expanders are present */ 739 devmap = (pci_conf_read(tag, 0xd4) >> 16) & 0x3c; 740 741 if (!devmap) { 742 printf("Error: 450NX MIOC: No PCI Expander Bridge present.\n"); 743 return; 744 } 745 746 #if 0 747 /* 748 * This hack is in the spirit of the config_orion() routine. 749 * It *would* work, except that some 450NX-based servers are 750 * set up to SKIP PCI busses, presumably to support hot-plug 751 * PCI cards that contain a single PCI-PCI bridge chip. 752 */ 753 754 /* Now pciroots just needs to get set to the number of bits set... */ 755 756 pciroots = 0; 757 for (i = 2; i < 6; i++) 758 if (devmap & (1 << i)) 759 pciroots++; 760 #else 761 /* 762 * Since the buses are configured in order, we just have to 763 * find the highest bus, and use those numbers. 764 * This is `wrong', but there is nothing else I can really do... 765 */ 766 if (devmap & 0x20) { /* B1, 0xd5 */ 767 pciroots = (pci_conf_read(tag, 0xd4) >> 8) & 0xff; 768 } else if (devmap & 0x10) { /* A1, 0xd4 */ 769 pciroots = pci_conf_read(tag, 0xd4) & 0xff; 770 } else if (devmap & 0x8) { /* B0, 0xd2 */ 771 pciroots = (pci_conf_read(tag, 0xd0) >> 16) & 0xff; 772 } else /* if (devmap & 0x4) */ { /* A0, 0xd1 */ 773 pciroots = (pci_conf_read(tag, 0xd0) >> 8) & 0xff; 774 } 775 #endif 776 777 if (bootverbose) 778 printf("config_450nx: %d PCI busses found\n", pciroots); 779 } 780 781 782 static void 783 chipset_attach (pcici_t config_id, int unit) 784 { 785 switch (pci_conf_read (config_id, PCI_ID_REG)) { 786 787 case 0x84c48086: /* Intel Orion */ 788 config_orion (config_id); 789 break; 790 case 0x12258086: /* unidentified Intel host bridge, dev ID == 0x1225 */ 791 config_i1225 (config_id); 792 break; 793 case 0x00051166: /* Ross ??? */ 794 config_Ross (config_id); 795 break; 796 case 0x84ca8086: /* Intel 450NX */ 797 config_450nx (config_id); 798 break; 799 } 800 #ifndef PCI_QUIET 801 if (!bootverbose) 802 return; 803 804 switch (pci_conf_read (config_id, PCI_ID_REG)) { 805 case 0x04868086: 806 writeconfig (config_id, conf82425ex); 807 break; 808 case 0x04838086: 809 writeconfig (config_id, conf82424zx); 810 break; 811 case 0x04a38086: 812 writeconfig (config_id, conf82434lx); 813 break; 814 case 0x04848086: 815 writeconfig (config_id, conf82378); 816 break; 817 case 0x122d8086: 818 writeconfig (config_id, conf82437fx); 819 break; 820 case 0x70308086: 821 writeconfig (config_id, conf82437vx); 822 break; 823 case 0x70008086: 824 case 0x122e8086: 825 writeconfig (config_id, conf82371fb); 826 break; 827 case 0x70108086: 828 case 0x12308086: 829 writeconfig (config_id, conf82371fb2); 830 break; 831 #if 0 832 case 0x00011011: /* DEC 21050 */ 833 case 0x00221014: /* IBM xxx */ 834 writeconfig (config_id, conf_pci2pci); 835 break; 836 #endif 837 }; 838 #endif /* PCI_QUIET */ 839 } 840 841 /*--------------------------------------------------------- 842 ** 843 ** Catchall driver for VGA devices 844 ** 845 ** By Garrett Wollman 846 ** <wollman@halloran-eldar.lcs.mit.edu> 847 ** 848 **--------------------------------------------------------- 849 */ 850 851 static char* vga_probe (pcici_t tag, pcidi_t type); 852 static void vga_attach (pcici_t tag, int unit); 853 static u_long vga_count; 854 855 static struct pci_device vga_device = { 856 "vga", 857 vga_probe, 858 vga_attach, 859 &vga_count, 860 NULL 861 }; 862 863 DATA_SET (pcidevice_set, vga_device); 864 865 static char* vga_probe (pcici_t tag, pcidi_t type) 866 { 867 int data = pci_conf_read(tag, PCI_CLASS_REG); 868 869 switch (data & PCI_CLASS_MASK) { 870 871 case PCI_CLASS_PREHISTORIC: 872 if ((data & PCI_SUBCLASS_MASK) 873 != PCI_SUBCLASS_PREHISTORIC_VGA) 874 break; 875 876 case PCI_CLASS_DISPLAY: 877 if ((data & PCI_SUBCLASS_MASK) 878 == PCI_SUBCLASS_DISPLAY_VGA) 879 return ("VGA-compatible display device"); 880 else 881 return ("Display device"); 882 }; 883 return ((char*)0); 884 } 885 886 static void vga_attach (pcici_t tag, int unit) 887 { 888 /* 889 ** If the assigned addresses are remapped, 890 ** the console driver has to be informed about the new address. 891 */ 892 #if 0 893 vm_offset_t va; 894 vm_offset_t pa; 895 int reg; 896 for (reg = PCI_MAP_REG_START; reg < PCI_MAP_REG_END; reg += 4) 897 (void) pci_map_mem (tag, reg, &va, &pa); 898 #endif 899 } 900 901 /*--------------------------------------------------------- 902 ** 903 ** Hook for loadable pci drivers 904 ** 905 **--------------------------------------------------------- 906 */ 907 908 static char* lkm_probe (pcici_t tag, pcidi_t type); 909 static void lkm_attach (pcici_t tag, int unit); 910 static u_long lkm_count; 911 912 static struct pci_device lkm_device = { 913 "lkm", 914 lkm_probe, 915 lkm_attach, 916 &lkm_count, 917 NULL 918 }; 919 920 DATA_SET (pcidevice_set, lkm_device); 921 922 static char* 923 lkm_probe (pcici_t tag, pcidi_t type) 924 { 925 /* 926 ** Not yet! 927 ** (Should try to load a matching driver) 928 */ 929 return ((char*)0); 930 } 931 932 static void 933 lkm_attach (pcici_t tag, int unit) 934 {} 935 936 /*--------------------------------------------------------- 937 ** 938 ** Devices to ignore 939 ** 940 **--------------------------------------------------------- 941 */ 942 943 static char* ign_probe (pcici_t tag, pcidi_t type); 944 static void ign_attach (pcici_t tag, int unit); 945 static u_long ign_count; 946 947 static struct pci_device ign_device = { 948 NULL, 949 ign_probe, 950 ign_attach, 951 &ign_count, 952 NULL 953 }; 954 955 DATA_SET (pcidevice_set, ign_device); 956 957 static char* 958 ign_probe (pcici_t tag, pcidi_t type) 959 { 960 switch (type) { 961 962 case 0x10001042ul: /* wd */ 963 return (""); 964 /* return ("SMC FDC 37c665");*/ 965 }; 966 return ((char*)0); 967 } 968 969 static void 970 ign_attach (pcici_t tag, int unit) 971 {}
Cache object: d4a26e67b82732b46d132835b6487741
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