Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/tek390.h
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1 /*********************************************************************** 2 ;* File Name : TEK390.H * 3 ;* TEKRAM DC-390 PCI SCSI Bus Master Host Adapter * 4 ;* Device Driver * 5 ;***********************************************************************/ 6 7 #ifndef TEK390_H 8 #define TEK390_H 9 10 typedef unsigned char UCHAR; 11 typedef unsigned short USHORT; 12 typedef unsigned long ULONG; 13 typedef unsigned int UINT; 14 15 typedef UCHAR *PUCHAR; 16 typedef USHORT *PUSHORT; 17 typedef ULONG *PULONG; 18 typedef struct scsi_link *PSCLINK, SCSILINK; 19 typedef struct scsi_xfer *PSCSICMD, SCSICMD; 20 typedef void *PVOID; 21 22 23 /*;-----------------------------------------------------------------------*/ 24 typedef struct _SyncMsg 25 { 26 UCHAR ExtendMsg; 27 UCHAR ExtMsgLen; 28 UCHAR SyncXferReq; 29 UCHAR Period; 30 UCHAR ReqOffset; 31 } SyncMsg; 32 /*;-----------------------------------------------------------------------*/ 33 typedef struct _Capacity 34 { 35 ULONG BlockCount; 36 ULONG BlockLength; 37 } Capacity; 38 /*;-----------------------------------------------------------------------*/ 39 typedef struct _SGentry 40 { 41 ULONG SGXLen; 42 ULONG SGXPtr; 43 } SGentry, *PSEG; 44 45 typedef struct _SGentry1 46 { 47 ULONG SGXPtr1; 48 ULONG SGXLen1; 49 } SGentry1, *PSEG1; 50 51 52 #define MAX_ADAPTER_NUM 4 53 #define MAX_SCSI_ID 8 54 #define MAX_SG_ENTRY 33 55 #define MAX_DEVICES 10 56 #define MAX_CMD_QUEUE 20 57 #define MAX_CMD_PER_LUN 6 58 #define MAX_SRB_CNT MAX_CMD_PER_LUN*4 59 #define PAGELEN 4096 60 61 /* 62 ;----------------------------------------------------------------------- 63 ; SCSI Request Block 64 ;----------------------------------------------------------------------- 65 */ 66 struct _SRB 67 { 68 UCHAR CmdBlock[12]; 69 70 struct _SRB *pNextSRB; 71 struct _DCB *pSRBDCB; 72 PSCSICMD pcmd; 73 PSEG pSegmentList; 74 75 ULONG PhysSRB; 76 ULONG TotalXferredLen; 77 ULONG SGPhysAddr; /*;a segment starting address */ 78 ULONG SGToBeXferLen; /*; to be xfer length */ 79 ULONG Segment0[2]; 80 ULONG Segment1[2]; 81 82 SGentry SGsegment[MAX_SG_ENTRY]; 83 SGentry Segmentx; /* make a one entry of S/G list table */ 84 85 PUCHAR pMsgPtr; 86 USHORT SRBState; 87 USHORT Revxx2; /* ??? */ 88 89 UCHAR MsgInBuf[6]; 90 UCHAR MsgOutBuf[6]; 91 92 UCHAR AdaptStatus; 93 UCHAR TargetStatus; 94 UCHAR MsgCnt; 95 UCHAR EndMessage; 96 UCHAR TagNumber; 97 UCHAR SGcount; 98 UCHAR SGIndex; 99 UCHAR IORBFlag; /*;81h-Reset, 2-retry */ 100 101 UCHAR SRBStatus; 102 UCHAR RetryCnt; 103 UCHAR SRBFlag; /*; b0-AutoReqSense,b6-Read,b7-write */ 104 /*; b4-settimeout,b5-Residual valid */ 105 UCHAR ScsiCmdLen; 106 UCHAR ScsiPhase; 107 UCHAR Reserved3[3]; /*;for dword alignment */ 108 }; 109 110 typedef struct _SRB DC390_SRB, *PSRB; 111 112 /* 113 ;----------------------------------------------------------------------- 114 ; Device Control Block 115 ;----------------------------------------------------------------------- 116 */ 117 struct _DCB 118 { 119 struct _DCB *pNextDCB; 120 struct _ACB *pDCBACB; 121 122 PSRB pWaitingSRB; 123 PSRB pWaitLast; 124 PSRB pGoingSRB; 125 PSRB pGoingLast; 126 PSRB pActiveSRB; 127 USHORT GoingSRBCnt; 128 USHORT WaitSRBCnt; /* ??? */ 129 130 ULONG TagMask; 131 132 USHORT MaxCommand; 133 USHORT AdaptIndex; /*; UnitInfo struc start */ 134 USHORT UnitIndex; /*; nth Unit on this card */ 135 UCHAR UnitSCSIID; /*; SCSI Target ID (SCSI Only) */ 136 UCHAR UnitSCSILUN; /*; SCSI Log. Unit (SCSI Only) */ 137 138 UCHAR IdentifyMsg; 139 UCHAR CtrlR1; 140 UCHAR CtrlR3; 141 UCHAR CtrlR4; 142 143 UCHAR InqDataBuf[8]; 144 UCHAR CapacityBuf[8]; 145 UCHAR DevMode; 146 UCHAR AdpMode; 147 UCHAR SyncMode; /*; 0:async mode */ 148 UCHAR NegoPeriod; /*;for nego. */ 149 UCHAR SyncPeriod; /*;for reg. */ 150 UCHAR SyncOffset; /*;for reg. and nego.(low nibble) */ 151 UCHAR UnitCtrlFlag; 152 UCHAR DCBFlag; 153 UCHAR DevType; 154 UCHAR Reserved2[3]; /*;for dword alignment */ 155 }; 156 157 typedef struct _DCB DC390_DCB, *PDCB; 158 /* 159 ;----------------------------------------------------------------------- 160 ; Adapter Control Block 161 ;----------------------------------------------------------------------- 162 */ 163 struct _ACB 164 { 165 ULONG PhysACB; 166 struct _ACB *pNextACB; 167 USHORT IOPortBase; 168 USHORT Revxx1; /* ??? */ 169 170 PDCB pLinkDCB; 171 PDCB pDCBRunRobin; 172 PDCB pActiveDCB; 173 PDCB pDCB_free; 174 PSRB pFreeSRB; 175 PSRB pTmpSRB; 176 USHORT SRBCount; 177 USHORT AdapterIndex; /*; nth Adapter this driver */ 178 USHORT max_id; 179 USHORT max_lun; 180 SCSILINK ScsiLink; 181 182 UCHAR msgin123[4]; 183 UCHAR status; 184 UCHAR AdaptSCSIID; /*; Adapter SCSI Target ID */ 185 UCHAR AdaptSCSILUN; /*; Adapter SCSI LUN */ 186 UCHAR DeviceCnt; 187 UCHAR IRQLevel; 188 UCHAR TagMaxNum; 189 UCHAR ACBFlag; 190 UCHAR Gmode2; 191 UCHAR LUNchk; 192 UCHAR scan_devices; 193 UCHAR HostID_Bit; 194 UCHAR Reserved1[1]; /*;for dword alignment */ 195 UCHAR DCBmap[MAX_SCSI_ID]; 196 DC390_DCB DCB_array[MAX_DEVICES]; /* +74h, Len=3E8 */ 197 DC390_SRB SRB_array[MAX_SRB_CNT]; /* +45Ch, Len= */ 198 DC390_SRB TmpSRB; 199 }; 200 201 typedef struct _ACB DC390_ACB, *PACB; 202 203 /*;-----------------------------------------------------------------------*/ 204 205 206 #define BIT31 0x80000000 207 #define BIT30 0x40000000 208 #define BIT29 0x20000000 209 #define BIT28 0x10000000 210 #define BIT27 0x08000000 211 #define BIT26 0x04000000 212 #define BIT25 0x02000000 213 #define BIT24 0x01000000 214 #define BIT23 0x00800000 215 #define BIT22 0x00400000 216 #define BIT21 0x00200000 217 #define BIT20 0x00100000 218 #define BIT19 0x00080000 219 #define BIT18 0x00040000 220 #define BIT17 0x00020000 221 #define BIT16 0x00010000 222 #define BIT15 0x00008000 223 #define BIT14 0x00004000 224 #define BIT13 0x00002000 225 #define BIT12 0x00001000 226 #define BIT11 0x00000800 227 #define BIT10 0x00000400 228 #define BIT9 0x00000200 229 #define BIT8 0x00000100 230 #define BIT7 0x00000080 231 #define BIT6 0x00000040 232 #define BIT5 0x00000020 233 #define BIT4 0x00000010 234 #define BIT3 0x00000008 235 #define BIT2 0x00000004 236 #define BIT1 0x00000002 237 #define BIT0 0x00000001 238 239 /*;---UnitCtrlFlag */ 240 #define UNIT_ALLOCATED BIT0 241 #define UNIT_INFO_CHANGED BIT1 242 #define FORMATING_MEDIA BIT2 243 #define UNIT_RETRY BIT3 244 245 /*;---UnitFlags */ 246 #define DASD_SUPPORT BIT0 247 #define SCSI_SUPPORT BIT1 248 #define ASPI_SUPPORT BIT2 249 250 /*;----SRBState machine definition */ 251 #define SRB_FREE 0 252 #define SRB_WAIT BIT0 253 #define SRB_READY BIT1 254 #define SRB_MSGOUT BIT2 /*;arbitration+msg_out 1st byte*/ 255 #define SRB_MSGIN BIT3 256 #define SRB_MSGIN_MULTI BIT4 257 #define SRB_COMMAND BIT5 258 #define SRB_START_ BIT6 /*;arbitration+msg_out+command_out*/ 259 #define SRB_DISCONNECT BIT7 260 #define SRB_DATA_XFER BIT8 261 #define SRB_XFERPAD BIT9 262 #define SRB_STATUS BIT10 263 #define SRB_COMPLETED BIT11 264 #define SRB_ABORT_SENT BIT12 265 #define DO_SYNC_NEGO BIT13 266 #define SRB_UNEXPECT_RESEL BIT14 267 268 /*;---ACBFlag */ 269 #define RESET_DEV BIT0 270 #define RESET_DETECT BIT1 271 #define RESET_DONE BIT2 272 273 /*;---DCBFlag */ 274 #define ABORT_DEV_ BIT0 275 276 /*;---SRBstatus */ 277 #define SRB_OK BIT0 278 #define ABORTION BIT1 279 #define OVER_RUN BIT2 280 #define UNDER_RUN BIT3 281 #define PARITY_ERROR BIT4 282 #define SRB_ERROR BIT5 283 284 /*;---SRBFlag */ 285 #define DATAOUT BIT7 286 #define DATAIN BIT6 287 #define RESIDUAL_VALID BIT5 288 #define ENABLE_TIMER BIT4 289 #define RESET_DEV0 BIT2 290 #define ABORT_DEV BIT1 291 #define AUTO_REQSENSE BIT0 292 293 /*;---Adapter status */ 294 #define H_STATUS_GOOD 0 295 #define H_SEL_TIMEOUT 0x11 296 #define H_OVER_UNDER_RUN 0x12 297 #define H_UNEXP_BUS_FREE 0x13 298 #define H_TARGET_PHASE_F 0x14 299 #define H_INVALID_CCB_OP 0x16 300 #define H_LINK_CCB_BAD 0x17 301 #define H_BAD_TARGET_DIR 0x18 302 #define H_DUPLICATE_CCB 0x19 303 #define H_BAD_CCB_OR_SG 0x1A 304 #define H_ABORT 0x0FF 305 306 /*; SCSI Status byte codes*/ 307 #define SCSI_STAT_GOOD 0x0 /*; Good status */ 308 #define SCSI_STAT_CHECKCOND 0x02 /*; SCSI Check Condition */ 309 #define SCSI_STAT_CONDMET 0x04 /*; Condition Met */ 310 #define SCSI_STAT_BUSY 0x08 /*; Target busy status */ 311 #define SCSI_STAT_INTER 0x10 /*; Intermediate status */ 312 #define SCSI_STAT_INTERCONDMET 0x14 /*; Intermediate condition met */ 313 #define SCSI_STAT_RESCONFLICT 0x18 /*; Reservation conflict */ 314 #define SCSI_STAT_CMDTERM 0x22 /*; Command Terminated */ 315 #define SCSI_STAT_QUEUEFULL 0x28 /*; Queue Full */ 316 317 #define SCSI_STAT_UNEXP_BUS_F 0xFD /*; Unexpect Bus Free */ 318 #define SCSI_STAT_BUS_RST_DETECT 0xFE /*; Scsi Bus Reset detected */ 319 #define SCSI_STAT_SEL_TIMEOUT 0xFF /*; Selection Time out */ 320 321 /*;---Sync_Mode */ 322 #define SYNC_DISABLE 0 323 #define SYNC_ENABLE BIT0 324 #define SYNC_NEGO_DONE BIT1 325 #define WIDE_ENABLE BIT2 326 #define WIDE_NEGO_DONE BIT3 327 #define EN_TAG_QUEUING BIT4 328 #define EN_ATN_STOP BIT5 329 330 #define SYNC_NEGO_OFFSET 15 331 332 /*;---SCSI bus phase*/ 333 #define SCSI_DATA_OUT_ 0 334 #define SCSI_DATA_IN_ 1 335 #define SCSI_COMMAND 2 336 #define SCSI_STATUS_ 3 337 #define SCSI_NOP0 4 338 #define SCSI_NOP1 5 339 #define SCSI_MSG_OUT 6 340 #define SCSI_MSG_IN 7 341 342 /*;----SCSI MSG BYTE*/ 343 #define MSG_COMPLETE 0x00 344 #define MSG_EXTENDED 0x01 345 #define MSG_SAVE_PTR 0x02 346 #define MSG_RESTORE_PTR 0x03 347 #define MSG_DISCONNECT 0x04 348 #define MSG_INITIATOR_ERROR 0x05 349 #define MSG_ABORT 0x06 350 #define MSG_REJECT_ 0x07 351 #define MSG_NOP 0x08 352 #define MSG_PARITY_ERROR 0x09 353 #define MSG_LINK_CMD_COMPL 0x0A 354 #define MSG_LINK_CMD_COMPL_FLG 0x0B 355 #define MSG_BUS_RESET 0x0C 356 #define MSG_ABORT_TAG 0x0D 357 #define MSG_SIMPLE_QTAG 0x20 358 #define MSG_HEAD_QTAG 0x21 359 #define MSG_ORDER_QTAG 0x22 360 #define MSG_IDENTIFY 0x80 361 #define MSG_HOST_ID 0x0C0 362 363 /*;----SCSI STATUS BYTE*/ 364 #define STATUS_GOOD 0x00 365 #define CHECK_CONDITION_ 0x02 366 #define STATUS_BUSY 0x08 367 #define STATUS_INTERMEDIATE 0x10 368 #define RESERVE_CONFLICT 0x18 369 370 /* cmd->result */ 371 #define STATUS_MASK_ 0xFF 372 #define MSG_MASK 0xFF00 373 #define RETURN_MASK 0xFF0000 374 375 /* 376 ** Inquiry Data format 377 */ 378 379 typedef struct _SCSIInqData { /* INQ */ 380 381 UCHAR DevType; /* Periph Qualifier & Periph Dev Type*/ 382 UCHAR RMB_TypeMod; /* rem media bit & Dev Type Modifier */ 383 UCHAR Vers; /* ISO, ECMA, & ANSI versions */ 384 UCHAR RDF; /* AEN, TRMIOP, & response data format*/ 385 UCHAR AddLen; /* length of additional data */ 386 UCHAR Res1; /* reserved */ 387 UCHAR Res2; /* reserved */ 388 UCHAR Flags; /* RelADr,Wbus32,Wbus16,Sync,etc. */ 389 UCHAR VendorID[8]; /* Vendor Identification */ 390 UCHAR ProductID[16]; /* Product Identification */ 391 UCHAR ProductRev[4]; /* Product Revision */ 392 393 394 } SCSI_INQDATA, *PSCSI_INQDATA; 395 396 397 /* Inquiry byte 0 masks */ 398 399 400 #define SCSI_DEVTYPE 0x1F /* Peripheral Device Type */ 401 #define SCSI_PERIPHQUAL 0xE0 /* Peripheral Qualifier */ 402 403 404 /* Inquiry byte 1 mask */ 405 406 #define SCSI_REMOVABLE_MEDIA 0x80 /* Removable Media bit (1=removable) */ 407 408 409 /* Peripheral Device Type definitions */ 410 411 #define SCSI_DASD 0x00 /* Direct-access Device */ 412 #define SCSI_SEQACESS 0x01 /* Sequential-access device */ 413 #define SCSI_PRINTER 0x02 /* Printer device */ 414 #define SCSI_PROCESSOR 0x03 /* Processor device */ 415 #define SCSI_WRITEONCE 0x04 /* Write-once device */ 416 #define SCSI_CDROM 0x05 /* CD-ROM device */ 417 #define SCSI_SCANNER 0x06 /* Scanner device */ 418 #define SCSI_OPTICAL 0x07 /* Optical memory device */ 419 #define SCSI_MEDCHGR 0x08 /* Medium changer device */ 420 #define SCSI_COMM 0x09 /* Communications device */ 421 #define SCSI_NODEV 0x1F /* Unknown or no device type */ 422 423 /* 424 ** Inquiry flag definitions (Inq data byte 7) 425 */ 426 427 #define SCSI_INQ_RELADR 0x80 /* device supports relative addressing*/ 428 #define SCSI_INQ_WBUS32 0x40 /* device supports 32 bit data xfers */ 429 #define SCSI_INQ_WBUS16 0x20 /* device supports 16 bit data xfers */ 430 #define SCSI_INQ_SYNC 0x10 /* device supports synchronous xfer */ 431 #define SCSI_INQ_LINKED 0x08 /* device supports linked commands */ 432 #define SCSI_INQ_CMDQUEUE 0x02 /* device supports command queueing */ 433 #define SCSI_INQ_SFTRE 0x01 /* device supports soft resets */ 434 435 436 /* 437 ;========================================================== 438 ; EEPROM byte offset 439 ;========================================================== 440 */ 441 typedef struct _EEprom 442 { 443 UCHAR EE_MODE1; 444 UCHAR EE_SPEED; 445 UCHAR xx1; 446 UCHAR xx2; 447 } EEprom, *PEEprom; 448 449 #define EE_ADAPT_SCSI_ID 64 450 #define EE_MODE2 65 451 #define EE_DELAY 66 452 #define EE_TAG_CMD_NUM 67 453 454 /*; EE_MODE1 bits definition*/ 455 #define PARITY_CHK_ BIT0 456 #define SYNC_NEGO_ BIT1 457 #define EN_DISCONNECT_ BIT2 458 #define SEND_START_ BIT3 459 #define TAG_QUEUING_ BIT4 460 461 /*; EE_MODE2 bits definition*/ 462 #define MORE2_DRV BIT0 463 #define GREATER_1G BIT1 464 #define RST_SCSI_BUS BIT2 465 #define ACTIVE_NEGATION BIT3 466 #define NO_SEEK BIT4 467 #define LUN_CHECK BIT5 468 469 #define ENABLE_CE 1 470 #define DISABLE_CE 0 471 #define EEPROM_READ 0x80 472 473 /* 474 ;========================================================== 475 ; AMD 53C974 Registers bit Definition 476 ;========================================================== 477 */ 478 /* 479 ;==================== 480 ; SCSI Register 481 ;==================== 482 */ 483 484 /*; Command Reg.(+0CH) */ 485 #define DMA_COMMAND BIT7 486 #define NOP_CMD 0 487 #define CLEAR_FIFO_CMD 1 488 #define RST_DEVICE_CMD 2 489 #define RST_SCSI_BUS_CMD 3 490 #define INFO_XFER_CMD 0x10 491 #define INITIATOR_CMD_CMPLTE 0x11 492 #define MSG_ACCEPTED_CMD 0x12 493 #define XFER_PAD_BYTE 0x18 494 #define SET_ATN_CMD 0x1A 495 #define RESET_ATN_CMD 0x1B 496 #define SELECT_W_ATN 0x42 497 #define SEL_W_ATN_STOP 0x43 498 #define EN_SEL_RESEL 0x44 499 #define SEL_W_ATN2 0x46 500 #define DATA_XFER_CMD INFO_XFER_CMD 501 502 503 /*; SCSI Status Reg.(+10H) */ 504 #define INTERRUPT BIT7 505 #define ILLEGAL_OP_ERR BIT6 506 #define PARITY_ERR BIT5 507 #define COUNT_2_ZERO BIT4 508 #define GROUP_CODE_VALID BIT3 509 #define SCSI_PHASE_MASK (BIT2+BIT1+BIT0) 510 511 /*; Interrupt Status Reg.(+14H) */ 512 #define SCSI_RESET_ BIT7 513 #define INVALID_CMD BIT6 514 #define DISCONNECTED BIT5 515 #define SERVICE_REQUEST BIT4 516 #define SUCCESSFUL_OP BIT3 517 #define RESELECTED BIT2 518 #define SEL_ATTENTION BIT1 519 #define SELECTED BIT0 520 521 /*; Internal State Reg.(+18H) */ 522 #define SYNC_OFFSET_FLAG BIT3 523 #define INTRN_STATE_MASK (BIT2+BIT1+BIT0) 524 525 /*; Clock Factor Reg.(+24H) */ 526 #define CLK_FREQ_40MHZ 0 527 #define CLK_FREQ_35MHZ (BIT2+BIT1+BIT0) 528 #define CLK_FREQ_30MHZ (BIT2+BIT1) 529 #define CLK_FREQ_25MHZ (BIT2+BIT0) 530 #define CLK_FREQ_20MHZ BIT2 531 #define CLK_FREQ_15MHZ (BIT1+BIT0) 532 #define CLK_FREQ_10MHZ BIT1 533 534 /*; Control Reg. 1(+20H) */ 535 #define EXTENDED_TIMING BIT7 536 #define DIS_INT_ON_SCSI_RST BIT6 537 #define PARITY_ERR_REPO BIT4 538 #define SCSI_ID_ON_BUS (BIT2+BIT1+BIT0) 539 540 /*; Control Reg. 2(+2CH) */ 541 #define EN_FEATURE BIT6 542 #define EN_SCSI2_CMD BIT3 543 544 /*; Control Reg. 3(+30H) */ 545 #define ID_MSG_CHECK BIT7 546 #define EN_QTAG_MSG BIT6 547 #define EN_GRP2_CMD BIT5 548 #define FAST_SCSI BIT4 /* ;10MB/SEC */ 549 #define FAST_CLK BIT3 /* ;25 - 40 MHZ */ 550 551 /*; Control Reg. 4(+34H) */ 552 #define EATER_12NS 0 553 #define EATER_25NS BIT7 554 #define EATER_35NS BIT6 555 #define EATER_0NS (BIT7+BIT6) 556 #define NEGATE_REQACKDATA BIT2 557 #define NEGATE_REQACK BIT3 558 /* 559 ;==================== 560 ; DMA Register 561 ;==================== 562 */ 563 /*; DMA Command Reg.(+40H) */ 564 #define READ_DIRECTION BIT7 565 #define WRITE_DIRECTION 0 566 #define EN_DMA_INT BIT6 567 #define MAP_TO_MDL BIT5 568 #define DMA_DIAGNOSTIC BIT4 569 #define DMA_IDLE_CMD 0 570 #define DMA_BLAST_CMD BIT0 571 #define DMA_ABORT_CMD BIT1 572 #define DMA_START_CMD (BIT1+BIT0) 573 574 /*; DMA Status Reg.(+54H) */ 575 #define PCI_MS_ABORT BIT6 576 #define BLAST_COMPLETE BIT5 577 #define SCSI_INTERRUPT BIT4 578 #define DMA_XFER_DONE BIT3 579 #define DMA_XFER_ABORT BIT2 580 #define DMA_XFER_ERROR BIT1 581 #define POWER_DOWN BIT0 582 583 /* 584 ; DMA SCSI Bus and Ctrl.(+70H) 585 ;EN_INT_ON_PCI_ABORT 586 */ 587 588 /* 589 ;========================================================== 590 ; SCSI Chip register address offset 591 ;========================================================== 592 */ 593 #define CtcReg_Low 0x00 594 #define CtcReg_Mid 0x04 595 #define ScsiFifo 0x08 596 #define ScsiCmd 0x0C 597 #define Scsi_Status 0x10 598 #define INT_Status 0x14 599 #define Sync_Period 0x18 600 #define Sync_Offset 0x1C 601 #define CtrlReg1 0x20 602 #define Clk_Factor 0x24 603 #define CtrlReg2 0x2C 604 #define CtrlReg3 0x30 605 #define CtrlReg4 0x34 606 #define CtcReg_High 0x38 607 #define DMA_Cmd 0x40 608 #define DMA_XferCnt 0x44 609 #define DMA_XferAddr 0x48 610 #define DMA_Wk_ByteCntr 0x4C 611 #define DMA_Wk_AddrCntr 0x50 612 #define DMA_Status 0x54 613 #define DMA_MDL_Addr 0x58 614 #define DMA_Wk_MDL_Cntr 0x5C 615 #define DMA_ScsiBusCtrl 0x70 616 617 #define StcReg_Low CtcReg_Low 618 #define StcReg_Mid CtcReg_Mid 619 #define Scsi_Dest_ID Scsi_Status 620 #define Scsi_TimeOut INT_Status 621 #define Intern_State Sync_Period 622 #define Current_Fifo Sync_Offset 623 #define StcReg_High CtcReg_High 624 625 #define am_target Scsi_Status 626 #define am_timeout INT_Status 627 #define am_seq_step Sync_Period 628 #define am_fifo_count Sync_Offset 629 630 631 #define DC390_read8(address) \ 632 inb(DC390_ioport + (address))) 633 634 #define DC390_read16(address) \ 635 inw(DC390_ioport + (address))) 636 637 #define DC390_read32(address) \ 638 inl(DC390_ioport + (address))) 639 640 #define DC390_write8(address,value) \ 641 outb((value), DC390_ioport + (address))) 642 643 #define DC390_write16(address,value) \ 644 outw((value), DC390_ioport + (address))) 645 646 #define DC390_write32(address,value) \ 647 outl((value), DC390_ioport + (address))) 648 649 650 /* Configuration method #1 */ 651 #define PCI_CFG1_ADDRESS_REG 0xcf8 652 #define PCI_CFG1_DATA_REG 0xcfc 653 #define PCI_CFG1_ENABLE 0x80000000 654 #define PCI_CFG1_TUPPLE(bus, device, function, register) \ 655 (PCI_CFG1_ENABLE | (((bus) << 16) & 0xff0000) | \ 656 (((device) << 11) & 0xf800) | (((function) << 8) & 0x700)| \ 657 (((register) << 2) & 0xfc)) 658 659 /* Configuration method #2 */ 660 #define PCI_CFG2_ENABLE_REG 0xcf8 661 #define PCI_CFG2_FORWARD_REG 0xcfa 662 #define PCI_CFG2_ENABLE 0x0f0 663 #define PCI_CFG2_TUPPLE(function) \ 664 (PCI_CFG2_ENABLE | (((function) << 1) & 0xe)) 665 666 667 #endif /* TEK390_H */
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