The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/pci/wd82371reg.h

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    1 /*
    2  * Copyright 1996 Massachusetts Institute of Technology
    3  *
    4  * Permission to use, copy, modify, and distribute this software and
    5  * its documentation for any purpose and without fee is hereby
    6  * granted, provided that both the above copyright notice and this
    7  * permission notice appear in all copies, that both the above
    8  * copyright notice and this permission notice appear in all
    9  * supporting documentation, and that the name of M.I.T. not be used
   10  * in advertising or publicity pertaining to distribution of the
   11  * software without specific, written prior permission.  M.I.T. makes
   12  * no representations about the suitability of this software for any
   13  * purpose.  It is provided "as is" without express or implied
   14  * warranty.
   15  * 
   16  * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''.  M.I.T. DISCLAIMS
   17  * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
   18  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
   19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
   20  * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
   21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
   22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
   23  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
   24  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
   25  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
   26  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  * $FreeBSD: src/sys/pci/wd82371reg.h,v 1.1.4.1 1999/09/05 08:21:28 peter Exp $
   30  */
   31 
   32 #ifndef _PCI_WD82371REG_H_
   33 #define _PCI_WD82371REG_H_      1
   34 
   35 /* Contents of IDETM register, as two 16-bit words (high ctlr 1, low ctlr 0) */
   36 #define IDETM_ENABLE            0x8000
   37 #define IDETM_IORDY_SAMP        0x3000 /* 00:5, 01:4, 10:3, 11:2 clocks */
   38 #define IDETM_RECOVERY_TIME     0x0300 /* 00:4, 01:3, 10:2, 11:1 clocks */
   39 #define IDETM_TIMING_ENB_1      0x0080
   40 #define IDETM_PREFETCH_POST_1   0x0040
   41 #define IDETM_ISP_ENB_1         0x0020 /* enabled IORDY sampling */
   42 #define IDETM_FAST_TIMING_1     0x0010
   43 #define IDETM_TIMING_ENB_0      0x0008
   44 #define IDETM_PREFETCH_POST_0   0x0004
   45 #define IDETM_ISP_ENB_0         0x0002
   46 #define IDETM_FAST_TIMING_0     0x0001
   47 
   48 #define IDETM_CTLR_0(x)         (x)
   49 #define IDETM_CTLR_1(x)         ((x) >> 16)
   50 
   51 /* Ports are for controller 0.  Add PIIX_CTLR_1 for controller 1. */
   52 #define PIIX_CTLR_1             8
   53 
   54 /* Contents of BMICOM register */
   55 #define BMICOM_PORT             0
   56 #define BMICOM_READ_WRITE       0x0008 /* false = read, true = write */
   57 #define BMICOM_STOP_START       0x0001 /* false = stop, true = start */
   58 
   59 /* Contents of BMISTA register */
   60 #define BMISTA_PORT             2
   61 #define BMISTA_DMA1CAP          0x0040 /* true = drive 1 can DMA */
   62 #define BMISTA_DMA0CAP          0x0020 /* true = drive 0 can DMA */
   63 #define BMISTA_INTERRUPT        0x0004
   64 #define BMISTA_DMA_ERROR        0x0002
   65 #define BMISTA_DMA_ACTIVE       0x0001
   66 
   67 #define BMIDTP_PORT             4      /* use outl */
   68 
   69 struct piix_prd {
   70         u_int32_t prd_base;
   71         u_int16_t prd_eot;
   72         u_int16_t prd_count;
   73 };
   74 
   75 #define PRD_EOT_BIT             0x8000
   76 
   77 #define PRD_ALLOC_SIZE          4096
   78 #define PRD_MAX_SEGS            (PRD_ALLOC_SIZE / 4)
   79 
   80 #endif /* _PCI_WD82371REG_H_ */

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