Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/xrpu.c
Version:
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1 /* 2 * ---------------------------------------------------------------------------- 3 * "THE BEER-WARE LICENSE" (Revision 42): 4 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you 5 * can do whatever you want with this stuff. If we meet some day, and you think 6 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp 7 * ---------------------------------------------------------------------------- 8 * 9 * $FreeBSD$ 10 * 11 * A very simple device driver for PCI cards based on Xilinx 6200 series 12 * FPGA/RPU devices. Current Functionality is to allow you to open and 13 * mmap the entire thing into your program. 14 * 15 * Hardware currently supported: 16 * www.vcc.com HotWorks 1 6216 based card. 17 * 18 */ 19 20 #include <sys/param.h> 21 #include <sys/systm.h> 22 #include <sys/conf.h> 23 #include <sys/kernel.h> 24 #include <sys/malloc.h> 25 #include <sys/timepps.h> 26 #include <sys/xrpuio.h> 27 #include <sys/bus.h> 28 #include <machine/bus.h> 29 #include <sys/rman.h> 30 #include <machine/resource.h> 31 #include <pci/pcireg.h> 32 #include <pci/pcivar.h> 33 #include "pci_if.h" 34 35 /* 36 * Device driver initialization stuff 37 */ 38 39 static d_open_t xrpu_open; 40 static d_close_t xrpu_close; 41 static d_ioctl_t xrpu_ioctl; 42 static d_mmap_t xrpu_mmap; 43 44 #define CDEV_MAJOR 100 45 static struct cdevsw xrpu_cdevsw = { 46 /* open */ xrpu_open, 47 /* close */ xrpu_close, 48 /* read */ noread, 49 /* write */ nowrite, 50 /* ioctl */ xrpu_ioctl, 51 /* poll */ nopoll, 52 /* mmap */ xrpu_mmap, 53 /* strategy */ nostrategy, 54 /* name */ "xrpu", 55 /* maj */ CDEV_MAJOR, 56 /* dump */ nodump, 57 /* psize */ nopsize, 58 /* flags */ 0, 59 /* bmaj */ -1 60 }; 61 62 static MALLOC_DEFINE(M_XRPU, "xrpu", "XRPU related"); 63 64 static devclass_t xrpu_devclass; 65 66 #define dev2unit(devt) (minor(devt) & 0xff) 67 #define dev2pps(devt) ((minor(devt) >> 16)-1) 68 69 struct softc { 70 enum { NORMAL, TIMECOUNTER } mode; 71 vm_offset_t virbase, physbase; 72 u_int *virbase62; 73 struct timecounter tc; 74 u_int *trigger, *latch, dummy; 75 struct pps_state pps[XRPU_MAX_PPS]; 76 u_int *assert[XRPU_MAX_PPS], *clear[XRPU_MAX_PPS]; 77 }; 78 79 static unsigned 80 xrpu_get_timecount(struct timecounter *tc) 81 { 82 struct softc *sc = tc->tc_priv; 83 84 sc->dummy += *sc->trigger; 85 return (*sc->latch & tc->tc_counter_mask); 86 } 87 88 static void 89 xrpu_poll_pps(struct timecounter *tc) 90 { 91 struct softc *sc = tc->tc_priv; 92 int i, j; 93 unsigned count1, ppscount; 94 95 for (i = 0; i < XRPU_MAX_PPS; i++) { 96 if (sc->assert[i]) { 97 ppscount = *(sc->assert[i]) & tc->tc_counter_mask; 98 j = 0; 99 do { 100 count1 = ppscount; 101 ppscount = *(sc->assert[i]) & tc->tc_counter_mask; 102 } while (ppscount != count1 && ++j < 5); 103 pps_event(&sc->pps[i], tc, ppscount, PPS_CAPTUREASSERT); 104 } 105 if (sc->clear[i]) { 106 j = 0; 107 ppscount = *(sc->clear[i]) & tc->tc_counter_mask; 108 do { 109 count1 = ppscount; 110 ppscount = *(sc->clear[i]) & tc->tc_counter_mask; 111 } while (ppscount != count1 && ++j < 5); 112 pps_event(&sc->pps[i], tc, ppscount, PPS_CAPTURECLEAR); 113 } 114 } 115 } 116 117 static int 118 xrpu_open(dev_t dev, int flag, int mode, struct proc *p) 119 { 120 struct softc *sc = devclass_get_softc(xrpu_devclass, dev2unit(dev)); 121 122 if (!sc) 123 return (ENXIO); 124 dev->si_drv1 = sc; 125 return (0); 126 } 127 128 static int 129 xrpu_close(dev_t dev, int flag, int mode, struct proc *p) 130 { 131 return (0); 132 } 133 134 static int 135 xrpu_mmap(dev_t dev, vm_offset_t offset, int nprot) 136 { 137 struct softc *sc = dev->si_drv1; 138 if (offset >= 0x1000000) 139 return (-1); 140 return (i386_btop(sc->physbase + offset)); 141 } 142 143 static int 144 xrpu_ioctl(dev_t dev, u_long cmd, caddr_t arg, int flag, struct proc *pr) 145 { 146 struct softc *sc = dev->si_drv1; 147 int i, error; 148 149 if (sc->mode == TIMECOUNTER) { 150 i = dev2pps(dev); 151 if (i < 0 || i >= XRPU_MAX_PPS) 152 return ENODEV; 153 error = pps_ioctl(cmd, arg, &sc->pps[i]); 154 return (error); 155 } 156 157 if (cmd == XRPU_IOC_TIMECOUNTING) { 158 struct xrpu_timecounting *xt = (struct xrpu_timecounting *)arg; 159 160 /* Name SHALL be zero terminated */ 161 xt->xt_name[sizeof xt->xt_name - 1] = '\0'; 162 i = strlen(xt->xt_name); 163 sc->tc.tc_name = (char *)malloc(i + 1, M_XRPU, M_WAITOK); 164 strcpy(sc->tc.tc_name, xt->xt_name); 165 sc->tc.tc_frequency = xt->xt_frequency; 166 sc->tc.tc_get_timecount = xrpu_get_timecount; 167 sc->tc.tc_poll_pps = xrpu_poll_pps; 168 sc->tc.tc_priv = sc; 169 sc->tc.tc_counter_mask = xt->xt_mask; 170 sc->trigger = sc->virbase62 + xt->xt_addr_trigger; 171 sc->latch = sc->virbase62 + xt->xt_addr_latch; 172 173 for (i = 0; i < XRPU_MAX_PPS; i++) { 174 if (xt->xt_pps[i].xt_addr_assert == 0 175 && xt->xt_pps[i].xt_addr_clear == 0) 176 continue; 177 make_dev(&xrpu_cdevsw, (i+1)<<16, 178 UID_ROOT, GID_WHEEL, 0600, "xpps%d", i); 179 sc->pps[i].ppscap = 0; 180 if (xt->xt_pps[i].xt_addr_assert) { 181 sc->assert[i] = sc->virbase62 + xt->xt_pps[i].xt_addr_assert; 182 sc->pps[i].ppscap |= PPS_CAPTUREASSERT; 183 } 184 if (xt->xt_pps[i].xt_addr_clear) { 185 sc->clear[i] = sc->virbase62 + xt->xt_pps[i].xt_addr_clear; 186 sc->pps[i].ppscap |= PPS_CAPTURECLEAR; 187 } 188 pps_init(&sc->pps[i]); 189 } 190 sc->mode = TIMECOUNTER; 191 init_timecounter(&sc->tc); 192 return (0); 193 } 194 error = ENOTTY; 195 return (error); 196 } 197 198 /* 199 * PCI initialization stuff 200 */ 201 202 static int 203 xrpu_probe(device_t self) 204 { 205 char *desc; 206 207 desc = NULL; 208 switch (pci_get_devid(self)) { 209 case 0x6216133e: 210 desc = "VCC Hotworks-I xc6216"; 211 break; 212 } 213 if (desc == NULL) 214 return ENXIO; 215 216 device_set_desc(self, desc); 217 return 0; 218 } 219 220 static int 221 xrpu_attach(device_t self) 222 { 223 struct softc *sc; 224 struct resource *res; 225 int rid, unit; 226 227 unit = device_get_unit(self); 228 sc = device_get_softc(self); 229 sc->mode = NORMAL; 230 rid = PCIR_MAPS; 231 res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid, 232 0, ~0, 1, RF_ACTIVE); 233 if (res == NULL) { 234 device_printf(self, "Could not map memory\n"); 235 return ENXIO; 236 } 237 sc->virbase = (vm_offset_t)rman_get_virtual(res); 238 sc->physbase = rman_get_start(res); 239 sc->virbase62 = (u_int *)(sc->virbase + 0x800000); 240 241 if (bootverbose) 242 printf("Mapped physbase %#lx to virbase %#lx\n", 243 (u_long)sc->physbase, (u_long)sc->virbase); 244 245 make_dev(&xrpu_cdevsw, 0, UID_ROOT, GID_WHEEL, 0600, "xrpu%d", unit); 246 return 0; 247 } 248 249 static device_method_t xrpu_methods[] = { 250 /* Device interface */ 251 DEVMETHOD(device_probe, xrpu_probe), 252 DEVMETHOD(device_attach, xrpu_attach), 253 DEVMETHOD(device_suspend, bus_generic_suspend), 254 DEVMETHOD(device_resume, bus_generic_resume), 255 DEVMETHOD(device_shutdown, bus_generic_shutdown), 256 257 {0, 0} 258 }; 259 260 static driver_t xrpu_driver = { 261 "xrpu", 262 xrpu_methods, 263 sizeof(struct softc) 264 }; 265 266 267 DRIVER_MODULE(xrpu, pci, xrpu_driver, xrpu_devclass, 0, 0);
Cache object: b4103ec857532eb4864f5ed57009ce81
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