Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/xrpu.c
Version:
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1 /* 2 * ---------------------------------------------------------------------------- 3 * "THE BEER-WARE LICENSE" (Revision 42): 4 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you 5 * can do whatever you want with this stuff. If we meet some day, and you think 6 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp 7 * ---------------------------------------------------------------------------- 8 * 9 * $FreeBSD: releng/5.1/sys/pci/xrpu.c 113506 2003-04-15 06:37:30Z mdodd $ 10 * 11 * A very simple device driver for PCI cards based on Xilinx 6200 series 12 * FPGA/RPU devices. Current Functionality is to allow you to open and 13 * mmap the entire thing into your program. 14 * 15 * Hardware currently supported: 16 * www.vcc.com HotWorks 1 6216 based card. 17 * 18 */ 19 20 #include <sys/param.h> 21 #include <sys/systm.h> 22 #include <sys/conf.h> 23 #include <sys/kernel.h> 24 #include <sys/malloc.h> 25 #include <sys/timetc.h> 26 #include <sys/timepps.h> 27 #include <sys/xrpuio.h> 28 #include <sys/bus.h> 29 #include <machine/bus.h> 30 #include <sys/rman.h> 31 #include <machine/resource.h> 32 #include <pci/pcireg.h> 33 #include <pci/pcivar.h> 34 #include "pci_if.h" 35 36 /* 37 * Device driver initialization stuff 38 */ 39 40 static d_open_t xrpu_open; 41 static d_close_t xrpu_close; 42 static d_ioctl_t xrpu_ioctl; 43 static d_mmap_t xrpu_mmap; 44 45 #define CDEV_MAJOR 100 46 static struct cdevsw xrpu_cdevsw = { 47 .d_open = xrpu_open, 48 .d_close = xrpu_close, 49 .d_ioctl = xrpu_ioctl, 50 .d_mmap = xrpu_mmap, 51 .d_name = "xrpu", 52 .d_maj = CDEV_MAJOR, 53 }; 54 55 static MALLOC_DEFINE(M_XRPU, "xrpu", "XRPU related"); 56 57 static devclass_t xrpu_devclass; 58 59 #define dev2unit(devt) (minor(devt) & 0xff) 60 #define dev2pps(devt) ((minor(devt) >> 16)-1) 61 62 struct softc { 63 enum { NORMAL, TIMECOUNTER } mode; 64 vm_offset_t virbase, physbase; 65 u_int *virbase62; 66 struct timecounter tc; 67 u_int *trigger, *latch, dummy; 68 struct pps_state pps[XRPU_MAX_PPS]; 69 u_int *assert[XRPU_MAX_PPS], *clear[XRPU_MAX_PPS]; 70 }; 71 72 static unsigned 73 xrpu_get_timecount(struct timecounter *tc) 74 { 75 struct softc *sc = tc->tc_priv; 76 77 sc->dummy += *sc->trigger; 78 return (*sc->latch & tc->tc_counter_mask); 79 } 80 81 static void 82 xrpu_poll_pps(struct timecounter *tc) 83 { 84 struct softc *sc = tc->tc_priv; 85 int i, j; 86 unsigned count1, ppscount; 87 88 for (i = 0; i < XRPU_MAX_PPS; i++) { 89 if (sc->assert[i]) { 90 pps_capture(&sc->pps[i]); 91 ppscount = *(sc->assert[i]) & tc->tc_counter_mask; 92 j = 0; 93 do { 94 count1 = ppscount; 95 ppscount = *(sc->assert[i]) & tc->tc_counter_mask; 96 } while (ppscount != count1 && ++j < 5); 97 sc->pps[i].capcount = ppscount; 98 pps_event(&sc->pps[i], PPS_CAPTUREASSERT); 99 } 100 if (sc->clear[i]) { 101 pps_capture(&sc->pps[i]); 102 j = 0; 103 ppscount = *(sc->clear[i]) & tc->tc_counter_mask; 104 do { 105 count1 = ppscount; 106 ppscount = *(sc->clear[i]) & tc->tc_counter_mask; 107 } while (ppscount != count1 && ++j < 5); 108 sc->pps[i].capcount = ppscount; 109 pps_event(&sc->pps[i], PPS_CAPTURECLEAR); 110 } 111 } 112 } 113 114 static int 115 xrpu_open(dev_t dev, int flag, int mode, struct thread *td) 116 { 117 struct softc *sc = devclass_get_softc(xrpu_devclass, dev2unit(dev)); 118 119 if (!sc) 120 return (ENXIO); 121 dev->si_drv1 = sc; 122 return (0); 123 } 124 125 static int 126 xrpu_close(dev_t dev, int flag, int mode, struct thread *td) 127 { 128 return (0); 129 } 130 131 static int 132 xrpu_mmap(dev_t dev, vm_offset_t offset, vm_paddr_t *paddr, int nprot) 133 { 134 struct softc *sc = dev->si_drv1; 135 if (offset >= 0x1000000) 136 return (-1); 137 *paddr = sc->physbase + offset; 138 return (0); 139 } 140 141 static int 142 xrpu_ioctl(dev_t dev, u_long cmd, caddr_t arg, int flag, struct thread *tdr) 143 { 144 struct softc *sc = dev->si_drv1; 145 int i, error; 146 147 if (sc->mode == TIMECOUNTER) { 148 i = dev2pps(dev); 149 if (i < 0 || i >= XRPU_MAX_PPS) 150 return ENODEV; 151 error = pps_ioctl(cmd, arg, &sc->pps[i]); 152 return (error); 153 } 154 155 if (cmd == XRPU_IOC_TIMECOUNTING) { 156 struct xrpu_timecounting *xt = (struct xrpu_timecounting *)arg; 157 158 /* Name SHALL be zero terminated */ 159 xt->xt_name[sizeof xt->xt_name - 1] = '\0'; 160 i = strlen(xt->xt_name); 161 sc->tc.tc_name = (char *)malloc(i + 1, M_XRPU, M_WAITOK); 162 strcpy(sc->tc.tc_name, xt->xt_name); 163 sc->tc.tc_frequency = xt->xt_frequency; 164 sc->tc.tc_get_timecount = xrpu_get_timecount; 165 sc->tc.tc_poll_pps = xrpu_poll_pps; 166 sc->tc.tc_priv = sc; 167 sc->tc.tc_counter_mask = xt->xt_mask; 168 sc->trigger = sc->virbase62 + xt->xt_addr_trigger; 169 sc->latch = sc->virbase62 + xt->xt_addr_latch; 170 171 for (i = 0; i < XRPU_MAX_PPS; i++) { 172 if (xt->xt_pps[i].xt_addr_assert == 0 173 && xt->xt_pps[i].xt_addr_clear == 0) 174 continue; 175 make_dev(&xrpu_cdevsw, (i+1)<<16, 176 UID_ROOT, GID_WHEEL, 0600, "xpps%d", i); 177 sc->pps[i].ppscap = 0; 178 if (xt->xt_pps[i].xt_addr_assert) { 179 sc->assert[i] = sc->virbase62 + xt->xt_pps[i].xt_addr_assert; 180 sc->pps[i].ppscap |= PPS_CAPTUREASSERT; 181 } 182 if (xt->xt_pps[i].xt_addr_clear) { 183 sc->clear[i] = sc->virbase62 + xt->xt_pps[i].xt_addr_clear; 184 sc->pps[i].ppscap |= PPS_CAPTURECLEAR; 185 } 186 pps_init(&sc->pps[i]); 187 } 188 sc->mode = TIMECOUNTER; 189 tc_init(&sc->tc); 190 return (0); 191 } 192 error = ENOTTY; 193 return (error); 194 } 195 196 /* 197 * PCI initialization stuff 198 */ 199 200 static int 201 xrpu_probe(device_t self) 202 { 203 char *desc; 204 205 desc = NULL; 206 switch (pci_get_devid(self)) { 207 case 0x6216133e: 208 desc = "VCC Hotworks-I xc6216"; 209 break; 210 } 211 if (desc == NULL) 212 return ENXIO; 213 214 device_set_desc(self, desc); 215 return 0; 216 } 217 218 static int 219 xrpu_attach(device_t self) 220 { 221 struct softc *sc; 222 struct resource *res; 223 int rid, unit; 224 225 unit = device_get_unit(self); 226 sc = device_get_softc(self); 227 sc->mode = NORMAL; 228 rid = PCIR_MAPS; 229 res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid, 230 0, ~0, 1, RF_ACTIVE); 231 if (res == NULL) { 232 device_printf(self, "Could not map memory\n"); 233 return ENXIO; 234 } 235 sc->virbase = (vm_offset_t)rman_get_virtual(res); 236 sc->physbase = rman_get_start(res); 237 sc->virbase62 = (u_int *)(sc->virbase + 0x800000); 238 239 if (bootverbose) 240 printf("Mapped physbase %#lx to virbase %#lx\n", 241 (u_long)sc->physbase, (u_long)sc->virbase); 242 243 make_dev(&xrpu_cdevsw, 0, UID_ROOT, GID_WHEEL, 0600, "xrpu%d", unit); 244 return 0; 245 } 246 247 static device_method_t xrpu_methods[] = { 248 /* Device interface */ 249 DEVMETHOD(device_probe, xrpu_probe), 250 DEVMETHOD(device_attach, xrpu_attach), 251 DEVMETHOD(device_suspend, bus_generic_suspend), 252 DEVMETHOD(device_resume, bus_generic_resume), 253 DEVMETHOD(device_shutdown, bus_generic_shutdown), 254 255 {0, 0} 256 }; 257 258 static driver_t xrpu_driver = { 259 "xrpu", 260 xrpu_methods, 261 sizeof(struct softc) 262 }; 263 264 265 DRIVER_MODULE(xrpu, pci, xrpu_driver, xrpu_devclass, 0, 0); 266 MODULE_DEPEND(xrpu, pci, 1, 1, 1);
Cache object: 34615306b65d4ed022aabb11004abb1b
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