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sys/powerpc/aim/trap_subr32.S
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1 /* $FreeBSD$ */ 2 /* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */ 3 4 /*- 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * NOTICE: This is not a standalone file. to use it, #include it in 37 * your port's locore.S, like so: 38 * 39 * #include <powerpc/aim/trap_subr.S> 40 */ 41 42 /* 43 * Save/restore segment registers 44 */ 45 #define RESTORE_SRS(pmap,sr) mtsr 0,sr; \ 46 lwz sr,1*4(pmap); mtsr 1,sr; \ 47 lwz sr,2*4(pmap); mtsr 2,sr; \ 48 lwz sr,3*4(pmap); mtsr 3,sr; \ 49 lwz sr,4*4(pmap); mtsr 4,sr; \ 50 lwz sr,5*4(pmap); mtsr 5,sr; \ 51 lwz sr,6*4(pmap); mtsr 6,sr; \ 52 lwz sr,7*4(pmap); mtsr 7,sr; \ 53 lwz sr,8*4(pmap); mtsr 8,sr; \ 54 lwz sr,9*4(pmap); mtsr 9,sr; \ 55 lwz sr,10*4(pmap); mtsr 10,sr; \ 56 lwz sr,11*4(pmap); mtsr 11,sr; \ 57 /* Skip segment 12 (USER_SR), which is restored differently */ \ 58 lwz sr,13*4(pmap); mtsr 13,sr; \ 59 lwz sr,14*4(pmap); mtsr 14,sr; \ 60 lwz sr,15*4(pmap); mtsr 15,sr; isync; 61 62 /* 63 * User SRs are loaded through a pointer to the current pmap. 64 */ 65 #define RESTORE_USER_SRS(pmap,sr) \ 66 GET_CPUINFO(pmap); \ 67 lwz pmap,PC_CURPMAP(pmap); \ 68 lwzu sr,PM_SR(pmap); \ 69 RESTORE_SRS(pmap,sr) \ 70 /* Restore SR 12 */ \ 71 lwz sr,12*4(pmap); mtsr 12,sr; isync 72 73 /* 74 * Kernel SRs are loaded directly from kernel_pmap_ 75 */ 76 #define RESTORE_KERN_SRS(pmap,sr) \ 77 lwz pmap,TRAP_TOCBASE(0); \ 78 lwz pmap,CNAME(kernel_pmap_store)@got(pmap); \ 79 lwzu sr,PM_SR(pmap); \ 80 RESTORE_SRS(pmap,sr) 81 82 /* 83 * FRAME_SETUP assumes: 84 * SPRG1 SP (1) 85 * SPRG3 trap type 86 * savearea r28-r31,DAR,DSISR (DAR & DSISR only for DSI traps) 87 * r28 LR 88 * r29 CR 89 * r30 scratch 90 * r31 scratch 91 * r1 kernel stack 92 * SRR0/1 as at start of trap 93 */ 94 #define FRAME_SETUP(savearea) \ 95 /* Have to enable translation to allow access of kernel stack: */ \ 96 GET_CPUINFO(%r31); \ 97 mfsrr0 %r30; \ 98 stw %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \ 99 mfsrr1 %r30; \ 100 stw %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \ 101 mfmsr %r30; \ 102 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \ 103 mtmsr %r30; /* stack can now be accessed */ \ 104 isync; \ 105 mfsprg1 %r31; /* get saved SP */ \ 106 stwu %r31,-FRAMELEN(%r1); /* save it in the callframe */ \ 107 stw %r0, FRAME_0+8(%r1); /* save r0 in the trapframe */ \ 108 stw %r31,FRAME_1+8(%r1); /* save SP " " */ \ 109 stw %r2, FRAME_2+8(%r1); /* save r2 " " */ \ 110 stw %r28,FRAME_LR+8(%r1); /* save LR " " */ \ 111 stw %r29,FRAME_CR+8(%r1); /* save CR " " */ \ 112 GET_CPUINFO(%r2); \ 113 lwz %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \ 114 lwz %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \ 115 lwz %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \ 116 lwz %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \ 117 stw %r3, FRAME_3+8(%r1); /* save r3-r31 */ \ 118 stw %r4, FRAME_4+8(%r1); \ 119 stw %r5, FRAME_5+8(%r1); \ 120 stw %r6, FRAME_6+8(%r1); \ 121 stw %r7, FRAME_7+8(%r1); \ 122 stw %r8, FRAME_8+8(%r1); \ 123 stw %r9, FRAME_9+8(%r1); \ 124 stw %r10, FRAME_10+8(%r1); \ 125 stw %r11, FRAME_11+8(%r1); \ 126 stw %r12, FRAME_12+8(%r1); \ 127 stw %r13, FRAME_13+8(%r1); \ 128 stw %r14, FRAME_14+8(%r1); \ 129 stw %r15, FRAME_15+8(%r1); \ 130 stw %r16, FRAME_16+8(%r1); \ 131 stw %r17, FRAME_17+8(%r1); \ 132 stw %r18, FRAME_18+8(%r1); \ 133 stw %r19, FRAME_19+8(%r1); \ 134 stw %r20, FRAME_20+8(%r1); \ 135 stw %r21, FRAME_21+8(%r1); \ 136 stw %r22, FRAME_22+8(%r1); \ 137 stw %r23, FRAME_23+8(%r1); \ 138 stw %r24, FRAME_24+8(%r1); \ 139 stw %r25, FRAME_25+8(%r1); \ 140 stw %r26, FRAME_26+8(%r1); \ 141 stw %r27, FRAME_27+8(%r1); \ 142 stw %r28, FRAME_28+8(%r1); \ 143 stw %r29, FRAME_29+8(%r1); \ 144 stw %r30, FRAME_30+8(%r1); \ 145 stw %r31, FRAME_31+8(%r1); \ 146 lwz %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \ 147 lwz %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\ 148 lwz %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \ 149 lwz %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \ 150 mfxer %r3; \ 151 mfctr %r4; \ 152 mfsprg3 %r5; \ 153 stw %r3, FRAME_XER+8(1); /* save xer/ctr/exc */ \ 154 stw %r4, FRAME_CTR+8(1); \ 155 stw %r5, FRAME_EXC+8(1); \ 156 stw %r28,FRAME_AIM_DAR+8(1); \ 157 stw %r29,FRAME_AIM_DSISR+8(1); /* save dsisr/srr0/srr1 */ \ 158 stw %r30,FRAME_SRR0+8(1); \ 159 stw %r31,FRAME_SRR1+8(1); \ 160 lwz %r2,PC_CURTHREAD(%r2) /* set curthread pointer */ 161 162 #define FRAME_LEAVE(savearea) \ 163 /* Disable exceptions: */ \ 164 mfmsr %r2; \ 165 andi. %r2,%r2,~PSL_EE@l; \ 166 mtmsr %r2; \ 167 isync; \ 168 /* Now restore regs: */ \ 169 lwz %r2,FRAME_SRR0+8(%r1); \ 170 lwz %r3,FRAME_SRR1+8(%r1); \ 171 lwz %r4,FRAME_CTR+8(%r1); \ 172 lwz %r5,FRAME_XER+8(%r1); \ 173 lwz %r6,FRAME_LR+8(%r1); \ 174 GET_CPUINFO(%r7); \ 175 stw %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \ 176 stw %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \ 177 lwz %r7,FRAME_CR+8(%r1); \ 178 mtctr %r4; \ 179 mtxer %r5; \ 180 mtlr %r6; \ 181 mtsprg1 %r7; /* save cr */ \ 182 lwz %r31,FRAME_31+8(%r1); /* restore r0-31 */ \ 183 lwz %r30,FRAME_30+8(%r1); \ 184 lwz %r29,FRAME_29+8(%r1); \ 185 lwz %r28,FRAME_28+8(%r1); \ 186 lwz %r27,FRAME_27+8(%r1); \ 187 lwz %r26,FRAME_26+8(%r1); \ 188 lwz %r25,FRAME_25+8(%r1); \ 189 lwz %r24,FRAME_24+8(%r1); \ 190 lwz %r23,FRAME_23+8(%r1); \ 191 lwz %r22,FRAME_22+8(%r1); \ 192 lwz %r21,FRAME_21+8(%r1); \ 193 lwz %r20,FRAME_20+8(%r1); \ 194 lwz %r19,FRAME_19+8(%r1); \ 195 lwz %r18,FRAME_18+8(%r1); \ 196 lwz %r17,FRAME_17+8(%r1); \ 197 lwz %r16,FRAME_16+8(%r1); \ 198 lwz %r15,FRAME_15+8(%r1); \ 199 lwz %r14,FRAME_14+8(%r1); \ 200 lwz %r13,FRAME_13+8(%r1); \ 201 lwz %r12,FRAME_12+8(%r1); \ 202 lwz %r11,FRAME_11+8(%r1); \ 203 lwz %r10,FRAME_10+8(%r1); \ 204 lwz %r9, FRAME_9+8(%r1); \ 205 lwz %r8, FRAME_8+8(%r1); \ 206 lwz %r7, FRAME_7+8(%r1); \ 207 lwz %r6, FRAME_6+8(%r1); \ 208 lwz %r5, FRAME_5+8(%r1); \ 209 lwz %r4, FRAME_4+8(%r1); \ 210 lwz %r3, FRAME_3+8(%r1); \ 211 lwz %r2, FRAME_2+8(%r1); \ 212 lwz %r0, FRAME_0+8(%r1); \ 213 lwz %r1, FRAME_1+8(%r1); \ 214 /* Can't touch %r1 from here on */ \ 215 mtsprg2 %r2; /* save r2 & r3 */ \ 216 mtsprg3 %r3; \ 217 /* Disable translation, machine check and recoverability: */ \ 218 mfmsr %r2; \ 219 andi. %r2,%r2,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \ 220 mtmsr %r2; \ 221 isync; \ 222 /* Decide whether we return to user mode: */ \ 223 GET_CPUINFO(%r2); \ 224 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); \ 225 mtcr %r3; \ 226 bf 17,1f; /* branch if PSL_PR is false */ \ 227 /* Restore user SRs */ \ 228 RESTORE_USER_SRS(%r2,%r3); \ 229 1: mfsprg1 %r2; /* restore cr */ \ 230 mtcr %r2; \ 231 GET_CPUINFO(%r2); \ 232 lwz %r3,(savearea+CPUSAVE_SRR0)(%r2); /* restore srr0 */ \ 233 mtsrr0 %r3; \ 234 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); /* restore srr1 */ \ 235 \ 236 /* Make sure HV bit of MSR propagated to SRR1 */ \ 237 mfmsr %r2; \ 238 or %r3,%r2,%r3; \ 239 \ 240 mtsrr1 %r3; \ 241 mfsprg2 %r2; /* restore r2 & r3 */ \ 242 mfsprg3 %r3 243 244 #ifdef KDTRACE_HOOKS 245 .data 246 .globl dtrace_invop_calltrap_addr 247 .align 4 248 .type dtrace_invop_calltrap_addr, @object 249 .size dtrace_invop_calltrap_addr, 4 250 dtrace_invop_calltrap_addr: 251 .word 0 252 .word 0 253 254 .text 255 #endif 256 257 /* 258 * The next two routines are 64-bit glue code. The first is used to test if 259 * we are on a 64-bit system. By copying it to the illegal instruction 260 * handler, we can test for 64-bit mode by trying to execute a 64-bit 261 * instruction and seeing what happens. The second gets copied in front 262 * of all the other handlers to restore 32-bit bridge mode when traps 263 * are taken. 264 */ 265 266 /* 64-bit test code. Sets SPRG2 to 0 if an illegal instruction is executed */ 267 268 .globl CNAME(testppc64),CNAME(testppc64size) 269 CNAME(testppc64): 270 mtsprg1 %r31 271 mfsrr0 %r31 272 addi %r31, %r31, 4 273 mtsrr0 %r31 274 275 li %r31, 0 276 mtsprg2 %r31 277 mfsprg1 %r31 278 279 rfi 280 CNAME(testppc64size) = .-CNAME(testppc64) 281 282 283 /* 64-bit bridge mode restore snippet. Gets copied in front of everything else 284 * on 64-bit systems. */ 285 286 .globl CNAME(restorebridge),CNAME(restorebridgesize) 287 CNAME(restorebridge): 288 mtsprg1 %r31 289 mfmsr %r31 290 clrldi %r31,%r31,1 291 mtmsrd %r31 292 mfsprg1 %r31 293 isync 294 CNAME(restorebridgesize) = .-CNAME(restorebridge) 295 296 /* 297 * Processor reset exception handler. These are typically 298 * the first instructions the processor executes after a 299 * software reset. We do this in two bits so that we are 300 * not still hanging around in the trap handling region 301 * once the MMU is turned on. 302 */ 303 .globl CNAME(rstcode), CNAME(rstcodeend) 304 CNAME(rstcode): 305 lwz %r31, TRAP_GENTRAP(0) 306 addi %r31, %r31, (cpu_reset - generictrap) 307 mtlr %r31 308 blrl 309 CNAME(rstcodeend): 310 311 cpu_reset: 312 bl 1f 313 314 .space 124 315 316 1: 317 mflr %r1 318 addi %r1,%r1,(124-16)@l 319 lwz %r30,TRAP_TOCBASE(0) 320 321 bl CNAME(cpudep_ap_early_bootstrap) 322 lis %r3,1@l 323 bl CNAME(pmap_cpu_bootstrap) 324 bl CNAME(cpudep_ap_bootstrap) 325 mr %r1,%r3 326 bl CNAME(cpudep_ap_setup) 327 GET_CPUINFO(%r5) 328 lwz %r3,(PC_RESTORE)(%r5) 329 cmplwi %cr0,%r3,0 330 beq %cr0,2f 331 li %r4, 1 332 b CNAME(longjmp) 333 2: 334 #ifdef SMP 335 bl CNAME(machdep_ap_bootstrap) 336 #endif 337 338 /* Should not be reached */ 339 9: 340 b 9b 341 342 /* 343 * This code gets copied to all the trap vectors 344 * (except ISI/DSI, ALI, and the interrupts) 345 */ 346 347 .globl CNAME(trapcode),CNAME(trapcodeend) 348 CNAME(trapcode): 349 mtsprg1 %r1 /* save SP */ 350 mflr %r1 /* Save the old LR in r1 */ 351 mtsprg2 %r1 /* And then in SPRG2 */ 352 lwz %r1, TRAP_ENTRY(0) /* Get branch address */ 353 mtlr %r1 354 li %r1, 0xe0 /* How to get the vector from LR */ 355 blrl /* LR & (0xff00 | r1) is exception # */ 356 CNAME(trapcodeend): 357 358 /* 359 * For ALI: has to save DSISR and DAR 360 */ 361 .globl CNAME(alitrap),CNAME(aliend) 362 CNAME(alitrap): 363 mtsprg1 %r1 /* save SP */ 364 GET_CPUINFO(%r1) 365 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 366 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 367 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 368 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 369 mfdar %r30 370 mfdsisr %r31 371 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 372 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 373 mfsprg1 %r1 /* restore SP, in case of branch */ 374 mflr %r28 /* save LR */ 375 mfcr %r29 /* save CR */ 376 377 /* Put our exception vector in SPRG3 */ 378 li %r31, EXC_ALI 379 mtsprg3 %r31 380 381 /* Test whether we already had PR set */ 382 mfsrr1 %r31 383 mtcr %r31 384 385 /* Jump to s_trap */ 386 lwz %r31, TRAP_GENTRAP(0) 387 addi %r31, %r31, (s_trap - generictrap) 388 mtlr %r31 389 blrl 390 CNAME(aliend): 391 392 /* 393 * G2 specific: instuction TLB miss. 394 */ 395 .globl CNAME(imisstrap),CNAME(imisssize) 396 CNAME(imisstrap): 397 mfspr %r2, SPR_HASH1 /* get first pointer */ 398 addi %r1, 0, 8 /* load 8 for counter */ 399 mfctr %r0 /* save counter */ 400 mfspr %r3, SPR_ICMP /* get first compare value */ 401 addi %r2, %r2, -8 /* pre dec the pointer */ 402 im0: 403 mtctr %r1 /* load counter */ 404 im1: 405 lwzu %r1, 8(%r2) /* get next pte */ 406 cmp 0, 0, %r1, %r3 /* see if found pte */ 407 bdnzf 2, im1 /* dec count br if cmp ne and if 408 * count not zero */ 409 bne instr_sec_hash /* if not found set up second hash 410 * or exit */ 411 lwz %r1, +4(%r2) /* load tlb entry lower-word */ 412 andi. %r3, %r1, 8 /* check G bit */ 413 bne do_isi_prot /* if guarded, take an ISI */ 414 mtctr %r0 /* restore counter */ 415 mfspr %r0, SPR_IMISS /* get the miss address for the tlbli */ 416 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 417 mtcrf 0x80, %r3 /* restore CR0 */ 418 mtspr SPR_RPA, %r1 /* set the pte */ 419 ori %r1, %r1, 0x100 /* set reference bit */ 420 srwi %r1, %r1, 8 /* get byte 7 of pte */ 421 tlbli %r0 /* load the itlb */ 422 stb %r1, +6(%r2) /* update page table */ 423 rfi /* return to executing program */ 424 425 instr_sec_hash: 426 andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 427 bne do_isi /* if so, go to ISI interrupt */ 428 mfspr %r2, SPR_HASH2 /* get the second pointer */ 429 ori %r3, %r3, 0x0040 /* change the compare value */ 430 addi %r1, 0, 8 /* load 8 for counter */ 431 addi %r2, %r2, -8 /* pre dec for update on load */ 432 b im0 /* try second hash */ 433 434 /* Create a faked ISI interrupt as the address was not found */ 435 do_isi_prot: 436 mfspr %r3, SPR_SRR1 /* get srr1 */ 437 andi. %r2, %r3, 0xffff /* clean upper srr1 */ 438 addis %r2, %r2, 0x0800 /* or in srr<4> = 1 to flag prot 439 * violation */ 440 b isi1 441 do_isi: 442 mfspr %r3, SPR_SRR1 /* get srr1 */ 443 andi. %r2, %r3, 0xffff /* clean srr1 */ 444 addis %r2, %r2, 0x4000 /* or in srr1<1> = 1 to flag pte 445 * not found */ 446 isi1: 447 mtctr %r0 /* restore counter */ 448 mtspr SPR_SRR1, %r2 /* set srr1 */ 449 mfmsr %r0 /* get msr */ 450 xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */ 451 mtcrf 0x80, %r3 /* restore CR0 */ 452 mtmsr %r0 /* flip back to the native gprs */ 453 ba EXC_ISI /* go to instr. access interrupt */ 454 455 CNAME(imisssize) = .-CNAME(imisstrap) 456 457 /* 458 * G2 specific: data load TLB miss. 459 */ 460 .globl CNAME(dlmisstrap),CNAME(dlmisssize) 461 CNAME(dlmisstrap): 462 mfspr %r2, SPR_HASH1 /* get first pointer */ 463 addi %r1, 0, 8 /* load 8 for counter */ 464 mfctr %r0 /* save counter */ 465 mfspr %r3, SPR_DCMP /* get first compare value */ 466 addi %r2, %r2, -8 /* pre dec the pointer */ 467 dm0: 468 mtctr %r1 /* load counter */ 469 dm1: 470 lwzu %r1, 8(%r2) /* get next pte */ 471 cmp 0, 0, %r1, %r3 /* see if found pte */ 472 bdnzf 2, dm1 /* dec count br if cmp ne and if 473 * count not zero */ 474 bne data_sec_hash /* if not found set up second hash 475 * or exit */ 476 lwz %r1, +4(%r2) /* load tlb entry lower-word */ 477 mtctr %r0 /* restore counter */ 478 mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */ 479 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 480 mtcrf 0x80, %r3 /* restore CR0 */ 481 mtspr SPR_RPA, %r1 /* set the pte */ 482 ori %r1, %r1, 0x100 /* set reference bit */ 483 srwi %r1, %r1, 8 /* get byte 7 of pte */ 484 tlbld %r0 /* load the dtlb */ 485 stb %r1, +6(%r2) /* update page table */ 486 rfi /* return to executing program */ 487 488 data_sec_hash: 489 andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 490 bne do_dsi /* if so, go to DSI interrupt */ 491 mfspr %r2, SPR_HASH2 /* get the second pointer */ 492 ori %r3, %r3, 0x0040 /* change the compare value */ 493 addi %r1, 0, 8 /* load 8 for counter */ 494 addi %r2, %r2, -8 /* pre dec for update on load */ 495 b dm0 /* try second hash */ 496 497 CNAME(dlmisssize) = .-CNAME(dlmisstrap) 498 499 /* 500 * G2 specific: data store TLB miss. 501 */ 502 .globl CNAME(dsmisstrap),CNAME(dsmisssize) 503 CNAME(dsmisstrap): 504 mfspr %r2, SPR_HASH1 /* get first pointer */ 505 addi %r1, 0, 8 /* load 8 for counter */ 506 mfctr %r0 /* save counter */ 507 mfspr %r3, SPR_DCMP /* get first compare value */ 508 addi %r2, %r2, -8 /* pre dec the pointer */ 509 ds0: 510 mtctr %r1 /* load counter */ 511 ds1: 512 lwzu %r1, 8(%r2) /* get next pte */ 513 cmp 0, 0, %r1, %r3 /* see if found pte */ 514 bdnzf 2, ds1 /* dec count br if cmp ne and if 515 * count not zero */ 516 bne data_store_sec_hash /* if not found set up second hash 517 * or exit */ 518 lwz %r1, +4(%r2) /* load tlb entry lower-word */ 519 andi. %r3, %r1, 0x80 /* check the C-bit */ 520 beq data_store_chk_prot /* if (C==0) 521 * go check protection modes */ 522 ds2: 523 mtctr %r0 /* restore counter */ 524 mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */ 525 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 526 mtcrf 0x80, %r3 /* restore CR0 */ 527 mtspr SPR_RPA, %r1 /* set the pte */ 528 tlbld %r0 /* load the dtlb */ 529 rfi /* return to executing program */ 530 531 data_store_sec_hash: 532 andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 533 bne do_dsi /* if so, go to DSI interrupt */ 534 mfspr %r2, SPR_HASH2 /* get the second pointer */ 535 ori %r3, %r3, 0x0040 /* change the compare value */ 536 addi %r1, 0, 8 /* load 8 for counter */ 537 addi %r2, %r2, -8 /* pre dec for update on load */ 538 b ds0 /* try second hash */ 539 540 /* Check the protection before setting PTE(c-bit) */ 541 data_store_chk_prot: 542 rlwinm. %r3,%r1,30,0,1 /* test PP */ 543 bge- chk0 /* if (PP == 00 or PP == 01) 544 * goto chk0: */ 545 andi. %r3, %r1, 1 /* test PP[0] */ 546 beq+ chk2 /* return if PP[0] == 0 */ 547 b do_dsi_prot /* else DSIp */ 548 chk0: 549 mfspr %r3,SPR_SRR1 /* get old msr */ 550 andis. %r3,%r3,0x0008 /* test the KEY bit (SRR1-bit 12) */ 551 beq chk2 /* if (KEY==0) goto chk2: */ 552 b do_dsi_prot /* else do_dsi_prot */ 553 chk2: 554 ori %r1, %r1, 0x180 /* set reference and change bit */ 555 sth %r1, 6(%r2) /* update page table */ 556 b ds2 /* and back we go */ 557 558 /* Create a faked DSI interrupt as the address was not found */ 559 do_dsi: 560 mfspr %r3, SPR_SRR1 /* get srr1 */ 561 rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for 562 * load/store, zero rest */ 563 addis %r1, %r1, 0x4000 /* or in dsisr<1> = 1 to flag pte 564 * not found */ 565 b dsi1 566 567 do_dsi_prot: 568 mfspr %r3, SPR_SRR1 /* get srr1 */ 569 rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for 570 *load/store, zero rest */ 571 addis %r1, %r1, 0x0800 /* or in dsisr<4> = 1 to flag prot 572 * violation */ 573 574 dsi1: 575 mtctr %r0 /* restore counter */ 576 andi. %r2, %r3, 0xffff /* clear upper bits of srr1 */ 577 mtspr SPR_SRR1, %r2 /* set srr1 */ 578 mtspr SPR_DSISR, %r1 /* load the dsisr */ 579 mfspr %r1, SPR_DMISS /* get miss address */ 580 rlwinm. %r2,%r2,0,31,31 /* test LE bit */ 581 beq dsi2 /* if little endian then: */ 582 xor %r1, %r1, 0x07 /* de-mung the data address */ 583 dsi2: 584 mtspr SPR_DAR, %r1 /* put in dar */ 585 mfmsr %r0 /* get msr */ 586 xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */ 587 mtcrf 0x80, %r3 /* restore CR0 */ 588 mtmsr %r0 /* flip back to the native gprs */ 589 ba EXC_DSI /* branch to DSI interrupt */ 590 591 CNAME(dsmisssize) = .-CNAME(dsmisstrap) 592 593 /* 594 * Similar to the above for DSI 595 * Has to handle BAT spills 596 * and standard pagetable spills 597 */ 598 .globl CNAME(dsitrap),CNAME(dsiend) 599 CNAME(dsitrap): 600 mtsprg1 %r1 /* save SP */ 601 GET_CPUINFO(%r1) 602 stw %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 603 stw %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 604 stw %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 605 stw %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 606 mfsprg1 %r1 /* restore SP */ 607 mfcr %r29 /* save CR */ 608 mfxer %r30 /* save XER */ 609 mtsprg2 %r30 /* in SPRG2 */ 610 mfsrr1 %r31 /* test kernel mode */ 611 mtcr %r31 612 bt 17,1f /* branch if PSL_PR is set */ 613 mfdar %r31 /* get fault address */ 614 rlwinm %r31,%r31,7,25,28 /* get segment * 8 */ 615 616 /* get batu */ 617 lwz %r30,TRAP_TOCBASE(0) 618 lwz %r30,CNAME(battable)@got(%r30) 619 add %r31,%r30,%r31 620 lwz %r30,0(%r31) 621 mtcr %r30 622 bf 30,1f /* branch if supervisor valid is 623 false */ 624 /* get batl */ 625 lwz %r31,4(%r31) 626 /* We randomly use the highest two bat registers here */ 627 mftb %r28 628 andi. %r28,%r28,1 629 bne 2f 630 mtdbatu 2,%r30 631 mtdbatl 2,%r31 632 b 3f 633 2: 634 mtdbatu 3,%r30 635 mtdbatl 3,%r31 636 3: 637 mfsprg2 %r30 /* restore XER */ 638 mtxer %r30 639 mtcr %r29 /* restore CR */ 640 mtsprg1 %r1 641 GET_CPUINFO(%r1) 642 lwz %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* restore r28-r31 */ 643 lwz %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 644 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 645 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 646 mfsprg1 %r1 647 rfi /* return to trapped code */ 648 1: 649 mflr %r28 /* save LR (SP already saved) */ 650 651 /* Jump to disitrap */ 652 lwz %r1, TRAP_GENTRAP(0) 653 addi %r1, %r1, (disitrap - generictrap) 654 mtlr %r1 655 blrl 656 CNAME(dsiend): 657 658 /* 659 * Preamble code for DSI/ISI traps 660 */ 661 disitrap: 662 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 663 mflr %r1 664 andi. %r1,%r1,0xff00 665 mtsprg3 %r1 666 667 GET_CPUINFO(%r1) 668 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) 669 stw %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 670 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) 671 stw %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 672 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 673 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 674 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 675 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 676 mfdar %r30 677 mfdsisr %r31 678 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 679 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 680 681 #ifdef KDB 682 /* Try to detect a kernel stack overflow */ 683 mfsrr1 %r31 684 mtcr %r31 685 bt 17,realtrap /* branch is user mode */ 686 mfsprg1 %r31 /* get old SP */ 687 clrrwi %r31,%r31,12 /* Round SP down to nearest page */ 688 sub. %r30,%r31,%r30 /* SP - DAR */ 689 bge 1f 690 neg %r30,%r30 /* modulo value */ 691 1: cmplwi %cr0,%r30,4096 /* is DAR within a page of SP? */ 692 bge %cr0,realtrap /* no, too far away. */ 693 694 /* Now convert this DSI into a DDB trap. */ 695 GET_CPUINFO(%r1) 696 lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */ 697 stw %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */ 698 lwz %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */ 699 stw %r31,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */ 700 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */ 701 stw %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */ 702 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */ 703 stw %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */ 704 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */ 705 stw %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */ 706 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */ 707 stw %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */ 708 b dbtrap 709 #endif 710 711 /* XXX need stack probe here */ 712 realtrap: 713 /* Test whether we already had PR set */ 714 mfsrr1 %r1 715 mtcr %r1 716 mfsprg1 %r1 /* restore SP (might have been 717 overwritten) */ 718 bf 17,k_trap /* branch if PSL_PR is false */ 719 GET_CPUINFO(%r1) 720 lwz %r1,PC_CURPCB(%r1) 721 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */ 722 b s_trap 723 724 /* 725 * generictrap does some standard setup for trap handling to minimize 726 * the code that need be installed in the actual vectors. It expects 727 * the following conditions. 728 * 729 * R1 - Trap vector = LR & (0xff00 | R1) 730 * SPRG1 - Original R1 contents 731 * SPRG2 - Original LR 732 */ 733 734 .globl CNAME(generictrap64) 735 generictrap64: 736 mtsprg3 %r31 737 mfmsr %r31 738 clrldi %r31,%r31,1 739 mtmsrd %r31 740 mfsprg3 %r31 741 isync 742 743 .globl CNAME(generictrap) 744 generictrap: 745 /* Save R1 for computing the exception vector */ 746 mtsprg3 %r1 747 748 /* Save interesting registers */ 749 GET_CPUINFO(%r1) 750 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 751 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 752 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 753 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 754 mfsprg1 %r1 /* restore SP, in case of branch */ 755 mfsprg2 %r28 /* save LR */ 756 mfcr %r29 /* save CR */ 757 758 /* Compute the exception vector from the link register */ 759 mfsprg3 %r31 760 ori %r31,%r31,0xff00 761 mflr %r30 762 and %r30,%r30,%r31 763 mtsprg3 %r30 764 765 /* Test whether we already had PR set */ 766 mfsrr1 %r31 767 mtcr %r31 768 769 s_trap: 770 bf 17,k_trap /* branch if PSL_PR is false */ 771 GET_CPUINFO(%r1) 772 u_trap: 773 lwz %r1,PC_CURPCB(%r1) 774 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */ 775 776 /* 777 * Now the common trap catching code. 778 */ 779 k_trap: 780 FRAME_SETUP(PC_TEMPSAVE) 781 /* Restore USER_SR */ 782 GET_CPUINFO(%r30) 783 lwz %r30,PC_CURPCB(%r30) 784 lwz %r30,PCB_AIM_USR_VSID(%r30) 785 mtsr USER_SR,%r30; sync; isync 786 /* Call C interrupt dispatcher: */ 787 trapagain: 788 addi %r3,%r1,8 789 bl CNAME(powerpc_interrupt) 790 .globl CNAME(trapexit) /* backtrace code sentinel */ 791 CNAME(trapexit): 792 793 /* Disable interrupts: */ 794 mfmsr %r3 795 andi. %r3,%r3,~PSL_EE@l 796 mtmsr %r3 797 isync 798 /* Test AST pending: */ 799 lwz %r5,FRAME_SRR1+8(%r1) 800 mtcr %r5 801 bf 17,1f /* branch if PSL_PR is false */ 802 803 GET_CPUINFO(%r3) /* get per-CPU pointer */ 804 lwz %r4, TD_AST(%r2) /* get thread ast value 805 * (r2 is curthread) */ 806 cmpwi %r4, 0 807 beq 1f 808 mfmsr %r3 /* re-enable interrupts */ 809 ori %r3,%r3,PSL_EE@l 810 mtmsr %r3 811 isync 812 addi %r3,%r1,8 813 bl CNAME(ast) 814 .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */ 815 CNAME(asttrapexit): 816 b trapexit /* test ast ret value ? */ 817 1: 818 FRAME_LEAVE(PC_TEMPSAVE) 819 820 .globl CNAME(rfi_patch1) /* replace rfi with rfid on ppc64 */ 821 CNAME(rfi_patch1): 822 rfi 823 824 .globl CNAME(rfid_patch) 825 CNAME(rfid_patch): 826 rfid 827 828 #if defined(KDB) 829 /* 830 * Deliberate entry to dbtrap 831 */ 832 .globl CNAME(breakpoint) 833 CNAME(breakpoint): 834 mtsprg1 %r1 835 mfmsr %r3 836 mtsrr1 %r3 837 andi. %r3,%r3,~(PSL_EE|PSL_ME)@l 838 mtmsr %r3 /* disable interrupts */ 839 isync 840 GET_CPUINFO(%r3) 841 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3) 842 stw %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3) 843 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3) 844 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3) 845 mflr %r28 846 li %r29,EXC_BPT 847 mtlr %r29 848 mfcr %r29 849 mtsrr0 %r28 850 851 /* 852 * Now the kdb trap catching code. 853 */ 854 dbtrap: 855 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 856 mflr %r1 857 andi. %r1,%r1,0xff00 858 mtsprg3 %r1 859 860 lwz %r1,TRAP_TOCBASE(0) /* get new SP */ 861 lwz %r1,trapstk@got(%r1) 862 addi %r1,%r1,TRAPSTKSZ-16 863 864 FRAME_SETUP(PC_DBSAVE) 865 /* Call C trap code: */ 866 addi %r3,%r1,8 867 bl CNAME(db_trap_glue) 868 or. %r3,%r3,%r3 869 bne dbleave 870 /* This wasn't for KDB, so switch to real trap: */ 871 lwz %r3,FRAME_EXC+8(%r1) /* save exception */ 872 GET_CPUINFO(%r4) 873 stw %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4) 874 FRAME_LEAVE(PC_DBSAVE) 875 mtsprg1 %r1 /* prepare for entrance to realtrap */ 876 GET_CPUINFO(%r1) 877 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 878 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 879 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 880 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 881 mflr %r28 882 mfcr %r29 883 lwz %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) 884 mtsprg3 %r31 /* SPRG3 was clobbered by FRAME_LEAVE */ 885 mfsprg1 %r1 886 b realtrap 887 dbleave: 888 FRAME_LEAVE(PC_DBSAVE) 889 .globl CNAME(rfi_patch2) /* replace rfi with rfid on ppc64 */ 890 CNAME(rfi_patch2): 891 rfi 892 893 /* 894 * In case of KDB we want a separate trap catcher for it 895 */ 896 .globl CNAME(dblow),CNAME(dbend) 897 CNAME(dblow): 898 mtsprg1 %r1 /* save SP */ 899 mtsprg2 %r29 /* save r29 */ 900 mfcr %r29 /* save CR in r29 */ 901 mfsrr1 %r1 902 mtcr %r1 903 bf 17,1f /* branch if privileged */ 904 /* Unprivileged case */ 905 mtcr %r29 /* put the condition register back */ 906 mfsprg2 %r29 /* ... and r29 */ 907 mflr %r1 /* save LR */ 908 mtsprg2 %r1 /* And then in SPRG2 */ 909 910 lwz %r1, TRAP_ENTRY(0) /* Get branch address */ 911 mtlr %r1 912 li %r1, 0 /* How to get the vector from LR */ 913 blrl /* LR & (0xff00 | r1) is exception # */ 914 1: 915 /* Privileged, so drop to KDB */ 916 GET_CPUINFO(%r1) 917 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */ 918 mfsprg2 %r28 /* r29 holds cr... */ 919 stw %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */ 920 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */ 921 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */ 922 mflr %r28 /* save LR */ 923 924 /* Jump to dbtrap */ 925 lwz %r1, TRAP_GENTRAP(0) 926 addi %r1, %r1, (dbtrap - generictrap) 927 mtlr %r1 928 blrl 929 CNAME(dbend): 930 #endif /* KDB */
Cache object: 33065d8e5576b1c078aaccde1d092154
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