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sys/powerpc/aim/trap_subr32.S
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1 /* $FreeBSD$ */ 2 /* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */ 3 4 /*- 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * NOTICE: This is not a standalone file. to use it, #include it in 37 * your port's locore.S, like so: 38 * 39 * #include <powerpc/aim/trap_subr.S> 40 */ 41 42 /* 43 * Save/restore segment registers 44 */ 45 #define RESTORE_SRS(pmap,sr) mtsr 0,sr; \ 46 lwz sr,1*4(pmap); mtsr 1,sr; \ 47 lwz sr,2*4(pmap); mtsr 2,sr; \ 48 lwz sr,3*4(pmap); mtsr 3,sr; \ 49 lwz sr,4*4(pmap); mtsr 4,sr; \ 50 lwz sr,5*4(pmap); mtsr 5,sr; \ 51 lwz sr,6*4(pmap); mtsr 6,sr; \ 52 lwz sr,7*4(pmap); mtsr 7,sr; \ 53 lwz sr,8*4(pmap); mtsr 8,sr; \ 54 lwz sr,9*4(pmap); mtsr 9,sr; \ 55 lwz sr,10*4(pmap); mtsr 10,sr; \ 56 lwz sr,11*4(pmap); mtsr 11,sr; \ 57 /* Skip segment 12 (USER_SR), which is restored differently */ \ 58 lwz sr,13*4(pmap); mtsr 13,sr; \ 59 lwz sr,14*4(pmap); mtsr 14,sr; \ 60 lwz sr,15*4(pmap); mtsr 15,sr; isync; 61 62 /* 63 * User SRs are loaded through a pointer to the current pmap. 64 */ 65 #define RESTORE_USER_SRS(pmap,sr) \ 66 GET_CPUINFO(pmap); \ 67 lwz pmap,PC_CURPMAP(pmap); \ 68 lwzu sr,PM_SR(pmap); \ 69 RESTORE_SRS(pmap,sr) \ 70 /* Restore SR 12 */ \ 71 lwz sr,12*4(pmap); mtsr 12,sr 72 73 /* 74 * Kernel SRs are loaded directly from kernel_pmap_ 75 */ 76 #define RESTORE_KERN_SRS(pmap,sr) \ 77 lis pmap,CNAME(kernel_pmap_store)@ha; \ 78 lwzu sr,CNAME(kernel_pmap_store)+PM_SR@l(pmap); \ 79 RESTORE_SRS(pmap,sr) 80 81 /* 82 * FRAME_SETUP assumes: 83 * SPRG1 SP (1) 84 * SPRG3 trap type 85 * savearea r28-r31,DAR,DSISR (DAR & DSISR only for DSI traps) 86 * r28 LR 87 * r29 CR 88 * r30 scratch 89 * r31 scratch 90 * r1 kernel stack 91 * SRR0/1 as at start of trap 92 */ 93 #define FRAME_SETUP(savearea) \ 94 /* Have to enable translation to allow access of kernel stack: */ \ 95 GET_CPUINFO(%r31); \ 96 mfsrr0 %r30; \ 97 stw %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \ 98 mfsrr1 %r30; \ 99 stw %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \ 100 mfmsr %r30; \ 101 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \ 102 mtmsr %r30; /* stack can now be accessed */ \ 103 isync; \ 104 mfsprg1 %r31; /* get saved SP */ \ 105 stwu %r31,-FRAMELEN(%r1); /* save it in the callframe */ \ 106 stw %r0, FRAME_0+8(%r1); /* save r0 in the trapframe */ \ 107 stw %r31,FRAME_1+8(%r1); /* save SP " " */ \ 108 stw %r2, FRAME_2+8(%r1); /* save r2 " " */ \ 109 stw %r28,FRAME_LR+8(%r1); /* save LR " " */ \ 110 stw %r29,FRAME_CR+8(%r1); /* save CR " " */ \ 111 GET_CPUINFO(%r2); \ 112 lwz %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \ 113 lwz %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \ 114 lwz %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \ 115 lwz %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \ 116 stw %r3, FRAME_3+8(%r1); /* save r3-r31 */ \ 117 stw %r4, FRAME_4+8(%r1); \ 118 stw %r5, FRAME_5+8(%r1); \ 119 stw %r6, FRAME_6+8(%r1); \ 120 stw %r7, FRAME_7+8(%r1); \ 121 stw %r8, FRAME_8+8(%r1); \ 122 stw %r9, FRAME_9+8(%r1); \ 123 stw %r10, FRAME_10+8(%r1); \ 124 stw %r11, FRAME_11+8(%r1); \ 125 stw %r12, FRAME_12+8(%r1); \ 126 stw %r13, FRAME_13+8(%r1); \ 127 stw %r14, FRAME_14+8(%r1); \ 128 stw %r15, FRAME_15+8(%r1); \ 129 stw %r16, FRAME_16+8(%r1); \ 130 stw %r17, FRAME_17+8(%r1); \ 131 stw %r18, FRAME_18+8(%r1); \ 132 stw %r19, FRAME_19+8(%r1); \ 133 stw %r20, FRAME_20+8(%r1); \ 134 stw %r21, FRAME_21+8(%r1); \ 135 stw %r22, FRAME_22+8(%r1); \ 136 stw %r23, FRAME_23+8(%r1); \ 137 stw %r24, FRAME_24+8(%r1); \ 138 stw %r25, FRAME_25+8(%r1); \ 139 stw %r26, FRAME_26+8(%r1); \ 140 stw %r27, FRAME_27+8(%r1); \ 141 stw %r28, FRAME_28+8(%r1); \ 142 stw %r29, FRAME_29+8(%r1); \ 143 stw %r30, FRAME_30+8(%r1); \ 144 stw %r31, FRAME_31+8(%r1); \ 145 lwz %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \ 146 lwz %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\ 147 lwz %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \ 148 lwz %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \ 149 mfxer %r3; \ 150 mfctr %r4; \ 151 mfsprg3 %r5; \ 152 stw %r3, FRAME_XER+8(1); /* save xer/ctr/exc */ \ 153 stw %r4, FRAME_CTR+8(1); \ 154 stw %r5, FRAME_EXC+8(1); \ 155 stw %r28,FRAME_AIM_DAR+8(1); \ 156 stw %r29,FRAME_AIM_DSISR+8(1); /* save dsisr/srr0/srr1 */ \ 157 stw %r30,FRAME_SRR0+8(1); \ 158 stw %r31,FRAME_SRR1+8(1); \ 159 lwz %r2,PC_CURTHREAD(%r2) /* set curthread pointer */ 160 161 #define FRAME_LEAVE(savearea) \ 162 /* Disable exceptions: */ \ 163 mfmsr %r2; \ 164 andi. %r2,%r2,~PSL_EE@l; \ 165 mtmsr %r2; \ 166 isync; \ 167 /* Now restore regs: */ \ 168 lwz %r2,FRAME_SRR0+8(%r1); \ 169 lwz %r3,FRAME_SRR1+8(%r1); \ 170 lwz %r4,FRAME_CTR+8(%r1); \ 171 lwz %r5,FRAME_XER+8(%r1); \ 172 lwz %r6,FRAME_LR+8(%r1); \ 173 GET_CPUINFO(%r7); \ 174 stw %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \ 175 stw %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \ 176 lwz %r7,FRAME_CR+8(%r1); \ 177 mtctr %r4; \ 178 mtxer %r5; \ 179 mtlr %r6; \ 180 mtsprg1 %r7; /* save cr */ \ 181 lwz %r31,FRAME_31+8(%r1); /* restore r0-31 */ \ 182 lwz %r30,FRAME_30+8(%r1); \ 183 lwz %r29,FRAME_29+8(%r1); \ 184 lwz %r28,FRAME_28+8(%r1); \ 185 lwz %r27,FRAME_27+8(%r1); \ 186 lwz %r26,FRAME_26+8(%r1); \ 187 lwz %r25,FRAME_25+8(%r1); \ 188 lwz %r24,FRAME_24+8(%r1); \ 189 lwz %r23,FRAME_23+8(%r1); \ 190 lwz %r22,FRAME_22+8(%r1); \ 191 lwz %r21,FRAME_21+8(%r1); \ 192 lwz %r20,FRAME_20+8(%r1); \ 193 lwz %r19,FRAME_19+8(%r1); \ 194 lwz %r18,FRAME_18+8(%r1); \ 195 lwz %r17,FRAME_17+8(%r1); \ 196 lwz %r16,FRAME_16+8(%r1); \ 197 lwz %r15,FRAME_15+8(%r1); \ 198 lwz %r14,FRAME_14+8(%r1); \ 199 lwz %r13,FRAME_13+8(%r1); \ 200 lwz %r12,FRAME_12+8(%r1); \ 201 lwz %r11,FRAME_11+8(%r1); \ 202 lwz %r10,FRAME_10+8(%r1); \ 203 lwz %r9, FRAME_9+8(%r1); \ 204 lwz %r8, FRAME_8+8(%r1); \ 205 lwz %r7, FRAME_7+8(%r1); \ 206 lwz %r6, FRAME_6+8(%r1); \ 207 lwz %r5, FRAME_5+8(%r1); \ 208 lwz %r4, FRAME_4+8(%r1); \ 209 lwz %r3, FRAME_3+8(%r1); \ 210 lwz %r2, FRAME_2+8(%r1); \ 211 lwz %r0, FRAME_0+8(%r1); \ 212 lwz %r1, FRAME_1+8(%r1); \ 213 /* Can't touch %r1 from here on */ \ 214 mtsprg2 %r2; /* save r2 & r3 */ \ 215 mtsprg3 %r3; \ 216 /* Disable translation, machine check and recoverability: */ \ 217 mfmsr %r2; \ 218 andi. %r2,%r2,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \ 219 mtmsr %r2; \ 220 isync; \ 221 /* Decide whether we return to user mode: */ \ 222 GET_CPUINFO(%r2); \ 223 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); \ 224 mtcr %r3; \ 225 bf 17,1f; /* branch if PSL_PR is false */ \ 226 /* Restore user SRs */ \ 227 RESTORE_USER_SRS(%r2,%r3); \ 228 1: mfsprg1 %r2; /* restore cr */ \ 229 mtcr %r2; \ 230 GET_CPUINFO(%r2); \ 231 lwz %r3,(savearea+CPUSAVE_SRR0)(%r2); /* restore srr0 */ \ 232 mtsrr0 %r3; \ 233 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); /* restore srr1 */ \ 234 \ 235 /* Make sure HV bit of MSR propagated to SRR1 */ \ 236 mfmsr %r2; \ 237 or %r3,%r2,%r3; \ 238 \ 239 mtsrr1 %r3; \ 240 mfsprg2 %r2; /* restore r2 & r3 */ \ 241 mfsprg3 %r3 242 243 /* 244 * The next two routines are 64-bit glue code. The first is used to test if 245 * we are on a 64-bit system. By copying it to the illegal instruction 246 * handler, we can test for 64-bit mode by trying to execute a 64-bit 247 * instruction and seeing what happens. The second gets copied in front 248 * of all the other handlers to restore 32-bit bridge mode when traps 249 * are taken. 250 */ 251 252 /* 64-bit test code. Sets SPRG2 to 0 if an illegal instruction is executed */ 253 254 .globl CNAME(testppc64),CNAME(testppc64size) 255 CNAME(testppc64): 256 mtsprg1 %r31 257 mfsrr0 %r31 258 addi %r31, %r31, 4 259 mtsrr0 %r31 260 261 li %r31, 0 262 mtsprg2 %r31 263 mfsprg1 %r31 264 265 rfi 266 CNAME(testppc64size) = .-CNAME(testppc64) 267 268 269 /* 64-bit bridge mode restore snippet. Gets copied in front of everything else 270 * on 64-bit systems. */ 271 272 .globl CNAME(restorebridge),CNAME(restorebridgesize) 273 CNAME(restorebridge): 274 mtsprg1 %r31 275 mfmsr %r31 276 clrldi %r31,%r31,1 277 mtmsrd %r31 278 mfsprg1 %r31 279 isync 280 CNAME(restorebridgesize) = .-CNAME(restorebridge) 281 282 #ifdef SMP 283 /* 284 * Processor reset exception handler. These are typically 285 * the first instructions the processor executes after a 286 * software reset. We do this in two bits so that we are 287 * not still hanging around in the trap handling region 288 * once the MMU is turned on. 289 */ 290 .globl CNAME(rstcode), CNAME(rstsize) 291 CNAME(rstcode): 292 ba cpu_reset 293 CNAME(rstsize) = . - CNAME(rstcode) 294 295 cpu_reset: 296 bl 1f 297 298 .space 124 299 300 1: 301 mflr %r1 302 addi %r1,%r1,(124-16)@l 303 304 lis %r3,1@l 305 bla CNAME(cpudep_ap_early_bootstrap) 306 bla CNAME(pmap_cpu_bootstrap) 307 bla CNAME(cpudep_ap_bootstrap) 308 mr %r1,%r3 309 bla CNAME(machdep_ap_bootstrap) 310 311 /* Should not be reached */ 312 9: 313 b 9b 314 #endif 315 316 /* 317 * This code gets copied to all the trap vectors 318 * (except ISI/DSI, ALI, and the interrupts) 319 */ 320 321 .globl CNAME(trapcode),CNAME(trapsize) 322 CNAME(trapcode): 323 mtsprg1 %r1 /* save SP */ 324 mflr %r1 /* Save the old LR in r1 */ 325 mtsprg2 %r1 /* And then in SPRG2 */ 326 li %r1, 0x20 /* How to get the vector from LR */ 327 bla generictrap /* LR & SPRG3 is exception # */ 328 CNAME(trapsize) = .-CNAME(trapcode) 329 330 /* 331 * 64-bit version of trapcode. Identical, except it calls generictrap64. 332 */ 333 .globl CNAME(trapcode64) 334 CNAME(trapcode64): 335 mtsprg1 %r1 /* save SP */ 336 mflr %r1 /* Save the old LR in r1 */ 337 mtsprg2 %r1 /* And then in SPRG2 */ 338 li %r1, 0x20 /* How to get the vector from LR */ 339 bla generictrap64 /* LR & SPRG3 is exception # */ 340 341 /* 342 * For ALI: has to save DSISR and DAR 343 */ 344 .globl CNAME(alitrap),CNAME(alisize) 345 CNAME(alitrap): 346 mtsprg1 %r1 /* save SP */ 347 GET_CPUINFO(%r1) 348 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 349 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 350 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 351 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 352 mfdar %r30 353 mfdsisr %r31 354 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 355 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 356 mfsprg1 %r1 /* restore SP, in case of branch */ 357 mflr %r28 /* save LR */ 358 mfcr %r29 /* save CR */ 359 360 /* Put our exception vector in SPRG3 */ 361 li %r31, EXC_ALI 362 mtsprg3 %r31 363 364 /* Test whether we already had PR set */ 365 mfsrr1 %r31 366 mtcr %r31 367 bla s_trap 368 CNAME(alisize) = .-CNAME(alitrap) 369 370 /* 371 * G2 specific: instuction TLB miss. 372 */ 373 .globl CNAME(imisstrap),CNAME(imisssize) 374 CNAME(imisstrap): 375 mfspr %r2, SPR_HASH1 /* get first pointer */ 376 addi %r1, 0, 8 /* load 8 for counter */ 377 mfctr %r0 /* save counter */ 378 mfspr %r3, SPR_ICMP /* get first compare value */ 379 addi %r2, %r2, -8 /* pre dec the pointer */ 380 im0: 381 mtctr %r1 /* load counter */ 382 im1: 383 lwzu %r1, 8(%r2) /* get next pte */ 384 cmp 0, %r1, %r3 /* see if found pte */ 385 bdnzf 2, im1 /* dec count br if cmp ne and if 386 * count not zero */ 387 bne instr_sec_hash /* if not found set up second hash 388 * or exit */ 389 lwz %r1, +4(%r2) /* load tlb entry lower-word */ 390 andi. %r3, %r1, 8 /* check G bit */ 391 bne do_isi_prot /* if guarded, take an ISI */ 392 mtctr %r0 /* restore counter */ 393 mfspr %r0, SPR_IMISS /* get the miss address for the tlbli */ 394 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 395 mtcrf 0x80, %r3 /* restore CR0 */ 396 mtspr SPR_RPA, %r1 /* set the pte */ 397 ori %r1, %r1, 0x100 /* set reference bit */ 398 srwi %r1, %r1, 8 /* get byte 7 of pte */ 399 tlbli %r0 /* load the itlb */ 400 stb %r1, +6(%r2) /* update page table */ 401 rfi /* return to executing program */ 402 403 instr_sec_hash: 404 andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 405 bne do_isi /* if so, go to ISI interrupt */ 406 mfspr %r2, SPR_HASH2 /* get the second pointer */ 407 ori %r3, %r3, 0x0040 /* change the compare value */ 408 addi %r1, %r0, 8 /* load 8 for counter */ 409 addi %r2, %r2, -8 /* pre dec for update on load */ 410 b im0 /* try second hash */ 411 412 /* Create a faked ISI interrupt as the address was not found */ 413 do_isi_prot: 414 mfspr %r3, SPR_SRR1 /* get srr1 */ 415 andi. %r2, %r3, 0xffff /* clean upper srr1 */ 416 addis %r2, %r2, 0x0800 /* or in srr<4> = 1 to flag prot 417 * violation */ 418 b isi1 419 do_isi: 420 mfspr %r3, SPR_SRR1 /* get srr1 */ 421 andi. %r2, %r3, 0xffff /* clean srr1 */ 422 addis %r2, %r2, 0x4000 /* or in srr1<1> = 1 to flag pte 423 * not found */ 424 isi1: 425 mtctr %r0 /* restore counter */ 426 mtspr SPR_SRR1, %r2 /* set srr1 */ 427 mfmsr %r0 /* get msr */ 428 xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */ 429 mtcrf 0x80, %r3 /* restore CR0 */ 430 mtmsr %r0 /* flip back to the native gprs */ 431 ba EXC_ISI /* go to instr. access interrupt */ 432 433 CNAME(imisssize) = .-CNAME(imisstrap) 434 435 /* 436 * G2 specific: data load TLB miss. 437 */ 438 .globl CNAME(dlmisstrap),CNAME(dlmisssize) 439 CNAME(dlmisstrap): 440 mfspr %r2, SPR_HASH1 /* get first pointer */ 441 addi %r1, 0, 8 /* load 8 for counter */ 442 mfctr %r0 /* save counter */ 443 mfspr %r3, SPR_DCMP /* get first compare value */ 444 addi %r2, %r2, -8 /* pre dec the pointer */ 445 dm0: 446 mtctr %r1 /* load counter */ 447 dm1: 448 lwzu %r1, 8(%r2) /* get next pte */ 449 cmp 0, 0, %r1, %r3 /* see if found pte */ 450 bdnzf 2, dm1 /* dec count br if cmp ne and if 451 * count not zero */ 452 bne data_sec_hash /* if not found set up second hash 453 * or exit */ 454 lwz %r1, +4(%r2) /* load tlb entry lower-word */ 455 mtctr %r0 /* restore counter */ 456 mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */ 457 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 458 mtcrf 0x80, %r3 /* restore CR0 */ 459 mtspr SPR_RPA, %r1 /* set the pte */ 460 ori %r1, %r1, 0x100 /* set reference bit */ 461 srwi %r1, %r1, 8 /* get byte 7 of pte */ 462 tlbld %r0 /* load the dtlb */ 463 stb %r1, +6(%r2) /* update page table */ 464 rfi /* return to executing program */ 465 466 data_sec_hash: 467 andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 468 bne do_dsi /* if so, go to DSI interrupt */ 469 mfspr %r2, SPR_HASH2 /* get the second pointer */ 470 ori %r3, %r3, 0x0040 /* change the compare value */ 471 addi %r1, 0, 8 /* load 8 for counter */ 472 addi %r2, %r2, -8 /* pre dec for update on load */ 473 b dm0 /* try second hash */ 474 475 CNAME(dlmisssize) = .-CNAME(dlmisstrap) 476 477 /* 478 * G2 specific: data store TLB miss. 479 */ 480 .globl CNAME(dsmisstrap),CNAME(dsmisssize) 481 CNAME(dsmisstrap): 482 mfspr %r2, SPR_HASH1 /* get first pointer */ 483 addi %r1, 0, 8 /* load 8 for counter */ 484 mfctr %r0 /* save counter */ 485 mfspr %r3, SPR_DCMP /* get first compare value */ 486 addi %r2, %r2, -8 /* pre dec the pointer */ 487 ds0: 488 mtctr %r1 /* load counter */ 489 ds1: 490 lwzu %r1, 8(%r2) /* get next pte */ 491 cmp 0, 0, %r1, %r3 /* see if found pte */ 492 bdnzf 2, ds1 /* dec count br if cmp ne and if 493 * count not zero */ 494 bne data_store_sec_hash /* if not found set up second hash 495 * or exit */ 496 lwz %r1, +4(%r2) /* load tlb entry lower-word */ 497 andi. %r3, %r1, 0x80 /* check the C-bit */ 498 beq data_store_chk_prot /* if (C==0) 499 * go check protection modes */ 500 ds2: 501 mtctr %r0 /* restore counter */ 502 mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */ 503 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 504 mtcrf 0x80, %r3 /* restore CR0 */ 505 mtspr SPR_RPA, %r1 /* set the pte */ 506 tlbld %r0 /* load the dtlb */ 507 rfi /* return to executing program */ 508 509 data_store_sec_hash: 510 andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 511 bne do_dsi /* if so, go to DSI interrupt */ 512 mfspr %r2, SPR_HASH2 /* get the second pointer */ 513 ori %r3, %r3, 0x0040 /* change the compare value */ 514 addi %r1, 0, 8 /* load 8 for counter */ 515 addi %r2, %r2, -8 /* pre dec for update on load */ 516 b ds0 /* try second hash */ 517 518 /* Check the protection before setting PTE(c-bit) */ 519 data_store_chk_prot: 520 rlwinm. %r3,%r1,30,0,1 /* test PP */ 521 bge- chk0 /* if (PP == 00 or PP == 01) 522 * goto chk0: */ 523 andi. %r3, %r1, 1 /* test PP[0] */ 524 beq+ chk2 /* return if PP[0] == 0 */ 525 b do_dsi_prot /* else DSIp */ 526 chk0: 527 mfspr %r3,SPR_SRR1 /* get old msr */ 528 andis. %r3,%r3,0x0008 /* test the KEY bit (SRR1-bit 12) */ 529 beq chk2 /* if (KEY==0) goto chk2: */ 530 b do_dsi_prot /* else do_dsi_prot */ 531 chk2: 532 ori %r1, %r1, 0x180 /* set reference and change bit */ 533 sth %r1, 6(%r2) /* update page table */ 534 b ds2 /* and back we go */ 535 536 /* Create a faked DSI interrupt as the address was not found */ 537 do_dsi: 538 mfspr %r3, SPR_SRR1 /* get srr1 */ 539 rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for 540 * load/store, zero rest */ 541 addis %r1, %r1, 0x4000 /* or in dsisr<1> = 1 to flag pte 542 * not found */ 543 b dsi1 544 545 do_dsi_prot: 546 mfspr %r3, SPR_SRR1 /* get srr1 */ 547 rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for 548 *load/store, zero rest */ 549 addis %r1, %r1, 0x0800 /* or in dsisr<4> = 1 to flag prot 550 * violation */ 551 552 dsi1: 553 mtctr %r0 /* restore counter */ 554 andi. %r2, %r3, 0xffff /* clear upper bits of srr1 */ 555 mtspr SPR_SRR1, %r2 /* set srr1 */ 556 mtspr SPR_DSISR, %r1 /* load the dsisr */ 557 mfspr %r1, SPR_DMISS /* get miss address */ 558 rlwinm. %r2,%r2,0,31,31 /* test LE bit */ 559 beq dsi2 /* if little endian then: */ 560 xor %r1, %r1, 0x07 /* de-mung the data address */ 561 dsi2: 562 mtspr SPR_DAR, %r1 /* put in dar */ 563 mfmsr %r0 /* get msr */ 564 xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */ 565 mtcrf 0x80, %r3 /* restore CR0 */ 566 mtmsr %r0 /* flip back to the native gprs */ 567 ba EXC_DSI /* branch to DSI interrupt */ 568 569 CNAME(dsmisssize) = .-CNAME(dsmisstrap) 570 571 /* 572 * Similar to the above for DSI 573 * Has to handle BAT spills 574 * and standard pagetable spills 575 */ 576 .globl CNAME(dsitrap),CNAME(dsisize) 577 CNAME(dsitrap): 578 mtsprg1 %r1 /* save SP */ 579 GET_CPUINFO(%r1) 580 stw %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 581 stw %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 582 stw %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 583 stw %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 584 mfsprg1 %r1 /* restore SP */ 585 mfcr %r29 /* save CR */ 586 mfxer %r30 /* save XER */ 587 mtsprg2 %r30 /* in SPRG2 */ 588 mfsrr1 %r31 /* test kernel mode */ 589 mtcr %r31 590 bt 17,1f /* branch if PSL_PR is set */ 591 mfdar %r31 /* get fault address */ 592 rlwinm %r31,%r31,7,25,28 /* get segment * 8 */ 593 594 /* get batu */ 595 addis %r31,%r31,CNAME(battable)@ha 596 lwz %r30,CNAME(battable)@l(31) 597 mtcr %r30 598 bf 30,1f /* branch if supervisor valid is 599 false */ 600 /* get batl */ 601 lwz %r31,CNAME(battable)+4@l(31) 602 /* We randomly use the highest two bat registers here */ 603 mftb %r28 604 andi. %r28,%r28,1 605 bne 2f 606 mtdbatu 2,%r30 607 mtdbatl 2,%r31 608 b 3f 609 2: 610 mtdbatu 3,%r30 611 mtdbatl 3,%r31 612 3: 613 mfsprg2 %r30 /* restore XER */ 614 mtxer %r30 615 mtcr %r29 /* restore CR */ 616 mtsprg1 %r1 617 GET_CPUINFO(%r1) 618 lwz %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* restore r28-r31 */ 619 lwz %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 620 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 621 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 622 mfsprg1 %r1 623 rfi /* return to trapped code */ 624 1: 625 mflr %r28 /* save LR (SP already saved) */ 626 bla disitrap 627 CNAME(dsisize) = .-CNAME(dsitrap) 628 629 /* 630 * Preamble code for DSI/ISI traps 631 */ 632 disitrap: 633 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 634 mflr %r1 635 andi. %r1,%r1,0xff00 636 mtsprg3 %r1 637 638 GET_CPUINFO(%r1) 639 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) 640 stw %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 641 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) 642 stw %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 643 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 644 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 645 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 646 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 647 mfdar %r30 648 mfdsisr %r31 649 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 650 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 651 652 #ifdef KDB 653 /* Try and detect a kernel stack overflow */ 654 mfsrr1 %r31 655 mtcr %r31 656 bt 17,realtrap /* branch is user mode */ 657 mfsprg1 %r31 /* get old SP */ 658 sub. %r30,%r31,%r30 /* SP - DAR */ 659 bge 1f 660 neg %r30,%r30 /* modulo value */ 661 1: cmplwi %cr0,%r30,4096 /* is DAR within a page of SP? */ 662 bge %cr0,realtrap /* no, too far away. */ 663 664 /* Now convert this DSI into a DDB trap. */ 665 GET_CPUINFO(%r1) 666 lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */ 667 stw %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */ 668 lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */ 669 stw %r30,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */ 670 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */ 671 stw %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */ 672 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */ 673 stw %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */ 674 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */ 675 stw %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */ 676 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */ 677 stw %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */ 678 b dbtrap 679 #endif 680 681 /* XXX need stack probe here */ 682 realtrap: 683 /* Test whether we already had PR set */ 684 mfsrr1 %r1 685 mtcr %r1 686 mfsprg1 %r1 /* restore SP (might have been 687 overwritten) */ 688 bf 17,k_trap /* branch if PSL_PR is false */ 689 GET_CPUINFO(%r1) 690 lwz %r1,PC_CURPCB(%r1) 691 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */ 692 ba s_trap 693 694 /* 695 * generictrap does some standard setup for trap handling to minimize 696 * the code that need be installed in the actual vectors. It expects 697 * the following conditions. 698 * 699 * R1 - Trap vector = LR & (0xff00 | R1) 700 * SPRG1 - Original R1 contents 701 * SPRG2 - Original LR 702 */ 703 704 generictrap64: 705 mtsprg3 %r31 706 mfmsr %r31 707 clrldi %r31,%r31,1 708 mtmsrd %r31 709 mfsprg3 %r31 710 isync 711 712 generictrap: 713 /* Save R1 for computing the exception vector */ 714 mtsprg3 %r1 715 716 /* Save interesting registers */ 717 GET_CPUINFO(%r1) 718 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 719 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 720 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 721 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 722 mfsprg1 %r1 /* restore SP, in case of branch */ 723 mfsprg2 %r28 /* save LR */ 724 mfcr %r29 /* save CR */ 725 726 /* Compute the exception vector from the link register */ 727 mfsprg3 %r31 728 ori %r31,%r31,0xff00 729 mflr %r30 730 and %r30,%r30,%r31 731 mtsprg3 %r30 732 733 /* Test whether we already had PR set */ 734 mfsrr1 %r31 735 mtcr %r31 736 737 s_trap: 738 bf 17,k_trap /* branch if PSL_PR is false */ 739 GET_CPUINFO(%r1) 740 u_trap: 741 lwz %r1,PC_CURPCB(%r1) 742 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */ 743 744 /* 745 * Now the common trap catching code. 746 */ 747 k_trap: 748 FRAME_SETUP(PC_TEMPSAVE) 749 /* Restore USER_SR */ 750 GET_CPUINFO(%r30) 751 lwz %r30,PC_CURPCB(%r30) 752 lwz %r30,PCB_AIM_USR_VSID(%r30) 753 mtsr USER_SR,%r30; sync; isync 754 /* Call C interrupt dispatcher: */ 755 trapagain: 756 addi %r3,%r1,8 757 bl CNAME(powerpc_interrupt) 758 .globl CNAME(trapexit) /* backtrace code sentinel */ 759 CNAME(trapexit): 760 761 /* Disable interrupts: */ 762 mfmsr %r3 763 andi. %r3,%r3,~PSL_EE@l 764 mtmsr %r3 765 /* Test AST pending: */ 766 lwz %r5,FRAME_SRR1+8(%r1) 767 mtcr %r5 768 bf 17,1f /* branch if PSL_PR is false */ 769 770 GET_CPUINFO(%r3) /* get per-CPU pointer */ 771 lwz %r4, TD_FLAGS(%r2) /* get thread flags value 772 * (r2 is curthread) */ 773 lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h 774 ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l 775 and. %r4,%r4,%r5 776 beq 1f 777 mfmsr %r3 /* re-enable interrupts */ 778 ori %r3,%r3,PSL_EE@l 779 mtmsr %r3 780 isync 781 addi %r3,%r1,8 782 bl CNAME(ast) 783 .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */ 784 CNAME(asttrapexit): 785 b trapexit /* test ast ret value ? */ 786 1: 787 FRAME_LEAVE(PC_TEMPSAVE) 788 789 .globl CNAME(rfi_patch1) /* replace rfi with rfid on ppc64 */ 790 CNAME(rfi_patch1): 791 rfi 792 793 .globl CNAME(rfid_patch) 794 CNAME(rfid_patch): 795 rfid 796 797 #if defined(KDB) 798 /* 799 * Deliberate entry to dbtrap 800 */ 801 .globl CNAME(breakpoint) 802 CNAME(breakpoint): 803 mtsprg1 %r1 804 mfmsr %r3 805 mtsrr1 %r3 806 andi. %r3,%r3,~(PSL_EE|PSL_ME)@l 807 mtmsr %r3 /* disable interrupts */ 808 isync 809 GET_CPUINFO(%r3) 810 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3) 811 stw %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3) 812 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3) 813 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3) 814 mflr %r28 815 li %r29,EXC_BPT 816 mtlr %r29 817 mfcr %r29 818 mtsrr0 %r28 819 820 /* 821 * Now the kdb trap catching code. 822 */ 823 dbtrap: 824 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 825 mflr %r1 826 andi. %r1,%r1,0xff00 827 mtsprg3 %r1 828 829 lis %r1,(tmpstk+TMPSTKSZ-16)@ha /* get new SP */ 830 addi %r1,%r1,(tmpstk+TMPSTKSZ-16)@l 831 832 FRAME_SETUP(PC_DBSAVE) 833 /* Call C trap code: */ 834 addi %r3,%r1,8 835 bl CNAME(db_trap_glue) 836 or. %r3,%r3,%r3 837 bne dbleave 838 /* This wasn't for KDB, so switch to real trap: */ 839 lwz %r3,FRAME_EXC+8(%r1) /* save exception */ 840 GET_CPUINFO(%r4) 841 stw %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4) 842 FRAME_LEAVE(PC_DBSAVE) 843 mtsprg1 %r1 /* prepare for entrance to realtrap */ 844 GET_CPUINFO(%r1) 845 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 846 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 847 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 848 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 849 mflr %r28 850 mfcr %r29 851 lwz %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) 852 mtsprg3 %r31 /* SPRG3 was clobbered by FRAME_LEAVE */ 853 mfsprg1 %r1 854 b realtrap 855 dbleave: 856 FRAME_LEAVE(PC_DBSAVE) 857 .globl CNAME(rfi_patch2) /* replace rfi with rfid on ppc64 */ 858 CNAME(rfi_patch2): 859 rfi 860 861 /* 862 * In case of KDB we want a separate trap catcher for it 863 */ 864 .globl CNAME(dblow),CNAME(dbsize) 865 CNAME(dblow): 866 mtsprg1 %r1 /* save SP */ 867 mtsprg2 %r29 /* save r29 */ 868 mfcr %r29 /* save CR in r29 */ 869 mfsrr1 %r1 870 mtcr %r1 871 bf 17,1f /* branch if privileged */ 872 873 /* Unprivileged case */ 874 mtcr %r29 /* put the condition register back */ 875 mfsprg2 %r29 /* ... and r29 */ 876 mflr %r1 /* save LR */ 877 mtsprg2 %r1 /* And then in SPRG2 */ 878 li %r1, 0 /* How to get the vector from LR */ 879 880 bla generictrap /* and we look like a generic trap */ 881 1: 882 /* Privileged, so drop to KDB */ 883 GET_CPUINFO(%r1) 884 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */ 885 mfsprg2 %r28 /* r29 holds cr... */ 886 stw %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */ 887 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */ 888 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */ 889 mflr %r28 /* save LR */ 890 bla dbtrap 891 CNAME(dbsize) = .-CNAME(dblow) 892 #endif /* KDB */
Cache object: 6eedff72a1b58c9f0065c7cd332f5396
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