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sys/powerpc/aim/trap_subr64.S
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1 /* $FreeBSD$ */ 2 /* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */ 3 4 /*- 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * NOTICE: This is not a standalone file. to use it, #include it in 37 * your port's locore.S, like so: 38 * 39 * #include <powerpc/aim/trap_subr.S> 40 */ 41 42 /* 43 * Save/restore segment registers 44 */ 45 46 /* 47 * Restore SRs for a pmap 48 * 49 * Requires that r28-r31 be scratch, with r28 initialized to the SLB cache 50 */ 51 52 /* 53 * User SRs are loaded through a pointer to the current pmap. 54 */ 55 restore_usersrs: 56 GET_CPUINFO(%r28) 57 ld %r28,PC_USERSLB(%r28) 58 li %r29, 0 /* Set the counter to zero */ 59 60 slbia 61 slbmfee %r31,%r29 62 clrrdi %r31,%r31,28 63 slbie %r31 64 1: ld %r31, 0(%r28) /* Load SLB entry pointer */ 65 cmpli 0, %r31, 0 /* If NULL, stop */ 66 beqlr 67 68 ld %r30, 0(%r31) /* Load SLBV */ 69 ld %r31, 8(%r31) /* Load SLBE */ 70 or %r31, %r31, %r29 /* Set SLBE slot */ 71 slbmte %r30, %r31 /* Install SLB entry */ 72 73 addi %r28, %r28, 8 /* Advance pointer */ 74 addi %r29, %r29, 1 75 b 1b /* Repeat */ 76 77 /* 78 * Kernel SRs are loaded directly from the PCPU fields 79 */ 80 restore_kernsrs: 81 GET_CPUINFO(%r28) 82 addi %r28,%r28,PC_KERNSLB 83 li %r29, 0 /* Set the counter to zero */ 84 85 slbia 86 slbmfee %r31,%r29 87 clrrdi %r31,%r31,28 88 slbie %r31 89 1: cmpli 0, %r29, USER_SLB_SLOT /* Skip the user slot */ 90 beq- 2f 91 92 ld %r31, 8(%r28) /* Load SLBE */ 93 cmpli 0, %r31, 0 /* If SLBE is not valid, stop */ 94 beqlr 95 ld %r30, 0(%r28) /* Load SLBV */ 96 slbmte %r30, %r31 /* Install SLB entry */ 97 98 2: addi %r28, %r28, 16 /* Advance pointer */ 99 addi %r29, %r29, 1 100 cmpli 0, %r29, 64 /* Repeat if we are not at the end */ 101 blt 1b 102 blr 103 104 /* 105 * FRAME_SETUP assumes: 106 * SPRG1 SP (1) 107 * SPRG3 trap type 108 * savearea r27-r31,DAR,DSISR (DAR & DSISR only for DSI traps) 109 * r28 LR 110 * r29 CR 111 * r30 scratch 112 * r31 scratch 113 * r1 kernel stack 114 * SRR0/1 as at start of trap 115 * 116 * NOTE: SPRG1 is never used while the MMU is on, making it safe to reuse 117 * in any real-mode fault handler, including those handling double faults. 118 */ 119 #define FRAME_SETUP(savearea) \ 120 /* Have to enable translation to allow access of kernel stack: */ \ 121 GET_CPUINFO(%r31); \ 122 mfsrr0 %r30; \ 123 std %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \ 124 mfsrr1 %r30; \ 125 std %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \ 126 mfsprg1 %r31; /* get saved SP (clears SPRG1) */ \ 127 mfmsr %r30; \ 128 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \ 129 mtmsr %r30; /* stack can now be accessed */ \ 130 isync; \ 131 stdu %r31,-(FRAMELEN+288)(%r1); /* save it in the callframe */ \ 132 std %r0, FRAME_0+48(%r1); /* save r0 in the trapframe */ \ 133 std %r31,FRAME_1+48(%r1); /* save SP " " */ \ 134 std %r2, FRAME_2+48(%r1); /* save r2 " " */ \ 135 std %r28,FRAME_LR+48(%r1); /* save LR " " */ \ 136 std %r29,FRAME_CR+48(%r1); /* save CR " " */ \ 137 GET_CPUINFO(%r2); \ 138 ld %r27,(savearea+CPUSAVE_R27)(%r2); /* get saved r27 */ \ 139 ld %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \ 140 ld %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \ 141 ld %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \ 142 ld %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \ 143 std %r3, FRAME_3+48(%r1); /* save r3-r31 */ \ 144 std %r4, FRAME_4+48(%r1); \ 145 std %r5, FRAME_5+48(%r1); \ 146 std %r6, FRAME_6+48(%r1); \ 147 std %r7, FRAME_7+48(%r1); \ 148 std %r8, FRAME_8+48(%r1); \ 149 std %r9, FRAME_9+48(%r1); \ 150 std %r10, FRAME_10+48(%r1); \ 151 std %r11, FRAME_11+48(%r1); \ 152 std %r12, FRAME_12+48(%r1); \ 153 std %r13, FRAME_13+48(%r1); \ 154 std %r14, FRAME_14+48(%r1); \ 155 std %r15, FRAME_15+48(%r1); \ 156 std %r16, FRAME_16+48(%r1); \ 157 std %r17, FRAME_17+48(%r1); \ 158 std %r18, FRAME_18+48(%r1); \ 159 std %r19, FRAME_19+48(%r1); \ 160 std %r20, FRAME_20+48(%r1); \ 161 std %r21, FRAME_21+48(%r1); \ 162 std %r22, FRAME_22+48(%r1); \ 163 std %r23, FRAME_23+48(%r1); \ 164 std %r24, FRAME_24+48(%r1); \ 165 std %r25, FRAME_25+48(%r1); \ 166 std %r26, FRAME_26+48(%r1); \ 167 std %r27, FRAME_27+48(%r1); \ 168 std %r28, FRAME_28+48(%r1); \ 169 std %r29, FRAME_29+48(%r1); \ 170 std %r30, FRAME_30+48(%r1); \ 171 std %r31, FRAME_31+48(%r1); \ 172 ld %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \ 173 ld %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\ 174 ld %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \ 175 ld %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \ 176 mfxer %r3; \ 177 mfctr %r4; \ 178 mfsprg3 %r5; \ 179 std %r3, FRAME_XER+48(1); /* save xer/ctr/exc */ \ 180 std %r4, FRAME_CTR+48(1); \ 181 std %r5, FRAME_EXC+48(1); \ 182 std %r28,FRAME_AIM_DAR+48(1); \ 183 std %r29,FRAME_AIM_DSISR+48(1); /* save dsisr/srr0/srr1 */ \ 184 std %r30,FRAME_SRR0+48(1); \ 185 std %r31,FRAME_SRR1+48(1); \ 186 ld %r13,PC_CURTHREAD(%r2) /* set kernel curthread */ 187 188 #define FRAME_LEAVE(savearea) \ 189 /* Disable exceptions: */ \ 190 mfmsr %r2; \ 191 andi. %r2,%r2,~PSL_EE@l; \ 192 mtmsr %r2; \ 193 isync; \ 194 /* Now restore regs: */ \ 195 ld %r2,FRAME_SRR0+48(%r1); \ 196 ld %r3,FRAME_SRR1+48(%r1); \ 197 ld %r4,FRAME_CTR+48(%r1); \ 198 ld %r5,FRAME_XER+48(%r1); \ 199 ld %r6,FRAME_LR+48(%r1); \ 200 GET_CPUINFO(%r7); \ 201 std %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \ 202 std %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \ 203 ld %r7,FRAME_CR+48(%r1); \ 204 mtctr %r4; \ 205 mtxer %r5; \ 206 mtlr %r6; \ 207 mtsprg2 %r7; /* save cr */ \ 208 ld %r31,FRAME_31+48(%r1); /* restore r0-31 */ \ 209 ld %r30,FRAME_30+48(%r1); \ 210 ld %r29,FRAME_29+48(%r1); \ 211 ld %r28,FRAME_28+48(%r1); \ 212 ld %r27,FRAME_27+48(%r1); \ 213 ld %r26,FRAME_26+48(%r1); \ 214 ld %r25,FRAME_25+48(%r1); \ 215 ld %r24,FRAME_24+48(%r1); \ 216 ld %r23,FRAME_23+48(%r1); \ 217 ld %r22,FRAME_22+48(%r1); \ 218 ld %r21,FRAME_21+48(%r1); \ 219 ld %r20,FRAME_20+48(%r1); \ 220 ld %r19,FRAME_19+48(%r1); \ 221 ld %r18,FRAME_18+48(%r1); \ 222 ld %r17,FRAME_17+48(%r1); \ 223 ld %r16,FRAME_16+48(%r1); \ 224 ld %r15,FRAME_15+48(%r1); \ 225 ld %r14,FRAME_14+48(%r1); \ 226 ld %r13,FRAME_13+48(%r1); \ 227 ld %r12,FRAME_12+48(%r1); \ 228 ld %r11,FRAME_11+48(%r1); \ 229 ld %r10,FRAME_10+48(%r1); \ 230 ld %r9, FRAME_9+48(%r1); \ 231 ld %r8, FRAME_8+48(%r1); \ 232 ld %r7, FRAME_7+48(%r1); \ 233 ld %r6, FRAME_6+48(%r1); \ 234 ld %r5, FRAME_5+48(%r1); \ 235 ld %r4, FRAME_4+48(%r1); \ 236 ld %r3, FRAME_3+48(%r1); \ 237 ld %r2, FRAME_2+48(%r1); \ 238 ld %r0, FRAME_0+48(%r1); \ 239 ld %r1, FRAME_1+48(%r1); \ 240 /* Can't touch %r1 from here on */ \ 241 mtsprg3 %r3; /* save r3 */ \ 242 /* Disable translation, machine check and recoverability: */ \ 243 mfmsr %r3; \ 244 andi. %r3,%r3,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \ 245 mtmsr %r3; \ 246 isync; \ 247 /* Decide whether we return to user mode: */ \ 248 GET_CPUINFO(%r3); \ 249 ld %r3,(savearea+CPUSAVE_SRR1)(%r3); \ 250 mtcr %r3; \ 251 bf 17,1f; /* branch if PSL_PR is false */ \ 252 /* Restore user SRs */ \ 253 GET_CPUINFO(%r3); \ 254 std %r27,(savearea+CPUSAVE_R27)(%r3); \ 255 std %r28,(savearea+CPUSAVE_R28)(%r3); \ 256 std %r29,(savearea+CPUSAVE_R29)(%r3); \ 257 std %r30,(savearea+CPUSAVE_R30)(%r3); \ 258 std %r31,(savearea+CPUSAVE_R31)(%r3); \ 259 mflr %r27; /* preserve LR */ \ 260 bl restore_usersrs; /* uses r28-r31 */ \ 261 mtlr %r27; \ 262 ld %r31,(savearea+CPUSAVE_R31)(%r3); \ 263 ld %r30,(savearea+CPUSAVE_R30)(%r3); \ 264 ld %r29,(savearea+CPUSAVE_R29)(%r3); \ 265 ld %r28,(savearea+CPUSAVE_R28)(%r3); \ 266 ld %r27,(savearea+CPUSAVE_R27)(%r3); \ 267 1: mfsprg2 %r3; /* restore cr */ \ 268 mtcr %r3; \ 269 GET_CPUINFO(%r3); \ 270 ld %r3,(savearea+CPUSAVE_SRR0)(%r3); /* restore srr0 */ \ 271 mtsrr0 %r3; \ 272 GET_CPUINFO(%r3); \ 273 ld %r3,(savearea+CPUSAVE_SRR1)(%r3); /* restore srr1 */ \ 274 mtsrr1 %r3; \ 275 mfsprg3 %r3 /* restore r3 */ 276 277 #ifdef SMP 278 /* 279 * Processor reset exception handler. These are typically 280 * the first instructions the processor executes after a 281 * software reset. We do this in two bits so that we are 282 * not still hanging around in the trap handling region 283 * once the MMU is turned on. 284 */ 285 .globl CNAME(rstcode), CNAME(rstsize) 286 CNAME(rstcode): 287 /* Explicitly set MSR[SF] */ 288 mfmsr %r9 289 li %r8,1 290 insrdi %r9,%r8,1,0 291 mtmsrd %r9 292 isync 293 294 ba cpu_reset 295 CNAME(rstsize) = . - CNAME(rstcode) 296 297 cpu_reset: 298 lis %r1,(tmpstk+TMPSTKSZ-48)@ha /* get new SP */ 299 addi %r1,%r1,(tmpstk+TMPSTKSZ-48)@l 300 301 lis %r3,tocbase@ha 302 ld %r2,tocbase@l(%r3) 303 lis %r3,1@l 304 bl CNAME(cpudep_ap_early_bootstrap) /* Set PCPU */ 305 nop 306 bl CNAME(pmap_cpu_bootstrap) /* Turn on virtual memory */ 307 nop 308 bl CNAME(cpudep_ap_bootstrap) /* Set up PCPU and stack */ 309 nop 310 mr %r1,%r3 /* Use new stack */ 311 bl CNAME(machdep_ap_bootstrap) /* And away! */ 312 nop 313 314 /* Should not be reached */ 315 9: 316 b 9b 317 #endif 318 319 /* 320 * This code gets copied to all the trap vectors 321 * (except ISI/DSI, ALI, and the interrupts) 322 */ 323 324 .globl CNAME(trapcode),CNAME(trapsize) 325 CNAME(trapcode): 326 mtsprg1 %r1 /* save SP */ 327 mflr %r1 /* Save the old LR in r1 */ 328 mtsprg2 %r1 /* And then in SPRG2 */ 329 li %r1, 0xA0 /* How to get the vector from LR */ 330 bla generictrap /* LR & SPRG3 is exception # */ 331 CNAME(trapsize) = .-CNAME(trapcode) 332 333 /* 334 * For SLB misses: do special things for the kernel 335 * 336 * Note: SPRG1 is always safe to overwrite any time the MMU is on, which is 337 * the only time this can be called. 338 */ 339 .globl CNAME(slbtrap),CNAME(slbtrapsize) 340 CNAME(slbtrap): 341 mtsprg1 %r1 /* save SP */ 342 GET_CPUINFO(%r1) 343 std %r2,(PC_SLBSAVE+16)(%r1) 344 mfcr %r2 /* save CR */ 345 std %r2,(PC_SLBSAVE+104)(%r1) 346 mfsrr1 %r2 /* test kernel mode */ 347 mtcr %r2 348 bf 17,1f /* branch if PSL_PR is false */ 349 /* User mode */ 350 ld %r2,(PC_SLBSAVE+104)(%r1) /* Restore CR */ 351 mtcr %r2 352 ld %r2,(PC_SLBSAVE+16)(%r1) /* Restore R2 */ 353 mflr %r1 /* Save the old LR in r1 */ 354 mtsprg2 %r1 /* And then in SPRG2 */ 355 li %r1, 0x80 /* How to get the vector from LR */ 356 bla generictrap /* LR & SPRG3 is exception # */ 357 1: mflr %r2 /* Save the old LR in r2 */ 358 bla kern_slbtrap 359 CNAME(slbtrapsize) = .-CNAME(slbtrap) 360 361 kern_slbtrap: 362 std %r2,(PC_SLBSAVE+136)(%r1) /* old LR */ 363 std %r3,(PC_SLBSAVE+24)(%r1) /* save R3 */ 364 365 /* Check if this needs to be handled as a regular trap (userseg miss) */ 366 mflr %r2 367 andi. %r2,%r2,0xff80 368 cmpwi %r2,0x380 369 bne 1f 370 mfdar %r2 371 b 2f 372 1: mfsrr0 %r2 373 2: /* r2 now contains the fault address */ 374 lis %r3,SEGMENT_MASK@highesta 375 ori %r3,%r3,SEGMENT_MASK@highera 376 sldi %r3,%r3,32 377 oris %r3,%r3,SEGMENT_MASK@ha 378 ori %r3,%r3,SEGMENT_MASK@l 379 and %r2,%r2,%r3 /* R2 = segment base address */ 380 lis %r3,USER_ADDR@highesta 381 ori %r3,%r3,USER_ADDR@highera 382 sldi %r3,%r3,32 383 oris %r3,%r3,USER_ADDR@ha 384 ori %r3,%r3,USER_ADDR@l 385 cmpd %r2,%r3 /* Compare fault base to USER_ADDR */ 386 bne 3f 387 388 /* User seg miss, handle as a regular trap */ 389 ld %r2,(PC_SLBSAVE+104)(%r1) /* Restore CR */ 390 mtcr %r2 391 ld %r2,(PC_SLBSAVE+16)(%r1) /* Restore R2,R3 */ 392 ld %r3,(PC_SLBSAVE+24)(%r1) 393 ld %r1,(PC_SLBSAVE+136)(%r1) /* Save the old LR in r1 */ 394 mtsprg2 %r1 /* And then in SPRG2 */ 395 li %r1, 0x80 /* How to get the vector from LR */ 396 b generictrap /* Retain old LR using b */ 397 398 3: /* Real kernel SLB miss */ 399 std %r0,(PC_SLBSAVE+0)(%r1) /* free all volatile regs */ 400 mfsprg1 %r2 /* Old R1 */ 401 std %r2,(PC_SLBSAVE+8)(%r1) 402 /* R2,R3 already saved */ 403 std %r4,(PC_SLBSAVE+32)(%r1) 404 std %r5,(PC_SLBSAVE+40)(%r1) 405 std %r6,(PC_SLBSAVE+48)(%r1) 406 std %r7,(PC_SLBSAVE+56)(%r1) 407 std %r8,(PC_SLBSAVE+64)(%r1) 408 std %r9,(PC_SLBSAVE+72)(%r1) 409 std %r10,(PC_SLBSAVE+80)(%r1) 410 std %r11,(PC_SLBSAVE+88)(%r1) 411 std %r12,(PC_SLBSAVE+96)(%r1) 412 /* CR already saved */ 413 mfxer %r2 /* save XER */ 414 std %r2,(PC_SLBSAVE+112)(%r1) 415 mflr %r2 /* save LR (SP already saved) */ 416 std %r2,(PC_SLBSAVE+120)(%r1) 417 mfctr %r2 /* save CTR */ 418 std %r2,(PC_SLBSAVE+128)(%r1) 419 420 /* Call handler */ 421 addi %r1,%r1,PC_SLBSTACK-48+1024 422 li %r2,~15 423 and %r1,%r1,%r2 424 lis %r3,tocbase@ha 425 ld %r2,tocbase@l(%r3) 426 mflr %r3 427 andi. %r3,%r3,0xff80 428 mfdar %r4 429 mfsrr0 %r5 430 bl handle_kernel_slb_spill 431 nop 432 433 /* Save r28-31, restore r4-r12 */ 434 GET_CPUINFO(%r1) 435 ld %r4,(PC_SLBSAVE+32)(%r1) 436 ld %r5,(PC_SLBSAVE+40)(%r1) 437 ld %r6,(PC_SLBSAVE+48)(%r1) 438 ld %r7,(PC_SLBSAVE+56)(%r1) 439 ld %r8,(PC_SLBSAVE+64)(%r1) 440 ld %r9,(PC_SLBSAVE+72)(%r1) 441 ld %r10,(PC_SLBSAVE+80)(%r1) 442 ld %r11,(PC_SLBSAVE+88)(%r1) 443 ld %r12,(PC_SLBSAVE+96)(%r1) 444 std %r28,(PC_SLBSAVE+64)(%r1) 445 std %r29,(PC_SLBSAVE+72)(%r1) 446 std %r30,(PC_SLBSAVE+80)(%r1) 447 std %r31,(PC_SLBSAVE+88)(%r1) 448 449 /* Restore kernel mapping */ 450 bl restore_kernsrs 451 452 /* Restore remaining registers */ 453 ld %r28,(PC_SLBSAVE+64)(%r1) 454 ld %r29,(PC_SLBSAVE+72)(%r1) 455 ld %r30,(PC_SLBSAVE+80)(%r1) 456 ld %r31,(PC_SLBSAVE+88)(%r1) 457 458 ld %r2,(PC_SLBSAVE+104)(%r1) 459 mtcr %r2 460 ld %r2,(PC_SLBSAVE+112)(%r1) 461 mtxer %r2 462 ld %r2,(PC_SLBSAVE+120)(%r1) 463 mtlr %r2 464 ld %r2,(PC_SLBSAVE+128)(%r1) 465 mtctr %r2 466 ld %r2,(PC_SLBSAVE+136)(%r1) 467 mtlr %r2 468 469 /* Restore r0-r3 */ 470 ld %r0,(PC_SLBSAVE+0)(%r1) 471 ld %r2,(PC_SLBSAVE+16)(%r1) 472 ld %r3,(PC_SLBSAVE+24)(%r1) 473 mfsprg1 %r1 474 475 /* Back to whatever we were doing */ 476 rfid 477 478 /* 479 * For ALI: has to save DSISR and DAR 480 */ 481 .globl CNAME(alitrap),CNAME(alisize) 482 CNAME(alitrap): 483 mtsprg1 %r1 /* save SP */ 484 GET_CPUINFO(%r1) 485 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */ 486 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 487 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 488 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 489 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 490 mfdar %r30 491 mfdsisr %r31 492 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 493 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 494 mfsprg1 %r1 /* restore SP, in case of branch */ 495 mflr %r28 /* save LR */ 496 mfcr %r29 /* save CR */ 497 498 /* Put our exception vector in SPRG3 */ 499 li %r31, EXC_ALI 500 mtsprg3 %r31 501 502 /* Test whether we already had PR set */ 503 mfsrr1 %r31 504 mtcr %r31 505 bla s_trap 506 CNAME(alisize) = .-CNAME(alitrap) 507 508 /* 509 * Similar to the above for DSI 510 * Has to handle BAT spills 511 * and standard pagetable spills 512 */ 513 .globl CNAME(dsitrap),CNAME(dsisize) 514 CNAME(dsitrap): 515 mtsprg1 %r1 /* save SP */ 516 GET_CPUINFO(%r1) 517 std %r27,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */ 518 std %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) 519 std %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 520 std %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 521 std %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 522 mfsprg1 %r1 /* restore SP */ 523 mfcr %r29 /* save CR */ 524 mfxer %r30 /* save XER */ 525 mtsprg2 %r30 /* in SPRG2 */ 526 mfsrr1 %r31 /* test kernel mode */ 527 mtcr %r31 528 mflr %r28 /* save LR (SP already saved) */ 529 bla disitrap 530 CNAME(dsisize) = .-CNAME(dsitrap) 531 532 /* 533 * Preamble code for DSI/ISI traps 534 */ 535 disitrap: 536 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 537 mflr %r1 538 andi. %r1,%r1,0xff00 539 mtsprg3 %r1 540 541 GET_CPUINFO(%r1) 542 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1) 543 std %r31,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) 544 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) 545 std %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 546 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) 547 std %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 548 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 549 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 550 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 551 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 552 mfdar %r30 553 mfdsisr %r31 554 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 555 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 556 557 #ifdef KDB 558 /* Try and detect a kernel stack overflow */ 559 mfsrr1 %r31 560 mtcr %r31 561 bt 17,realtrap /* branch is user mode */ 562 mfsprg1 %r31 /* get old SP */ 563 sub. %r30,%r31,%r30 /* SP - DAR */ 564 bge 1f 565 neg %r30,%r30 /* modulo value */ 566 1: cmpldi %cr0,%r30,4096 /* is DAR within a page of SP? */ 567 bge %cr0,realtrap /* no, too far away. */ 568 569 /* Now convert this DSI into a DDB trap. */ 570 GET_CPUINFO(%r1) 571 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */ 572 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */ 573 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */ 574 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */ 575 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* get r27 */ 576 std %r31,(PC_DBSAVE +CPUSAVE_R27)(%r1) /* save r27 */ 577 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */ 578 std %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */ 579 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */ 580 std %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */ 581 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */ 582 std %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */ 583 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */ 584 std %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */ 585 b dbtrap 586 #endif 587 588 /* XXX need stack probe here */ 589 realtrap: 590 /* Test whether we already had PR set */ 591 mfsrr1 %r1 592 mtcr %r1 593 mfsprg1 %r1 /* restore SP (might have been 594 overwritten) */ 595 bf 17,k_trap /* branch if PSL_PR is false */ 596 GET_CPUINFO(%r1) 597 ld %r1,PC_CURPCB(%r1) 598 mr %r27,%r28 /* Save LR, r29 */ 599 mtsprg2 %r29 600 bl restore_kernsrs /* enable kernel mapping */ 601 mfsprg2 %r29 602 mr %r28,%r27 603 ba s_trap 604 605 /* 606 * generictrap does some standard setup for trap handling to minimize 607 * the code that need be installed in the actual vectors. It expects 608 * the following conditions. 609 * 610 * R1 - Trap vector = LR & (0xff00 | R1) 611 * SPRG1 - Original R1 contents 612 * SPRG2 - Original LR 613 */ 614 615 generictrap: 616 /* Save R1 for computing the exception vector */ 617 mtsprg3 %r1 618 619 /* Save interesting registers */ 620 GET_CPUINFO(%r1) 621 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */ 622 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 623 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 624 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 625 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 626 mfdar %r30 627 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 628 mfsprg1 %r1 /* restore SP, in case of branch */ 629 mfsprg2 %r28 /* save LR */ 630 mfcr %r29 /* save CR */ 631 632 /* Compute the exception vector from the link register */ 633 mfsprg3 %r31 634 ori %r31,%r31,0xff00 635 mflr %r30 636 and %r30,%r30,%r31 637 mtsprg3 %r30 638 639 /* Test whether we already had PR set */ 640 mfsrr1 %r31 641 mtcr %r31 642 643 s_trap: 644 bf 17,k_trap /* branch if PSL_PR is false */ 645 GET_CPUINFO(%r1) 646 u_trap: 647 ld %r1,PC_CURPCB(%r1) 648 mr %r27,%r28 /* Save LR, r29 */ 649 mtsprg2 %r29 650 bl restore_kernsrs /* enable kernel mapping */ 651 mfsprg2 %r29 652 mr %r28,%r27 653 654 /* 655 * Now the common trap catching code. 656 */ 657 k_trap: 658 FRAME_SETUP(PC_TEMPSAVE) 659 /* Call C interrupt dispatcher: */ 660 trapagain: 661 lis %r3,tocbase@ha 662 ld %r2,tocbase@l(%r3) 663 addi %r3,%r1,48 664 bl CNAME(powerpc_interrupt) 665 nop 666 667 .globl CNAME(trapexit) /* backtrace code sentinel */ 668 CNAME(trapexit): 669 /* Disable interrupts: */ 670 mfmsr %r3 671 andi. %r3,%r3,~PSL_EE@l 672 mtmsr %r3 673 isync 674 /* Test AST pending: */ 675 ld %r5,FRAME_SRR1+48(%r1) 676 mtcr %r5 677 bf 17,1f /* branch if PSL_PR is false */ 678 679 GET_CPUINFO(%r3) /* get per-CPU pointer */ 680 lwz %r4, TD_FLAGS(%r13) /* get thread flags value */ 681 lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h 682 ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l 683 and. %r4,%r4,%r5 684 beq 1f 685 mfmsr %r3 /* re-enable interrupts */ 686 ori %r3,%r3,PSL_EE@l 687 mtmsr %r3 688 isync 689 lis %r3,tocbase@ha 690 ld %r2,tocbase@l(%r3) 691 addi %r3,%r1,48 692 bl CNAME(ast) 693 nop 694 .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */ 695 CNAME(asttrapexit): 696 b trapexit /* test ast ret value ? */ 697 1: 698 FRAME_LEAVE(PC_TEMPSAVE) 699 rfid 700 701 #if defined(KDB) 702 /* 703 * Deliberate entry to dbtrap 704 */ 705 ASENTRY_NOPROF(breakpoint) 706 mtsprg1 %r1 707 mfmsr %r3 708 mtsrr1 %r3 709 andi. %r3,%r3,~(PSL_EE|PSL_ME)@l 710 mtmsr %r3 /* disable interrupts */ 711 isync 712 GET_CPUINFO(%r3) 713 std %r27,(PC_DBSAVE+CPUSAVE_R27)(%r3) 714 std %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3) 715 std %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3) 716 std %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3) 717 std %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3) 718 mflr %r28 719 li %r29,EXC_BPT 720 mtlr %r29 721 mfcr %r29 722 mtsrr0 %r28 723 724 /* 725 * Now the kdb trap catching code. 726 */ 727 dbtrap: 728 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 729 mflr %r1 730 andi. %r1,%r1,0xff00 731 mtsprg3 %r1 732 733 lis %r1,(tmpstk+TMPSTKSZ-48)@ha /* get new SP */ 734 addi %r1,%r1,(tmpstk+TMPSTKSZ-48)@l 735 736 FRAME_SETUP(PC_DBSAVE) 737 /* Call C trap code: */ 738 lis %r3,tocbase@ha 739 ld %r2,tocbase@l(%r3) 740 addi %r3,%r1,48 741 bl CNAME(db_trap_glue) 742 nop 743 or. %r3,%r3,%r3 744 bne dbleave 745 /* This wasn't for KDB, so switch to real trap: */ 746 ld %r3,FRAME_EXC+48(%r1) /* save exception */ 747 GET_CPUINFO(%r4) 748 std %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4) 749 FRAME_LEAVE(PC_DBSAVE) 750 mtsprg1 %r1 /* prepare for entrance to realtrap */ 751 GET_CPUINFO(%r1) 752 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) 753 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 754 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 755 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 756 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 757 mflr %r28 758 mfcr %r29 759 ld %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) 760 mtsprg3 %r31 /* SPRG3 was clobbered by FRAME_LEAVE */ 761 mfsprg1 %r1 762 b realtrap 763 dbleave: 764 FRAME_LEAVE(PC_DBSAVE) 765 rfid 766 767 /* 768 * In case of KDB we want a separate trap catcher for it 769 */ 770 .globl CNAME(dblow),CNAME(dbsize) 771 CNAME(dblow): 772 mtsprg1 %r1 /* save SP */ 773 mtsprg2 %r29 /* save r29 */ 774 mfcr %r29 /* save CR in r29 */ 775 mfsrr1 %r1 776 mtcr %r1 777 bf 17,1f /* branch if privileged */ 778 779 /* Unprivileged case */ 780 mtcr %r29 /* put the condition register back */ 781 mfsprg2 %r29 /* ... and r29 */ 782 mflr %r1 /* save LR */ 783 mtsprg2 %r1 /* And then in SPRG2 */ 784 li %r1, 0 /* How to get the vector from LR */ 785 786 bla generictrap /* and we look like a generic trap */ 787 1: 788 /* Privileged, so drop to KDB */ 789 GET_CPUINFO(%r1) 790 std %r27,(PC_DBSAVE+CPUSAVE_R27)(%r1) /* free r27 */ 791 std %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */ 792 mfsprg2 %r28 /* r29 holds cr... */ 793 std %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */ 794 std %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */ 795 std %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */ 796 mflr %r28 /* save LR */ 797 bla dbtrap 798 CNAME(dbsize) = .-CNAME(dblow) 799 #endif /* KDB */
Cache object: 5425d62255776eec8463392c4d7ff868
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