1 /*-
2 * Copyright (C) 2006-2012 Semihalf
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
19 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
20 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
21 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
22 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
23 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25 /*-
26 * Copyright (C) 2001 Benno Rice
27 * All rights reserved.
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
31 * are met:
32 * 1. Redistributions of source code must retain the above copyright
33 * notice, this list of conditions and the following disclaimer.
34 * 2. Redistributions in binary form must reproduce the above copyright
35 * notice, this list of conditions and the following disclaimer in the
36 * documentation and/or other materials provided with the distribution.
37 *
38 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
39 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
40 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
41 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
43 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
44 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
45 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
46 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
47 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 * $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $
49 */
50 /*-
51 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
52 * Copyright (C) 1995, 1996 TooLs GmbH.
53 * All rights reserved.
54 *
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
57 * are met:
58 * 1. Redistributions of source code must retain the above copyright
59 * notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 * notice, this list of conditions and the following disclaimer in the
62 * documentation and/or other materials provided with the distribution.
63 * 3. All advertising materials mentioning features or use of this software
64 * must display the following acknowledgement:
65 * This product includes software developed by TooLs GmbH.
66 * 4. The name of TooLs GmbH may not be used to endorse or promote products
67 * derived from this software without specific prior written permission.
68 *
69 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
72 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
73 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
74 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
75 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
76 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
77 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
78 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
79 */
80
81 #include <sys/cdefs.h>
82 __FBSDID("$FreeBSD$");
83
84 #include "opt_ddb.h"
85 #include "opt_hwpmc_hooks.h"
86 #include "opt_kstack_pages.h"
87 #include "opt_platform.h"
88
89 #include <sys/cdefs.h>
90 #include <sys/types.h>
91 #include <sys/param.h>
92 #include <sys/proc.h>
93 #include <sys/systm.h>
94 #include <sys/time.h>
95 #include <sys/bio.h>
96 #include <sys/buf.h>
97 #include <sys/bus.h>
98 #include <sys/cons.h>
99 #include <sys/cpu.h>
100 #include <sys/kdb.h>
101 #include <sys/kernel.h>
102 #include <sys/lock.h>
103 #include <sys/mutex.h>
104 #include <sys/rwlock.h>
105 #include <sys/sysctl.h>
106 #include <sys/exec.h>
107 #include <sys/ktr.h>
108 #include <sys/syscallsubr.h>
109 #include <sys/sysproto.h>
110 #include <sys/signalvar.h>
111 #include <sys/sysent.h>
112 #include <sys/imgact.h>
113 #include <sys/msgbuf.h>
114 #include <sys/ptrace.h>
115
116 #include <vm/vm.h>
117 #include <vm/pmap.h>
118 #include <vm/vm_extern.h>
119 #include <vm/vm_page.h>
120 #include <vm/vm_object.h>
121 #include <vm/vm_pager.h>
122
123 #include <machine/cpu.h>
124 #include <machine/kdb.h>
125 #include <machine/vmparam.h>
126 #include <machine/spr.h>
127 #include <machine/hid.h>
128 #include <machine/psl.h>
129 #include <machine/trap.h>
130 #include <machine/md_var.h>
131 #include <machine/mmuvar.h>
132 #include <machine/sigframe.h>
133 #include <machine/machdep.h>
134 #include <machine/metadata.h>
135 #include <machine/platform.h>
136
137 #include <sys/linker.h>
138 #include <sys/reboot.h>
139
140 #include <contrib/libfdt/libfdt.h>
141 #include <dev/fdt/fdt_common.h>
142 #include <dev/ofw/openfirm.h>
143
144 #ifdef DDB
145 #include <ddb/ddb.h>
146 #endif
147
148 #ifdef DEBUG
149 #define debugf(fmt, args...) printf(fmt, ##args)
150 #else
151 #define debugf(fmt, args...)
152 #endif
153
154 extern unsigned char _etext[];
155 extern unsigned char _edata[];
156 extern unsigned char __bss_start[];
157 extern unsigned char __sbss_start[];
158 extern unsigned char __sbss_end[];
159 extern unsigned char _end[];
160 extern vm_offset_t __endkernel;
161 extern vm_paddr_t kernload;
162
163 /*
164 * Bootinfo is passed to us by legacy loaders. Save the address of the
165 * structure to handle backward compatibility.
166 */
167 uint32_t *bootinfo;
168
169 void print_kernel_section_addr(void);
170 void print_kenv(void);
171 uintptr_t booke_init(u_long, u_long);
172 void ivor_setup(void);
173
174 extern void *interrupt_vector_base;
175 extern void *int_critical_input;
176 extern void *int_machine_check;
177 extern void *int_data_storage;
178 extern void *int_instr_storage;
179 extern void *int_external_input;
180 extern void *int_alignment;
181 extern void *int_fpu;
182 extern void *int_program;
183 extern void *int_syscall;
184 extern void *int_decrementer;
185 extern void *int_fixed_interval_timer;
186 extern void *int_watchdog;
187 extern void *int_data_tlb_error;
188 extern void *int_inst_tlb_error;
189 extern void *int_debug;
190 extern void *int_debug_ed;
191 extern void *int_vec;
192 extern void *int_vecast;
193 #ifdef __SPE__
194 extern void *int_spe_fpdata;
195 extern void *int_spe_fpround;
196 #endif
197 #ifdef HWPMC_HOOKS
198 extern void *int_performance_counter;
199 #endif
200
201 #define SET_TRAP(ivor, handler) \
202 KASSERT(((uintptr_t)(&handler) & ~0xffffUL) == \
203 ((uintptr_t)(&interrupt_vector_base) & ~0xffffUL), \
204 ("Handler " #handler " too far from interrupt vector base")); \
205 mtspr(ivor, (uintptr_t)(&handler) & 0xffffUL);
206
207 uintptr_t powerpc_init(vm_offset_t fdt, vm_offset_t, vm_offset_t, void *mdp,
208 uint32_t mdp_cookie);
209 void booke_cpu_init(void);
210
211 void
212 booke_cpu_init(void)
213 {
214
215 cpu_features |= PPC_FEATURE_BOOKE;
216
217 psl_kernset = PSL_CE | PSL_ME | PSL_EE;
218 #ifdef __powerpc64__
219 psl_kernset |= PSL_CM;
220 #endif
221 psl_userset = psl_kernset | PSL_PR;
222 #ifdef __powerpc64__
223 psl_userset32 = psl_userset & ~PSL_CM;
224 #endif
225 /*
226 * Zeroed bits in this variable signify that the value of the bit
227 * in its position is allowed to vary between userspace contexts.
228 *
229 * All other bits are required to be identical for every userspace
230 * context. The actual *value* of the bit is determined by
231 * psl_userset and/or psl_userset32, and is not allowed to change.
232 *
233 * Remember to update this set when implementing support for
234 * *conditionally* enabling a processor facility. Failing to do
235 * this will cause swapcontext() in userspace to break when a
236 * process uses a conditionally-enabled facility.
237 *
238 * When *unconditionally* implementing support for a processor
239 * facility, update psl_userset / psl_userset32 instead.
240 *
241 * See the access control check in set_mcontext().
242 */
243 psl_userstatic = ~(PSL_VEC | PSL_FP | PSL_FE0 | PSL_FE1);
244
245 pmap_mmu_install(MMU_TYPE_BOOKE, BUS_PROBE_GENERIC);
246 }
247
248 void
249 ivor_setup(void)
250 {
251
252 mtspr(SPR_IVPR, ((uintptr_t)&interrupt_vector_base) & ~0xffffUL);
253
254 SET_TRAP(SPR_IVOR0, int_critical_input);
255 SET_TRAP(SPR_IVOR1, int_machine_check);
256 SET_TRAP(SPR_IVOR2, int_data_storage);
257 SET_TRAP(SPR_IVOR3, int_instr_storage);
258 SET_TRAP(SPR_IVOR4, int_external_input);
259 SET_TRAP(SPR_IVOR5, int_alignment);
260 SET_TRAP(SPR_IVOR6, int_program);
261 SET_TRAP(SPR_IVOR8, int_syscall);
262 SET_TRAP(SPR_IVOR10, int_decrementer);
263 SET_TRAP(SPR_IVOR11, int_fixed_interval_timer);
264 SET_TRAP(SPR_IVOR12, int_watchdog);
265 SET_TRAP(SPR_IVOR13, int_data_tlb_error);
266 SET_TRAP(SPR_IVOR14, int_inst_tlb_error);
267 SET_TRAP(SPR_IVOR15, int_debug);
268 #ifdef HWPMC_HOOKS
269 SET_TRAP(SPR_IVOR35, int_performance_counter);
270 #endif
271 switch ((mfpvr() >> 16) & 0xffff) {
272 case FSL_E6500:
273 SET_TRAP(SPR_IVOR32, int_vec);
274 SET_TRAP(SPR_IVOR33, int_vecast);
275 /* FALLTHROUGH */
276 case FSL_E500mc:
277 case FSL_E5500:
278 SET_TRAP(SPR_IVOR7, int_fpu);
279 SET_TRAP(SPR_IVOR15, int_debug_ed);
280 break;
281 case FSL_E500v1:
282 case FSL_E500v2:
283 SET_TRAP(SPR_IVOR32, int_vec);
284 #ifdef __SPE__
285 SET_TRAP(SPR_IVOR33, int_spe_fpdata);
286 SET_TRAP(SPR_IVOR34, int_spe_fpround);
287 #endif
288 break;
289 }
290
291 #ifdef __powerpc64__
292 /* Set 64-bit interrupt mode. */
293 mtspr(SPR_EPCR, mfspr(SPR_EPCR) | EPCR_ICM);
294 #endif
295 }
296
297 static int
298 booke_check_for_fdt(uint32_t arg1, vm_offset_t *dtbp)
299 {
300 void *ptr;
301 int fdt_size;
302
303 if (arg1 % 8 != 0)
304 return (-1);
305
306 ptr = (void *)pmap_early_io_map(arg1, PAGE_SIZE);
307 if (fdt_check_header(ptr) != 0)
308 return (-1);
309
310 /*
311 * Read FDT total size from the header of FDT.
312 * This for sure hits within first page which is
313 * already mapped.
314 */
315 fdt_size = fdt_totalsize((void *)ptr);
316
317 /*
318 * Ok, arg1 points to FDT, so we need to map it in.
319 * First, unmap this page and then map FDT again with full size
320 */
321 pmap_early_io_unmap((vm_offset_t)ptr, PAGE_SIZE);
322 ptr = (void *)pmap_early_io_map(arg1, fdt_size);
323 *dtbp = (vm_offset_t)ptr;
324
325 return (0);
326 }
327
328 uintptr_t
329 booke_init(u_long arg1, u_long arg2)
330 {
331 uintptr_t ret;
332 void *mdp;
333 vm_offset_t dtbp, end;
334
335 end = (uintptr_t)_end;
336 dtbp = (vm_offset_t)NULL;
337
338 /* Set up TLB initially */
339 bootinfo = NULL;
340 bzero(__sbss_start, __sbss_end - __sbss_start);
341 bzero(__bss_start, _end - __bss_start);
342 tlb1_init();
343
344 /*
345 * Handle the various ways we can get loaded and started:
346 * - FreeBSD's loader passes the pointer to the metadata
347 * in arg1, with arg2 undefined. arg1 has a value that's
348 * relative to the kernel's link address (i.e. larger
349 * than 0xc0000000).
350 * - Juniper's loader passes the metadata pointer in arg2
351 * and sets arg1 to zero. This is to signal that the
352 * loader maps the kernel and starts it at its link
353 * address (unlike the FreeBSD loader).
354 * - U-Boot passes the standard argc and argv parameters
355 * in arg1 and arg2 (resp). arg1 is between 1 and some
356 * relatively small number, such as 64K. arg2 is the
357 * physical address of the argv vector.
358 * - ePAPR loaders pass an FDT blob in r3 (arg1) and the magic hex
359 * string 0x45504150 ('EPAP') in r6 (which has been lost by now).
360 * r4 (arg2) is supposed to be set to zero, but is not always.
361 */
362
363 if (arg1 == 0) /* Juniper loader */
364 mdp = (void *)arg2;
365 else if (booke_check_for_fdt(arg1, &dtbp) == 0) { /* ePAPR */
366 end = roundup(end, 8);
367 memmove((void *)end, (void *)dtbp, fdt_totalsize((void *)dtbp));
368 dtbp = end;
369 end += fdt_totalsize((void *)dtbp);
370 __endkernel = end;
371 mdp = NULL;
372 } else if (arg1 > (uintptr_t)kernload) /* FreeBSD loader */
373 mdp = (void *)arg1;
374 else /* U-Boot */
375 mdp = NULL;
376
377 /* Default to 32 byte cache line size. */
378 switch ((mfpvr()) >> 16) {
379 case FSL_E500mc:
380 case FSL_E5500:
381 case FSL_E6500:
382 cacheline_size = 64;
383 break;
384 }
385
386 /*
387 * Last element is a magic cookie that indicates that the metadata
388 * pointer is meaningful.
389 */
390 ret = powerpc_init(dtbp, 0, 0, mdp, (mdp == NULL) ? 0 : 0xfb5d104d);
391
392 /* Enable caches */
393 booke_enable_l1_cache();
394 booke_enable_l2_cache();
395
396 booke_enable_bpred();
397
398 return (ret);
399 }
400
401 #define RES_GRANULE cacheline_size
402 extern uintptr_t tlb0_miss_locks[];
403
404 /* Initialise a struct pcpu. */
405 void
406 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz)
407 {
408
409 pcpu->pc_booke.tid_next = TID_MIN;
410
411 #ifdef SMP
412 uintptr_t *ptr;
413 int words_per_gran = RES_GRANULE / sizeof(uintptr_t);
414
415 ptr = &tlb0_miss_locks[cpuid * words_per_gran];
416 pcpu->pc_booke.tlb_lock = ptr;
417 *ptr = TLB_UNLOCKED;
418 *(ptr + 1) = 0; /* recurse counter */
419 #endif
420 }
421
422 /* Shutdown the CPU as much as possible. */
423 void
424 cpu_halt(void)
425 {
426
427 mtmsr(mfmsr() & ~(PSL_CE | PSL_EE | PSL_ME | PSL_DE));
428 while (1)
429 ;
430 }
431
432 int
433 ptrace_single_step(struct thread *td)
434 {
435 struct trapframe *tf;
436
437 tf = td->td_frame;
438 tf->srr1 |= PSL_DE;
439 tf->cpu.booke.dbcr0 |= (DBCR0_IDM | DBCR0_IC);
440 return (0);
441 }
442
443 int
444 ptrace_clear_single_step(struct thread *td)
445 {
446 struct trapframe *tf;
447
448 tf = td->td_frame;
449 tf->srr1 &= ~PSL_DE;
450 tf->cpu.booke.dbcr0 &= ~(DBCR0_IDM | DBCR0_IC);
451 return (0);
452 }
453
454 void
455 kdb_cpu_clear_singlestep(void)
456 {
457 register_t r;
458
459 r = mfspr(SPR_DBCR0);
460 mtspr(SPR_DBCR0, r & ~DBCR0_IC);
461 kdb_frame->srr1 &= ~PSL_DE;
462 }
463
464 void
465 kdb_cpu_set_singlestep(void)
466 {
467 register_t r;
468
469 r = mfspr(SPR_DBCR0);
470 mtspr(SPR_DBCR0, r | DBCR0_IC | DBCR0_IDM);
471 kdb_frame->srr1 |= PSL_DE;
472 }
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