1 /*-
2 * Copyright (c) 2008-2009 Semihalf, Rafal Jaworowski
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: releng/10.1/sys/powerpc/booke/mp_cpudep.c 266001 2014-05-14 03:09:37Z ian $");
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
33 #include <sys/bus.h>
34 #include <sys/pcpu.h>
35 #include <sys/proc.h>
36 #include <sys/smp.h>
37
38 #include <machine/pcb.h>
39 #include <machine/psl.h>
40 #include <machine/smp.h>
41 #include <machine/spr.h>
42
43 extern void dcache_enable(void);
44 extern void dcache_inval(void);
45 extern void icache_enable(void);
46 extern void icache_inval(void);
47
48 volatile void *ap_pcpu;
49
50 uintptr_t
51 cpudep_ap_bootstrap()
52 {
53 uint32_t msr, sp, csr;
54
55 /* Enable L1 caches */
56 csr = mfspr(SPR_L1CSR0);
57 if ((csr & L1CSR0_DCE) == 0) {
58 dcache_inval();
59 dcache_enable();
60 }
61
62 csr = mfspr(SPR_L1CSR1);
63 if ((csr & L1CSR1_ICE) == 0) {
64 icache_inval();
65 icache_enable();
66 }
67
68 /* Set MSR */
69 msr = PSL_ME;
70 mtmsr(msr);
71
72 /* Assign pcpu fields, return ptr to this AP's idle thread kstack */
73 pcpup->pc_curthread = pcpup->pc_idlethread;
74 #ifdef __powerpc64__
75 __asm __volatile("mr 13,%0" :: "r"(pcpup->pc_curthread));
76 #else
77 __asm __volatile("mr 2,%0" :: "r"(pcpup->pc_curthread));
78 #endif
79 pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb;
80 sp = pcpup->pc_curpcb->pcb_sp;
81
82 /* XXX shouldn't the pcb_sp be checked/forced for alignment here?? */
83
84 return (sp);
85 }
86
87 void
88 cpudep_ap_setup()
89 {
90 }
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