The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/powerpc/cpufreq/dfs.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2009 Nathan Whitehorn
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
   21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
   22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
   23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
   24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   26  * SUCH DAMAGE.
   27  */
   28 
   29 #include <sys/cdefs.h>
   30 __FBSDID("$FreeBSD$");
   31 
   32 #include <sys/param.h>
   33 #include <sys/systm.h>
   34 #include <sys/bus.h>
   35 #include <sys/cpu.h>
   36 #include <sys/kernel.h>
   37 #include <sys/module.h>
   38 
   39 #include "cpufreq_if.h"
   40 
   41 struct dfs_softc {
   42         device_t dev;
   43         int      dfs4;
   44 };
   45 
   46 static void     dfs_identify(driver_t *driver, device_t parent);
   47 static int      dfs_probe(device_t dev);
   48 static int      dfs_attach(device_t dev);
   49 static int      dfs_settings(device_t dev, struct cf_setting *sets, int *count);
   50 static int      dfs_set(device_t dev, const struct cf_setting *set);
   51 static int      dfs_get(device_t dev, struct cf_setting *set);
   52 static int      dfs_type(device_t dev, int *type);
   53 
   54 static device_method_t dfs_methods[] = {
   55         /* Device interface */
   56         DEVMETHOD(device_identify,      dfs_identify),
   57         DEVMETHOD(device_probe,         dfs_probe),
   58         DEVMETHOD(device_attach,        dfs_attach),
   59 
   60         /* cpufreq interface */
   61         DEVMETHOD(cpufreq_drv_set,      dfs_set),
   62         DEVMETHOD(cpufreq_drv_get,      dfs_get),
   63         DEVMETHOD(cpufreq_drv_type,     dfs_type),
   64         DEVMETHOD(cpufreq_drv_settings, dfs_settings),
   65         {0, 0}
   66 };
   67 
   68 static driver_t dfs_driver = {
   69         "dfs",
   70         dfs_methods,
   71         sizeof(struct dfs_softc)
   72 };
   73 
   74 DRIVER_MODULE(dfs, cpu, dfs_driver, 0, 0);
   75 
   76 /*
   77  * Bits of the HID1 register to enable DFS. See page 2-24 of "MPC7450
   78  * RISC Microprocessor Family Reference Manual", rev. 5.
   79  */
   80 
   81 #define HID1_DFS2       (1UL << 22)
   82 #define HID1_DFS4       (1UL << 23)
   83 
   84 static void
   85 dfs_identify(driver_t *driver, device_t parent)
   86 {
   87         uint16_t vers;
   88         vers = mfpvr() >> 16;
   89 
   90         /* Check for an MPC 7447A or 7448 CPU */
   91         switch (vers) {
   92                 case MPC7447A:
   93                 case MPC7448:
   94                         break;
   95                 default:
   96                         return;
   97         }
   98 
   99         /* Make sure we're not being doubly invoked. */
  100         if (device_find_child(parent, "dfs", -1) != NULL)
  101                 return;
  102 
  103         /*
  104          * We attach a child for every CPU since settings need to
  105          * be performed on every CPU in the SMP case.
  106          */
  107         if (BUS_ADD_CHILD(parent, 10, "dfs", -1) == NULL)
  108                 device_printf(parent, "add dfs child failed\n");
  109 }
  110 
  111 static int
  112 dfs_probe(device_t dev)
  113 {
  114         if (resource_disabled("dfs", 0))
  115                 return (ENXIO);
  116 
  117         device_set_desc(dev, "Dynamic Frequency Switching");
  118         return (0);
  119 }
  120 
  121 static int
  122 dfs_attach(device_t dev)
  123 {
  124         struct dfs_softc *sc;
  125         uint16_t vers;
  126 
  127         sc = device_get_softc(dev);
  128         sc->dev = dev;
  129         sc->dfs4 = 0;
  130         vers = mfpvr() >> 16;
  131 
  132         /* The 7448 supports divide-by-four as well */
  133         if (vers == MPC7448)
  134                 sc->dfs4 = 1;
  135 
  136         cpufreq_register(dev);
  137         return (0);
  138 }
  139 
  140 static int
  141 dfs_settings(device_t dev, struct cf_setting *sets, int *count)
  142 {
  143         struct dfs_softc *sc;
  144         int states;
  145 
  146         sc = device_get_softc(dev);
  147         states = sc->dfs4 ? 3 : 2;
  148         if (sets == NULL || count == NULL)
  149                 return (EINVAL);
  150         if (*count < states)
  151                 return (E2BIG);
  152 
  153         /* Return a list of valid settings for this driver. */
  154         memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * states);
  155 
  156         sets[0].freq = 10000; sets[0].dev = dev;
  157         sets[1].freq = 5000; sets[1].dev = dev;
  158         if (sc->dfs4) {
  159                 sets[2].freq = 2500;
  160                 sets[2].dev = dev;
  161         }
  162         *count = states;
  163 
  164         return (0);
  165 }
  166 
  167 static int
  168 dfs_set(device_t dev, const struct cf_setting *set)
  169 {
  170         register_t hid1;
  171 
  172         if (set == NULL)
  173                 return (EINVAL);
  174 
  175         hid1 = mfspr(SPR_HID1);
  176         hid1 &= ~(HID1_DFS2 | HID1_DFS4);
  177 
  178         if (set->freq == 5000)
  179                 hid1 |= HID1_DFS2;
  180         else if (set->freq == 2500)
  181                 hid1 |= HID1_DFS4;
  182 
  183         /*
  184          * Now set the HID1 register with new values. Calling sequence
  185          * taken from page 2-26 of the MPC7450 family CPU manual.
  186          */
  187 
  188         powerpc_sync();
  189         mtspr(SPR_HID1, hid1);
  190         powerpc_sync(); isync();
  191 
  192         return (0);
  193 }
  194 
  195 static int
  196 dfs_get(device_t dev, struct cf_setting *set)
  197 {
  198         struct dfs_softc *sc;
  199         register_t hid1;
  200 
  201         if (set == NULL)
  202                 return (EINVAL);
  203         sc = device_get_softc(dev);
  204 
  205         memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set));
  206 
  207         hid1 = mfspr(SPR_HID1);
  208 
  209         set->freq = 10000;
  210         if (hid1 & HID1_DFS2)
  211                 set->freq = 5000;
  212         else if (sc->dfs4 && (hid1 & HID1_DFS4))
  213                 set->freq = 2500;
  214 
  215         set->dev = dev;
  216 
  217         return (0);
  218 }
  219 
  220 static int
  221 dfs_type(device_t dev, int *type)
  222 {
  223 
  224         if (type == NULL)
  225                 return (EINVAL);
  226 
  227         *type = CPUFREQ_TYPE_RELATIVE;
  228         return (0);
  229 }

Cache object: 697e408794995ab34715281a96c8a6b6


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