The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/powerpc/cpufreq/dfs.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2009 Nathan Whitehorn
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
   21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
   22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
   23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
   24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   26  * SUCH DAMAGE.
   27  */
   28 
   29 #include <sys/cdefs.h>
   30 __FBSDID("$FreeBSD$");
   31 
   32 #include <sys/param.h>
   33 #include <sys/systm.h>
   34 #include <sys/bus.h>
   35 #include <sys/cpu.h>
   36 #include <sys/kernel.h>
   37 #include <sys/module.h>
   38 
   39 #include "cpufreq_if.h"
   40 
   41 struct dfs_softc {
   42         device_t dev;
   43         int      dfs4;
   44 };
   45 
   46 static void     dfs_identify(driver_t *driver, device_t parent);
   47 static int      dfs_probe(device_t dev);
   48 static int      dfs_attach(device_t dev);
   49 static int      dfs_settings(device_t dev, struct cf_setting *sets, int *count);
   50 static int      dfs_set(device_t dev, const struct cf_setting *set);
   51 static int      dfs_get(device_t dev, struct cf_setting *set);
   52 static int      dfs_type(device_t dev, int *type);
   53 
   54 static device_method_t dfs_methods[] = {
   55         /* Device interface */
   56         DEVMETHOD(device_identify,      dfs_identify),
   57         DEVMETHOD(device_probe,         dfs_probe),
   58         DEVMETHOD(device_attach,        dfs_attach),
   59 
   60         /* cpufreq interface */
   61         DEVMETHOD(cpufreq_drv_set,      dfs_set),
   62         DEVMETHOD(cpufreq_drv_get,      dfs_get),
   63         DEVMETHOD(cpufreq_drv_type,     dfs_type),
   64         DEVMETHOD(cpufreq_drv_settings, dfs_settings),
   65 
   66         {0, 0}
   67 };
   68 
   69 static driver_t dfs_driver = {
   70         "dfs",
   71         dfs_methods,
   72         sizeof(struct dfs_softc)
   73 };
   74 
   75 static devclass_t dfs_devclass;
   76 DRIVER_MODULE(dfs, cpu, dfs_driver, dfs_devclass, 0, 0);
   77 
   78 /*
   79  * Bits of the HID1 register to enable DFS. See page 2-24 of "MPC7450
   80  * RISC Microprocessor Family Reference Manual", rev. 5.
   81  */
   82 
   83 #define HID1_DFS2       (1UL << 22)
   84 #define HID1_DFS4       (1UL << 23)
   85 
   86 static void
   87 dfs_identify(driver_t *driver, device_t parent)
   88 {
   89         uint16_t vers;
   90         vers = mfpvr() >> 16;
   91 
   92         /* Check for an MPC 7447A or 7448 CPU */
   93         switch (vers) {
   94                 case MPC7447A:
   95                 case MPC7448:
   96                         break;
   97                 default:
   98                         return;
   99         }
  100 
  101         /* Make sure we're not being doubly invoked. */
  102         if (device_find_child(parent, "dfs", -1) != NULL)
  103                 return;
  104 
  105         /*
  106          * We attach a child for every CPU since settings need to
  107          * be performed on every CPU in the SMP case.
  108          */
  109         if (BUS_ADD_CHILD(parent, 10, "dfs", -1) == NULL)
  110                 device_printf(parent, "add dfs child failed\n");
  111 }
  112 
  113 static int
  114 dfs_probe(device_t dev)
  115 {
  116         if (resource_disabled("dfs", 0))
  117                 return (ENXIO);
  118 
  119         device_set_desc(dev, "Dynamic Frequency Switching");
  120         return (0);
  121 }
  122 
  123 static int
  124 dfs_attach(device_t dev)
  125 {
  126         struct dfs_softc *sc;
  127         uint16_t vers;
  128 
  129         sc = device_get_softc(dev);
  130         sc->dev = dev;
  131         sc->dfs4 = 0;
  132         vers = mfpvr() >> 16;
  133 
  134         /* The 7448 supports divide-by-four as well */
  135         if (vers == MPC7448)
  136                 sc->dfs4 = 1;
  137 
  138         cpufreq_register(dev);
  139         return (0);
  140 }
  141 
  142 static int
  143 dfs_settings(device_t dev, struct cf_setting *sets, int *count)
  144 {
  145         struct dfs_softc *sc;
  146         int states;
  147 
  148         sc = device_get_softc(dev);
  149         states = sc->dfs4 ? 3 : 2;
  150         if (sets == NULL || count == NULL)
  151                 return (EINVAL);
  152         if (*count < states)
  153                 return (E2BIG);
  154 
  155         /* Return a list of valid settings for this driver. */
  156         memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * states);
  157 
  158         sets[0].freq = 10000; sets[0].dev = dev;
  159         sets[1].freq = 5000; sets[1].dev = dev;
  160         if (sc->dfs4) {
  161                 sets[2].freq = 2500;
  162                 sets[2].dev = dev;
  163         }
  164         *count = states;
  165 
  166         return (0);
  167 }
  168 
  169 static int
  170 dfs_set(device_t dev, const struct cf_setting *set)
  171 {
  172         register_t hid1;
  173         
  174         if (set == NULL)
  175                 return (EINVAL);
  176 
  177         hid1 = mfspr(SPR_HID1);
  178         hid1 &= ~(HID1_DFS2 | HID1_DFS4);
  179 
  180         if (set->freq == 5000)
  181                 hid1 |= HID1_DFS2;
  182         else if (set->freq == 2500)
  183                 hid1 |= HID1_DFS4;
  184         
  185         /*
  186          * Now set the HID1 register with new values. Calling sequence
  187          * taken from page 2-26 of the MPC7450 family CPU manual.
  188          */
  189 
  190         powerpc_sync();
  191         mtspr(SPR_HID1, hid1);
  192         powerpc_sync(); isync();
  193 
  194         return (0);
  195 }
  196 
  197 static int
  198 dfs_get(device_t dev, struct cf_setting *set)
  199 {
  200         struct dfs_softc *sc;
  201         register_t hid1;
  202 
  203         if (set == NULL)
  204                 return (EINVAL);
  205         sc = device_get_softc(dev);
  206 
  207         memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set));
  208 
  209         hid1 = mfspr(SPR_HID1);
  210 
  211         set->freq = 10000;
  212         if (hid1 & HID1_DFS2)
  213                 set->freq = 5000;
  214         else if (sc->dfs4 && (hid1 & HID1_DFS4))
  215                 set->freq = 2500;
  216 
  217         set->dev = dev;
  218 
  219         return (0);
  220 }
  221 
  222 static int
  223 dfs_type(device_t dev, int *type)
  224 {
  225 
  226         if (type == NULL)
  227                 return (EINVAL);
  228 
  229         *type = CPUFREQ_TYPE_RELATIVE;
  230         return (0);
  231 }
  232 

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