The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/powerpc/fpu/fpu_compare.c

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    1 /*      $NetBSD: fpu_compare.c,v 1.4 2005/12/11 12:18:42 christos Exp $ */
    2 
    3 /*-
    4  * SPDX-License-Identifier: BSD-3-Clause
    5  *
    6  * Copyright (c) 1992, 1993
    7  *      The Regents of the University of California.  All rights reserved.
    8  *
    9  * This software was developed by the Computer Systems Engineering group
   10  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
   11  * contributed to Berkeley.
   12  *
   13  * All advertising materials mentioning features or use of this software
   14  * must display the following acknowledgement:
   15  *      This product includes software developed by the University of
   16  *      California, Lawrence Berkeley Laboratory.
   17  *
   18  * Redistribution and use in source and binary forms, with or without
   19  * modification, are permitted provided that the following conditions
   20  * are met:
   21  * 1. Redistributions of source code must retain the above copyright
   22  *    notice, this list of conditions and the following disclaimer.
   23  * 2. Redistributions in binary form must reproduce the above copyright
   24  *    notice, this list of conditions and the following disclaimer in the
   25  *    documentation and/or other materials provided with the distribution.
   26  * 3. Neither the name of the University nor the names of its contributors
   27  *    may be used to endorse or promote products derived from this software
   28  *    without specific prior written permission.
   29  *
   30  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   31  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   32  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   33  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   34  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   35  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   36  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   37  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   38  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   39  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   40  * SUCH DAMAGE.
   41  *
   42  *      @(#)fpu_compare.c       8.1 (Berkeley) 6/11/93
   43  */
   44 
   45 /*
   46  * FCMPU and FCMPO instructions.
   47  *
   48  * These rely on the fact that our internal wide format is achieved by
   49  * adding zero bits to the end of narrower mantissas.
   50  */
   51 
   52 #include <sys/cdefs.h>
   53 __FBSDID("$FreeBSD$");
   54 
   55 #include <sys/types.h>
   56 #include <sys/systm.h>
   57 
   58 #include <machine/fpu.h>
   59 
   60 #include <powerpc/fpu/fpu_arith.h>
   61 #include <powerpc/fpu/fpu_emu.h>
   62 
   63 /*
   64  * Perform a compare instruction (with or without unordered exception).
   65  * This updates the fcc field in the fsr.
   66  *
   67  * If either operand is NaN, the result is unordered.  For ordered, this
   68  * causes an NV exception.  Everything else is ordered:
   69  *      |Inf| > |numbers| > |0|.
   70  * We already arranged for fp_class(Inf) > fp_class(numbers) > fp_class(0),
   71  * so we get this directly.  Note, however, that two zeros compare equal
   72  * regardless of sign, while everything else depends on sign.
   73  *
   74  * Incidentally, two Infs of the same sign compare equal (per the 80387
   75  * manual---it would be nice if the SPARC documentation were more
   76  * complete).
   77  */
   78 void
   79 fpu_compare(struct fpemu *fe, int ordered)
   80 {
   81         struct fpn *a, *b, *r;
   82         int cc;
   83 
   84         a = &fe->fe_f1;
   85         b = &fe->fe_f2;
   86         r = &fe->fe_f3;
   87 
   88         if (ISNAN(a) || ISNAN(b)) {
   89                 /*
   90                  * In any case, we already got an exception for signalling
   91                  * NaNs; here we may replace that one with an identical
   92                  * exception, but so what?.
   93                  */
   94                 cc = FPSCR_FU;
   95                 if (ISSNAN(a) || ISSNAN(b))
   96                         cc |= FPSCR_VXSNAN;
   97                 if (ordered) {
   98                         if (fe->fe_fpscr & FPSCR_VE || ISQNAN(a) || ISQNAN(b))
   99                                 cc |= FPSCR_VXVC;
  100                 }
  101                 goto done;
  102         }
  103 
  104         /*
  105          * Must handle both-zero early to avoid sign goofs.  Otherwise,
  106          * at most one is 0, and if the signs differ we are done.
  107          */
  108         if (ISZERO(a) && ISZERO(b)) {
  109                 cc = FPSCR_FE;
  110                 goto done;
  111         }
  112         if (a->fp_sign) {               /* a < 0 (or -0) */
  113                 if (!b->fp_sign) {      /* b >= 0 (or if a = -0, b > 0) */
  114                         cc = FPSCR_FL;
  115                         goto done;
  116                 }
  117         } else {                        /* a > 0 (or +0) */
  118                 if (b->fp_sign) {       /* b <= -0 (or if a = +0, b < 0) */
  119                         cc = FPSCR_FG;
  120                         goto done;
  121                 }
  122         }
  123 
  124         /*
  125          * Now the signs are the same (but may both be negative).  All
  126          * we have left are these cases:
  127          *
  128          *      |a| < |b|               [classes or values differ]
  129          *      |a| > |b|               [classes or values differ]
  130          *      |a| == |b|              [classes and values identical]
  131          *
  132          * We define `diff' here to expand these as:
  133          *
  134          *      |a| < |b|, a,b >= 0: a < b => FSR_CC_LT
  135          *      |a| < |b|, a,b < 0:  a > b => FSR_CC_GT
  136          *      |a| > |b|, a,b >= 0: a > b => FSR_CC_GT
  137          *      |a| > |b|, a,b < 0:  a < b => FSR_CC_LT
  138          */
  139 #define opposite_cc(cc) ((cc) == FPSCR_FL ? FPSCR_FG : FPSCR_FL)
  140 #define diff(magnitude) (a->fp_sign ? opposite_cc(magnitude) :  (magnitude))
  141         if (a->fp_class < b->fp_class) {        /* |a| < |b| */
  142                 cc = diff(FPSCR_FL);
  143                 goto done;
  144         }
  145         if (a->fp_class > b->fp_class) {        /* |a| > |b| */
  146                 cc = diff(FPSCR_FG);
  147                 goto done;
  148         }
  149         /* now none can be 0: only Inf and numbers remain */
  150         if (ISINF(a)) {                         /* |Inf| = |Inf| */
  151                 cc = FPSCR_FE;
  152                 goto done;
  153         }
  154         fpu_sub(fe);
  155         if (ISZERO(r))
  156                 cc = FPSCR_FE;
  157         else if (r->fp_sign)
  158                 cc = FPSCR_FL;
  159         else
  160                 cc = FPSCR_FG;
  161 done:
  162         fe->fe_cx = cc;
  163 }

Cache object: a47c1c92f8e04d13b7223e2730defce0


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