1 /*-
2 * Copyright (c) 2009 Marcel Moolenaar
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD: releng/11.0/sys/powerpc/mpc85xx/atpic.c 257059 2013-10-24 15:37:32Z nwhitehorn $");
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/cpuset.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/rman.h>
36
37 #include <machine/bus.h>
38 #include <machine/intr_machdep.h>
39 #include <machine/pio.h>
40
41 #include <powerpc/mpc85xx/mpc85xx.h>
42
43 #include <dev/ic/i8259.h>
44
45 #include <isa/isareg.h>
46 #include <isa/isavar.h>
47
48 #include "pic_if.h"
49
50 #define ATPIC_MASTER 0
51 #define ATPIC_SLAVE 1
52
53 struct atpic_softc {
54 device_t sc_dev;
55
56 /* I/O port resources for master & slave. */
57 struct resource *sc_res[2];
58 int sc_rid[2];
59
60 /* Our "routing" interrupt */
61 struct resource *sc_ires;
62 void *sc_icookie;
63 int sc_irid;
64
65 int sc_vector[16];
66 uint8_t sc_mask[2];
67 };
68
69 static int atpic_isa_attach(device_t);
70 static void atpic_isa_identify(driver_t *, device_t);
71 static int atpic_isa_probe(device_t);
72
73 static void atpic_config(device_t, u_int, enum intr_trigger,
74 enum intr_polarity);
75 static void atpic_dispatch(device_t, struct trapframe *);
76 static void atpic_enable(device_t, u_int, u_int);
77 static void atpic_eoi(device_t, u_int);
78 static void atpic_ipi(device_t, u_int);
79 static void atpic_mask(device_t, u_int);
80 static void atpic_unmask(device_t, u_int);
81
82 static void atpic_ofw_translate_code(device_t, u_int irq, int code,
83 enum intr_trigger *trig, enum intr_polarity *pol);
84
85 static device_method_t atpic_isa_methods[] = {
86 /* Device interface */
87 DEVMETHOD(device_identify, atpic_isa_identify),
88 DEVMETHOD(device_probe, atpic_isa_probe),
89 DEVMETHOD(device_attach, atpic_isa_attach),
90
91 /* PIC interface */
92 DEVMETHOD(pic_config, atpic_config),
93 DEVMETHOD(pic_dispatch, atpic_dispatch),
94 DEVMETHOD(pic_enable, atpic_enable),
95 DEVMETHOD(pic_eoi, atpic_eoi),
96 DEVMETHOD(pic_ipi, atpic_ipi),
97 DEVMETHOD(pic_mask, atpic_mask),
98 DEVMETHOD(pic_unmask, atpic_unmask),
99
100 DEVMETHOD(pic_translate_code, atpic_ofw_translate_code),
101
102 { 0, 0 },
103 };
104
105 static driver_t atpic_isa_driver = {
106 "atpic",
107 atpic_isa_methods,
108 sizeof(struct atpic_softc)
109 };
110
111 static devclass_t atpic_devclass;
112
113 DRIVER_MODULE(atpic, isa, atpic_isa_driver, atpic_devclass, 0, 0);
114
115 static struct isa_pnp_id atpic_ids[] = {
116 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
117 { 0 }
118 };
119
120 static __inline uint8_t
121 atpic_read(struct atpic_softc *sc, int icu, int ofs)
122 {
123 uint8_t val;
124
125 val = bus_read_1(sc->sc_res[icu], ofs);
126 return (val);
127 }
128
129 static __inline void
130 atpic_write(struct atpic_softc *sc, int icu, int ofs, uint8_t val)
131 {
132
133 bus_write_1(sc->sc_res[icu], ofs, val);
134 bus_barrier(sc->sc_res[icu], ofs, 2 - ofs,
135 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
136 }
137
138 static void
139 atpic_intr(void *arg)
140 {
141
142 atpic_dispatch(arg, NULL);
143 }
144
145 static void
146 atpic_isa_identify(driver_t *drv, device_t parent)
147 {
148 device_t child;
149
150 child = BUS_ADD_CHILD(parent, ISA_ORDER_SENSITIVE, drv->name, -1);
151 device_set_driver(child, drv);
152 isa_set_logicalid(child, atpic_ids[0].ip_id);
153 isa_set_vendorid(child, atpic_ids[0].ip_id);
154
155 bus_set_resource(child, SYS_RES_IOPORT, ATPIC_MASTER, IO_ICU1, 2);
156 bus_set_resource(child, SYS_RES_IOPORT, ATPIC_SLAVE, IO_ICU2, 2);
157
158 /* ISA interrupts are routed through external interrupt 0. */
159 bus_set_resource(child, SYS_RES_IRQ, 0, 16, 1);
160 }
161
162 static int
163 atpic_isa_probe(device_t dev)
164 {
165 int res;
166
167 res = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
168 if (res > 0)
169 return (res);
170
171 device_set_desc(dev, "PC/AT compatible PIC");
172 return (res);
173 }
174
175 static void
176 atpic_init(struct atpic_softc *sc, int icu)
177 {
178
179 sc->sc_mask[icu] = 0xff - ((icu == ATPIC_MASTER) ? 4 : 0);
180
181 atpic_write(sc, icu, 0, ICW1_RESET | ICW1_IC4);
182 atpic_write(sc, icu, 1, (icu == ATPIC_SLAVE) ? 8 : 0);
183 atpic_write(sc, icu, 1, (icu == ATPIC_SLAVE) ? 2 : 4);
184 atpic_write(sc, icu, 1, ICW4_8086);
185 atpic_write(sc, icu, 1, sc->sc_mask[icu]);
186 atpic_write(sc, icu, 0, OCW3_SEL | OCW3_RR);
187 }
188
189 static int
190 atpic_isa_attach(device_t dev)
191 {
192 struct atpic_softc *sc;
193 int error;
194
195 sc = device_get_softc(dev);
196 sc->sc_dev = dev;
197
198 error = ENXIO;
199
200 sc->sc_rid[ATPIC_MASTER] = 0;
201 sc->sc_res[ATPIC_MASTER] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
202 &sc->sc_rid[ATPIC_MASTER], RF_ACTIVE);
203 if (sc->sc_res[ATPIC_MASTER] == NULL)
204 goto fail;
205
206 sc->sc_rid[ATPIC_SLAVE] = 1;
207 sc->sc_res[ATPIC_SLAVE] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
208 &sc->sc_rid[ATPIC_SLAVE], RF_ACTIVE);
209 if (sc->sc_res[ATPIC_SLAVE] == NULL)
210 goto fail;
211
212 sc->sc_irid = 0;
213 sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irid,
214 RF_ACTIVE);
215 if (sc->sc_ires == NULL)
216 goto fail;
217
218 error = bus_setup_intr(dev, sc->sc_ires, INTR_TYPE_MISC | INTR_MPSAFE,
219 NULL, atpic_intr, dev, &sc->sc_icookie);
220 if (error)
221 goto fail;
222
223 atpic_init(sc, ATPIC_SLAVE);
224 atpic_init(sc, ATPIC_MASTER);
225
226 powerpc_register_pic(dev, 0, 16, 0, TRUE);
227 return (0);
228
229 fail:
230 if (sc->sc_ires != NULL)
231 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
232 sc->sc_ires);
233 if (sc->sc_res[ATPIC_SLAVE] != NULL)
234 bus_release_resource(dev, SYS_RES_IOPORT,
235 sc->sc_rid[ATPIC_SLAVE], sc->sc_res[ATPIC_SLAVE]);
236 if (sc->sc_res[ATPIC_MASTER] != NULL)
237 bus_release_resource(dev, SYS_RES_IOPORT,
238 sc->sc_rid[ATPIC_MASTER], sc->sc_res[ATPIC_MASTER]);
239 return (error);
240 }
241
242
243 /*
244 * PIC interface.
245 */
246
247 static void
248 atpic_config(device_t dev, u_int irq, enum intr_trigger trig,
249 enum intr_polarity pol)
250 {
251 }
252
253 static void
254 atpic_dispatch(device_t dev, struct trapframe *tf)
255 {
256 struct atpic_softc *sc;
257 uint8_t irq;
258
259 sc = device_get_softc(dev);
260 atpic_write(sc, ATPIC_MASTER, 0, OCW3_SEL | OCW3_P);
261 irq = atpic_read(sc, ATPIC_MASTER, 0);
262 atpic_write(sc, ATPIC_MASTER, 0, OCW3_SEL | OCW3_RR);
263 if ((irq & 0x80) == 0)
264 return;
265
266 if (irq == 0x82) {
267 atpic_write(sc, ATPIC_SLAVE, 0, OCW3_SEL | OCW3_P);
268 irq = atpic_read(sc, ATPIC_SLAVE, 0) + 8;
269 atpic_write(sc, ATPIC_SLAVE, 0, OCW3_SEL | OCW3_RR);
270 if ((irq & 0x80) == 0)
271 return;
272 }
273
274 powerpc_dispatch_intr(sc->sc_vector[irq & 0x0f], tf);
275 }
276
277 static void
278 atpic_enable(device_t dev, u_int irq, u_int vector)
279 {
280 struct atpic_softc *sc;
281
282 sc = device_get_softc(dev);
283 sc->sc_vector[irq] = vector;
284 atpic_unmask(dev, irq);
285 }
286
287 static void
288 atpic_eoi(device_t dev, u_int irq)
289 {
290 struct atpic_softc *sc;
291
292 sc = device_get_softc(dev);
293 if (irq > 7)
294 atpic_write(sc, ATPIC_SLAVE, 0, OCW2_EOI);
295 atpic_write(sc, ATPIC_MASTER, 0, OCW2_EOI);
296 }
297
298 static void
299 atpic_ipi(device_t dev, u_int cpu)
300 {
301 /* No SMP support. */
302 }
303
304 static void
305 atpic_mask(device_t dev, u_int irq)
306 {
307 struct atpic_softc *sc;
308
309 sc = device_get_softc(dev);
310 if (irq > 7) {
311 sc->sc_mask[ATPIC_SLAVE] |= 1 << (irq - 8);
312 atpic_write(sc, ATPIC_SLAVE, 1, sc->sc_mask[ATPIC_SLAVE]);
313 } else {
314 sc->sc_mask[ATPIC_MASTER] |= 1 << irq;
315 atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]);
316 }
317 }
318
319 static void
320 atpic_unmask(device_t dev, u_int irq)
321 {
322 struct atpic_softc *sc;
323
324 sc = device_get_softc(dev);
325 if (irq > 7) {
326 sc->sc_mask[ATPIC_SLAVE] &= ~(1 << (irq - 8));
327 atpic_write(sc, ATPIC_SLAVE, 1, sc->sc_mask[ATPIC_SLAVE]);
328 } else {
329 sc->sc_mask[ATPIC_MASTER] &= ~(1 << irq);
330 atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]);
331 }
332 }
333
334 static void
335 atpic_ofw_translate_code(device_t dev, u_int irq, int code,
336 enum intr_trigger *trig, enum intr_polarity *pol)
337 {
338 switch (code) {
339 case 0:
340 /* Active L level */
341 *trig = INTR_TRIGGER_LEVEL;
342 *pol = INTR_POLARITY_LOW;
343 break;
344 case 1:
345 /* Active H level */
346 *trig = INTR_TRIGGER_LEVEL;
347 *pol = INTR_POLARITY_HIGH;
348 break;
349 case 2:
350 /* H to L edge */
351 *trig = INTR_TRIGGER_EDGE;
352 *pol = INTR_POLARITY_LOW;
353 break;
354 case 3:
355 /* L to H edge */
356 *trig = INTR_TRIGGER_EDGE;
357 *pol = INTR_POLARITY_HIGH;
358 break;
359 default:
360 *trig = INTR_TRIGGER_CONFORM;
361 *pol = INTR_POLARITY_CONFORM;
362 }
363 }
364
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