1 /*-
2 * Copyright (c) 2006-2008, Juniper Networks, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: releng/11.0/sys/powerpc/mpc85xx/lbc.h 238045 2012-07-03 00:06:14Z marcel $
27 */
28
29 #ifndef _MACHINE_LBC_H_
30 #define _MACHINE_LBC_H_
31
32 /* Maximum number of devices on Local Bus */
33 #define LBC_DEV_MAX 8
34
35 /* Local access registers */
36 #define LBC85XX_BR(n) (0x0 + (8 * n)) /* Base register 0-7 */
37 #define LBC85XX_OR(n) (0x4 + (8 * n)) /* Options register 0-7 */
38 #define LBC85XX_MAR 0x068 /* UPM address register */
39 #define LBC85XX_MAMR 0x070 /* UPMA mode register */
40 #define LBC85XX_MBMR 0x074 /* UPMB mode register */
41 #define LBC85XX_MCMR 0x078 /* UPMC mode register */
42 #define LBC85XX_MRTPR 0x084 /* Memory refresh timer prescaler */
43 #define LBC85XX_MDR 0x088 /* UPM data register */
44 #define LBC85XX_LSOR 0x090 /* Special operation initiation */
45 #define LBC85XX_LURT 0x0a0 /* UPM refresh timer */
46 #define LBC85XX_LSRT 0x0a4 /* SDRAM refresh timer */
47 #define LBC85XX_LTESR 0x0b0 /* Transfer error status register */
48 #define LBC85XX_LTEDR 0x0b4 /* Transfer error disable register */
49 #define LBC85XX_LTEIR 0x0b8 /* Transfer error interrupt register */
50 #define LBC85XX_LTEATR 0x0bc /* Transfer error attributes register */
51 #define LBC85XX_LTEAR 0x0c0 /* Transfer error address register */
52 #define LBC85XX_LTECCR 0x0c4 /* Transfer error ECC register */
53 #define LBC85XX_LBCR 0x0d0 /* Configuration register */
54 #define LBC85XX_LCRR 0x0d4 /* Clock ratio register */
55 #define LBC85XX_FMR 0x0e0 /* Flash mode register */
56 #define LBC85XX_FIR 0x0e4 /* Flash instruction register */
57 #define LBC85XX_FCR 0x0e8 /* Flash command register */
58 #define LBC85XX_FBAR 0x0ec /* Flash block address register */
59 #define LBC85XX_FPAR 0x0f0 /* Flash page address register */
60 #define LBC85XX_FBCR 0x0f4 /* Flash byte count register */
61 #define LBC85XX_FECC0 0x100 /* Flash ECC block 0 register */
62 #define LBC85XX_FECC1 0x104 /* Flash ECC block 0 register */
63 #define LBC85XX_FECC2 0x108 /* Flash ECC block 0 register */
64 #define LBC85XX_FECC3 0x10c /* Flash ECC block 0 register */
65
66 /* LBC machine select */
67 #define LBCRES_MSEL_GPCM 0
68 #define LBCRES_MSEL_FCM 1
69 #define LBCRES_MSEL_UPMA 8
70 #define LBCRES_MSEL_UPMB 9
71 #define LBCRES_MSEL_UPMC 10
72
73 /* LBC data error checking modes */
74 #define LBCRES_DECC_DISABLED 0
75 #define LBCRES_DECC_NORMAL 1
76 #define LBCRES_DECC_RMW 2
77
78 /* LBC atomic operation modes */
79 #define LBCRES_ATOM_DISABLED 0
80 #define LBCRES_ATOM_RAWA 1
81 #define LBCRES_ATOM_WARA 2
82
83 struct lbc_memrange {
84 vm_paddr_t addr;
85 vm_size_t size;
86 vm_offset_t kva;
87 };
88
89 struct lbc_bank {
90 vm_paddr_t addr; /* physical addr of the bank */
91 vm_size_t size; /* bank size */
92 vm_offset_t kva; /* VA of the bank */
93
94 /*
95 * XXX the following bank attributes do not have properties specified
96 * in the LBC DTS bindings yet (11.2009), so they are mainly a
97 * placeholder for future extensions.
98 */
99 int width; /* data bus width */
100 uint8_t msel; /* machine select */
101 uint8_t atom; /* atomic op mode */
102 uint8_t wp; /* write protect */
103 uint8_t decc; /* data error checking */
104 };
105
106 struct lbc_softc {
107 device_t sc_dev;
108
109 struct resource *sc_mres;
110 bus_space_handle_t sc_bsh;
111 bus_space_tag_t sc_bst;
112 int sc_mrid;
113
114 int sc_irid;
115 struct resource *sc_ires;
116 void *sc_icookie;
117
118 struct rman sc_rman;
119
120 int sc_addr_cells;
121 int sc_size_cells;
122
123 struct lbc_memrange sc_range[LBC_DEV_MAX];
124 struct lbc_bank sc_banks[LBC_DEV_MAX];
125
126 uint32_t sc_ltesr;
127 };
128
129 struct lbc_devinfo {
130 struct ofw_bus_devinfo di_ofw;
131 struct resource_list di_res;
132 int di_bank;
133 };
134
135 uint32_t lbc_read_reg(device_t child, u_int off);
136 void lbc_write_reg(device_t child, u_int off, uint32_t val);
137
138 #endif /* _MACHINE_LBC_H_ */
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