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sys/powerpc/mpc85xx/pci_ocp.c
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1 /*- 2 * Copyright 2006-2007 by Juniper Networks. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/ktr.h> 35 #include <sys/sockio.h> 36 #include <sys/mbuf.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/socket.h> 41 #include <sys/queue.h> 42 #include <sys/bus.h> 43 #include <sys/rman.h> 44 #include <sys/endian.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcib_private.h> 52 53 #include "pcib_if.h" 54 55 #include <machine/resource.h> 56 #include <machine/bus.h> 57 #include <machine/intr_machdep.h> 58 #include <machine/ocpbus.h> 59 #include <machine/spr.h> 60 61 #include <powerpc/mpc85xx/ocpbus.h> 62 63 #define REG_CFG_ADDR 0x0000 64 #define CONFIG_ACCESS_ENABLE 0x80000000 65 66 #define REG_CFG_DATA 0x0004 67 #define REG_INT_ACK 0x0008 68 69 #define REG_POTAR(n) (0x0c00 + 0x20 * (n)) 70 #define REG_POTEAR(n) (0x0c04 + 0x20 * (n)) 71 #define REG_POWBAR(n) (0x0c08 + 0x20 * (n)) 72 #define REG_POWAR(n) (0x0c10 + 0x20 * (n)) 73 74 #define REG_PITAR(n) (0x0e00 - 0x20 * (n)) 75 #define REG_PIWBAR(n) (0x0e08 - 0x20 * (n)) 76 #define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n)) 77 #define REG_PIWAR(n) (0x0e10 - 0x20 * (n)) 78 79 #define PCIR_FSL_LTSSM 0x404 80 #define FSL_LTSSM_L0 0x16 81 82 #define DEVFN(b, s, f) ((b << 16) | (s << 8) | f) 83 84 struct pci_ocp_softc { 85 device_t sc_dev; 86 87 struct rman sc_iomem; 88 bus_addr_t sc_iomem_va; /* Virtual mapping. */ 89 bus_addr_t sc_iomem_alloc; /* Next allocation. */ 90 struct rman sc_ioport; 91 bus_addr_t sc_ioport_va; /* Virtual mapping. */ 92 bus_addr_t sc_ioport_alloc; /* Next allocation. */ 93 94 struct resource *sc_res; 95 bus_space_handle_t sc_bsh; 96 bus_space_tag_t sc_bst; 97 int sc_rid; 98 99 int sc_busnr; 100 uint8_t sc_pcie_cap; 101 102 /* Devices that need special attention. */ 103 int sc_devfn_tundra; 104 int sc_devfn_via_ide; 105 }; 106 107 static int pci_ocp_attach(device_t); 108 static int pci_ocp_probe(device_t); 109 110 static struct resource *pci_ocp_alloc_resource(device_t, device_t, int, int *, 111 u_long, u_long, u_long, u_int); 112 static int pci_ocp_read_ivar(device_t, device_t, int, uintptr_t *); 113 static int pci_ocp_release_resource(device_t, device_t, int, int, 114 struct resource *); 115 static int pci_ocp_write_ivar(device_t, device_t, int, uintptr_t); 116 117 static int pci_ocp_maxslots(device_t); 118 static uint32_t pci_ocp_read_config(device_t, u_int, u_int, u_int, u_int, int); 119 static void pci_ocp_write_config(device_t, u_int, u_int, u_int, u_int, 120 uint32_t, int); 121 122 /* 123 * Bus interface definitions. 124 */ 125 static device_method_t pci_ocp_methods[] = { 126 /* Device interface */ 127 DEVMETHOD(device_probe, pci_ocp_probe), 128 DEVMETHOD(device_attach, pci_ocp_attach), 129 130 /* Bus interface */ 131 DEVMETHOD(bus_print_child, bus_generic_print_child), 132 DEVMETHOD(bus_read_ivar, pci_ocp_read_ivar), 133 DEVMETHOD(bus_write_ivar, pci_ocp_write_ivar), 134 DEVMETHOD(bus_alloc_resource, pci_ocp_alloc_resource), 135 DEVMETHOD(bus_release_resource, pci_ocp_release_resource), 136 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 137 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 138 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 139 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 140 141 /* pcib interface */ 142 DEVMETHOD(pcib_maxslots, pci_ocp_maxslots), 143 DEVMETHOD(pcib_read_config, pci_ocp_read_config), 144 DEVMETHOD(pcib_write_config, pci_ocp_write_config), 145 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 146 147 { 0, 0 } 148 }; 149 150 static driver_t pci_ocp_driver = { 151 "pcib", 152 pci_ocp_methods, 153 sizeof(struct pci_ocp_softc), 154 }; 155 156 devclass_t pcib_devclass; 157 158 DRIVER_MODULE(pcib, ocpbus, pci_ocp_driver, pcib_devclass, 0, 0); 159 160 static uint32_t 161 pci_ocp_cfgread(struct pci_ocp_softc *sc, u_int bus, u_int slot, u_int func, 162 u_int reg, int bytes) 163 { 164 uint32_t addr, data; 165 166 if (bus == sc->sc_busnr) 167 bus = 0; 168 169 addr = CONFIG_ACCESS_ENABLE; 170 addr |= (bus & 0xff) << 16; 171 addr |= (slot & 0x1f) << 11; 172 addr |= (func & 0x7) << 8; 173 addr |= reg & 0xfc; 174 if (sc->sc_pcie_cap) 175 addr |= (reg & 0xf00) << 16; 176 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 177 178 switch (bytes) { 179 case 1: 180 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 181 REG_CFG_DATA + (reg & 3)); 182 break; 183 case 2: 184 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 185 REG_CFG_DATA + (reg & 2))); 186 break; 187 case 4: 188 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 189 REG_CFG_DATA)); 190 break; 191 default: 192 data = ~0; 193 break; 194 } 195 return (data); 196 } 197 198 static void 199 pci_ocp_cfgwrite(struct pci_ocp_softc *sc, u_int bus, u_int slot, u_int func, 200 u_int reg, uint32_t data, int bytes) 201 { 202 uint32_t addr; 203 204 if (bus == sc->sc_busnr) 205 bus = 0; 206 207 addr = CONFIG_ACCESS_ENABLE; 208 addr |= (bus & 0xff) << 16; 209 addr |= (slot & 0x1f) << 11; 210 addr |= (func & 0x7) << 8; 211 addr |= reg & 0xfc; 212 if (sc->sc_pcie_cap) 213 addr |= (reg & 0xf00) << 16; 214 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 215 216 switch (bytes) { 217 case 1: 218 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 219 REG_CFG_DATA + (reg & 3), data); 220 break; 221 case 2: 222 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 223 REG_CFG_DATA + (reg & 2), htole16(data)); 224 break; 225 case 4: 226 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 227 REG_CFG_DATA, htole32(data)); 228 break; 229 } 230 } 231 232 #if 0 233 static void 234 dump(struct pci_ocp_softc *sc) 235 { 236 unsigned int i; 237 238 #define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o) 239 for (i = 0; i < 5; i++) { 240 printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i))); 241 printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i))); 242 printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i))); 243 printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i))); 244 } 245 printf("\n"); 246 for (i = 1; i < 4; i++) { 247 printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i))); 248 printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i))); 249 printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i))); 250 printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i))); 251 } 252 printf("\n"); 253 #undef RD 254 255 for (i = 0; i < 0x48; i += 4) { 256 printf("cfg%02x=0x%08x\n", i, pci_ocp_cfgread(sc, 0, 0, 0, 257 i, 4)); 258 } 259 } 260 #endif 261 262 static int 263 pci_ocp_maxslots(device_t dev) 264 { 265 struct pci_ocp_softc *sc = device_get_softc(dev); 266 267 return ((sc->sc_pcie_cap) ? 0 : 31); 268 } 269 270 static uint32_t 271 pci_ocp_read_config(device_t dev, u_int bus, u_int slot, u_int func, 272 u_int reg, int bytes) 273 { 274 struct pci_ocp_softc *sc = device_get_softc(dev); 275 u_int devfn; 276 277 if (bus == sc->sc_busnr && !sc->sc_pcie_cap && slot < 10) 278 return (~0); 279 devfn = DEVFN(bus, slot, func); 280 /* 281 * For the host controller itself, pretend to be a standard 282 * PCI bridge, rather than a PowerPC processor. That way the 283 * generic PCI code will enumerate all subordinate busses 284 * and devices as usual. 285 */ 286 if (sc->sc_pcie_cap && devfn == 0) { 287 if (reg == PCIR_CLASS && bytes == 1) 288 return (PCIC_BRIDGE); 289 if (reg == PCIR_SUBCLASS && bytes == 1) 290 return (PCIS_BRIDGE_PCI); 291 } 292 if (devfn == sc->sc_devfn_tundra) 293 return (~0); 294 if (devfn == sc->sc_devfn_via_ide && reg == PCIR_INTPIN) 295 return (1); 296 return (pci_ocp_cfgread(sc, bus, slot, func, reg, bytes)); 297 } 298 299 static void 300 pci_ocp_write_config(device_t dev, u_int bus, u_int slot, u_int func, 301 u_int reg, uint32_t val, int bytes) 302 { 303 struct pci_ocp_softc *sc = device_get_softc(dev); 304 305 if (bus == sc->sc_busnr && !sc->sc_pcie_cap && slot < 10) 306 return; 307 pci_ocp_cfgwrite(sc, bus, slot, func, reg, val, bytes); 308 } 309 310 static int 311 pci_ocp_probe(device_t dev) 312 { 313 char buf[128]; 314 struct pci_ocp_softc *sc; 315 const char *type; 316 device_t parent; 317 u_long start, size; 318 uintptr_t devtype; 319 uint32_t cfgreg; 320 uint8_t capptr; 321 int error; 322 323 parent = device_get_parent(dev); 324 error = BUS_READ_IVAR(parent, dev, OCPBUS_IVAR_DEVTYPE, &devtype); 325 if (error) 326 return (error); 327 if (devtype != OCPBUS_DEVTYPE_PCIB) 328 return (ENXIO); 329 330 sc = device_get_softc(dev); 331 sc->sc_dev = dev; 332 333 sc->sc_rid = 0; 334 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, 335 RF_ACTIVE); 336 if (sc->sc_res == NULL) 337 return (ENXIO); 338 339 sc->sc_bst = rman_get_bustag(sc->sc_res); 340 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 341 sc->sc_busnr = 0; 342 343 error = ENOENT; 344 cfgreg = pci_ocp_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2); 345 if (cfgreg != 0x1057 && cfgreg != 0x1957) 346 goto out; 347 348 cfgreg = pci_ocp_cfgread(sc, 0, 0, 0, PCIR_CLASS, 1); 349 if (cfgreg != PCIC_PROCESSOR) 350 goto out; 351 352 cfgreg = pci_ocp_cfgread(sc, 0, 0, 0, PCIR_SUBCLASS, 1); 353 if (cfgreg != PCIS_PROCESSOR_POWERPC) 354 goto out; 355 356 cfgreg = pci_ocp_cfgread(sc, 0, 0, 0, PCIR_PROGIF, 1); 357 if (cfgreg != 0) /* RC mode = 0, EP mode = 1 */ 358 goto out; 359 360 type = "PCI"; 361 capptr = pci_ocp_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1); 362 while (capptr != 0) { 363 cfgreg = pci_ocp_cfgread(sc, 0, 0, 0, capptr, 2); 364 switch (cfgreg & 0xff) { 365 case PCIY_PCIX: /* PCI-X */ 366 type = "PCI-X"; 367 break; 368 case PCIY_EXPRESS: /* PCI Express */ 369 type = "PCI Express"; 370 sc->sc_pcie_cap = capptr; 371 break; 372 } 373 capptr = (cfgreg >> 8) & 0xff; 374 } 375 376 error = bus_get_resource(dev, SYS_RES_MEMORY, 1, &start, &size); 377 if (error || start == 0 || size == 0) 378 goto out; 379 380 snprintf(buf, sizeof(buf), 381 "Freescale on-chip %s host controller", type); 382 device_set_desc_copy(dev, buf); 383 error = BUS_PROBE_DEFAULT; 384 385 out: 386 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_res); 387 return (error); 388 } 389 390 static void 391 pci_ocp_init_via(struct pci_ocp_softc *sc, uint16_t device, int bus, 392 int slot, int fn) 393 { 394 395 if (device == 0x0686) { 396 pci_ocp_write_config(sc->sc_dev, bus, slot, fn, 0x52, 0x34, 1); 397 pci_ocp_write_config(sc->sc_dev, bus, slot, fn, 0x77, 0x00, 1); 398 pci_ocp_write_config(sc->sc_dev, bus, slot, fn, 0x83, 0x98, 1); 399 pci_ocp_write_config(sc->sc_dev, bus, slot, fn, 0x85, 0x03, 1); 400 } else if (device == 0x0571) { 401 sc->sc_devfn_via_ide = DEVFN(bus, slot, fn); 402 pci_ocp_write_config(sc->sc_dev, bus, slot, fn, 0x40, 0x0b, 1); 403 } 404 } 405 406 static int 407 pci_ocp_init_bar(struct pci_ocp_softc *sc, int bus, int slot, int func, 408 int barno) 409 { 410 bus_addr_t *allocp; 411 uint32_t addr, mask, size; 412 int reg, width; 413 414 reg = PCIR_BAR(barno); 415 416 if (DEVFN(bus, slot, func) == sc->sc_devfn_via_ide) { 417 switch (barno) { 418 case 0: addr = 0x1f0; break; 419 case 1: addr = 0x3f4; break; 420 case 2: addr = 0x170; break; 421 case 3: addr = 0x374; break; 422 case 4: addr = 0xcc0; break; 423 default: return (1); 424 } 425 pci_ocp_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); 426 return (1); 427 } 428 429 pci_ocp_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4); 430 size = pci_ocp_read_config(sc->sc_dev, bus, slot, func, reg, 4); 431 if (size == 0) 432 return (1); 433 width = ((size & 7) == 4) ? 2 : 1; 434 435 if (size & 1) { /* I/O port */ 436 allocp = &sc->sc_ioport_alloc; 437 size &= ~3; 438 if ((size & 0xffff0000) == 0) 439 size |= 0xffff0000; 440 } else { /* memory */ 441 allocp = &sc->sc_iomem_alloc; 442 size &= ~15; 443 } 444 mask = ~size; 445 size = mask + 1; 446 /* Sanity check (must be a power of 2). */ 447 if (size & mask) 448 return (width); 449 450 addr = (*allocp + mask) & ~mask; 451 *allocp = addr + size; 452 453 if (bootverbose) 454 printf("PCI %u:%u:%u:%u: reg %x: size=%08x: addr=%08x\n", 455 device_get_unit(sc->sc_dev), bus, slot, func, reg, 456 size, addr); 457 458 pci_ocp_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); 459 if (width == 2) 460 pci_ocp_write_config(sc->sc_dev, bus, slot, func, reg + 4, 461 0, 4); 462 return (width); 463 } 464 465 static u_int 466 pci_ocp_route_int(struct pci_ocp_softc *sc, u_int bus, u_int slot, u_int func, 467 u_int intpin) 468 { 469 u_int devfn, intline; 470 471 devfn = DEVFN(bus, slot, func); 472 if (devfn == sc->sc_devfn_via_ide) 473 intline = 14; 474 else if (devfn == sc->sc_devfn_via_ide + 1) 475 intline = 10; 476 else if (devfn == sc->sc_devfn_via_ide + 2) 477 intline = 10; 478 else { 479 if (intpin != 0) { 480 intline = intpin - 1; 481 intline += (bus != sc->sc_busnr) ? slot : 0; 482 intline = PIC_IRQ_EXT(intline & 3); 483 } else 484 intline = 0xff; 485 } 486 487 if (bootverbose) 488 printf("PCI %u:%u:%u:%u: intpin %u: intline=%u\n", 489 device_get_unit(sc->sc_dev), bus, slot, func, 490 intpin, intline); 491 492 return (intline); 493 } 494 495 static int 496 pci_ocp_init(struct pci_ocp_softc *sc, int bus, int nslots) 497 { 498 int secbus, slot; 499 int func, maxfunc; 500 int bar, maxbar; 501 uint16_t vendor, device; 502 uint8_t command, hdrtype, class, subclass; 503 uint8_t intline, intpin; 504 505 secbus = bus; 506 for (slot = 0; slot < nslots; slot++) { 507 maxfunc = 0; 508 for (func = 0; func <= maxfunc; func++) { 509 hdrtype = pci_ocp_read_config(sc->sc_dev, bus, slot, 510 func, PCIR_HDRTYPE, 1); 511 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 512 continue; 513 514 if (func == 0 && (hdrtype & PCIM_MFDEV)) 515 maxfunc = PCI_FUNCMAX; 516 517 vendor = pci_ocp_read_config(sc->sc_dev, bus, slot, 518 func, PCIR_VENDOR, 2); 519 device = pci_ocp_read_config(sc->sc_dev, bus, slot, 520 func, PCIR_DEVICE, 2); 521 522 if (vendor == 0x1957 && device == 0x3fff) { 523 sc->sc_devfn_tundra = DEVFN(bus, slot, func); 524 continue; 525 } 526 527 command = pci_ocp_read_config(sc->sc_dev, bus, slot, 528 func, PCIR_COMMAND, 1); 529 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 530 pci_ocp_write_config(sc->sc_dev, bus, slot, func, 531 PCIR_COMMAND, command, 1); 532 533 if (vendor == 0x1106) 534 pci_ocp_init_via(sc, device, bus, slot, func); 535 536 /* Program the base address registers. */ 537 maxbar = (hdrtype & PCIM_HDRTYPE) ? 1 : 6; 538 bar = 0; 539 while (bar < maxbar) 540 bar += pci_ocp_init_bar(sc, bus, slot, func, 541 bar); 542 543 /* Perform interrupt routing. */ 544 intpin = pci_ocp_read_config(sc->sc_dev, bus, slot, 545 func, PCIR_INTPIN, 1); 546 intline = pci_ocp_route_int(sc, bus, slot, func, 547 intpin); 548 pci_ocp_write_config(sc->sc_dev, bus, slot, func, 549 PCIR_INTLINE, intline, 1); 550 551 command |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN; 552 pci_ocp_write_config(sc->sc_dev, bus, slot, func, 553 PCIR_COMMAND, command, 1); 554 555 /* 556 * Handle PCI-PCI bridges 557 */ 558 class = pci_ocp_read_config(sc->sc_dev, bus, slot, 559 func, PCIR_CLASS, 1); 560 if (class != PCIC_BRIDGE) 561 continue; 562 subclass = pci_ocp_read_config(sc->sc_dev, bus, slot, 563 func, PCIR_SUBCLASS, 1); 564 if (subclass != PCIS_BRIDGE_PCI) 565 continue; 566 567 secbus++; 568 569 /* Program I/O decoder. */ 570 pci_ocp_write_config(sc->sc_dev, bus, slot, func, 571 PCIR_IOBASEL_1, sc->sc_ioport.rm_start >> 8, 1); 572 pci_ocp_write_config(sc->sc_dev, bus, slot, func, 573 PCIR_IOLIMITL_1, sc->sc_ioport.rm_end >> 8, 1); 574 pci_ocp_write_config(sc->sc_dev, bus, slot, func, 575 PCIR_IOBASEH_1, sc->sc_ioport.rm_start >> 16, 2); 576 pci_ocp_write_config(sc->sc_dev, bus, slot, func, 577 PCIR_IOLIMITH_1, sc->sc_ioport.rm_end >> 16, 2); 578 579 /* Program (non-prefetchable) memory decoder. */ 580 pci_ocp_write_config(sc->sc_dev, bus, slot, func, 581 PCIR_MEMBASE_1, sc->sc_iomem.rm_start >> 16, 2); 582 pci_ocp_write_config(sc->sc_dev, bus, slot, func, 583 PCIR_MEMLIMIT_1, sc->sc_iomem.rm_end >> 16, 2); 584 585 /* Program prefetchable memory decoder. */ 586 pci_ocp_write_config(sc->sc_dev, bus, slot, func, 587 PCIR_PMBASEL_1, 0x0010, 2); 588 pci_ocp_write_config(sc->sc_dev, bus, slot, func, 589 PCIR_PMLIMITL_1, 0x000f, 2); 590 pci_ocp_write_config(sc->sc_dev, bus, slot, func, 591 PCIR_PMBASEH_1, 0x00000000, 4); 592 pci_ocp_write_config(sc->sc_dev, bus, slot, func, 593 PCIR_PMLIMITH_1, 0x00000000, 4); 594 595 pci_ocp_write_config(sc->sc_dev, bus, slot, func, 596 PCIR_PRIBUS_1, bus, 1); 597 pci_ocp_write_config(sc->sc_dev, bus, slot, func, 598 PCIR_SECBUS_1, secbus, 1); 599 pci_ocp_write_config(sc->sc_dev, bus, slot, func, 600 PCIR_SUBBUS_1, 0xff, 1); 601 602 secbus = pci_ocp_init(sc, secbus, 603 (subclass == PCIS_BRIDGE_PCI) ? 32 : 1); 604 605 pci_ocp_write_config(sc->sc_dev, bus, slot, func, 606 PCIR_SUBBUS_1, secbus, 1); 607 } 608 } 609 610 return (secbus); 611 } 612 613 static void 614 pci_ocp_inbound(struct pci_ocp_softc *sc, int wnd, int tgt, u_long start, 615 u_long size, u_long pci_start) 616 { 617 uint32_t attr, bar, tar; 618 619 KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__)); 620 621 switch (tgt) { 622 case OCP85XX_TGTIF_RAM1: 623 attr = 0xa0f55000 | (ffsl(size) - 2); 624 break; 625 default: 626 attr = 0; 627 break; 628 } 629 tar = start >> 12; 630 bar = pci_start >> 12; 631 632 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar); 633 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0); 634 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar); 635 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr); 636 } 637 638 static void 639 pci_ocp_outbound(struct pci_ocp_softc *sc, int wnd, int res, u_long start, 640 u_long size, u_long pci_start) 641 { 642 uint32_t attr, bar, tar; 643 644 switch (res) { 645 case SYS_RES_MEMORY: 646 attr = 0x80044000 | (ffsl(size) - 2); 647 break; 648 case SYS_RES_IOPORT: 649 attr = 0x80088000 | (ffsl(size) - 2); 650 break; 651 default: 652 attr = 0x0004401f; 653 break; 654 } 655 bar = start >> 12; 656 tar = pci_start >> 12; 657 658 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar); 659 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0); 660 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar); 661 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr); 662 } 663 664 static int 665 pci_ocp_iorange(struct pci_ocp_softc *sc, int type, int wnd) 666 { 667 struct rman *rm; 668 u_long start, end, size, alloc; 669 bus_addr_t pci_start, pci_end; 670 bus_addr_t *vap, *allocp; 671 int error; 672 673 error = bus_get_resource(sc->sc_dev, type, 1, &start, &size); 674 if (error) 675 return (error); 676 677 end = start + size - 1; 678 679 switch (type) { 680 case SYS_RES_IOPORT: 681 rm = &sc->sc_ioport; 682 pci_start = 0x0000; 683 pci_end = 0xffff; 684 alloc = 0x1000; 685 vap = &sc->sc_ioport_va; 686 allocp = &sc->sc_ioport_alloc; 687 break; 688 case SYS_RES_MEMORY: 689 rm = &sc->sc_iomem; 690 pci_start = start; 691 pci_end = end; 692 alloc = 0; 693 vap = &sc->sc_iomem_va; 694 allocp = &sc->sc_iomem_alloc; 695 break; 696 default: 697 return (EINVAL); 698 } 699 700 rm->rm_type = RMAN_ARRAY; 701 rm->rm_start = pci_start; 702 rm->rm_end = pci_end; 703 error = rman_init(rm); 704 if (error) 705 return (error); 706 707 error = rman_manage_region(rm, pci_start, pci_end); 708 if (error) { 709 rman_fini(rm); 710 return (error); 711 } 712 713 *allocp = pci_start + alloc; 714 *vap = (uintptr_t)pmap_mapdev(start, size); 715 if (wnd != -1) 716 pci_ocp_outbound(sc, wnd, type, start, size, pci_start); 717 return (0); 718 } 719 720 static int 721 pci_ocp_attach(device_t dev) 722 { 723 struct pci_ocp_softc *sc; 724 uint32_t cfgreg; 725 int error, nslots; 726 727 sc = device_get_softc(dev); 728 sc->sc_dev = dev; 729 730 sc->sc_rid = 0; 731 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, 732 RF_ACTIVE); 733 if (sc->sc_res == NULL) { 734 device_printf(dev, "could not map I/O memory\n"); 735 return (ENXIO); 736 } 737 sc->sc_bst = rman_get_bustag(sc->sc_res); 738 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 739 740 cfgreg = pci_ocp_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2); 741 cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 742 PCIM_CMD_PORTEN; 743 pci_ocp_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2); 744 745 pci_ocp_outbound(sc, 0, -1, 0, 0, 0); 746 error = pci_ocp_iorange(sc, SYS_RES_MEMORY, 1); 747 error = pci_ocp_iorange(sc, SYS_RES_IOPORT, 2); 748 pci_ocp_outbound(sc, 3, -1, 0, 0, 0); 749 pci_ocp_outbound(sc, 4, -1, 0, 0, 0); 750 751 pci_ocp_inbound(sc, 1, -1, 0, 0, 0); 752 pci_ocp_inbound(sc, 2, -1, 0, 0, 0); 753 pci_ocp_inbound(sc, 3, OCP85XX_TGTIF_RAM1, 0, 2U*1024U*1024U*1024U, 0); 754 755 sc->sc_devfn_tundra = -1; 756 sc->sc_devfn_via_ide = -1; 757 758 /* 759 * PCI Express host controllers require a link. We don't 760 * fail the attach if there's no link, but we also don't 761 * create a child pci(4) device. 762 */ 763 if (sc->sc_pcie_cap) { 764 cfgreg = pci_ocp_cfgread(sc, 0, 0, 0, PCIR_FSL_LTSSM, 4); 765 if (cfgreg < FSL_LTSSM_L0) 766 return (0); 767 } 768 769 nslots = (sc->sc_pcie_cap) ? 1 : 32; 770 pci_ocp_init(sc, sc->sc_busnr, nslots); 771 772 device_add_child(dev, "pci", -1); 773 return (bus_generic_attach(dev)); 774 } 775 776 static struct resource * 777 pci_ocp_alloc_resource(device_t dev, device_t child, int type, int *rid, 778 u_long start, u_long end, u_long count, u_int flags) 779 { 780 struct pci_ocp_softc *sc = device_get_softc(dev); 781 struct rman *rm; 782 struct resource *res; 783 bus_addr_t va; 784 785 switch (type) { 786 case SYS_RES_IOPORT: 787 rm = &sc->sc_ioport; 788 va = sc->sc_ioport_va; 789 break; 790 case SYS_RES_MEMORY: 791 rm = &sc->sc_iomem; 792 va = sc->sc_iomem_va; 793 break; 794 case SYS_RES_IRQ: 795 if (start < PIC_IRQ_START) { 796 device_printf(dev, "%s requested ISA interrupt %lu\n", 797 device_get_nameunit(child), start); 798 } 799 flags |= RF_SHAREABLE; 800 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 801 type, rid, start, end, count, flags)); 802 default: 803 return (NULL); 804 } 805 806 res = rman_reserve_resource(rm, start, end, count, flags, child); 807 if (res == NULL) 808 return (NULL); 809 810 rman_set_bustag(res, &bs_le_tag); 811 rman_set_bushandle(res, va + rman_get_start(res) - rm->rm_start); 812 return (res); 813 } 814 815 static int 816 pci_ocp_release_resource(device_t dev, device_t child, int type, int rid, 817 struct resource *res) 818 { 819 820 return (rman_release_resource(res)); 821 } 822 823 static int 824 pci_ocp_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 825 { 826 struct pci_ocp_softc *sc = device_get_softc(dev); 827 828 switch (which) { 829 case PCIB_IVAR_BUS: 830 *result = sc->sc_busnr; 831 return (0); 832 case PCIB_IVAR_DOMAIN: 833 *result = device_get_unit(dev); 834 return (0); 835 } 836 return (ENOENT); 837 } 838 839 static int 840 pci_ocp_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 841 { 842 struct pci_ocp_softc *sc = device_get_softc(dev); 843 844 switch (which) { 845 case PCIB_IVAR_BUS: 846 sc->sc_busnr = value; 847 return (0); 848 } 849 return (ENOENT); 850 }
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