ata_macio.c

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    1 /*-
    2  * Copyright 2002 by Peter Grehan. All rights reserved.
    3  *
    4  * Redistribution and use in source and binary forms, with or without
    5  * modification, are permitted provided that the following conditions
    6  * are met:
    7  * 1. Redistributions of source code must retain the above copyright
    8  *    notice, this list of conditions and the following disclaimer.
    9  * 2. Redistributions in binary form must reproduce the above copyright
   10  *    notice, this list of conditions and the following disclaimer in the
   11  *    documentation and/or other materials provided with the distribution.
   12  * 3. The name of the author may not be used to endorse or promote products
   13  *    derived from this software without specific prior written permission.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
   20  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
   21  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
   22  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
   23  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  */
   27 
   28 #include <sys/cdefs.h>
   29 __FBSDID("$FreeBSD$");
   30 
   31 /*
   32  * Mac-io ATA controller
   33  */
   34 #include "opt_ata.h"
   35 #include <sys/param.h>
   36 #include <sys/systm.h>
   37 #include <sys/kernel.h>
   38 #include <sys/module.h>
   39 #include <sys/bus.h>
   40 #include <sys/malloc.h>
   41 #include <sys/sema.h>
   42 #include <sys/taskqueue.h>
   43 #include <vm/uma.h>
   44 #include <machine/stdarg.h>
   45 #include <machine/resource.h>
   46 #include <machine/bus.h>
   47 #include <sys/rman.h>
   48 #include <sys/ata.h>
   49 #include <dev/ata/ata-all.h>
   50 #include <ata_if.h>
   51 
   52 #include <dev/ofw/ofw_bus.h>
   53 
   54 #include "ata_dbdma.h"
   55 
   56 /*
   57  * Offset to control registers from base
   58  */
   59 #define ATA_MACIO_ALTOFFSET     0x160
   60 
   61 /*
   62  * Define the gap between registers
   63  */
   64 #define ATA_MACIO_REGGAP        16
   65 
   66 /*
   67  * Whether or not to bind to the DBDMA IRQ
   68  */
   69 #define USE_DBDMA_IRQ           0
   70 
   71 /*
   72  * Timing register
   73  */
   74 #define ATA_MACIO_TIMINGREG     0x200
   75 
   76 #define ATA_TIME_TO_TICK(rev,time) howmany(time, (rev == 4) ? 15 : 30)
   77 #define PIO_REC_OFFSET 4
   78 #define PIO_REC_MIN 1
   79 #define PIO_ACT_MIN 1
   80 #define DMA_REC_OFFSET 1
   81 #define DMA_REC_MIN 1
   82 #define DMA_ACT_MIN 1
   83 
   84 struct ide_timings {
   85         int cycle;      /* minimum cycle time [ns] */
   86         int active;     /* minimum command active time [ns] */
   87 };
   88 
   89 static const struct ide_timings pio_timings[5] = {
   90         { 600, 180 },   /* PIO 0 */
   91         { 390, 150 },   /* PIO 1 */
   92         { 240, 105 },   /* PIO 2 */
   93         { 180,  90 },   /* PIO 3 */
   94         { 120,  75 }    /* PIO 4 */
   95 };
   96 
   97 static const struct ide_timings dma_timings[3] = {
   98         { 480, 240 },   /* WDMA 0 */
   99         { 165,  90 },   /* WDMA 1 */
  100         { 120,  75 }    /* WDMA 2 */
  101 };
  102 
  103 static const struct ide_timings udma_timings[5] = {
  104         { 120, 180 },   /* UDMA 0 */
  105         {  90, 150 },   /* UDMA 1 */
  106         {  60, 120 },   /* UDMA 2 */
  107         {  45,  90 },   /* UDMA 3 */
  108         {  30,  90 }    /* UDMA 4 */
  109 };
  110 
  111 /*
  112  * Define the macio ata bus attachment.
  113  */
  114 static  int  ata_macio_probe(device_t dev);
  115 static  int  ata_macio_setmode(device_t dev, int target, int mode);
  116 static  int  ata_macio_attach(device_t dev);
  117 static  int  ata_macio_begin_transaction(struct ata_request *request);
  118 
  119 static device_method_t ata_macio_methods[] = {
  120         /* Device interface */
  121         DEVMETHOD(device_probe,         ata_macio_probe),
  122         DEVMETHOD(device_attach,        ata_macio_attach),
  123 
  124         /* ATA interface */
  125         DEVMETHOD(ata_setmode,          ata_macio_setmode),
  126         DEVMETHOD_END
  127 };
  128 
  129 struct ata_macio_softc {
  130         struct ata_dbdma_channel sc_ch;
  131 
  132         int rev;
  133         int max_mode;
  134         struct resource *sc_mem;
  135 
  136         uint32_t udmaconf[2];
  137         uint32_t wdmaconf[2];
  138         uint32_t pioconf[2];
  139 };
  140 
  141 static driver_t ata_macio_driver = {
  142         "ata",
  143         ata_macio_methods,
  144         sizeof(struct ata_macio_softc),
  145 };
  146 
  147 DRIVER_MODULE(ata, macio, ata_macio_driver, ata_devclass, NULL, NULL);
  148 MODULE_DEPEND(ata, ata, 1, 1, 1);
  149 
  150 static int
  151 ata_macio_probe(device_t dev)
  152 {
  153         const char *type = ofw_bus_get_type(dev);
  154         const char *name = ofw_bus_get_name(dev);
  155         struct ata_macio_softc *sc;
  156         struct ata_channel *ch;
  157         int rid, i;
  158 
  159         if (strcmp(type, "ata") != 0 &&
  160             strcmp(type, "ide") != 0)
  161                 return (ENXIO);
  162 
  163         sc = device_get_softc(dev);
  164         bzero(sc, sizeof(struct ata_macio_softc));
  165         ch = &sc->sc_ch.sc_ch;
  166 
  167         if (strcmp(name,"ata-4") == 0) {
  168                 device_set_desc(dev,"Apple MacIO Ultra ATA Controller");
  169                 sc->rev = 4;
  170                 sc->max_mode = ATA_UDMA4;
  171         } else {
  172                 device_set_desc(dev,"Apple MacIO ATA Controller");
  173                 sc->rev = 3;
  174                 sc->max_mode = ATA_WDMA2;
  175         }
  176 
  177         rid = 0;
  178         sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 
  179             RF_ACTIVE);
  180         if (sc->sc_mem == NULL) {
  181                 device_printf(dev, "could not allocate memory\n");
  182                 return (ENXIO);
  183         }
  184 
  185         /*
  186          * Set up the resource vectors
  187          */
  188         for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
  189                 ch->r_io[i].res = sc->sc_mem;
  190                 ch->r_io[i].offset = i * ATA_MACIO_REGGAP;
  191         }
  192         ch->r_io[ATA_CONTROL].res = sc->sc_mem;
  193         ch->r_io[ATA_CONTROL].offset = ATA_MACIO_ALTOFFSET;
  194         ata_default_registers(dev);
  195 
  196         ch->unit = 0;
  197         ch->flags |= ATA_USE_16BIT | ATA_NO_ATAPI_DMA;
  198         ata_generic_hw(dev);
  199 
  200         return (ata_probe(dev));
  201 }
  202 
  203 static int
  204 ata_macio_attach(device_t dev)
  205 {
  206         struct ata_macio_softc *sc = device_get_softc(dev);
  207         uint32_t timingreg;
  208 
  209 #if USE_DBDMA_IRQ
  210         int dbdma_irq_rid = 1;
  211         struct resource *dbdma_irq;
  212         void *cookie;
  213 #endif
  214 
  215         /* Init DMA engine */
  216 
  217         sc->sc_ch.dbdma_rid = 1;
  218         sc->sc_ch.dbdma_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 
  219             &sc->sc_ch.dbdma_rid, RF_ACTIVE); 
  220 
  221         ata_dbdma_dmainit(dev);
  222 
  223         /* Configure initial timings */
  224         timingreg = bus_read_4(sc->sc_mem, ATA_MACIO_TIMINGREG);
  225         if (sc->rev == 4) {
  226                 sc->udmaconf[0] = sc->udmaconf[1] = timingreg & 0x1ff00000;
  227                 sc->wdmaconf[0] = sc->wdmaconf[1] = timingreg & 0x001ffc00;
  228                 sc->pioconf[0]  = sc->pioconf[1]  = timingreg & 0x000003ff;
  229         } else {
  230                 sc->udmaconf[0] = sc->udmaconf[1] = 0;
  231                 sc->wdmaconf[0] = sc->wdmaconf[1] = timingreg & 0xfffff800;
  232                 sc->pioconf[0]  = sc->pioconf[1]  = timingreg & 0x000007ff;
  233         }
  234 
  235 #if USE_DBDMA_IRQ
  236         /* Bind to DBDMA interrupt as well */
  237 
  238         if ((dbdma_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
  239             &dbdma_irq_rid, RF_SHAREABLE | RF_ACTIVE)) != NULL) {
  240                 bus_setup_intr(dev, dbdma_irq, ATA_INTR_FLAGS, NULL,
  241                         (driver_intr_t *)ata_interrupt, sc,&cookie);
  242         } 
  243 #endif
  244 
  245         /* Set begin_transaction */
  246         sc->sc_ch.sc_ch.hw.begin_transaction = ata_macio_begin_transaction;
  247 
  248         return ata_attach(dev);
  249 }
  250 
  251 static int
  252 ata_macio_setmode(device_t dev, int target, int mode)
  253 {
  254         struct ata_macio_softc *sc = device_get_softc(dev);
  255 
  256         int min_cycle = 0, min_active = 0;
  257         int cycle_tick = 0, act_tick = 0, inact_tick = 0, half_tick;
  258 
  259         mode = min(mode, sc->max_mode);
  260 
  261         if ((mode & ATA_DMA_MASK) == ATA_UDMA0) {
  262                 min_cycle = udma_timings[mode & ATA_MODE_MASK].cycle;
  263                 min_active = udma_timings[mode & ATA_MODE_MASK].active;
  264         
  265                 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle);
  266                 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active);
  267 
  268                 /* mask: 0x1ff00000 */
  269                 sc->udmaconf[target] =
  270                     (cycle_tick << 21) | (act_tick << 25) | 0x100000;
  271         } else if ((mode & ATA_DMA_MASK) == ATA_WDMA0) {
  272                 min_cycle = dma_timings[mode & ATA_MODE_MASK].cycle;
  273                 min_active = dma_timings[mode & ATA_MODE_MASK].active;
  274         
  275                 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle);
  276                 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active);
  277 
  278                 if (sc->rev == 4) {
  279                         inact_tick = cycle_tick - act_tick;
  280                         /* mask: 0x001ffc00 */
  281                         sc->wdmaconf[target] = 
  282                             (act_tick << 10) | (inact_tick << 15);
  283                 } else {
  284                         inact_tick = cycle_tick - act_tick - DMA_REC_OFFSET;
  285                         if (inact_tick < DMA_REC_MIN)
  286                                 inact_tick = DMA_REC_MIN;
  287                         half_tick = 0;  /* XXX */
  288 
  289                         /* mask: 0xfffff800 */
  290                         sc->wdmaconf[target] = (half_tick << 21) 
  291                             | (inact_tick << 16) | (act_tick << 11);
  292                 }
  293         } else {
  294                 min_cycle = 
  295                     pio_timings[(mode & ATA_MODE_MASK) - ATA_PIO0].cycle;
  296                 min_active = 
  297                     pio_timings[(mode & ATA_MODE_MASK) - ATA_PIO0].active;
  298         
  299                 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle);
  300                 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active);
  301 
  302                 if (sc->rev == 4) {
  303                         inact_tick = cycle_tick - act_tick;
  304 
  305                         /* mask: 0x000003ff */
  306                         sc->pioconf[target] =
  307                             (inact_tick << 5) | act_tick;
  308                 } else {
  309                         if (act_tick < PIO_ACT_MIN)
  310                                 act_tick = PIO_ACT_MIN;
  311 
  312                         inact_tick = cycle_tick - act_tick - PIO_REC_OFFSET;
  313                         if (inact_tick < PIO_REC_MIN)
  314                                 inact_tick = PIO_REC_MIN;
  315 
  316                         /* mask: 0x000007ff */
  317                         sc->pioconf[target] = 
  318                             (inact_tick << 5) | act_tick;
  319                 }
  320         }
  321 
  322         return (mode);
  323 }
  324 
  325 static int
  326 ata_macio_begin_transaction(struct ata_request *request)
  327 {
  328         struct ata_macio_softc *sc = device_get_softc(request->parent);
  329 
  330         bus_write_4(sc->sc_mem, ATA_MACIO_TIMINGREG, 
  331             sc->udmaconf[request->unit] | sc->wdmaconf[request->unit] 
  332             | sc->pioconf[request->unit]); 
  333 
  334         return ata_begin_transaction(request);
  335 }
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