1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2012 Justin Hibbits
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/systm.h>
35 #include <sys/module.h>
36 #include <sys/kernel.h>
37 #include <sys/rman.h>
38 #include <sys/sysctl.h>
39
40 #include <machine/bus.h>
41
42 #include <dev/ofw/openfirm.h>
43 #include <dev/pci/pcivar.h>
44
45 #ifndef PCI_VENDOR_ID_ATI
46 #define PCI_VENDOR_ID_ATI 0x1002
47 #endif
48
49 /* From the xf86-video-ati driver's radeon_reg.h */
50 #define RADEON_LVDS_GEN_CNTL 0x02d0
51 #define RADEON_LVDS_ON (1 << 0)
52 #define RADEON_LVDS_DISPLAY_DIS (1 << 1)
53 #define RADEON_LVDS_PANEL_TYPE (1 << 2)
54 #define RADEON_LVDS_PANEL_FORMAT (1 << 3)
55 #define RADEON_LVDS_RST_FM (1 << 6)
56 #define RADEON_LVDS_EN (1 << 7)
57 #define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8
58 #define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8)
59 #define RADEON_LVDS_BL_MOD_EN (1 << 16)
60 #define RADEON_LVDS_DIGON (1 << 18)
61 #define RADEON_LVDS_BLON (1 << 19)
62 #define RADEON_LVDS_PLL_CNTL 0x02d4
63 #define RADEON_LVDS_PLL_EN (1 << 16)
64 #define RADEON_LVDS_PLL_RESET (1 << 17)
65 #define RADEON_PIXCLKS_CNTL 0x002d
66 #define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14)
67 #define RADEON_DISP_PWR_MAN 0x0d08
68 #define RADEON_AUTO_PWRUP_EN (1 << 26)
69 #define RADEON_CLOCK_CNTL_DATA 0x000c
70 #define RADEON_CLOCK_CNTL_INDEX 0x0008
71 #define RADEON_PLL_WR_EN (1 << 7)
72 #define RADEON_CRTC_GEN_CNTL 0x0050
73
74 struct atibl_softc {
75 struct resource *sc_memr;
76 int sc_level;
77 };
78
79 static void atibl_identify(driver_t *driver, device_t parent);
80 static int atibl_probe(device_t dev);
81 static int atibl_attach(device_t dev);
82 static int atibl_setlevel(struct atibl_softc *sc, int newlevel);
83 static int atibl_getlevel(struct atibl_softc *sc);
84 static int atibl_resume(device_t dev);
85 static int atibl_suspend(device_t dev);
86 static int atibl_sysctl(SYSCTL_HANDLER_ARGS);
87
88 static device_method_t atibl_methods[] = {
89 /* Device interface */
90 DEVMETHOD(device_identify, atibl_identify),
91 DEVMETHOD(device_probe, atibl_probe),
92 DEVMETHOD(device_attach, atibl_attach),
93 DEVMETHOD(device_suspend, atibl_suspend),
94 DEVMETHOD(device_resume, atibl_resume),
95 {0, 0},
96 };
97
98 static driver_t atibl_driver = {
99 "backlight",
100 atibl_methods,
101 sizeof(struct atibl_softc)
102 };
103
104 DRIVER_MODULE(atibl, vgapci, atibl_driver, 0, 0);
105
106 static void
107 atibl_identify(driver_t *driver, device_t parent)
108 {
109 if (OF_finddevice("mac-io/backlight") == -1)
110 return;
111 if (device_find_child(parent, "backlight", -1) == NULL)
112 device_add_child(parent, "backlight", -1);
113 }
114
115 static int
116 atibl_probe(device_t dev)
117 {
118 char control[8];
119 phandle_t handle;
120
121 handle = OF_finddevice("mac-io/backlight");
122
123 if (handle == -1)
124 return (ENXIO);
125
126 if (OF_getprop(handle, "backlight-control", &control, sizeof(control)) < 0)
127 return (ENXIO);
128
129 if (strcmp(control, "ati") != 0 &&
130 (strcmp(control, "mnca") != 0 ||
131 pci_get_vendor(device_get_parent(dev)) != 0x1002))
132 return (ENXIO);
133
134 device_set_desc(dev, "PowerBook backlight for ATI graphics");
135
136 return (0);
137 }
138
139 static int
140 atibl_attach(device_t dev)
141 {
142 struct atibl_softc *sc;
143 struct sysctl_ctx_list *ctx;
144 struct sysctl_oid *tree;
145 int rid;
146
147 sc = device_get_softc(dev);
148
149 rid = 0x18; /* BAR[2], for the MMIO register */
150 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
151 RF_ACTIVE | RF_SHAREABLE);
152 if (sc->sc_memr == NULL) {
153 device_printf(dev, "Could not alloc mem resource!\n");
154 return (ENXIO);
155 }
156
157 ctx = device_get_sysctl_ctx(dev);
158 tree = device_get_sysctl_tree(dev);
159
160 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
161 "level", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
162 atibl_sysctl, "I", "Backlight level (0-100)");
163
164 return (0);
165 }
166
167 static uint32_t __inline
168 atibl_pll_rreg(struct atibl_softc *sc, uint32_t reg)
169 {
170 uint32_t data, save, tmp;
171
172 bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, (reg & 0x3f));
173 (void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
174 (void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL);
175
176 data = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
177
178 /* Only necessary on R300, but won't hurt others. */
179 save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX);
180 tmp = save & (~0x3f | RADEON_PLL_WR_EN);
181 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, tmp);
182 tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
183 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, save);
184
185 return data;
186 }
187
188 static void __inline
189 atibl_pll_wreg(struct atibl_softc *sc, uint32_t reg, uint32_t val)
190 {
191 uint32_t save, tmp;
192
193 bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX,
194 ((reg & 0x3f) | RADEON_PLL_WR_EN));
195 (void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
196 (void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL);
197
198 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA, val);
199 DELAY(5000);
200
201 /* Only necessary on R300, but won't hurt others. */
202 save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX);
203 tmp = save & (~0x3f | RADEON_PLL_WR_EN);
204 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, tmp);
205 tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
206 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, save);
207 }
208
209 static int
210 atibl_setlevel(struct atibl_softc *sc, int newlevel)
211 {
212 uint32_t lvds_gen_cntl;
213 uint32_t lvds_pll_cntl;
214 uint32_t pixclks_cntl;
215 uint32_t disp_pwr_reg;
216
217 if (newlevel > 100)
218 newlevel = 100;
219
220 if (newlevel < 0)
221 newlevel = 0;
222
223 lvds_gen_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL);
224
225 if (newlevel > 0) {
226 newlevel = (newlevel * 5) / 2 + 5;
227 disp_pwr_reg = bus_read_4(sc->sc_memr, RADEON_DISP_PWR_MAN);
228 disp_pwr_reg |= RADEON_AUTO_PWRUP_EN;
229 bus_write_4(sc->sc_memr, RADEON_DISP_PWR_MAN, disp_pwr_reg);
230 lvds_pll_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL);
231 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
232 bus_write_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
233 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
234 bus_write_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
235 DELAY(1000);
236
237 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS |
238 RADEON_LVDS_BL_MOD_LEVEL_MASK);
239 lvds_gen_cntl |= RADEON_LVDS_ON | RADEON_LVDS_EN |
240 RADEON_LVDS_DIGON | RADEON_LVDS_BLON;
241 lvds_gen_cntl |= (newlevel << RADEON_LVDS_BL_MOD_LEVEL_SHIFT) &
242 RADEON_LVDS_BL_MOD_LEVEL_MASK;
243 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
244 DELAY(200000);
245 bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
246 } else {
247 pixclks_cntl = atibl_pll_rreg(sc, RADEON_PIXCLKS_CNTL);
248 atibl_pll_wreg(sc, RADEON_PIXCLKS_CNTL,
249 pixclks_cntl & ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
250 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
251 lvds_gen_cntl &= ~(RADEON_LVDS_BL_MOD_EN | RADEON_LVDS_BL_MOD_LEVEL_MASK);
252 bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
253 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
254 DELAY(200000);
255 bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
256
257 atibl_pll_wreg(sc, RADEON_PIXCLKS_CNTL, pixclks_cntl);
258 DELAY(200000);
259 }
260
261 return (0);
262 }
263
264 static int
265 atibl_getlevel(struct atibl_softc *sc)
266 {
267 uint32_t lvds_gen_cntl;
268 int level;
269
270 lvds_gen_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL);
271
272 level = ((lvds_gen_cntl & RADEON_LVDS_BL_MOD_LEVEL_MASK) >>
273 RADEON_LVDS_BL_MOD_LEVEL_SHIFT);
274 if (level != 0)
275 level = ((level - 5) * 2) / 5;
276
277 return (level);
278 }
279
280 static int
281 atibl_suspend(device_t dev)
282 {
283 struct atibl_softc *sc;
284
285 sc = device_get_softc(dev);
286
287 sc->sc_level = atibl_getlevel(sc);
288 atibl_setlevel(sc, 0);
289
290 return (0);
291 }
292
293 static int
294 atibl_resume(device_t dev)
295 {
296 struct atibl_softc *sc;
297
298 sc = device_get_softc(dev);
299
300 atibl_setlevel(sc, sc->sc_level);
301
302 return (0);
303 }
304
305 static int
306 atibl_sysctl(SYSCTL_HANDLER_ARGS)
307 {
308 struct atibl_softc *sc;
309 int newlevel, error;
310
311 sc = arg1;
312
313 newlevel = atibl_getlevel(sc);
314
315 error = sysctl_handle_int(oidp, &newlevel, 0, req);
316
317 if (error || !req->newptr)
318 return (error);
319
320 return (atibl_setlevel(sc, newlevel));
321 }
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