Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/powerpc/powermac/cpcht.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2008-2010 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/module.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/pciio.h> 40 #include <sys/rman.h> 41 42 #include <dev/ofw/openfirm.h> 43 #include <dev/ofw/ofw_pci.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 48 #include <machine/bus.h> 49 #include <machine/intr_machdep.h> 50 #include <machine/md_var.h> 51 #include <machine/openpicreg.h> 52 #include <machine/openpicvar.h> 53 #include <machine/pio.h> 54 #include <machine/resource.h> 55 56 #include <dev/ofw/ofw_bus.h> 57 #include <dev/ofw/ofw_bus_subr.h> 58 #include <dev/ofw/ofwpci.h> 59 60 #include <vm/vm.h> 61 #include <vm/pmap.h> 62 63 #include "pcib_if.h" 64 #include <dev/pci/pcib_private.h> 65 #include "pic_if.h" 66 67 /* 68 * IBM CPC9X5 Hypertransport Device interface. 69 */ 70 static int cpcht_probe(device_t); 71 static int cpcht_attach(device_t); 72 73 static void cpcht_configure_htbridge(device_t, phandle_t); 74 75 /* 76 * pcib interface. 77 */ 78 static u_int32_t cpcht_read_config(device_t, u_int, u_int, u_int, 79 u_int, int); 80 static void cpcht_write_config(device_t, u_int, u_int, u_int, 81 u_int, u_int32_t, int); 82 static int cpcht_route_interrupt(device_t, device_t, int); 83 static int cpcht_alloc_msi(device_t dev, device_t child, 84 int count, int maxcount, int *irqs); 85 static int cpcht_release_msi(device_t dev, device_t child, 86 int count, int *irqs); 87 static int cpcht_alloc_msix(device_t dev, device_t child, 88 int *irq); 89 static int cpcht_release_msix(device_t dev, device_t child, 90 int irq); 91 static int cpcht_map_msi(device_t dev, device_t child, 92 int irq, uint64_t *addr, uint32_t *data); 93 94 /* 95 * Driver methods. 96 */ 97 static device_method_t cpcht_methods[] = { 98 /* Device interface */ 99 DEVMETHOD(device_probe, cpcht_probe), 100 DEVMETHOD(device_attach, cpcht_attach), 101 102 /* pcib interface */ 103 DEVMETHOD(pcib_read_config, cpcht_read_config), 104 DEVMETHOD(pcib_write_config, cpcht_write_config), 105 DEVMETHOD(pcib_route_interrupt, cpcht_route_interrupt), 106 DEVMETHOD(pcib_alloc_msi, cpcht_alloc_msi), 107 DEVMETHOD(pcib_release_msi, cpcht_release_msi), 108 DEVMETHOD(pcib_alloc_msix, cpcht_alloc_msix), 109 DEVMETHOD(pcib_release_msix, cpcht_release_msix), 110 DEVMETHOD(pcib_map_msi, cpcht_map_msi), 111 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), 112 113 DEVMETHOD_END 114 }; 115 116 struct cpcht_irq { 117 enum { 118 IRQ_NONE, IRQ_HT, IRQ_MSI, IRQ_INTERNAL 119 } irq_type; 120 121 int ht_source; 122 123 vm_offset_t ht_base; 124 vm_offset_t apple_eoi; 125 uint32_t eoi_data; 126 int edge; 127 }; 128 129 static struct cpcht_irq *cpcht_irqmap = NULL; 130 uint32_t cpcht_msipic = 0; 131 132 struct cpcht_softc { 133 struct ofw_pci_softc pci_sc; 134 vm_offset_t sc_data; 135 uint64_t sc_populated_slots; 136 137 struct cpcht_irq htirq_map[128]; 138 struct mtx htirq_mtx; 139 }; 140 141 DEFINE_CLASS_1(pcib, cpcht_driver, cpcht_methods, sizeof(struct cpcht_softc), 142 ofw_pcib_driver); 143 EARLY_DRIVER_MODULE(cpcht, ofwbus, cpcht_driver, 0, 0, BUS_PASS_BUS); 144 145 #define CPCHT_IOPORT_BASE 0xf4000000UL /* Hardwired */ 146 #define CPCHT_IOPORT_SIZE 0x00400000UL 147 148 #define HTAPIC_REQUEST_EOI 0x20 149 #define HTAPIC_TRIGGER_LEVEL 0x02 150 #define HTAPIC_MASK 0x01 151 152 static int 153 cpcht_probe(device_t dev) 154 { 155 const char *type, *compatible; 156 157 type = ofw_bus_get_type(dev); 158 compatible = ofw_bus_get_compat(dev); 159 160 if (type == NULL || compatible == NULL) 161 return (ENXIO); 162 163 if (strcmp(type, "ht") != 0) 164 return (ENXIO); 165 166 if (strcmp(compatible, "u3-ht") != 0) 167 return (ENXIO); 168 169 device_set_desc(dev, "IBM CPC9X5 HyperTransport Tunnel"); 170 return (0); 171 } 172 173 static int 174 cpcht_attach(device_t dev) 175 { 176 struct cpcht_softc *sc; 177 phandle_t node, child; 178 u_int32_t reg[3]; 179 int i; 180 181 node = ofw_bus_get_node(dev); 182 sc = device_get_softc(dev); 183 184 if (OF_getencprop(node, "reg", reg, sizeof(reg)) < 12) 185 return (ENXIO); 186 187 if (OF_getproplen(node, "ranges") <= 0) 188 sc->pci_sc.sc_quirks = OFW_PCI_QUIRK_RANGES_ON_CHILDREN; 189 sc->sc_populated_slots = 0; 190 sc->sc_data = (vm_offset_t)pmap_mapdev(reg[1], reg[2]); 191 192 /* 193 * Set up the resource manager and the HT->MPIC mapping. For cpcht, 194 * the ranges are properties of the child bridges, and this is also 195 * where we get the HT interrupts properties. 196 */ 197 198 #if 0 199 /* I/O port mappings are usually not in the device tree */ 200 rman_manage_region(&sc->pci_sc.sc_io_rman, 0, CPCHT_IOPORT_SIZE - 1); 201 #endif 202 203 bzero(sc->htirq_map, sizeof(sc->htirq_map)); 204 mtx_init(&sc->htirq_mtx, "cpcht irq", NULL, MTX_DEF); 205 for (i = 0; i < 8; i++) 206 sc->htirq_map[i].irq_type = IRQ_INTERNAL; 207 for (child = OF_child(node); child != 0; child = OF_peer(child)) 208 cpcht_configure_htbridge(dev, child); 209 210 /* Now make the mapping table available to the MPIC */ 211 cpcht_irqmap = sc->htirq_map; 212 213 return (ofw_pcib_attach(dev)); 214 } 215 216 static void 217 cpcht_configure_htbridge(device_t dev, phandle_t child) 218 { 219 struct cpcht_softc *sc; 220 struct ofw_pci_register pcir; 221 int ptr, nextptr; 222 uint32_t vend, val; 223 int i, nirq, irq; 224 u_int b, f, s; 225 226 sc = device_get_softc(dev); 227 if (OF_getencprop(child, "reg", (pcell_t *)&pcir, sizeof(pcir)) == -1) 228 return; 229 230 b = OFW_PCI_PHYS_HI_BUS(pcir.phys_hi); 231 s = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi); 232 f = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi); 233 234 /* 235 * Mark this slot is populated. The remote south bridge does 236 * not like us talking to unpopulated slots on the root bus. 237 */ 238 sc->sc_populated_slots |= (1 << s); 239 240 /* 241 * Next build up any HT->MPIC mappings for this sub-bus. One would 242 * naively hope that enabling, disabling, and EOIing interrupts would 243 * cause the appropriate HT bus transactions to that effect. This is 244 * not the case. 245 * 246 * Instead, we have to muck about on the HT peer's root PCI bridges, 247 * figure out what interrupts they send, enable them, and cache 248 * the location of their WaitForEOI registers so that we can 249 * send EOIs later. 250 */ 251 252 /* All the devices we are interested in have caps */ 253 if (!(PCIB_READ_CONFIG(dev, b, s, f, PCIR_STATUS, 2) 254 & PCIM_STATUS_CAPPRESENT)) 255 return; 256 257 nextptr = PCIB_READ_CONFIG(dev, b, s, f, PCIR_CAP_PTR, 1); 258 while (nextptr != 0) { 259 ptr = nextptr; 260 nextptr = PCIB_READ_CONFIG(dev, b, s, f, 261 ptr + PCICAP_NEXTPTR, 1); 262 263 /* Find the HT IRQ capabilities */ 264 if (PCIB_READ_CONFIG(dev, b, s, f, 265 ptr + PCICAP_ID, 1) != PCIY_HT) 266 continue; 267 268 val = PCIB_READ_CONFIG(dev, b, s, f, ptr + PCIR_HT_COMMAND, 2); 269 if ((val & PCIM_HTCMD_CAP_MASK) != PCIM_HTCAP_INTERRUPT) 270 continue; 271 272 /* Ask for the IRQ count */ 273 PCIB_WRITE_CONFIG(dev, b, s, f, ptr + PCIR_HT_COMMAND, 0x1, 1); 274 nirq = PCIB_READ_CONFIG(dev, b, s, f, ptr + 4, 4); 275 nirq = ((nirq >> 16) & 0xff) + 1; 276 277 device_printf(dev, "%d HT IRQs on device %d.%d\n", nirq, s, f); 278 279 for (i = 0; i < nirq; i++) { 280 PCIB_WRITE_CONFIG(dev, b, s, f, 281 ptr + PCIR_HT_COMMAND, 0x10 + (i << 1), 1); 282 irq = PCIB_READ_CONFIG(dev, b, s, f, ptr + 4, 4); 283 284 /* 285 * Mask this interrupt for now. 286 */ 287 PCIB_WRITE_CONFIG(dev, b, s, f, ptr + 4, 288 irq | HTAPIC_MASK, 4); 289 irq = (irq >> 16) & 0xff; 290 291 sc->htirq_map[irq].irq_type = IRQ_HT; 292 sc->htirq_map[irq].ht_source = i; 293 sc->htirq_map[irq].ht_base = sc->sc_data + 294 (((((s & 0x1f) << 3) | (f & 0x07)) << 8) | (ptr)); 295 296 PCIB_WRITE_CONFIG(dev, b, s, f, 297 ptr + PCIR_HT_COMMAND, 0x11 + (i << 1), 1); 298 sc->htirq_map[irq].eoi_data = 299 PCIB_READ_CONFIG(dev, b, s, f, ptr + 4, 4) | 300 0x80000000; 301 302 /* 303 * Apple uses a non-compliant IO/APIC that differs 304 * in how we signal EOIs. Check if this device was 305 * made by Apple, and act accordingly. 306 */ 307 vend = PCIB_READ_CONFIG(dev, b, s, f, 308 PCIR_DEVVENDOR, 4); 309 if ((vend & 0xffff) == 0x106b) 310 sc->htirq_map[irq].apple_eoi = 311 (sc->htirq_map[irq].ht_base - ptr) + 0x60; 312 } 313 } 314 } 315 316 static u_int32_t 317 cpcht_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 318 int width) 319 { 320 struct cpcht_softc *sc; 321 vm_offset_t caoff; 322 323 sc = device_get_softc(dev); 324 caoff = sc->sc_data + 325 (((((slot & 0x1f) << 3) | (func & 0x07)) << 8) | reg); 326 327 if (bus == 0 && (!(sc->sc_populated_slots & (1 << slot)) || func > 0)) 328 return (0xffffffff); 329 330 if (bus > 0) 331 caoff += 0x01000000UL + (bus << 16); 332 333 switch (width) { 334 case 1: 335 return (in8rb(caoff)); 336 break; 337 case 2: 338 return (in16rb(caoff)); 339 break; 340 case 4: 341 return (in32rb(caoff)); 342 break; 343 } 344 345 return (0xffffffff); 346 } 347 348 static void 349 cpcht_write_config(device_t dev, u_int bus, u_int slot, u_int func, 350 u_int reg, u_int32_t val, int width) 351 { 352 struct cpcht_softc *sc; 353 vm_offset_t caoff; 354 355 sc = device_get_softc(dev); 356 caoff = sc->sc_data + 357 (((((slot & 0x1f) << 3) | (func & 0x07)) << 8) | reg); 358 359 if (bus == 0 && (!(sc->sc_populated_slots & (1 << slot)) || func > 0)) 360 return; 361 362 if (bus > 0) 363 caoff += 0x01000000UL + (bus << 16); 364 365 switch (width) { 366 case 1: 367 out8rb(caoff, val); 368 break; 369 case 2: 370 out16rb(caoff, val); 371 break; 372 case 4: 373 out32rb(caoff, val); 374 break; 375 } 376 } 377 378 static int 379 cpcht_route_interrupt(device_t bus, device_t dev, int pin) 380 { 381 return (pin); 382 } 383 384 static int 385 cpcht_alloc_msi(device_t dev, device_t child, int count, int maxcount, 386 int *irqs) 387 { 388 struct cpcht_softc *sc; 389 int i, j; 390 391 sc = device_get_softc(dev); 392 j = 0; 393 394 /* Bail if no MSI PIC yet */ 395 if (cpcht_msipic == 0) 396 return (ENXIO); 397 398 mtx_lock(&sc->htirq_mtx); 399 for (i = 8; i < 124 - count; i++) { 400 for (j = 0; j < count; j++) { 401 if (sc->htirq_map[i+j].irq_type != IRQ_NONE) 402 break; 403 } 404 if (j == count) 405 break; 406 407 i += j; /* We know there isn't a large enough run */ 408 } 409 410 if (j != count) { 411 mtx_unlock(&sc->htirq_mtx); 412 return (ENXIO); 413 } 414 415 for (j = 0; j < count; j++) { 416 irqs[j] = MAP_IRQ(cpcht_msipic, i+j); 417 sc->htirq_map[i+j].irq_type = IRQ_MSI; 418 } 419 mtx_unlock(&sc->htirq_mtx); 420 421 return (0); 422 } 423 424 static int 425 cpcht_release_msi(device_t dev, device_t child, int count, int *irqs) 426 { 427 struct cpcht_softc *sc; 428 int i; 429 430 sc = device_get_softc(dev); 431 432 mtx_lock(&sc->htirq_mtx); 433 for (i = 0; i < count; i++) 434 sc->htirq_map[irqs[i] & 0xff].irq_type = IRQ_NONE; 435 mtx_unlock(&sc->htirq_mtx); 436 437 return (0); 438 } 439 440 static int 441 cpcht_alloc_msix(device_t dev, device_t child, int *irq) 442 { 443 struct cpcht_softc *sc; 444 int i; 445 446 sc = device_get_softc(dev); 447 448 /* Bail if no MSI PIC yet */ 449 if (cpcht_msipic == 0) 450 return (ENXIO); 451 452 mtx_lock(&sc->htirq_mtx); 453 for (i = 8; i < 124; i++) { 454 if (sc->htirq_map[i].irq_type == IRQ_NONE) { 455 sc->htirq_map[i].irq_type = IRQ_MSI; 456 *irq = MAP_IRQ(cpcht_msipic, i); 457 458 mtx_unlock(&sc->htirq_mtx); 459 return (0); 460 } 461 } 462 mtx_unlock(&sc->htirq_mtx); 463 464 return (ENXIO); 465 } 466 467 static int 468 cpcht_release_msix(device_t dev, device_t child, int irq) 469 { 470 struct cpcht_softc *sc; 471 472 sc = device_get_softc(dev); 473 474 mtx_lock(&sc->htirq_mtx); 475 sc->htirq_map[irq & 0xff].irq_type = IRQ_NONE; 476 mtx_unlock(&sc->htirq_mtx); 477 478 return (0); 479 } 480 481 static int 482 cpcht_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, 483 uint32_t *data) 484 { 485 device_t pcib; 486 struct pci_devinfo *dinfo; 487 struct pcicfg_ht *ht = NULL; 488 489 for (pcib = child; pcib != dev; pcib = 490 device_get_parent(device_get_parent(pcib))) { 491 dinfo = device_get_ivars(pcib); 492 ht = &dinfo->cfg.ht; 493 494 if (ht == NULL) 495 continue; 496 } 497 498 if (ht == NULL) 499 return (ENXIO); 500 501 *addr = ht->ht_msiaddr; 502 *data = irq & 0xff; 503 504 return (0); 505 } 506 507 /* 508 * Driver for the integrated MPIC on U3/U4 (CPC925/CPC945) 509 */ 510 511 static int openpic_cpcht_probe(device_t); 512 static int openpic_cpcht_attach(device_t); 513 static void openpic_cpcht_config(device_t, u_int irq, 514 enum intr_trigger trig, enum intr_polarity pol); 515 static void openpic_cpcht_enable(device_t, u_int irq, u_int vector, 516 void **priv); 517 static void openpic_cpcht_unmask(device_t, u_int irq, void *priv); 518 static void openpic_cpcht_eoi(device_t, u_int irq, void *priv); 519 520 static device_method_t openpic_cpcht_methods[] = { 521 /* Device interface */ 522 DEVMETHOD(device_probe, openpic_cpcht_probe), 523 DEVMETHOD(device_attach, openpic_cpcht_attach), 524 525 /* PIC interface */ 526 DEVMETHOD(pic_bind, openpic_bind), 527 DEVMETHOD(pic_config, openpic_cpcht_config), 528 DEVMETHOD(pic_dispatch, openpic_dispatch), 529 DEVMETHOD(pic_enable, openpic_cpcht_enable), 530 DEVMETHOD(pic_eoi, openpic_cpcht_eoi), 531 DEVMETHOD(pic_ipi, openpic_ipi), 532 DEVMETHOD(pic_mask, openpic_mask), 533 DEVMETHOD(pic_unmask, openpic_cpcht_unmask), 534 535 { 0, 0 }, 536 }; 537 538 struct openpic_cpcht_softc { 539 struct openpic_softc sc_openpic; 540 541 struct mtx sc_ht_mtx; 542 }; 543 544 static driver_t openpic_cpcht_driver = { 545 "htpic", 546 openpic_cpcht_methods, 547 sizeof(struct openpic_cpcht_softc), 548 }; 549 550 EARLY_DRIVER_MODULE(openpic, unin, openpic_cpcht_driver, 0, 0, 551 BUS_PASS_INTERRUPT); 552 553 static int 554 openpic_cpcht_probe(device_t dev) 555 { 556 const char *type = ofw_bus_get_type(dev); 557 558 if (strcmp(type, "open-pic") != 0) 559 return (ENXIO); 560 561 device_set_desc(dev, OPENPIC_DEVSTR); 562 return (0); 563 } 564 565 static int 566 openpic_cpcht_attach(device_t dev) 567 { 568 struct openpic_cpcht_softc *sc; 569 phandle_t node; 570 int err, irq; 571 572 node = ofw_bus_get_node(dev); 573 err = openpic_common_attach(dev, node); 574 if (err != 0) 575 return (err); 576 577 /* 578 * The HT APIC stuff is not thread-safe, so we need a mutex to 579 * protect it. 580 */ 581 sc = device_get_softc(dev); 582 mtx_init(&sc->sc_ht_mtx, "htpic", NULL, MTX_SPIN); 583 584 /* 585 * Interrupts 0-3 are internally sourced and are level triggered 586 * active low. Interrupts 4-123 are connected to a pulse generator 587 * and should be programmed as edge triggered low-to-high. 588 * 589 * IBM CPC945 Manual, Section 9.3. 590 */ 591 592 for (irq = 0; irq < 4; irq++) 593 openpic_config(dev, irq, INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW); 594 for (irq = 4; irq < 124; irq++) 595 openpic_config(dev, irq, INTR_TRIGGER_EDGE, INTR_POLARITY_LOW); 596 597 /* 598 * Use this PIC for MSI only if it is the root PIC. This may not 599 * be necessary, but Linux does it, and I cannot find any U3 machines 600 * with MSI devices to test. 601 */ 602 if (dev == root_pic) 603 cpcht_msipic = node; 604 605 return (0); 606 } 607 608 static void 609 openpic_cpcht_config(device_t dev, u_int irq, enum intr_trigger trig, 610 enum intr_polarity pol) 611 { 612 struct openpic_cpcht_softc *sc; 613 uint32_t ht_irq; 614 615 /* 616 * The interrupt settings for the MPIC are completely determined 617 * by the internal wiring in the northbridge. Real changes to these 618 * settings need to be negotiated with the remote IO-APIC on the HT 619 * link. 620 */ 621 622 sc = device_get_softc(dev); 623 624 if (cpcht_irqmap != NULL && irq < 128 && 625 cpcht_irqmap[irq].ht_base > 0 && !cpcht_irqmap[irq].edge) { 626 mtx_lock_spin(&sc->sc_ht_mtx); 627 628 /* Program the data port */ 629 out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND, 630 0x10 + (cpcht_irqmap[irq].ht_source << 1)); 631 632 /* Grab the IRQ config register */ 633 ht_irq = in32rb(cpcht_irqmap[irq].ht_base + 4); 634 635 /* Mask the IRQ while we fiddle settings */ 636 out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq | HTAPIC_MASK); 637 638 /* Program the interrupt sense */ 639 ht_irq &= ~(HTAPIC_TRIGGER_LEVEL | HTAPIC_REQUEST_EOI); 640 if (trig == INTR_TRIGGER_EDGE) { 641 cpcht_irqmap[irq].edge = 1; 642 } else { 643 cpcht_irqmap[irq].edge = 0; 644 ht_irq |= HTAPIC_TRIGGER_LEVEL | HTAPIC_REQUEST_EOI; 645 } 646 out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq); 647 648 mtx_unlock_spin(&sc->sc_ht_mtx); 649 } 650 } 651 652 static void 653 openpic_cpcht_enable(device_t dev, u_int irq, u_int vec, void **priv) 654 { 655 struct openpic_cpcht_softc *sc; 656 uint32_t ht_irq; 657 658 openpic_enable(dev, irq, vec, priv); 659 660 sc = device_get_softc(dev); 661 662 if (cpcht_irqmap != NULL && irq < 128 && 663 cpcht_irqmap[irq].ht_base > 0) { 664 mtx_lock_spin(&sc->sc_ht_mtx); 665 666 /* Program the data port */ 667 out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND, 668 0x10 + (cpcht_irqmap[irq].ht_source << 1)); 669 670 /* Unmask the interrupt */ 671 ht_irq = in32rb(cpcht_irqmap[irq].ht_base + 4); 672 ht_irq &= ~HTAPIC_MASK; 673 out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq); 674 675 mtx_unlock_spin(&sc->sc_ht_mtx); 676 } 677 678 openpic_cpcht_eoi(dev, irq, *priv); 679 } 680 681 static void 682 openpic_cpcht_unmask(device_t dev, u_int irq, void *priv) 683 { 684 struct openpic_cpcht_softc *sc; 685 uint32_t ht_irq; 686 687 openpic_unmask(dev, irq, priv); 688 689 sc = device_get_softc(dev); 690 691 if (cpcht_irqmap != NULL && irq < 128 && 692 cpcht_irqmap[irq].ht_base > 0) { 693 mtx_lock_spin(&sc->sc_ht_mtx); 694 695 /* Program the data port */ 696 out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND, 697 0x10 + (cpcht_irqmap[irq].ht_source << 1)); 698 699 /* Unmask the interrupt */ 700 ht_irq = in32rb(cpcht_irqmap[irq].ht_base + 4); 701 ht_irq &= ~HTAPIC_MASK; 702 out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq); 703 704 mtx_unlock_spin(&sc->sc_ht_mtx); 705 } 706 707 openpic_cpcht_eoi(dev, irq, priv); 708 } 709 710 static void 711 openpic_cpcht_eoi(device_t dev, u_int irq, void *priv) 712 { 713 struct openpic_cpcht_softc *sc; 714 uint32_t off, mask; 715 716 if (irq == 255) 717 return; 718 719 sc = device_get_softc(dev); 720 721 if (cpcht_irqmap != NULL && irq < 128 && 722 cpcht_irqmap[irq].ht_base > 0 && !cpcht_irqmap[irq].edge) { 723 /* If this is an HT IRQ, acknowledge it at the remote APIC */ 724 725 if (cpcht_irqmap[irq].apple_eoi) { 726 off = (cpcht_irqmap[irq].ht_source >> 3) & ~3; 727 mask = 1 << (cpcht_irqmap[irq].ht_source & 0x1f); 728 out32rb(cpcht_irqmap[irq].apple_eoi + off, mask); 729 } else { 730 mtx_lock_spin(&sc->sc_ht_mtx); 731 732 out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND, 733 0x11 + (cpcht_irqmap[irq].ht_source << 1)); 734 out32rb(cpcht_irqmap[irq].ht_base + 4, 735 cpcht_irqmap[irq].eoi_data); 736 737 mtx_unlock_spin(&sc->sc_ht_mtx); 738 } 739 } 740 741 openpic_eoi(dev, irq, priv); 742 }
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