1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2008 Nathan Whitehorn
5 * All rights reserved
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 */
30
31 #ifndef _POWERPC_POWERMAC_DBDMAVAR_H_
32 #define _POWERPC_POWERMAC_DBDMAVAR_H_
33
34 struct dbdma_command {
35 uint8_t cmd:4; /* DBDMA command */
36
37 uint8_t _resd1:1;
38 uint8_t key:3; /* Stream number, or 6 for KEY_SYSTEM */
39 uint8_t _resd2:2;
40
41 /* Interrupt, branch, and wait flags */
42 uint8_t intr:2;
43 uint8_t branch:2;
44 uint8_t wait:2;
45
46 uint16_t reqCount; /* Bytes to transfer */
47
48 uint32_t address; /* 32-bit system physical address */
49 uint32_t cmdDep; /* Branch address or quad word to load/store */
50
51 uint16_t xferStatus; /* Contents of channel status after completion */
52 uint16_t resCount; /* Number of residual bytes outstanding */
53 };
54
55 struct dbdma_channel {
56 struct resource *sc_regs;
57 u_int sc_off;
58
59 struct dbdma_command *sc_slots;
60 int sc_nslots;
61 bus_addr_t sc_slots_pa;
62
63 bus_dma_tag_t sc_dmatag;
64 bus_dmamap_t sc_dmamap;
65 uint32_t sc_saved_regs[5];
66 };
67
68 /*
69 DBDMA registers are found at 0x8000 + n*0x100 in the macio register space,
70 and are laid out as follows within each block:
71
72 Address: Description: Length (bytes):
73 0x000 Channel Control 4
74 0x004 Channel Status 4
75 0x00C Command Phys Addr 4
76 0x010 Interrupt Select 4
77 0x014 Branch Select 4
78 0x018 Wait Select 4
79 */
80
81 #define CHAN_CONTROL_REG 0x00
82 #define CHAN_STATUS_REG 0x04
83 #define CHAN_CMDPTR_HI 0x08
84 #define CHAN_CMDPTR 0x0C
85 #define CHAN_INTR_SELECT 0x10
86 #define CHAN_BRANCH_SELECT 0x14
87 #define CHAN_WAIT_SELECT 0x18
88
89 /* Channel control is the write channel to channel status, the upper 16 bits
90 are a mask of which bytes to change */
91
92 #define DBDMA_REG_MASK_SHIFT 16
93
94 /* Status bits 0-7 are device dependent status bits */
95
96 /*
97 The Interrupt/Branch/Wait Select triggers the corresponding condition bits
98 in the event that (select.mask & device dependent status) == select.value
99
100 They are defined a follows:
101 Byte 1: Reserved
102 Byte 2: Mask
103 Byte 3: Reserved
104 Byte 4: Value
105 */
106
107 #endif /* _POWERPC_POWERMAC_DBDMAVAR_H_ */
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