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sys/powerpc/powerpc/bus_machdep.c
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1 /*- 2 * Copyright (c) 2006 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 8 * NASA Ames Research Center. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD: releng/10.2/sys/powerpc/powerpc/bus_machdep.c 265996 2014-05-14 00:51:26Z ian $"); 41 42 #define KTR_BE_IO 0 43 #define KTR_LE_IO 0 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/bus.h> 48 #include <sys/ktr.h> 49 #include <vm/vm.h> 50 #include <vm/pmap.h> 51 52 #include <machine/bus.h> 53 #include <machine/pio.h> 54 #include <machine/md_var.h> 55 56 #define TODO panic("%s: not implemented", __func__) 57 58 #define MAX_EARLYBOOT_MAPPINGS 6 59 60 static struct { 61 vm_offset_t virt; 62 bus_addr_t addr; 63 bus_size_t size; 64 int flags; 65 } earlyboot_mappings[MAX_EARLYBOOT_MAPPINGS]; 66 static int earlyboot_map_idx = 0; 67 68 void bs_remap_earlyboot(void); 69 70 static __inline void * 71 __ppc_ba(bus_space_handle_t bsh, bus_size_t ofs) 72 { 73 return ((void *)(bsh + ofs)); 74 } 75 76 static int 77 bs_gen_map(bus_addr_t addr, bus_size_t size, int flags, 78 bus_space_handle_t *bshp) 79 { 80 vm_memattr_t ma; 81 82 /* 83 * Record what we did if we haven't enabled the MMU yet. We 84 * will need to remap it as soon as the MMU comes up. 85 */ 86 if (!pmap_bootstrapped) { 87 KASSERT(earlyboot_map_idx < MAX_EARLYBOOT_MAPPINGS, 88 ("%s: too many early boot mapping requests", __func__)); 89 earlyboot_mappings[earlyboot_map_idx].addr = addr; 90 earlyboot_mappings[earlyboot_map_idx].virt = 91 pmap_early_io_map(addr, size); 92 earlyboot_mappings[earlyboot_map_idx].size = size; 93 earlyboot_mappings[earlyboot_map_idx].flags = flags; 94 *bshp = earlyboot_mappings[earlyboot_map_idx].virt; 95 earlyboot_map_idx++; 96 } else { 97 ma = VM_MEMATTR_DEFAULT; 98 switch (flags) { 99 case BUS_SPACE_MAP_CACHEABLE: 100 ma = VM_MEMATTR_CACHEABLE; 101 break; 102 case BUS_SPACE_MAP_PREFETCHABLE: 103 ma = VM_MEMATTR_PREFETCHABLE; 104 break; 105 } 106 *bshp = (bus_space_handle_t)pmap_mapdev_attr(addr, size, ma); 107 } 108 109 return (0); 110 } 111 112 void 113 bs_remap_earlyboot(void) 114 { 115 int i; 116 vm_offset_t pa, spa, va; 117 vm_memattr_t ma; 118 119 for (i = 0; i < earlyboot_map_idx; i++) { 120 spa = earlyboot_mappings[i].addr; 121 if (spa == earlyboot_mappings[i].virt && 122 pmap_dev_direct_mapped(spa, earlyboot_mappings[i].size) == 0) 123 continue; 124 125 ma = VM_MEMATTR_DEFAULT; 126 switch (earlyboot_mappings[i].flags) { 127 case BUS_SPACE_MAP_CACHEABLE: 128 ma = VM_MEMATTR_CACHEABLE; 129 break; 130 case BUS_SPACE_MAP_PREFETCHABLE: 131 ma = VM_MEMATTR_PREFETCHABLE; 132 break; 133 } 134 135 pa = trunc_page(spa); 136 va = trunc_page(earlyboot_mappings[i].virt); 137 while (pa < spa + earlyboot_mappings[i].size) { 138 pmap_kenter_attr(va, pa, ma); 139 va += PAGE_SIZE; 140 pa += PAGE_SIZE; 141 } 142 } 143 } 144 145 static void 146 bs_gen_unmap(bus_size_t size __unused) 147 { 148 } 149 150 static int 151 bs_gen_subregion(bus_space_handle_t bsh, bus_size_t ofs, 152 bus_size_t size __unused, bus_space_handle_t *nbshp) 153 { 154 *nbshp = bsh + ofs; 155 return (0); 156 } 157 158 static int 159 bs_gen_alloc(bus_addr_t rstart __unused, bus_addr_t rend __unused, 160 bus_size_t size __unused, bus_size_t alignment __unused, 161 bus_size_t boundary __unused, int flags __unused, 162 bus_addr_t *bpap __unused, bus_space_handle_t *bshp __unused) 163 { 164 TODO; 165 } 166 167 static void 168 bs_gen_free(bus_space_handle_t bsh __unused, bus_size_t size __unused) 169 { 170 TODO; 171 } 172 173 static void 174 bs_gen_barrier(bus_space_handle_t bsh __unused, bus_size_t ofs __unused, 175 bus_size_t size __unused, int flags __unused) 176 { 177 178 powerpc_iomb(); 179 } 180 181 /* 182 * Big-endian access functions 183 */ 184 static uint8_t 185 bs_be_rs_1(bus_space_handle_t bsh, bus_size_t ofs) 186 { 187 volatile uint8_t *addr; 188 uint8_t res; 189 190 addr = __ppc_ba(bsh, ofs); 191 res = *addr; 192 powerpc_iomb(); 193 CTR4(KTR_BE_IO, "%s(bsh=%#x, ofs=%#x) = %#x", __func__, bsh, ofs, res); 194 return (res); 195 } 196 197 static uint16_t 198 bs_be_rs_2(bus_space_handle_t bsh, bus_size_t ofs) 199 { 200 volatile uint16_t *addr; 201 uint16_t res; 202 203 addr = __ppc_ba(bsh, ofs); 204 res = *addr; 205 powerpc_iomb(); 206 CTR4(KTR_BE_IO, "%s(bsh=%#x, ofs=%#x) = %#x", __func__, bsh, ofs, res); 207 return (res); 208 } 209 210 static uint32_t 211 bs_be_rs_4(bus_space_handle_t bsh, bus_size_t ofs) 212 { 213 volatile uint32_t *addr; 214 uint32_t res; 215 216 addr = __ppc_ba(bsh, ofs); 217 res = *addr; 218 powerpc_iomb(); 219 CTR4(KTR_BE_IO, "%s(bsh=%#x, ofs=%#x) = %#x", __func__, bsh, ofs, res); 220 return (res); 221 } 222 223 static uint64_t 224 bs_be_rs_8(bus_space_handle_t bsh, bus_size_t ofs) 225 { 226 volatile uint64_t *addr; 227 uint64_t res; 228 229 addr = __ppc_ba(bsh, ofs); 230 res = *addr; 231 powerpc_iomb(); 232 return (res); 233 } 234 235 static void 236 bs_be_rm_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t *addr, size_t cnt) 237 { 238 ins8(__ppc_ba(bsh, ofs), addr, cnt); 239 } 240 241 static void 242 bs_be_rm_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t *addr, size_t cnt) 243 { 244 ins16(__ppc_ba(bsh, ofs), addr, cnt); 245 } 246 247 static void 248 bs_be_rm_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t *addr, size_t cnt) 249 { 250 ins32(__ppc_ba(bsh, ofs), addr, cnt); 251 } 252 253 static void 254 bs_be_rm_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t *addr, size_t cnt) 255 { 256 ins64(__ppc_ba(bsh, ofs), addr, cnt); 257 } 258 259 static void 260 bs_be_rr_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t *addr, size_t cnt) 261 { 262 volatile uint8_t *s = __ppc_ba(bsh, ofs); 263 264 while (cnt--) 265 *addr++ = *s++; 266 powerpc_iomb(); 267 } 268 269 static void 270 bs_be_rr_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t *addr, size_t cnt) 271 { 272 volatile uint16_t *s = __ppc_ba(bsh, ofs); 273 274 while (cnt--) 275 *addr++ = *s++; 276 powerpc_iomb(); 277 } 278 279 static void 280 bs_be_rr_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t *addr, size_t cnt) 281 { 282 volatile uint32_t *s = __ppc_ba(bsh, ofs); 283 284 while (cnt--) 285 *addr++ = *s++; 286 powerpc_iomb(); 287 } 288 289 static void 290 bs_be_rr_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t *addr, size_t cnt) 291 { 292 volatile uint64_t *s = __ppc_ba(bsh, ofs); 293 294 while (cnt--) 295 *addr++ = *s++; 296 powerpc_iomb(); 297 } 298 299 static void 300 bs_be_ws_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t val) 301 { 302 volatile uint8_t *addr; 303 304 addr = __ppc_ba(bsh, ofs); 305 *addr = val; 306 powerpc_iomb(); 307 CTR4(KTR_BE_IO, "%s(bsh=%#x, ofs=%#x, val=%#x)", __func__, bsh, ofs, val); 308 } 309 310 static void 311 bs_be_ws_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t val) 312 { 313 volatile uint16_t *addr; 314 315 addr = __ppc_ba(bsh, ofs); 316 *addr = val; 317 powerpc_iomb(); 318 CTR4(KTR_BE_IO, "%s(bsh=%#x, ofs=%#x, val=%#x)", __func__, bsh, ofs, val); 319 } 320 321 static void 322 bs_be_ws_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t val) 323 { 324 volatile uint32_t *addr; 325 326 addr = __ppc_ba(bsh, ofs); 327 *addr = val; 328 powerpc_iomb(); 329 CTR4(KTR_BE_IO, "%s(bsh=%#x, ofs=%#x, val=%#x)", __func__, bsh, ofs, val); 330 } 331 332 static void 333 bs_be_ws_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t val) 334 { 335 volatile uint64_t *addr; 336 337 addr = __ppc_ba(bsh, ofs); 338 *addr = val; 339 powerpc_iomb(); 340 } 341 342 static void 343 bs_be_wm_1(bus_space_handle_t bsh, bus_size_t ofs, const uint8_t *addr, 344 bus_size_t cnt) 345 { 346 outsb(__ppc_ba(bsh, ofs), addr, cnt); 347 } 348 349 static void 350 bs_be_wm_2(bus_space_handle_t bsh, bus_size_t ofs, const uint16_t *addr, 351 bus_size_t cnt) 352 { 353 outsw(__ppc_ba(bsh, ofs), addr, cnt); 354 } 355 356 static void 357 bs_be_wm_4(bus_space_handle_t bsh, bus_size_t ofs, const uint32_t *addr, 358 bus_size_t cnt) 359 { 360 outsl(__ppc_ba(bsh, ofs), addr, cnt); 361 } 362 363 static void 364 bs_be_wm_8(bus_space_handle_t bsh, bus_size_t ofs, const uint64_t *addr, 365 bus_size_t cnt) 366 { 367 outsll(__ppc_ba(bsh, ofs), addr, cnt); 368 } 369 370 static void 371 bs_be_wr_1(bus_space_handle_t bsh, bus_size_t ofs, const uint8_t *addr, 372 size_t cnt) 373 { 374 volatile uint8_t *d = __ppc_ba(bsh, ofs); 375 376 while (cnt--) 377 *d++ = *addr++; 378 powerpc_iomb(); 379 } 380 381 static void 382 bs_be_wr_2(bus_space_handle_t bsh, bus_size_t ofs, const uint16_t *addr, 383 size_t cnt) 384 { 385 volatile uint16_t *d = __ppc_ba(bsh, ofs); 386 387 while (cnt--) 388 *d++ = *addr++; 389 powerpc_iomb(); 390 } 391 392 static void 393 bs_be_wr_4(bus_space_handle_t bsh, bus_size_t ofs, const uint32_t *addr, 394 size_t cnt) 395 { 396 volatile uint32_t *d = __ppc_ba(bsh, ofs); 397 398 while (cnt--) 399 *d++ = *addr++; 400 powerpc_iomb(); 401 } 402 403 static void 404 bs_be_wr_8(bus_space_handle_t bsh, bus_size_t ofs, const uint64_t *addr, 405 size_t cnt) 406 { 407 volatile uint64_t *d = __ppc_ba(bsh, ofs); 408 409 while (cnt--) 410 *d++ = *addr++; 411 powerpc_iomb(); 412 } 413 414 static void 415 bs_be_sm_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t val, size_t cnt) 416 { 417 volatile uint8_t *d = __ppc_ba(bsh, ofs); 418 419 while (cnt--) 420 *d = val; 421 powerpc_iomb(); 422 } 423 424 static void 425 bs_be_sm_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t val, size_t cnt) 426 { 427 volatile uint16_t *d = __ppc_ba(bsh, ofs); 428 429 while (cnt--) 430 *d = val; 431 powerpc_iomb(); 432 } 433 434 static void 435 bs_be_sm_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t val, size_t cnt) 436 { 437 volatile uint32_t *d = __ppc_ba(bsh, ofs); 438 439 while (cnt--) 440 *d = val; 441 powerpc_iomb(); 442 } 443 444 static void 445 bs_be_sm_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t val, size_t cnt) 446 { 447 volatile uint64_t *d = __ppc_ba(bsh, ofs); 448 449 while (cnt--) 450 *d = val; 451 powerpc_iomb(); 452 } 453 454 static void 455 bs_be_sr_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t val, size_t cnt) 456 { 457 volatile uint8_t *d = __ppc_ba(bsh, ofs); 458 459 while (cnt--) 460 *d++ = val; 461 powerpc_iomb(); 462 } 463 464 static void 465 bs_be_sr_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t val, size_t cnt) 466 { 467 volatile uint16_t *d = __ppc_ba(bsh, ofs); 468 469 while (cnt--) 470 *d++ = val; 471 powerpc_iomb(); 472 } 473 474 static void 475 bs_be_sr_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t val, size_t cnt) 476 { 477 volatile uint32_t *d = __ppc_ba(bsh, ofs); 478 479 while (cnt--) 480 *d++ = val; 481 powerpc_iomb(); 482 } 483 484 static void 485 bs_be_sr_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t val, size_t cnt) 486 { 487 volatile uint64_t *d = __ppc_ba(bsh, ofs); 488 489 while (cnt--) 490 *d++ = val; 491 powerpc_iomb(); 492 } 493 494 /* 495 * Little-endian access functions 496 */ 497 static uint8_t 498 bs_le_rs_1(bus_space_handle_t bsh, bus_size_t ofs) 499 { 500 volatile uint8_t *addr; 501 uint8_t res; 502 503 addr = __ppc_ba(bsh, ofs); 504 res = *addr; 505 powerpc_iomb(); 506 CTR4(KTR_LE_IO, "%s(bsh=%#x, ofs=%#x) = %#x", __func__, bsh, ofs, res); 507 return (res); 508 } 509 510 static uint16_t 511 bs_le_rs_2(bus_space_handle_t bsh, bus_size_t ofs) 512 { 513 volatile uint16_t *addr; 514 uint16_t res; 515 516 addr = __ppc_ba(bsh, ofs); 517 __asm __volatile("lhbrx %0, 0, %1" : "=r"(res) : "r"(addr)); 518 powerpc_iomb(); 519 CTR4(KTR_LE_IO, "%s(bsh=%#x, ofs=%#x) = %#x", __func__, bsh, ofs, res); 520 return (res); 521 } 522 523 static uint32_t 524 bs_le_rs_4(bus_space_handle_t bsh, bus_size_t ofs) 525 { 526 volatile uint32_t *addr; 527 uint32_t res; 528 529 addr = __ppc_ba(bsh, ofs); 530 __asm __volatile("lwbrx %0, 0, %1" : "=r"(res) : "r"(addr)); 531 powerpc_iomb(); 532 CTR4(KTR_LE_IO, "%s(bsh=%#x, ofs=%#x) = %#x", __func__, bsh, ofs, res); 533 return (res); 534 } 535 536 static uint64_t 537 bs_le_rs_8(bus_space_handle_t bsh, bus_size_t ofs) 538 { 539 TODO; 540 } 541 542 static void 543 bs_le_rm_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t *addr, size_t cnt) 544 { 545 ins8(__ppc_ba(bsh, ofs), addr, cnt); 546 } 547 548 static void 549 bs_le_rm_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t *addr, size_t cnt) 550 { 551 ins16rb(__ppc_ba(bsh, ofs), addr, cnt); 552 } 553 554 static void 555 bs_le_rm_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t *addr, size_t cnt) 556 { 557 ins32rb(__ppc_ba(bsh, ofs), addr, cnt); 558 } 559 560 static void 561 bs_le_rm_8(bus_space_handle_t bshh, bus_size_t ofs, uint64_t *addr, size_t cnt) 562 { 563 TODO; 564 } 565 566 static void 567 bs_le_rr_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t *addr, size_t cnt) 568 { 569 volatile uint8_t *s = __ppc_ba(bsh, ofs); 570 571 while (cnt--) 572 *addr++ = *s++; 573 powerpc_iomb(); 574 } 575 576 static void 577 bs_le_rr_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t *addr, size_t cnt) 578 { 579 volatile uint16_t *s = __ppc_ba(bsh, ofs); 580 581 while (cnt--) 582 *addr++ = in16rb(s++); 583 powerpc_iomb(); 584 } 585 586 static void 587 bs_le_rr_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t *addr, size_t cnt) 588 { 589 volatile uint32_t *s = __ppc_ba(bsh, ofs); 590 591 while (cnt--) 592 *addr++ = in32rb(s++); 593 powerpc_iomb(); 594 } 595 596 static void 597 bs_le_rr_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t *addr, size_t cnt) 598 { 599 TODO; 600 } 601 602 static void 603 bs_le_ws_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t val) 604 { 605 volatile uint8_t *addr; 606 607 addr = __ppc_ba(bsh, ofs); 608 *addr = val; 609 powerpc_iomb(); 610 CTR4(KTR_LE_IO, "%s(bsh=%#x, ofs=%#x, val=%#x)", __func__, bsh, ofs, val); 611 } 612 613 static void 614 bs_le_ws_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t val) 615 { 616 volatile uint16_t *addr; 617 618 addr = __ppc_ba(bsh, ofs); 619 __asm __volatile("sthbrx %0, 0, %1" :: "r"(val), "r"(addr)); 620 powerpc_iomb(); 621 CTR4(KTR_LE_IO, "%s(bsh=%#x, ofs=%#x, val=%#x)", __func__, bsh, ofs, val); 622 } 623 624 static void 625 bs_le_ws_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t val) 626 { 627 volatile uint32_t *addr; 628 629 addr = __ppc_ba(bsh, ofs); 630 __asm __volatile("stwbrx %0, 0, %1" :: "r"(val), "r"(addr)); 631 powerpc_iomb(); 632 CTR4(KTR_LE_IO, "%s(bsh=%#x, ofs=%#x, val=%#x)", __func__, bsh, ofs, val); 633 } 634 635 static void 636 bs_le_ws_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t val) 637 { 638 TODO; 639 } 640 641 static void 642 bs_le_wm_1(bus_space_handle_t bsh, bus_size_t ofs, const uint8_t *addr, 643 bus_size_t cnt) 644 { 645 outs8(__ppc_ba(bsh, ofs), addr, cnt); 646 } 647 648 static void 649 bs_le_wm_2(bus_space_handle_t bsh, bus_size_t ofs, const uint16_t *addr, 650 bus_size_t cnt) 651 { 652 outs16rb(__ppc_ba(bsh, ofs), addr, cnt); 653 } 654 655 static void 656 bs_le_wm_4(bus_space_handle_t bsh, bus_size_t ofs, const uint32_t *addr, 657 bus_size_t cnt) 658 { 659 outs32rb(__ppc_ba(bsh, ofs), addr, cnt); 660 } 661 662 static void 663 bs_le_wm_8(bus_space_handle_t bsh, bus_size_t ofs, const uint64_t *addr, 664 bus_size_t cnt) 665 { 666 TODO; 667 } 668 669 static void 670 bs_le_wr_1(bus_space_handle_t bsh, bus_size_t ofs, const uint8_t *addr, 671 size_t cnt) 672 { 673 volatile uint8_t *d = __ppc_ba(bsh, ofs); 674 675 while (cnt--) 676 *d++ = *addr++; 677 powerpc_iomb(); 678 } 679 680 static void 681 bs_le_wr_2(bus_space_handle_t bsh, bus_size_t ofs, const uint16_t *addr, 682 size_t cnt) 683 { 684 volatile uint16_t *d = __ppc_ba(bsh, ofs); 685 686 while (cnt--) 687 out16rb(d++, *addr++); 688 powerpc_iomb(); 689 } 690 691 static void 692 bs_le_wr_4(bus_space_handle_t bsh, bus_size_t ofs, const uint32_t *addr, 693 size_t cnt) 694 { 695 volatile uint32_t *d = __ppc_ba(bsh, ofs); 696 697 while (cnt--) 698 out32rb(d++, *addr++); 699 powerpc_iomb(); 700 } 701 702 static void 703 bs_le_wr_8(bus_space_handle_t bsh, bus_size_t ofs, const uint64_t *addr, 704 size_t cnt) 705 { 706 TODO; 707 } 708 709 static void 710 bs_le_sm_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t val, size_t cnt) 711 { 712 volatile uint8_t *d = __ppc_ba(bsh, ofs); 713 714 while (cnt--) 715 *d = val; 716 powerpc_iomb(); 717 } 718 719 static void 720 bs_le_sm_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t val, size_t cnt) 721 { 722 volatile uint16_t *d = __ppc_ba(bsh, ofs); 723 724 while (cnt--) 725 out16rb(d, val); 726 powerpc_iomb(); 727 } 728 729 static void 730 bs_le_sm_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t val, size_t cnt) 731 { 732 volatile uint32_t *d = __ppc_ba(bsh, ofs); 733 734 while (cnt--) 735 out32rb(d, val); 736 powerpc_iomb(); 737 } 738 739 static void 740 bs_le_sm_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t val, size_t cnt) 741 { 742 TODO; 743 } 744 745 static void 746 bs_le_sr_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t val, size_t cnt) 747 { 748 volatile uint8_t *d = __ppc_ba(bsh, ofs); 749 750 while (cnt--) 751 *d++ = val; 752 powerpc_iomb(); 753 } 754 755 static void 756 bs_le_sr_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t val, size_t cnt) 757 { 758 volatile uint16_t *d = __ppc_ba(bsh, ofs); 759 760 while (cnt--) 761 out16rb(d++, val); 762 powerpc_iomb(); 763 } 764 765 static void 766 bs_le_sr_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t val, size_t cnt) 767 { 768 volatile uint32_t *d = __ppc_ba(bsh, ofs); 769 770 while (cnt--) 771 out32rb(d++, val); 772 powerpc_iomb(); 773 } 774 775 static void 776 bs_le_sr_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t val, size_t cnt) 777 { 778 TODO; 779 } 780 781 struct bus_space bs_be_tag = { 782 /* mapping/unmapping */ 783 bs_gen_map, 784 bs_gen_unmap, 785 bs_gen_subregion, 786 787 /* allocation/deallocation */ 788 bs_gen_alloc, 789 bs_gen_free, 790 791 /* barrier */ 792 bs_gen_barrier, 793 794 /* read (single) */ 795 bs_be_rs_1, 796 bs_be_rs_2, 797 bs_be_rs_4, 798 bs_be_rs_8, 799 800 bs_be_rs_2, 801 bs_be_rs_4, 802 bs_be_rs_8, 803 804 /* read multiple */ 805 bs_be_rm_1, 806 bs_be_rm_2, 807 bs_be_rm_4, 808 bs_be_rm_8, 809 810 bs_be_rm_2, 811 bs_be_rm_4, 812 bs_be_rm_8, 813 814 /* read region */ 815 bs_be_rr_1, 816 bs_be_rr_2, 817 bs_be_rr_4, 818 bs_be_rr_8, 819 820 bs_be_rr_2, 821 bs_be_rr_4, 822 bs_be_rr_8, 823 824 /* write (single) */ 825 bs_be_ws_1, 826 bs_be_ws_2, 827 bs_be_ws_4, 828 bs_be_ws_8, 829 830 bs_be_ws_2, 831 bs_be_ws_4, 832 bs_be_ws_8, 833 834 /* write multiple */ 835 bs_be_wm_1, 836 bs_be_wm_2, 837 bs_be_wm_4, 838 bs_be_wm_8, 839 840 bs_be_wm_2, 841 bs_be_wm_4, 842 bs_be_wm_8, 843 844 /* write region */ 845 bs_be_wr_1, 846 bs_be_wr_2, 847 bs_be_wr_4, 848 bs_be_wr_8, 849 850 bs_be_wr_2, 851 bs_be_wr_4, 852 bs_be_wr_8, 853 854 /* set multiple */ 855 bs_be_sm_1, 856 bs_be_sm_2, 857 bs_be_sm_4, 858 bs_be_sm_8, 859 860 bs_be_sm_2, 861 bs_be_sm_4, 862 bs_be_sm_8, 863 864 /* set region */ 865 bs_be_sr_1, 866 bs_be_sr_2, 867 bs_be_sr_4, 868 bs_be_sr_8, 869 870 bs_be_sr_2, 871 bs_be_sr_4, 872 bs_be_sr_8, 873 }; 874 875 struct bus_space bs_le_tag = { 876 /* mapping/unmapping */ 877 bs_gen_map, 878 bs_gen_unmap, 879 bs_gen_subregion, 880 881 /* allocation/deallocation */ 882 bs_gen_alloc, 883 bs_gen_free, 884 885 /* barrier */ 886 bs_gen_barrier, 887 888 /* read (single) */ 889 bs_le_rs_1, 890 bs_le_rs_2, 891 bs_le_rs_4, 892 bs_le_rs_8, 893 894 bs_be_rs_2, 895 bs_be_rs_4, 896 bs_be_rs_8, 897 898 /* read multiple */ 899 bs_le_rm_1, 900 bs_le_rm_2, 901 bs_le_rm_4, 902 bs_le_rm_8, 903 904 bs_be_rm_2, 905 bs_be_rm_4, 906 bs_be_rm_8, 907 908 /* read region */ 909 bs_le_rr_1, 910 bs_le_rr_2, 911 bs_le_rr_4, 912 bs_le_rr_8, 913 914 bs_be_rr_2, 915 bs_be_rr_4, 916 bs_be_rr_8, 917 918 /* write (single) */ 919 bs_le_ws_1, 920 bs_le_ws_2, 921 bs_le_ws_4, 922 bs_le_ws_8, 923 924 bs_be_ws_2, 925 bs_be_ws_4, 926 bs_be_ws_8, 927 928 /* write multiple */ 929 bs_le_wm_1, 930 bs_le_wm_2, 931 bs_le_wm_4, 932 bs_le_wm_8, 933 934 bs_be_wm_2, 935 bs_be_wm_4, 936 bs_be_wm_8, 937 938 /* write region */ 939 bs_le_wr_1, 940 bs_le_wr_2, 941 bs_le_wr_4, 942 bs_le_wr_8, 943 944 bs_be_wr_2, 945 bs_be_wr_4, 946 bs_be_wr_8, 947 948 /* set multiple */ 949 bs_le_sm_1, 950 bs_le_sm_2, 951 bs_le_sm_4, 952 bs_le_sm_8, 953 954 bs_be_sm_2, 955 bs_be_sm_4, 956 bs_be_sm_8, 957 958 /* set region */ 959 bs_le_sr_1, 960 bs_le_sr_2, 961 bs_le_sr_4, 962 bs_le_sr_8, 963 964 bs_be_sr_2, 965 bs_be_sr_4, 966 bs_be_sr_8, 967 };
Cache object: 6fb0453ed4bf83980dd29c458456abdb
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