1 /*-
2 * Copyright (c) 2006 Semihalf, Rafal Jaworowski <raj@semihalf.com>
3 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
8 * NASA Ames Research Center.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 #include <sys/cdefs.h>
40 __FBSDID("$FreeBSD: releng/8.1/sys/powerpc/powerpc/bus_machdep.c 193578 2009-06-06 09:33:32Z raj $");
41
42 #define KTR_BE_IO 0
43 #define KTR_LE_IO 0
44
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/bus.h>
48 #include <sys/ktr.h>
49 #include <vm/vm.h>
50 #include <vm/pmap.h>
51
52 #include <machine/bus.h>
53 #include <machine/pio.h>
54 #include <machine/md_var.h>
55
56 #define TODO panic("%s: not implemented", __func__)
57
58 #define MAX_EARLYBOOT_MAPPINGS 6
59
60 static struct {
61 bus_addr_t addr;
62 bus_size_t size;
63 } earlyboot_mappings[MAX_EARLYBOOT_MAPPINGS];
64 static int earlyboot_map_idx = 0;
65
66 void bs_remap_earlyboot(void);
67
68 static __inline void *
69 __ppc_ba(bus_space_handle_t bsh, bus_size_t ofs)
70 {
71 return ((void *)(bsh + ofs));
72 }
73
74 static int
75 bs_gen_map(bus_addr_t addr, bus_size_t size __unused, int flags __unused,
76 bus_space_handle_t *bshp)
77 {
78 /*
79 * Record what we did if we haven't enabled the MMU yet. We
80 * will need to remap it as soon as the MMU comes up.
81 */
82 if (!pmap_bootstrapped) {
83 KASSERT(earlyboot_map_idx < MAX_EARLYBOOT_MAPPINGS,
84 ("%s: too many early boot mapping requests", __func__));
85 earlyboot_mappings[earlyboot_map_idx].addr = addr;
86 earlyboot_mappings[earlyboot_map_idx].size = size;
87 earlyboot_map_idx++;
88 *bshp = addr;
89 } else {
90 *bshp = (bus_space_handle_t)pmap_mapdev(addr,size);
91 }
92
93 return (0);
94 }
95
96 void
97 bs_remap_earlyboot(void)
98 {
99 int i;
100 vm_offset_t pa, spa;
101
102 if (hw_direct_map)
103 return;
104
105 for (i = 0; i < earlyboot_map_idx; i++) {
106 spa = earlyboot_mappings[i].addr;
107
108 pa = trunc_page(spa);
109 while (pa < spa + earlyboot_mappings[i].size) {
110 pmap_kenter(pa,pa);
111 pa += PAGE_SIZE;
112 }
113 }
114 }
115
116 static void
117 bs_gen_unmap(bus_size_t size __unused)
118 {
119 }
120
121 static int
122 bs_gen_subregion(bus_space_handle_t bsh, bus_size_t ofs,
123 bus_size_t size __unused, bus_space_handle_t *nbshp)
124 {
125 *nbshp = bsh + ofs;
126 return (0);
127 }
128
129 static int
130 bs_gen_alloc(bus_addr_t rstart __unused, bus_addr_t rend __unused,
131 bus_size_t size __unused, bus_size_t alignment __unused,
132 bus_size_t boundary __unused, int flags __unused,
133 bus_addr_t *bpap __unused, bus_space_handle_t *bshp __unused)
134 {
135 TODO;
136 }
137
138 static void
139 bs_gen_free(bus_space_handle_t bsh __unused, bus_size_t size __unused)
140 {
141 TODO;
142 }
143
144 static void
145 bs_gen_barrier(bus_space_handle_t bsh __unused, bus_size_t ofs __unused,
146 bus_size_t size __unused, int flags __unused)
147 {
148 __asm __volatile("eieio; sync" : : : "memory");
149 }
150
151 /*
152 * Big-endian access functions
153 */
154 static uint8_t
155 bs_be_rs_1(bus_space_handle_t bsh, bus_size_t ofs)
156 {
157 volatile uint8_t *addr;
158 uint8_t res;
159
160 addr = __ppc_ba(bsh, ofs);
161 res = *addr;
162 CTR4(KTR_BE_IO, "%s(bsh=%#x, ofs=%#x) = %#x", __func__, bsh, ofs, res);
163 return (res);
164 }
165
166 static uint16_t
167 bs_be_rs_2(bus_space_handle_t bsh, bus_size_t ofs)
168 {
169 volatile uint16_t *addr;
170 uint16_t res;
171
172 addr = __ppc_ba(bsh, ofs);
173 res = *addr;
174 CTR4(KTR_BE_IO, "%s(bsh=%#x, ofs=%#x) = %#x", __func__, bsh, ofs, res);
175 return (res);
176 }
177
178 static uint32_t
179 bs_be_rs_4(bus_space_handle_t bsh, bus_size_t ofs)
180 {
181 volatile uint32_t *addr;
182 uint32_t res;
183
184 addr = __ppc_ba(bsh, ofs);
185 res = *addr;
186 CTR4(KTR_BE_IO, "%s(bsh=%#x, ofs=%#x) = %#x", __func__, bsh, ofs, res);
187 return (res);
188 }
189
190 static uint64_t
191 bs_be_rs_8(bus_space_handle_t bsh, bus_size_t ofs)
192 {
193 volatile uint64_t *addr;
194 uint64_t res;
195
196 addr = __ppc_ba(bsh, ofs);
197 res = *addr;
198 return (res);
199 }
200
201 static void
202 bs_be_rm_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t *addr, size_t cnt)
203 {
204 ins8(__ppc_ba(bsh, ofs), addr, cnt);
205 }
206
207 static void
208 bs_be_rm_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t *addr, size_t cnt)
209 {
210 ins16(__ppc_ba(bsh, ofs), addr, cnt);
211 }
212
213 static void
214 bs_be_rm_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t *addr, size_t cnt)
215 {
216 ins32(__ppc_ba(bsh, ofs), addr, cnt);
217 }
218
219 static void
220 bs_be_rm_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t *addr, size_t cnt)
221 {
222 ins64(__ppc_ba(bsh, ofs), addr, cnt);
223 }
224
225 static void
226 bs_be_rr_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t *addr, size_t cnt)
227 {
228 volatile uint8_t *s = __ppc_ba(bsh, ofs);
229
230 while (cnt--)
231 *addr++ = *s++;
232 __asm __volatile("eieio; sync");
233 }
234
235 static void
236 bs_be_rr_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t *addr, size_t cnt)
237 {
238 volatile uint16_t *s = __ppc_ba(bsh, ofs);
239
240 while (cnt--)
241 *addr++ = *s++;
242 __asm __volatile("eieio; sync");
243 }
244
245 static void
246 bs_be_rr_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t *addr, size_t cnt)
247 {
248 volatile uint32_t *s = __ppc_ba(bsh, ofs);
249
250 while (cnt--)
251 *addr++ = *s++;
252 __asm __volatile("eieio; sync");
253 }
254
255 static void
256 bs_be_rr_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t *addr, size_t cnt)
257 {
258 volatile uint64_t *s = __ppc_ba(bsh, ofs);
259
260 while (cnt--)
261 *addr++ = *s++;
262 __asm __volatile("eieio; sync");
263 }
264
265 static void
266 bs_be_ws_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t val)
267 {
268 volatile uint8_t *addr;
269
270 addr = __ppc_ba(bsh, ofs);
271 *addr = val;
272 CTR4(KTR_BE_IO, "%s(bsh=%#x, ofs=%#x, val=%#x)", __func__, bsh, ofs, val);
273 }
274
275 static void
276 bs_be_ws_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t val)
277 {
278 volatile uint16_t *addr;
279
280 addr = __ppc_ba(bsh, ofs);
281 *addr = val;
282 CTR4(KTR_BE_IO, "%s(bsh=%#x, ofs=%#x, val=%#x)", __func__, bsh, ofs, val);
283 }
284
285 static void
286 bs_be_ws_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t val)
287 {
288 volatile uint32_t *addr;
289
290 addr = __ppc_ba(bsh, ofs);
291 *addr = val;
292 CTR4(KTR_BE_IO, "%s(bsh=%#x, ofs=%#x, val=%#x)", __func__, bsh, ofs, val);
293 }
294
295 static void
296 bs_be_ws_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t val)
297 {
298 volatile uint64_t *addr;
299
300 addr = __ppc_ba(bsh, ofs);
301 *addr = val;
302 }
303
304 static void
305 bs_be_wm_1(bus_space_handle_t bsh, bus_size_t ofs, const uint8_t *addr,
306 bus_size_t cnt)
307 {
308 outsb(__ppc_ba(bsh, ofs), addr, cnt);
309 }
310
311 static void
312 bs_be_wm_2(bus_space_handle_t bsh, bus_size_t ofs, const uint16_t *addr,
313 bus_size_t cnt)
314 {
315 outsw(__ppc_ba(bsh, ofs), addr, cnt);
316 }
317
318 static void
319 bs_be_wm_4(bus_space_handle_t bsh, bus_size_t ofs, const uint32_t *addr,
320 bus_size_t cnt)
321 {
322 outsl(__ppc_ba(bsh, ofs), addr, cnt);
323 }
324
325 static void
326 bs_be_wm_8(bus_space_handle_t bsh, bus_size_t ofs, const uint64_t *addr,
327 bus_size_t cnt)
328 {
329 outsll(__ppc_ba(bsh, ofs), addr, cnt);
330 }
331
332 static void
333 bs_be_wr_1(bus_space_handle_t bsh, bus_size_t ofs, const uint8_t *addr,
334 size_t cnt)
335 {
336 volatile uint8_t *d = __ppc_ba(bsh, ofs);
337
338 while (cnt--)
339 *d++ = *addr++;
340 __asm __volatile("eieio; sync");
341 }
342
343 static void
344 bs_be_wr_2(bus_space_handle_t bsh, bus_size_t ofs, const uint16_t *addr,
345 size_t cnt)
346 {
347 volatile uint16_t *d = __ppc_ba(bsh, ofs);
348
349 while (cnt--)
350 *d++ = *addr++;
351 __asm __volatile("eieio; sync");
352 }
353
354 static void
355 bs_be_wr_4(bus_space_handle_t bsh, bus_size_t ofs, const uint32_t *addr,
356 size_t cnt)
357 {
358 volatile uint32_t *d = __ppc_ba(bsh, ofs);
359
360 while (cnt--)
361 *d++ = *addr++;
362 __asm __volatile("eieio; sync");
363 }
364
365 static void
366 bs_be_wr_8(bus_space_handle_t bsh, bus_size_t ofs, const uint64_t *addr,
367 size_t cnt)
368 {
369 volatile uint64_t *d = __ppc_ba(bsh, ofs);
370
371 while (cnt--)
372 *d++ = *addr++;
373 __asm __volatile("eieio; sync");
374 }
375
376 static void
377 bs_be_sm_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t val, size_t cnt)
378 {
379 volatile uint8_t *d = __ppc_ba(bsh, ofs);
380
381 while (cnt--)
382 *d = val;
383 __asm __volatile("eieio; sync");
384 }
385
386 static void
387 bs_be_sm_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t val, size_t cnt)
388 {
389 volatile uint16_t *d = __ppc_ba(bsh, ofs);
390
391 while (cnt--)
392 *d = val;
393 __asm __volatile("eieio; sync");
394 }
395
396 static void
397 bs_be_sm_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t val, size_t cnt)
398 {
399 volatile uint32_t *d = __ppc_ba(bsh, ofs);
400
401 while (cnt--)
402 *d = val;
403 __asm __volatile("eieio; sync");
404 }
405
406 static void
407 bs_be_sm_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t val, size_t cnt)
408 {
409 volatile uint64_t *d = __ppc_ba(bsh, ofs);
410
411 while (cnt--)
412 *d = val;
413 __asm __volatile("eieio; sync");
414 }
415
416 static void
417 bs_be_sr_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t val, size_t cnt)
418 {
419 volatile uint8_t *d = __ppc_ba(bsh, ofs);
420
421 while (cnt--)
422 *d++ = val;
423 __asm __volatile("eieio; sync");
424 }
425
426 static void
427 bs_be_sr_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t val, size_t cnt)
428 {
429 volatile uint16_t *d = __ppc_ba(bsh, ofs);
430
431 while (cnt--)
432 *d++ = val;
433 __asm __volatile("eieio; sync");
434 }
435
436 static void
437 bs_be_sr_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t val, size_t cnt)
438 {
439 volatile uint32_t *d = __ppc_ba(bsh, ofs);
440
441 while (cnt--)
442 *d++ = val;
443 __asm __volatile("eieio; sync");
444 }
445
446 static void
447 bs_be_sr_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t val, size_t cnt)
448 {
449 volatile uint64_t *d = __ppc_ba(bsh, ofs);
450
451 while (cnt--)
452 *d++ = val;
453 __asm __volatile("eieio; sync");
454 }
455
456 /*
457 * Little-endian access functions
458 */
459 static uint8_t
460 bs_le_rs_1(bus_space_handle_t bsh, bus_size_t ofs)
461 {
462 volatile uint8_t *addr;
463 uint8_t res;
464
465 addr = __ppc_ba(bsh, ofs);
466 res = *addr;
467 CTR4(KTR_LE_IO, "%s(bsh=%#x, ofs=%#x) = %#x", __func__, bsh, ofs, res);
468 return (res);
469 }
470
471 static uint16_t
472 bs_le_rs_2(bus_space_handle_t bsh, bus_size_t ofs)
473 {
474 volatile uint16_t *addr;
475 uint16_t res;
476
477 addr = __ppc_ba(bsh, ofs);
478 __asm __volatile("lhbrx %0, 0, %1" : "=r"(res) : "r"(addr));
479 CTR4(KTR_LE_IO, "%s(bsh=%#x, ofs=%#x) = %#x", __func__, bsh, ofs, res);
480 return (res);
481 }
482
483 static uint32_t
484 bs_le_rs_4(bus_space_handle_t bsh, bus_size_t ofs)
485 {
486 volatile uint32_t *addr;
487 uint32_t res;
488
489 addr = __ppc_ba(bsh, ofs);
490 __asm __volatile("lwbrx %0, 0, %1" : "=r"(res) : "r"(addr));
491 CTR4(KTR_LE_IO, "%s(bsh=%#x, ofs=%#x) = %#x", __func__, bsh, ofs, res);
492 return (res);
493 }
494
495 static uint64_t
496 bs_le_rs_8(bus_space_handle_t bsh, bus_size_t ofs)
497 {
498 TODO;
499 }
500
501 static void
502 bs_le_rm_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t *addr, size_t cnt)
503 {
504 ins8(__ppc_ba(bsh, ofs), addr, cnt);
505 }
506
507 static void
508 bs_le_rm_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t *addr, size_t cnt)
509 {
510 ins16rb(__ppc_ba(bsh, ofs), addr, cnt);
511 }
512
513 static void
514 bs_le_rm_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t *addr, size_t cnt)
515 {
516 ins32rb(__ppc_ba(bsh, ofs), addr, cnt);
517 }
518
519 static void
520 bs_le_rm_8(bus_space_handle_t bshh, bus_size_t ofs, uint64_t *addr, size_t cnt)
521 {
522 TODO;
523 }
524
525 static void
526 bs_le_rr_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t *addr, size_t cnt)
527 {
528 volatile uint8_t *s = __ppc_ba(bsh, ofs);
529
530 while (cnt--)
531 *addr++ = *s++;
532 __asm __volatile("eieio; sync");
533 }
534
535 static void
536 bs_le_rr_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t *addr, size_t cnt)
537 {
538 volatile uint16_t *s = __ppc_ba(bsh, ofs);
539
540 while (cnt--)
541 *addr++ = in16rb(s++);
542 __asm __volatile("eieio; sync");
543 }
544
545 static void
546 bs_le_rr_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t *addr, size_t cnt)
547 {
548 volatile uint32_t *s = __ppc_ba(bsh, ofs);
549
550 while (cnt--)
551 *addr++ = in32rb(s++);
552 __asm __volatile("eieio; sync");
553 }
554
555 static void
556 bs_le_rr_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t *addr, size_t cnt)
557 {
558 TODO;
559 }
560
561 static void
562 bs_le_ws_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t val)
563 {
564 volatile uint8_t *addr;
565
566 addr = __ppc_ba(bsh, ofs);
567 *addr = val;
568 CTR4(KTR_LE_IO, "%s(bsh=%#x, ofs=%#x, val=%#x)", __func__, bsh, ofs, val);
569 }
570
571 static void
572 bs_le_ws_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t val)
573 {
574 volatile uint16_t *addr;
575
576 addr = __ppc_ba(bsh, ofs);
577 __asm __volatile("sthbrx %0, 0, %1" :: "r"(val), "r"(addr));
578 CTR4(KTR_LE_IO, "%s(bsh=%#x, ofs=%#x, val=%#x)", __func__, bsh, ofs, val);
579 }
580
581 static void
582 bs_le_ws_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t val)
583 {
584 volatile uint32_t *addr;
585
586 addr = __ppc_ba(bsh, ofs);
587 __asm __volatile("stwbrx %0, 0, %1" :: "r"(val), "r"(addr));
588 CTR4(KTR_LE_IO, "%s(bsh=%#x, ofs=%#x, val=%#x)", __func__, bsh, ofs, val);
589 }
590
591 static void
592 bs_le_ws_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t val)
593 {
594 TODO;
595 }
596
597 static void
598 bs_le_wm_1(bus_space_handle_t bsh, bus_size_t ofs, const uint8_t *addr,
599 bus_size_t cnt)
600 {
601 outs8(__ppc_ba(bsh, ofs), addr, cnt);
602 }
603
604 static void
605 bs_le_wm_2(bus_space_handle_t bsh, bus_size_t ofs, const uint16_t *addr,
606 bus_size_t cnt)
607 {
608 outs16rb(__ppc_ba(bsh, ofs), addr, cnt);
609 }
610
611 static void
612 bs_le_wm_4(bus_space_handle_t bsh, bus_size_t ofs, const uint32_t *addr,
613 bus_size_t cnt)
614 {
615 outs32rb(__ppc_ba(bsh, ofs), addr, cnt);
616 }
617
618 static void
619 bs_le_wm_8(bus_space_handle_t bsh, bus_size_t ofs, const uint64_t *addr,
620 bus_size_t cnt)
621 {
622 TODO;
623 }
624
625 static void
626 bs_le_wr_1(bus_space_handle_t bsh, bus_size_t ofs, const uint8_t *addr,
627 size_t cnt)
628 {
629 volatile uint8_t *d = __ppc_ba(bsh, ofs);
630
631 while (cnt--)
632 *d++ = *addr++;
633 __asm __volatile("eieio; sync");
634 }
635
636 static void
637 bs_le_wr_2(bus_space_handle_t bsh, bus_size_t ofs, const uint16_t *addr,
638 size_t cnt)
639 {
640 volatile uint16_t *d = __ppc_ba(bsh, ofs);
641
642 while (cnt--)
643 out16rb(d++, *addr++);
644 __asm __volatile("eieio; sync");
645 }
646
647 static void
648 bs_le_wr_4(bus_space_handle_t bsh, bus_size_t ofs, const uint32_t *addr,
649 size_t cnt)
650 {
651 volatile uint32_t *d = __ppc_ba(bsh, ofs);
652
653 while (cnt--)
654 out32rb(d++, *addr++);
655 __asm __volatile("eieio; sync");
656 }
657
658 static void
659 bs_le_wr_8(bus_space_handle_t bsh, bus_size_t ofs, const uint64_t *addr,
660 size_t cnt)
661 {
662 TODO;
663 }
664
665 static void
666 bs_le_sm_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t val, size_t cnt)
667 {
668 volatile uint8_t *d = __ppc_ba(bsh, ofs);
669
670 while (cnt--)
671 *d = val;
672 __asm __volatile("eieio; sync");
673 }
674
675 static void
676 bs_le_sm_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t val, size_t cnt)
677 {
678 volatile uint16_t *d = __ppc_ba(bsh, ofs);
679
680 while (cnt--)
681 out16rb(d, val);
682 __asm __volatile("eieio; sync");
683 }
684
685 static void
686 bs_le_sm_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t val, size_t cnt)
687 {
688 volatile uint32_t *d = __ppc_ba(bsh, ofs);
689
690 while (cnt--)
691 out32rb(d, val);
692 __asm __volatile("eieio; sync");
693 }
694
695 static void
696 bs_le_sm_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t val, size_t cnt)
697 {
698 TODO;
699 }
700
701 static void
702 bs_le_sr_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t val, size_t cnt)
703 {
704 volatile uint8_t *d = __ppc_ba(bsh, ofs);
705
706 while (cnt--)
707 *d++ = val;
708 __asm __volatile("eieio; sync");
709 }
710
711 static void
712 bs_le_sr_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t val, size_t cnt)
713 {
714 volatile uint16_t *d = __ppc_ba(bsh, ofs);
715
716 while (cnt--)
717 out16rb(d++, val);
718 __asm __volatile("eieio; sync");
719 }
720
721 static void
722 bs_le_sr_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t val, size_t cnt)
723 {
724 volatile uint32_t *d = __ppc_ba(bsh, ofs);
725
726 while (cnt--)
727 out32rb(d++, val);
728 __asm __volatile("eieio; sync");
729 }
730
731 static void
732 bs_le_sr_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t val, size_t cnt)
733 {
734 TODO;
735 }
736
737 struct bus_space bs_be_tag = {
738 /* mapping/unmapping */
739 bs_gen_map,
740 bs_gen_unmap,
741 bs_gen_subregion,
742
743 /* allocation/deallocation */
744 bs_gen_alloc,
745 bs_gen_free,
746
747 /* barrier */
748 bs_gen_barrier,
749
750 /* read (single) */
751 bs_be_rs_1,
752 bs_be_rs_2,
753 bs_be_rs_4,
754 bs_be_rs_8,
755
756 bs_be_rs_2,
757 bs_be_rs_4,
758 bs_be_rs_8,
759
760 /* read multiple */
761 bs_be_rm_1,
762 bs_be_rm_2,
763 bs_be_rm_4,
764 bs_be_rm_8,
765
766 bs_be_rm_2,
767 bs_be_rm_4,
768 bs_be_rm_8,
769
770 /* read region */
771 bs_be_rr_1,
772 bs_be_rr_2,
773 bs_be_rr_4,
774 bs_be_rr_8,
775
776 bs_be_rr_2,
777 bs_be_rr_4,
778 bs_be_rr_8,
779
780 /* write (single) */
781 bs_be_ws_1,
782 bs_be_ws_2,
783 bs_be_ws_4,
784 bs_be_ws_8,
785
786 bs_be_ws_2,
787 bs_be_ws_4,
788 bs_be_ws_8,
789
790 /* write multiple */
791 bs_be_wm_1,
792 bs_be_wm_2,
793 bs_be_wm_4,
794 bs_be_wm_8,
795
796 bs_be_wm_2,
797 bs_be_wm_4,
798 bs_be_wm_8,
799
800 /* write region */
801 bs_be_wr_1,
802 bs_be_wr_2,
803 bs_be_wr_4,
804 bs_be_wr_8,
805
806 bs_be_wr_2,
807 bs_be_wr_4,
808 bs_be_wr_8,
809
810 /* set multiple */
811 bs_be_sm_1,
812 bs_be_sm_2,
813 bs_be_sm_4,
814 bs_be_sm_8,
815
816 bs_be_sm_2,
817 bs_be_sm_4,
818 bs_be_sm_8,
819
820 /* set region */
821 bs_be_sr_1,
822 bs_be_sr_2,
823 bs_be_sr_4,
824 bs_be_sr_8,
825
826 bs_be_sr_2,
827 bs_be_sr_4,
828 bs_be_sr_8,
829 };
830
831 struct bus_space bs_le_tag = {
832 /* mapping/unmapping */
833 bs_gen_map,
834 bs_gen_unmap,
835 bs_gen_subregion,
836
837 /* allocation/deallocation */
838 bs_gen_alloc,
839 bs_gen_free,
840
841 /* barrier */
842 bs_gen_barrier,
843
844 /* read (single) */
845 bs_le_rs_1,
846 bs_le_rs_2,
847 bs_le_rs_4,
848 bs_le_rs_8,
849
850 bs_be_rs_2,
851 bs_be_rs_4,
852 bs_be_rs_8,
853
854 /* read multiple */
855 bs_le_rm_1,
856 bs_le_rm_2,
857 bs_le_rm_4,
858 bs_le_rm_8,
859
860 bs_be_rm_2,
861 bs_be_rm_4,
862 bs_be_rm_8,
863
864 /* read region */
865 bs_le_rr_1,
866 bs_le_rr_2,
867 bs_le_rr_4,
868 bs_le_rr_8,
869
870 bs_be_rr_2,
871 bs_be_rr_4,
872 bs_be_rr_8,
873
874 /* write (single) */
875 bs_le_ws_1,
876 bs_le_ws_2,
877 bs_le_ws_4,
878 bs_le_ws_8,
879
880 bs_be_ws_2,
881 bs_be_ws_4,
882 bs_be_ws_8,
883
884 /* write multiple */
885 bs_le_wm_1,
886 bs_le_wm_2,
887 bs_le_wm_4,
888 bs_le_wm_8,
889
890 bs_be_wm_2,
891 bs_be_wm_4,
892 bs_be_wm_8,
893
894 /* write region */
895 bs_le_wr_1,
896 bs_le_wr_2,
897 bs_le_wr_4,
898 bs_le_wr_8,
899
900 bs_be_wr_2,
901 bs_be_wr_4,
902 bs_be_wr_8,
903
904 /* set multiple */
905 bs_le_sm_1,
906 bs_le_sm_2,
907 bs_le_sm_4,
908 bs_le_sm_8,
909
910 bs_be_sm_2,
911 bs_be_sm_4,
912 bs_be_sm_8,
913
914 /* set region */
915 bs_le_sr_1,
916 bs_le_sr_2,
917 bs_le_sr_4,
918 bs_le_sr_8,
919
920 bs_be_sr_2,
921 bs_be_sr_4,
922 bs_be_sr_8,
923 };
Cache object: b4a34e88ae0955bd96df67082013fb47
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